Attachment 147318 Details for Bug 226715 – tut_irsim_scmos2um.prm

tut_irsim_scmos2um.prm

tut_irsim_scmos2um.prm (text/plain), 3.42 KB, created by Chitlesh GOORAH on 2007-02-04 19:41:22 UTC

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Creator: Chitlesh GOORAH

Created: 2007-02-04 19:41:22 UTC

Size: 3.42 KB

patch

obsolete

>; configuration file for scmos with lamba = 1.0 (2um process)
>; 
>
>capm2a  .00000  ; 2nd metal capacitance -- area, pf/sq-micron
>capm2p  .00020  ; 2nd metal capacitance -- perimeter, pf/micron
>capma   .00003  ; 1st metal capacitance -- area, pf/sq-micron
>capmp   .00020  ; 1st metal capacitance -- perimeter, pf/micron
>cappa   .00007  ; poly capacitance -- area, pf/sq-micron
>cappp   .00020  ; poly capacitance -- perimeter, pf/micron
>capda	.00030	; n-diffusion capacitance -- area, pf/sq-micron
>capdp	.00030	; n-diffusion capacitance -- perimeter, pf/micron
>cappda	.00030	; p-diffusion capacitance -- area, pf/sq-micron
>cappdp	.00030	; p-diffusion capacitance -- perimeter, pf/micron
>
>capga	.000816	; gate capacitance        -- area, pf/sq-micron
>
>
>diffext  0	; diffusion extension for each transistor
>
>lambda  1.0     ; microns/lambda (conversion from .sim file units
>                ; to units used in cap parameters)
>
>lowthresh  0.4  ; logic low threshold as a normalized voltage
>
>highthresh 0.6  ; logic high threshold as a normalized voltage
>
>cntpullup 0	; irrelevant, cmos technology; no depletion transistors
>                ; <>0 means that the capacitor formed by gate of
>                ; pullup should be included in capacitance of output
>                ; node
>
>diffperim 0	; don't include diffusion perimeters for sidewall cap.
>                ; <>0 means do not include diffusion perimeters
>                ; that border on transistor gates when figuring
>                ; sidewall capacitance (*)
>
>subparea 0	; poly over transistor won't count as part pf bulk-poly cap.
>                ; <>0 means that poly over transistor region will not
>                ; be counted as part of the poly-bulk capacitor (*)
>
>
>diffext 0       ; diffusion extension for each transistor, i.e., each
>                ; transistor is assumed to have a rectangular source
>                ; and drain diffusion extending diffext units wide and
>                ; transistor-width units high.  The effect of the
>                ; diffusion extension is to add some capacitance to
>                ; the source and drain node of each transistor --
>                ; useful when processing the output of NET to improve
>                ; the capacitive loading approximations without adding
>                ; explicit load capacitors.  diffext is specified in
>                ; lambda (it will be converted using the lambda factor
>                ; above).
>
>;resistance channel context width length resist
>; this command specifies the equivalent resistance for a transistor
>; of type channel with the specified width and length.  Transistors
>; matching this entry will have the specified resistance; linear
>; interpolation is done if the width and/or length is not matched
>; exactly.
>;  channel is one of "enh", "dep", "intrinsic", "low-power",
>;                    "pullup", or "p-chan"
>;  context is one of "static", "dynamic-high", "dynamic-low", or "power"
>;  width   is given in lambda
>;  length  is given in lambda
>;  resist  is given in ohms
>
>
>; n-channel resistance
>;Keyword   Type      Context            Width   Length  Resistance
>;--------- --------- ------------       -----   ------  ----------
>resistance n-channel dynamic-high	10.0	2.0	3847.0
>resistance n-channel dynamic-low	10.0	2.0	1856.0
>resistance n-channel static		10.0	2.0	2472.0
>
>; p-channel resistance
>resistance p-channel dynamic-high	20.0	2.0	2020.0
>resistance p-channel dynamic-low	20.0	2.0	3969.0
>resistance p-channel static		20.0	2.0	2011.0

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Attachments on bug 226715: 147073 | 147103 | 147317 | 147318 | 147319 | 147320 | 147321 | 147327 | 147364