Attachment 147789 Details for Bug 228045 – X log

X log

Xorg.0.log (text/plain), 88.87 KB, created by Bill Nottingham on 2007-02-09 18:15:21 UTC

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Creator: Bill Nottingham

Created: 2007-02-09 18:15:21 UTC

Size: 88.87 KB

patch

obsolete

>
>X Window System Version 7.2.0
>Release Date: 24 December 2006
>X Protocol Version 11, Revision 0, Release 7.2
>Build Operating System: Fedora Core 7 Red Hat, Inc.
>Current Operating System: Linux apone.devel.redhat.com 2.6.20-1.2922.fc7 #1 SMP Sun Feb 4 18:20:53 EST 2007 x86_64
>Build Date: 04 February 2007
>Build ID: xorg-x11-server 1.2.0-5.fc7 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Fri Feb  9 13:05:44 2007
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Default Layout"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "<default monitor>"
>(**) |   |-->Device "Videocard0"
>(WW) No monitor specified for screen "Screen0".
>	Using a default monitor configuration.
>(**) |-->Input Device "Keyboard0"
>(==) |-->Input Device "<default pointer>"
>(WW) The core pointer device wasn't specified explicitly in the layout.
>	Using the default mouse configuration.
>(WW) No FontPath specified.  Using compiled-in default.
>(==) FontPath set to:
>	unix/:7100,
>	built-ins
>(==) RgbPath set to "/usr/share/X11/rgb"
>(==) ModulePath set to "/usr/lib64/xorg/modules"
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) Loader magic: 0x79f680
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 1.0
>	X.Org XInput driver : 0.6
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /usr/lib64/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(++) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,29a0 card 8086,514d rev 02 class 06,00,00 hdr 00
>(II) PCI: 00:02:0: chip 8086,29a2 card 8086,514d rev 02 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,29a3 card 8086,514d rev 02 class 03,80,00 hdr 80
>(II) PCI: 00:03:0: chip 8086,29a4 card 8086,514d rev 02 class 07,80,00 hdr 80
>(II) PCI: 00:19:0: chip 8086,104b card 8086,0001 rev 02 class 02,00,00 hdr 00
>(II) PCI: 00:1a:0: chip 8086,2834 card 8086,514d rev 02 class 0c,03,00 hdr 80
>(II) PCI: 00:1a:1: chip 8086,2835 card 8086,514d rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1a:7: chip 8086,283a card 8086,514d rev 02 class 0c,03,20 hdr 00
>(II) PCI: 00:1b:0: chip 8086,284b card 8086,2501 rev 02 class 04,03,00 hdr 00
>(II) PCI: 00:1c:0: chip 8086,283f card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:1: chip 8086,2841 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:2: chip 8086,2843 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:3: chip 8086,2845 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:4: chip 8086,2847 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1d:0: chip 8086,2830 card 8086,514d rev 02 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:1: chip 8086,2831 card 8086,514d rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:2: chip 8086,2832 card 8086,514d rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,2836 card 8086,514d rev 02 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,244e card 0000,0000 rev f2 class 06,04,01 hdr 01
>(II) PCI: 00:1f:0: chip 8086,2812 card 8086,514d rev 02 class 06,01,00 hdr 80
>(II) PCI: 00:1f:2: chip 8086,2821 card 8086,514d rev 02 class 01,06,01 hdr 00
>(II) PCI: 00:1f:3: chip 8086,283e card 8086,514d rev 02 class 0c,05,00 hdr 00
>(II) PCI: 02:00:0: chip 11ab,6101 card 11ab,6101 rev b1 class 01,01,8f hdr 00
>(II) PCI: 06:03:0: chip 104c,8023 card 8086,514d rev 00 class 0c,00,10 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,6), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:28:0), (0,1,1), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0x50500000 - 0x505fffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 2: bridge is at (0:28:1), (0,2,2), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 2 I/O range:
>	[0] -1	0	0x00001000 - 0x000010ff (0x100) IX[B]
>	[1] -1	0	0x00001400 - 0x000014ff (0x100) IX[B]
>	[2] -1	0	0x00001800 - 0x000018ff (0x100) IX[B]
>	[3] -1	0	0x00001c00 - 0x00001cff (0x100) IX[B]
>(II) Bus 2 non-prefetchable memory range:
>	[0] -1	0	0x50100000 - 0x501fffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 3: bridge is at (0:28:2), (0,3,3), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 3 non-prefetchable memory range:
>	[0] -1	0	0x50600000 - 0x506fffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 4: bridge is at (0:28:3), (0,4,4), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 4 non-prefetchable memory range:
>	[0] -1	0	0x50700000 - 0x507fffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 5: bridge is at (0:28:4), (0,5,5), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 5 non-prefetchable memory range:
>	[0] -1	0	0x50800000 - 0x508fffff (0x100000) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 6: bridge is at (0:30:0), (0,6,6), BCTRL: 0x0004 (VGA_EN is cleared)
>(II) Bus 6 non-prefetchable memory range:
>	[0] -1	0	0x50000000 - 0x500fffff (0x100000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(--) PCI:*(0:2:0) Intel Corporation 82G965 Integrated Graphics Controller rev 2, Mem @ 0x50300000/20, 0x40000000/28, I/O @ 0x2110/3
>(--) PCI: (0:2:1) Intel Corporation 82G965 Integrated Graphics Controller rev 2, Mem @ 0x50200000/20
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[1] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[2] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[3] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[4] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[5] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[6] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[7] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[8] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[9] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[10] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[11] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[12] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[13] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[14] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[15] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[16] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[17] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[18] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[19] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[20] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[21] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[22] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[23] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[24] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[25] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[26] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[27] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[28] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[29] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[30] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[31] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[1] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[2] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[3] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[4] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[5] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[6] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[7] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[8] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[9] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[10] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[11] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[12] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[13] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[14] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[15] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[16] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[17] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[18] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[19] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[20] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[21] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[22] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[23] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[24] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[25] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[26] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[27] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[28] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[29] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[30] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[31] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[5] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[6] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[7] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[8] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[9] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[10] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[11] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[12] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[13] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[14] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[15] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[16] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[17] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[18] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[19] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[20] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[21] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[22] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[23] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[24] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[25] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[26] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[27] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[28] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[29] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[30] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[31] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[32] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[33] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[34] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[35] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[36] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[37] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib64/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib64/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib64/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "freetype"
>(II) Loading /usr/lib64/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 7.2.0, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "type1"
>(II) Loading /usr/lib64/xorg/modules/fonts//libtype1.so
>(II) Module type1: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.2
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font Type1
>(II) LoadModule: "record"
>(II) Loading /usr/lib64/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "dri"
>(II) Loading /usr/lib64/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "intel"
>(II) Loading /usr/lib64/xorg/modules/drivers//intel_drv.so
>(II) Module i810: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.7.2
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 1.0
>(II) LoadModule: "kbd"
>(II) Loading /usr/lib64/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 7.1.1, module version = 1.1.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) LoadModule: "mouse"
>(II) Loading /usr/lib64/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 7.1.1, module version = 1.1.1
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) INTEL: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 965G, 965G, 965Q, 946GZ
>(II) Primary Device is: PCI 00:02:0
>(--) Assigning device section with no busID to primary device
>(WW) INTEL: No matching Device section for instance (BusID PCI:0:2:1) found
>(--) Chipset 965G found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[5] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[6] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[7] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[8] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[9] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[10] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[11] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[12] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[13] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[14] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[15] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[16] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[17] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[18] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[19] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[20] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[21] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[22] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[23] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[24] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[25] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[26] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[27] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[28] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[29] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[30] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[31] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[32] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[33] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[34] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[35] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[36] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[37] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[5] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[6] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[7] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[8] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[9] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[10] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[11] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[12] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[13] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[14] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[15] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[16] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[17] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[18] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[19] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[20] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[21] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[22] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[23] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[24] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[25] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[26] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[27] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[28] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[29] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[30] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[31] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[32] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[33] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[34] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[35] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[36] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[37] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[38] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[39] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[40] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>	[41] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[42] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Loading /usr/lib64/xorg/modules//libint10.so
>(II) Module int10: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vbe"
>(II) LoadModule: "vbe"
>(II) Loading /usr/lib64/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib64/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(**) INTEL(0): Depth 24, (--) framebuffer bpp 32
>(==) INTEL(0): RGB weight 888
>(==) INTEL(0): Default visual is TrueColor
>(II) INTEL(0): Integrated Graphics Chipset: Intel(R) 965G
>(--) INTEL(0): Chipset: "965G"
>(--) INTEL(0): Linear framebuffer at 0x40000000
>(--) INTEL(0): IO registers at addr 0x50300000
>(II) INTEL(0): Hardware state on X startup:
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00040000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x70000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x8000001c (enabled, pipe A, stall disabled, detected)
>(II) INTEL(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) INTEL(0):              SDVOUDI: 0x00000020
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x1f8f0f0f
>(II) INTEL(0):               DSPFW2: 0x00000f0f
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x00008c18
>(II) INTEL(0):                 LVDS: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x8000001c
>(II) INTEL(0):                 DVOC: 0x00080018
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) INTEL(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80000000
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x10001000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000c80 (3200 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPA0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0xc4020c00 (enabled, dvo, VGA, dac/serial mode, default clock, p1 = 2, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_A: 0x038302cf (720 active, 900 total)
>(II) INTEL(0):             HBLANK_A: 0x038302cf (720 start, 900 end)
>(II) INTEL(0):              HSYNC_A: 0x036802fc (765 start, 873 end)
>(II) INTEL(0):             VTOTAL_A: 0x01c0018f (400 active, 449 total)
>(II) INTEL(0):             VBLANK_A: 0x01c0018f (400 start, 449 end)
>(II) INTEL(0):              VSYNC_A: 0x019d019b (412 start, 414 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_B_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):             VGACNTRL: 0x0000008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x00000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x20
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): pipe A dot 113280 n 3 m1 20 m2 6 p1 2 p2 10
>(II) INTEL(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): 2 display pipes available.
>(II) INTEL(0): detected 512 kB GTT.
>(II) INTEL(0): detected 7676 kB stolen memory.
>(II) INTEL(0): Kernel reported 236800 total, 1 used
>(II) INTEL(0): I830CheckAvailableMemory: 947196 kB available
>(==) INTEL(0): Using XAA for acceleration
>(--) INTEL(0): Will try to allocate texture pool for old Mesa 3D driver.
>(II) INTEL(0): Will try to reserve 32768 kiB of AGP aperture space
>	for the DRM memory manager.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Loading /usr/lib64/xorg/modules//libddc.so
>(II) Module ddc: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Loading /usr/lib64/xorg/modules//libi2c.so
>(II) Module i2c: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) INTEL(0): I2C bus "CRTDDC_A" initialized.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) INTEL(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) INTEL(0): SDVO: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) INTEL(0): SDVO: R: 02 43 00 01 01 01 01 00 (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) INTEL(0): SDVO: R: C4 09 20 4E             (Success)
>(II) INTEL(0): SDVO device VID/DID: 02:43.00, clock range 25.0MHz - 200.0MHz, input 1: Y, input 2: N, output 1: Y, output 2: N
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) INTEL(0): No SDVO device found on SDVOC
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) INTEL(0): SDVO: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R: 08                      (Success)
>(II) INTEL(0): Current clock rate multiplier: 8
>(II) INTEL(0): SDVO: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R: 01 00                   (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) INTEL(0): SDVO: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) INTEL(0): SDVO: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) INTEL(0): SDVO: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) INTEL(0): SDVO: R: 01 00                   (Success)
>(II) INTEL(0): SDVO: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) INTEL(0): SDVO: R: 01 00                   (Success)
>(II) INTEL(0): I2C device "SDVOB DDC Bus:ddc2" registered at address 0xA0.
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) INTEL(0): I2C device "SDVOB DDC Bus:ddc2" removed.
>(II) INTEL(0): EDID for output TMDS-1
>(II) INTEL(0): Manufacturer: DEL  Model: e009  Serial#: 861422156
>(II) INTEL(0): Year: 2006  Week: 5
>(II) INTEL(0): EDID Version: 1.3
>(II) INTEL(0): Digital Display Input
>(II) INTEL(0): Max H-Image Size [cm]: horiz.: 43  vert.: 27
>(II) INTEL(0): Gamma: 2.20
>(II) INTEL(0): DPMS capabilities: StandBy Suspend Off; RGB/Color Display
>(II) INTEL(0): First detailed timing is preferred mode
>(II) INTEL(0): redX: 0.637 redY: 0.340   greenX: 0.297 greenY: 0.610
>(II) INTEL(0): blueX: 0.146 blueY: 0.071   whiteX: 0.313 whiteY: 0.329
>(II) INTEL(0): Supported VESA Video Modes:
>(II) INTEL(0): 720x400@70Hz
>(II) INTEL(0): 640x480@60Hz
>(II) INTEL(0): 640x480@75Hz
>(II) INTEL(0): 800x600@60Hz
>(II) INTEL(0): 800x600@75Hz
>(II) INTEL(0): 1024x768@60Hz
>(II) INTEL(0): 1024x768@75Hz
>(II) INTEL(0): 1280x1024@75Hz
>(II) INTEL(0): Manufacturer's mask: 0
>(II) INTEL(0): Supported Future Video Modes:
>(II) INTEL(0): #0: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
>(II) INTEL(0): #1: hsize: 1152  vsize 864  refresh: 75  vid: 20337
>(II) INTEL(0): Supported additional Video Mode:
>(II) INTEL(0): clock: 119.0 MHz   Image Size:  434 x 270 mm
>(II) INTEL(0): h_active: 1680  h_sync: 1728  h_sync_end 1760 h_blank_end 1840 h_border: 0
>(II) INTEL(0): v_active: 1050  v_sync: 1053  v_sync_end 1059 v_blanking: 1080 v_border: 0
>(II) INTEL(0): Serial No: T61306213XBL
>(II) INTEL(0): Ranges: V min: 56  V max: 75 Hz, H min: 30  H max: 83 kHz, PixClock max 140 MHz
>(II) INTEL(0): Monitor name: DELL 2005FPW
>(II) INTEL(0): EDID (in hex):
>(II) INTEL(0): 	00ffffffffffff0010ac09e04c425833
>(II) INTEL(0): 	05100103ee2b1b78ea0195a3574c9c25
>(II) INTEL(0): 	125054a54b008180714f010101010101
>(II) INTEL(0): 	0101010101017c2e90a0601a1e403020
>(II) INTEL(0): 	3600b20e1100001a000000ff00543631
>(II) INTEL(0): 	33303632313358424c0a000000fd0038
>(II) INTEL(0): 	4b1e530e000a202020202020000000fc
>(II) INTEL(0): 	0044454c4c20323030354650570a00c9
>(II) INTEL(0): EDID vendor "DEL", prod id 57353
>(II) INTEL(0): Not using default mode "640x350" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "640x400" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "720x400" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x960" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x960" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x1024" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x1024" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x1024" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1792x1344" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1792x1344" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1856x1392" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1856x1392" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1440" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1440" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "832x624" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1152x864" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x720" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x720" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x720" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x720" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x800" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x800" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x800" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x800" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1280x768" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1400x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1440x900" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1600x1024" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1680x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1680x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1680x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1680x1050" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1080" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1080" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1080" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1080" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1200" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "1920x1440" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2560x1600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2560x1600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2560x1600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Not using default mode "2560x1600" (bad mode clock/interlace/doublescan)
>(II) INTEL(0): Printing probed modes for output TMDS-1
>(II) INTEL(0): Modeline "1680x1050"x59.9  119.00  1680 1728 1760 1840  1050 1053 1059 1080 -hsync +vsync (64.7 kHz)
>(II) INTEL(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) INTEL(0): Modeline "1280x1024"x59.9  109.00  1280 1368 1496 1712  1024 1027 1034 1063 -hsync +vsync (63.7 kHz)
>(II) INTEL(0): Modeline "1152x864"x74.8  104.00  1152 1224 1344 1536  864 867 871 905 -hsync +vsync (67.7 kHz)
>(II) INTEL(0): Modeline "1024x768"x75.1   78.80  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.1 kHz)
>(II) INTEL(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) INTEL(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) INTEL(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) INTEL(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) INTEL(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) INTEL(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz)
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 16 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 17 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 14 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 15 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(--) INTEL(0): Pre-allocated VideoRam: 7676 kByte
>(==) INTEL(0): Potential VideoRam: 262144 kByte
>(==) INTEL(0): video overlay key set to 0x101fe
>(**) INTEL(0): page flipping disabled
>(==) INTEL(0): Using gamma correction (1.0, 1.0, 1.0)
>(WW) INTEL(0): DRM memory manager will be disabled
>	to make room for video memory
>(II) INTEL(0): Increasing the scanline pitch to allow tiling mode (1728 -> 1792).
>(==) INTEL(0): VideoRam: 91136 KB
>(==) INTEL(0): DPI set to (75, 75)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib64/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "xaa"
>(II) LoadModule: "xaa"
>(II) Loading /usr/lib64/xorg/modules//libxaa.so
>(II) Module xaa: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Loading /usr/lib64/xorg/modules//libramdac.so
>(II) Module ramdac: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) INTEL(0): Comparing regs from server start up to After PreInit
>(II) Loading sub module "shadow"
>(II) LoadModule: "shadow"
>(II) Loading /usr/lib64/xorg/modules//libshadow.so
>(II) Module shadow: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 0	0	0x40000000 - 0x4fffffff (0x10000000) MS[B]
>	[1] 0	0	0x50300000 - 0x503fffff (0x100000) MS[B]
>	[2] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[3] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[4] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[5] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[6] -1	0	0x50000000 - 0x50003fff (0x4000) MX[B]
>	[7] -1	0	0x50004000 - 0x500047ff (0x800) MX[B]
>	[8] -1	0	0x50100000 - 0x501001ff (0x200) MX[B]
>	[9] -1	0	0x50426000 - 0x504260ff (0x100) MX[B]
>	[10] -1	0	0x50425000 - 0x504257ff (0x800) MX[B]
>	[11] -1	0	0x50425800 - 0x50425bff (0x400) MX[B]
>	[12] -1	0	0x50420000 - 0x50423fff (0x4000) MX[B]
>	[13] -1	0	0x50425c00 - 0x50425fff (0x400) MX[B]
>	[14] -1	0	0x50424000 - 0x50424fff (0x1000) MX[B]
>	[15] -1	0	0x50400000 - 0x5041ffff (0x20000) MX[B]
>	[16] -1	0	0x50426100 - 0x5042610f (0x10) MX[B]
>	[17] -1	0	0x50200000 - 0x502fffff (0x100000) MX[B](B)
>	[18] -1	0	0x40000000 - 0x4fffffff (0x10000000) MX[B](B)
>	[19] -1	0	0x50300000 - 0x503fffff (0x100000) MX[B](B)
>	[20] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[21] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[22] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[23] 0	0	0x00002110 - 0x00002117 (0x8) IS[B]
>	[24] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[25] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[26] -1	0	0x00001000 - 0x0000100f (0x10) IX[B]
>	[27] -1	0	0x00001020 - 0x00001023 (0x4) IX[B]
>	[28] -1	0	0x00001010 - 0x00001017 (0x8) IX[B]
>	[29] -1	0	0x00001024 - 0x00001027 (0x4) IX[B]
>	[30] -1	0	0x00001018 - 0x0000101f (0x8) IX[B]
>	[31] -1	0	0x00002000 - 0x0000201f (0x20) IX[B]
>	[32] -1	0	0x00002020 - 0x0000203f (0x20) IX[B]
>	[33] -1	0	0x00002118 - 0x0000211b (0x4) IX[B]
>	[34] -1	0	0x00002100 - 0x00002107 (0x8) IX[B]
>	[35] -1	0	0x0000211c - 0x0000211f (0x4) IX[B]
>	[36] -1	0	0x00002108 - 0x0000210f (0x8) IX[B]
>	[37] -1	0	0x00002040 - 0x0000205f (0x20) IX[B]
>	[38] -1	0	0x00002060 - 0x0000207f (0x20) IX[B]
>	[39] -1	0	0x00002080 - 0x0000209f (0x20) IX[B]
>	[40] -1	0	0x000020a0 - 0x000020bf (0x20) IX[B]
>	[41] -1	0	0x000020c0 - 0x000020df (0x20) IX[B]
>	[42] -1	0	0x000020e0 - 0x000020ff (0x20) IX[B]
>	[43] -1	0	0x00002110 - 0x00002117 (0x8) IX[B](B)
>	[44] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[45] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) INTEL(0): Allocated 128 kB for the ring buffer at 0x0
>(II) INTEL(0): Allocating at least 4316 scanlines for pixmap cache
>(II) INTEL(0): Initial framebuffer allocation size: 41972 kByte
>(II) INTEL(0): Allocated 4 kB for HW cursor at 0xffff000
>(II) INTEL(0): Allocated 16 kB for HW (ARGB) cursor at 0xfffb000
>(II) INTEL(0): Allocated 4 kB for HW cursor at 0xfffa000
>(II) INTEL(0): Allocated 16 kB for HW (ARGB) cursor at 0xfff6000
>(II) INTEL(0): Allocated 4 kB for Overlay registers at 0xfff5000 (0x158c8000).
>(II) INTEL(0): Allocated 64 kB for the scratch buffer at 0xffe5000
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: drmOpenMinor returns 8
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) INTEL(0): [drm] DRM interface version 1.3
>(II) INTEL(0): [drm] created "i915" driver at busid "pci:0000:00:02.0"
>(II) INTEL(0): [drm] added 8192 byte SAREA at 0x2efff000
>(II) INTEL(0): [drm] mapped SAREA 0x2efff000 to 0x2aaaad7fb000
>(II) INTEL(0): [drm] framebuffer handle = 0x40020000
>(II) INTEL(0): [drm] added 1 reserved context for kernel
>(II) INTEL(0): Not enabling the DRM memory manager.
>(II) INTEL(0): Allocated 32 kB for the logical context at 0xffdd000.
>(II) INTEL(0): Allocated 7392 kB for the back buffer at 0xf000000.
>(II) INTEL(0): Allocated 7392 kB for the depth buffer at 0xe800000.
>(II) INTEL(0): Allocated 34048 kB for textures at 0xc6c0000
>(II) INTEL(0): 0x9dd758: Memory at offset 0x00020000, size 41972 kBytes
>(II) INTEL(0): 0x9e0c38: Memory at offset 0x0ffff000, size 4 kBytes
>(II) INTEL(0): 0x9e0c78: Memory at offset 0x0fffb000, size 16 kBytes
>(II) INTEL(0): 0x9e1198: Memory at offset 0x0fffa000, size 4 kBytes
>(II) INTEL(0): 0x9e11d8: Memory at offset 0x0fff6000, size 16 kBytes
>(II) INTEL(0): 0xa0b2a8: Memory at offset 0x00000000, size 128 kBytes
>(II) INTEL(0): 0x9dd7d8: Memory at offset 0x0ffe5000, size 64 kBytes
>(II) INTEL(0): 0xa0b1a0: Memory at offset 0x0fff5000, size 4 kBytes
>(II) INTEL(0): 0x9dda38: Memory at offset 0x0ffdd000, size 32 kBytes
>(II) INTEL(0): 0x9dda78: Memory at offset 0x0f000000, size 7392 kBytes
>(II) INTEL(0): 0x9ddab8: Memory at offset 0x0e800000, size 7392 kBytes
>(II) INTEL(0): 0x9ddaf8: Memory at offset 0x0c6c0000, size 34048 kBytes
>(II) INTEL(0): Activating tiled memory for the back buffer.
>(II) INTEL(0): Activating tiled memory for the depth buffer.
>(II) INTEL(0): [drm] Registers = 0x50300000
>(II) INTEL(0): [drm] ring buffer = 0x40000000
>(II) INTEL(0): [drm] init sarea width,height = 1680 x 1050 (pitch 1792)
>(II) INTEL(0): [drm] Back Buffer = 0x4f000000
>(II) INTEL(0): [drm] Depth Buffer = 0x4e800000
>(II) INTEL(0): [drm] textures = 0x4c6c0000
>(II) INTEL(0): [drm] Initialized kernel agp heap manager, 34865152
>(II) INTEL(0): [dri] visual configs initialized
>(==) INTEL(0): Write-combining range (0x40000000,0x10000000)
>(II) INTEL(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) INTEL(0): SDVO: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R: 08                      (Success)
>(II) INTEL(0): Current clock rate multiplier: 8
>(II) INTEL(0): SDVO: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R: 01 00                   (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) INTEL(0): SDVO: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) INTEL(0): SDVO: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) INTEL(0): xf86BindGARTMemory: bind key 10 at 0x0077f000 (pgoffset 1919)
>(II) INTEL(0): xf86BindGARTMemory: bind key 0 at 0x0ffff000 (pgoffset 65535)
>(II) INTEL(0): xf86BindGARTMemory: bind key 1 at 0x0fffb000 (pgoffset 65531)
>(II) INTEL(0): xf86BindGARTMemory: bind key 2 at 0x0fffa000 (pgoffset 65530)
>(II) INTEL(0): xf86BindGARTMemory: bind key 3 at 0x0fff6000 (pgoffset 65526)
>(II) INTEL(0): xf86BindGARTMemory: bind key 5 at 0x0ffe5000 (pgoffset 65509)
>(II) INTEL(0): xf86BindGARTMemory: bind key 4 at 0x0fff5000 (pgoffset 65525)
>(II) INTEL(0): xf86BindGARTMemory: bind key 6 at 0x0ffdd000 (pgoffset 65501)
>(II) INTEL(0): xf86BindGARTMemory: bind key 7 at 0x0f000000 (pgoffset 61440)
>(II) INTEL(0): xf86BindGARTMemory: bind key 8 at 0x0e800000 (pgoffset 59392)
>(II) INTEL(0): xf86BindGARTMemory: bind key 9 at 0x0c6c0000 (pgoffset 50880)
>(WW) INTEL(0): ESR is 0x00000010, page table error
>(EE) INTEL(0): PGTBL_ER is 0x00040000, overlay tiling
>(EE) INTEL(0): Existing errors found in hardware state
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>chosen: dotclock 115200 vco 2304000 ((m 120, m1 20, m2 8), n 3, (p 20, p1 2, p2 10))
>clock regs: 0xd4020c00, 0x00031408
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 16 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 17 30 20 36 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 14 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 15 30 20 36 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(WW) INTEL(0): No pipe mode list for pipe 1,continuing with desired mode
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00040000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x70000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x80080084 (enabled, pipe A, stall disabled, detected)
>(II) INTEL(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) INTEL(0):              SDVOUDI: 0x00000020
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x1f8f0f0f
>(II) INTEL(0):               DSPFW2: 0x00000f0f
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x00008c18
>(II) INTEL(0):                 LVDS: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x80080084
>(II) INTEL(0):                 DVOC: 0x00080018
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) INTEL(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x00000000
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x10000e39
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00001c00 (7168 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00020000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEASRC: 0x068f0419 (1680, 1050)
>(II) INTEL(0):                 FPA0: 0x00031408 (n = 3, m1 = 20, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0xd4020c00 (enabled, dvo, dac/serial mode, default clock, p1 = 2, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x072f068f (1680 active, 1840 total)
>(II) INTEL(0):             HBLANK_A: 0x072f068f (1680 start, 1840 end)
>(II) INTEL(0):              HSYNC_A: 0x06df06bf (1728 start, 1760 end)
>(II) INTEL(0):             VTOTAL_A: 0x04370419 (1050 active, 1080 total)
>(II) INTEL(0):             VBLANK_A: 0x04370419 (1050 start, 1080 end)
>(II) INTEL(0):              VSYNC_A: 0x0422041c (1053 start, 1059 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x04800c00 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_B_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):             VGACNTRL: 0x80000000 (disabled)
>(II) INTEL(0):               TV_CTL: 0x00000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x0e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0xff
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): pipe A dot 115200 n 3 m1 20 m2 8 p1 2 p2 10
>(II) INTEL(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): Output configuration:
>(II) INTEL(0):   Pipe A is on
>(II) INTEL(0):   Display plane A is now enabled and connected to pipe A.
>(II) INTEL(0):   Pipe B is off
>(II) INTEL(0):   Display plane B is now disabled and connected to pipe B.
>(II) INTEL(0):   Output VGA is connected to pipe none
>(II) INTEL(0):   Output TMDS-1 is connected to pipe A
>(II) INTEL(0): Using XFree86 Acceleration Architecture (XAA)
>	Screen to screen bit blits
>	Solid filled rectangles
>	8x8 mono pattern filled rectangles
>	Indirect CPU to Screen color expansion
>	Solid Horizontal and Vertical Lines
>	Offscreen Pixmaps
>	Setting up tile and stipple cache:
>		32 128x128 slots
>		32 256x256 slots
>		16 512x512 slots
>(==) INTEL(0): Backing store disabled
>(==) INTEL(0): Silken mouse enabled
>(II) INTEL(0): Initializing HW Cursor
>(II) INTEL(0): Set up textured video
>(II) INTEL(0): X context handle = 0x1
>(II) INTEL(0): [drm] installed DRM signal handler
>(II) INTEL(0): [DRI] installation complete
>(II) INTEL(0): [drm] dma control initialized, using IRQ 16
>(II) INTEL(0): direct rendering: Enabled
>(II) INTEL(0): RandR enabled, ignore the following RandR disabled message.
>(II) INTEL(0): Rotating to 0 degrees
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: drmOpenMinor returns 9
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(WW) AIGLX: 3D driver claims to not support visual 0x23
>(WW) AIGLX: 3D driver claims to not support visual 0x24
>(WW) AIGLX: 3D driver claims to not support visual 0x25
>(WW) AIGLX: 3D driver claims to not support visual 0x26
>(WW) AIGLX: 3D driver claims to not support visual 0x27
>(WW) AIGLX: 3D driver claims to not support visual 0x28
>(WW) AIGLX: 3D driver claims to not support visual 0x29
>(WW) AIGLX: 3D driver claims to not support visual 0x2a
>(WW) AIGLX: 3D driver claims to not support visual 0x2b
>(WW) AIGLX: 3D driver claims to not support visual 0x2c
>(WW) AIGLX: 3D driver claims to not support visual 0x2d
>(WW) AIGLX: 3D driver claims to not support visual 0x2e
>(WW) AIGLX: 3D driver claims to not support visual 0x2f
>(WW) AIGLX: 3D driver claims to not support visual 0x30
>(WW) AIGLX: 3D driver claims to not support visual 0x31
>(WW) AIGLX: 3D driver claims to not support visual 0x32
>(II) AIGLX: Loaded and initialized /usr/lib64/dri/i965_dri.so
>(II) GLX: Initialized DRI GL provider for screen 0
>(II) INTEL(0): Setting screen physical size to 569 x 356
>(**) Option "CoreKeyboard"
>(**) Keyboard0: Core Keyboard
>(**) Option "Protocol" "standard"
>(**) Keyboard0: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Keyboard0: XkbRules: "xorg"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard0: XkbModel: "pc105"
>(**) Option "XkbLayout" "us"
>(**) Keyboard0: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard0: CustomKeycodes disabled
>(WW) <default pointer>: No Device specified, looking for one...
>(II) <default pointer>: Setting Device option to "/dev/input/mice"
>(--) <default pointer>: Device: "/dev/input/mice"
>(==) <default pointer>: Protocol: "Auto"
>(**) Option "CorePointer"
>(**) <default pointer>: Core Pointer
>(==) <default pointer>: Emulate3Buttons, Emulate3Timeout: 50
>(**) <default pointer>: ZAxisMapping: buttons 4 and 5
>(**) <default pointer>: Buttons: 9
>(II) XINPUT: Adding extended input device "<default pointer>" (type: MOUSE)
>(II) XINPUT: Adding extended input device "Keyboard0" (type: KEYBOARD)
>(--) <default pointer>: PnP-detected protocol: "ExplorerPS/2"
>(II) <default pointer>: ps2EnableDataReporting: succeeded
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 16 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 17 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 14 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 15 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): Comparing regs from server start up to After LeaveVT
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00040000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x70000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x8000001c (enabled, pipe A, stall disabled, detected)
>(II) INTEL(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) INTEL(0):              SDVOUDI: 0x00000020
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x1f8f0f0f
>(II) INTEL(0):               DSPFW2: 0x00000f0f
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x00008c18
>(II) INTEL(0):                 LVDS: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x8000001c
>(II) INTEL(0):                 DVOC: 0x00080018
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) INTEL(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80000000
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x10001000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000c80 (3200 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPA0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0xc4020c00 (enabled, dvo, VGA, dac/serial mode, default clock, p1 = 2, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_A: 0x038302cf (720 active, 900 total)
>(II) INTEL(0):             HBLANK_A: 0x038302cf (720 start, 900 end)
>(II) INTEL(0):              HSYNC_A: 0x036802fc (765 start, 873 end)
>(II) INTEL(0):             VTOTAL_A: 0x01c0018f (400 active, 449 total)
>(II) INTEL(0):             VBLANK_A: 0x01c0018f (400 start, 449 end)
>(II) INTEL(0):              VSYNC_A: 0x019d019b (412 start, 414 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_B_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):             VGACNTRL: 0x0000008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x00000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0xff
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): pipe A dot 113280 n 3 m1 20 m2 6 p1 2 p2 10
>(II) INTEL(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 10
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 0
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 1
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 2
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 3
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 5
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 4
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 6
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 7
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 8
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 9
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) INTEL(0): xf86BindGARTMemory: bind key 10 at 0x0077f000 (pgoffset 1919)
>(II) INTEL(0): xf86BindGARTMemory: bind key 0 at 0x0ffff000 (pgoffset 65535)
>(II) INTEL(0): xf86BindGARTMemory: bind key 1 at 0x0fffb000 (pgoffset 65531)
>(II) INTEL(0): xf86BindGARTMemory: bind key 2 at 0x0fffa000 (pgoffset 65530)
>(II) INTEL(0): xf86BindGARTMemory: bind key 3 at 0x0fff6000 (pgoffset 65526)
>(II) INTEL(0): xf86BindGARTMemory: bind key 5 at 0x0ffe5000 (pgoffset 65509)
>(II) INTEL(0): xf86BindGARTMemory: bind key 4 at 0x0fff5000 (pgoffset 65525)
>(II) INTEL(0): xf86BindGARTMemory: bind key 6 at 0x0ffdd000 (pgoffset 65501)
>(II) INTEL(0): xf86BindGARTMemory: bind key 7 at 0x0f000000 (pgoffset 61440)
>(II) INTEL(0): xf86BindGARTMemory: bind key 8 at 0x0e800000 (pgoffset 59392)
>(II) INTEL(0): xf86BindGARTMemory: bind key 9 at 0x0c6c0000 (pgoffset 50880)
>(WW) INTEL(0): ESR is 0x00000010, page table error
>(EE) INTEL(0): PGTBL_ER is 0x00040000, overlay tiling
>(EE) INTEL(0): Existing errors found in hardware state
>(II) INTEL(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>chosen: dotclock 115200 vco 2304000 ((m 120, m1 20, m2 8), n 3, (p 20, p1 2, p2 10))
>clock regs: 0xd4020c00, 0x00031408
>(II) INTEL(0): SDVO: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 16 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 17 30 20 36 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 14 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 15 30 20 36 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00040000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x70000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x80080084 (enabled, pipe A, stall disabled, detected)
>(II) INTEL(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) INTEL(0):              SDVOUDI: 0x00000020
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x1f8f0f0f
>(II) INTEL(0):               DSPFW2: 0x00000f0f
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x00008c18
>(II) INTEL(0):                 LVDS: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x80080084
>(II) INTEL(0):                 DVOC: 0x00080018
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) INTEL(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x00000000
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x10000e39
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00001c00 (7168 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00020000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0xc0000000 (enabled, double-wide)
>(II) INTEL(0):             PIPEASRC: 0x068f0419 (1680, 1050)
>(II) INTEL(0):                 FPA0: 0x00031408 (n = 3, m1 = 20, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0xd4020c00 (enabled, dvo, dac/serial mode, default clock, p1 = 2, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x072f068f (1680 active, 1840 total)
>(II) INTEL(0):             HBLANK_A: 0x072f068f (1680 start, 1840 end)
>(II) INTEL(0):              HSYNC_A: 0x06df06bf (1728 start, 1760 end)
>(II) INTEL(0):             VTOTAL_A: 0x04370419 (1050 active, 1080 total)
>(II) INTEL(0):             VBLANK_A: 0x04370419 (1050 start, 1080 end)
>(II) INTEL(0):              VSYNC_A: 0x0422041c (1053 start, 1059 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x04800c00 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_B_MD: 0x00000303
>(II) INTEL(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00020002
>(II) INTEL(0):             VGACNTRL: 0x80000000 (disabled)
>(II) INTEL(0):               TV_CTL: 0x00000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x20
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): pipe A dot 115200 n 3 m1 20 m2 8 p1 2 p2 10
>(II) INTEL(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): Output configuration:
>(II) INTEL(0):   Pipe A is on
>(II) INTEL(0):   Display plane A is now enabled and connected to pipe A.
>(II) INTEL(0):   Pipe B is off
>(II) INTEL(0):   Display plane B is now disabled and connected to pipe B.
>(II) INTEL(0):   Output VGA is connected to pipe none
>(II) INTEL(0):   Output TMDS-1 is connected to pipe A
>(II) INTEL(0): [drm] dma control initialized, using IRQ 16
>(II) INTEL(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) INTEL(0): SDVO: R: 01                      (Success)
>(II) INTEL(0): SDVO: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) INTEL(0): SDVO: R:                         (Success)
>(II) <default pointer>: ps2EnableDataReporting: succeeded

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Attachments on bug 228045: 147789 | 147790 | 147795