Attachment 148312 Details for Bug 216895 – diff output

diff output

v3.71tg3VsnativeR4.4 (text/plain), 119.07 KB, created by Shyam kumar Iyer on 2007-02-19 06:06:34 UTC

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Description:

Filename:

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Creator: Shyam kumar Iyer

Created: 2007-02-19 06:06:34 UTC

Size: 119.07 KB

patch

obsolete

>--- tg3.c	2006-12-16 06:49:48.000000000 +0530
>+++ ../kernel-2.6.9/linux-2.6.9/drivers/net/tg3.c	2007-02-17 12:30:37.000000000 +0530
>@@ -15,22 +15,10 @@
>  *	notice is accompanying it.
>  */
> 
>-#include <linux/version.h>
>-
>-#if (LINUX_VERSION_CODE < 0x020613)
> #include <linux/config.h>
>-#endif
> 
>-#if (LINUX_VERSION_CODE < 0x020500)
>-#if defined(CONFIG_MODVERSIONS) && defined(MODULE) && ! defined(MODVERSIONS)
>-#define MODVERSIONS
>-#include <linux/modversions.h>
>-#endif
>-#endif
> #include <linux/module.h>
>-#if (LINUX_VERSION_CODE >= 0x20600)
> #include <linux/moduleparam.h>
>-#endif
> #include <linux/kernel.h>
> #include <linux/types.h>
> #include <linux/compiler.h>
>@@ -48,14 +36,9 @@
> #include <linux/if_vlan.h>
> #include <linux/ip.h>
> #include <linux/tcp.h>
>-#if (LINUX_VERSION_CODE >= 0x20600)
> #include <linux/workqueue.h>
>-#endif
> #include <linux/prefetch.h>
>-#if (LINUX_VERSION_CODE >= 0x020600)
> #include <linux/dma-mapping.h>
>-#endif
>-#include <linux/bitops.h>
> 
> #include <net/checksum.h>
> 
>@@ -82,12 +65,13 @@
> #define TG3_TSO_SUPPORT	0
> #endif
> 
>+#include "tg3_compat.h"
> #include "tg3.h"
> 
> #define DRV_MODULE_NAME		"tg3"
> #define PFX DRV_MODULE_NAME	": "
>-#define DRV_MODULE_VERSION	"3.71b"
>-#define DRV_MODULE_RELDATE	"December 15, 2006"
>+#define DRV_MODULE_VERSION	"3.52-rh"
>+#define DRV_MODULE_RELDATE	"Mar 06, 2006"
> 
> #define TG3_DEF_MAC_MODE	0
> #define TG3_DEF_RX_MODE		0
>@@ -141,13 +125,16 @@
> 			           TG3_RX_RCB_RING_SIZE(tp))
> #define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
> 				 TG3_TX_RING_SIZE)
>+#define TX_BUFFS_AVAIL(TP)						\
>+	((TP)->tx_pending -						\
>+	 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
> #define NEXT_TX(N)		(((N) + 1) & (TG3_TX_RING_SIZE - 1))
> 
> #define RX_PKT_BUF_SZ		(1536 + tp->rx_offset + 64)
> #define RX_JUMBO_PKT_BUF_SZ	(9046 + tp->rx_offset + 64)
> 
> /* minimum number of free TX descriptors required to wake up TX process */
>-#define TG3_TX_WAKEUP_THRESH(tp)		((tp)->tx_pending / 4)
>+#define TG3_TX_WAKEUP_THRESH		(TG3_TX_RING_SIZE / 4)
> 
> /* number of ETHTOOL_GSTATS u64's */
> #define TG3_NUM_STATS		(sizeof(struct tg3_ethtool_stats)/sizeof(u64))
>@@ -163,78 +150,124 @@
> MODULE_VERSION(DRV_MODULE_VERSION);
> 
> static int tg3_debug = -1;	/* -1 == use TG3_DEF_MSG_ENABLE as value */
>-#if (LINUX_VERSION_CODE >= 0x20600)
> module_param(tg3_debug, int, 0);
> MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
>-#endif
> 
> static struct pci_device_id tg3_pci_tbl[] = {
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
>-	{PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
>-	{}
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
>+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
>+	{ 0, }
> };
> 
> MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
> 
>-static const struct {
>+static struct {
> 	const char string[ETH_GSTRING_LEN];
> } ethtool_stats_keys[TG3_NUM_STATS] = {
> 	{ "rx_octets" },
>@@ -315,7 +348,7 @@
> 	{ "nic_tx_threshold_hit" }
> };
> 
>-static const struct {
>+static struct {
> 	const char string[ETH_GSTRING_LEN];
> } ethtool_test_keys[TG3_NUM_TEST] = {
> 	{ "nvram test     (online) " },
>@@ -333,7 +366,7 @@
> 
> static u32 tg3_read32(struct tg3 *tp, u32 off)
> {
>-	return (readl(tp->regs + off));
>+	return (readl(tp->regs + off)); 
> }
> 
> static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
>@@ -449,16 +482,6 @@
> 		readl(mbox);
> }
> 
>-static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
>-{
>-	return (readl(tp->regs + off + GRCMBOX_BASE));
>-}
>-
>-static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
>-{
>-	writel(val, tp->regs + off + GRCMBOX_BASE);
>-}
>-
> #define tw32_mailbox(reg, val)	tp->write32_mbox(tp, reg, val)
> #define tw32_mailbox_f(reg, val)	tw32_mailbox_flush(tp, (reg), (val))
> #define tw32_rx_mbox(reg, val)	tp->write32_rx_mbox(tp, reg, val)
>@@ -474,51 +497,34 @@
> {
> 	unsigned long flags;
> 
>-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
>-	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
>-		return;
>-
> 	spin_lock_irqsave(&tp->indirect_lock, flags);
>-	if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
>-		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
>-		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
>-
>-		/* Always leave this as zero. */
>-		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
>-	} else {
>-		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
>-		tw32_f(TG3PCI_MEM_WIN_DATA, val);
>+	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
>+	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
> 
>-		/* Always leave this as zero. */
>-		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
>-	}
>+	/* Always leave this as zero. */
>+	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
> 	spin_unlock_irqrestore(&tp->indirect_lock, flags);
> }
> 
>+static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
>+{
>+	/* If no workaround is needed, write to mem space directly */
>+	if (tp->write32 != tg3_write_indirect_reg32)
>+		tw32(NIC_SRAM_WIN_BASE + off, val);
>+	else
>+		tg3_write_mem(tp, off, val);
>+}
>+
> static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
> {
> 	unsigned long flags;
> 
>-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
>-	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
>-		*val = 0;
>-		return;
>-	}
>-
> 	spin_lock_irqsave(&tp->indirect_lock, flags);
>-	if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
>-		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
>-		pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
>+	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
>+	pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
> 
>-		/* Always leave this as zero. */
>-		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
>-	} else {
>-		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
>-		*val = tr32(TG3PCI_MEM_WIN_DATA);
>-
>-		/* Always leave this as zero. */
>-		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
>-	}
>+	/* Always leave this as zero. */
>+	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
> 	spin_unlock_irqrestore(&tp->indirect_lock, flags);
> }
> 
>@@ -534,9 +540,6 @@
> 	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
> 	    (tp->hw_status->status & SD_STATUS_UPDATED))
> 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
>-	else
>-		tw32(HOSTCC_MODE, tp->coalesce_mode |
>-		     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
> }
> 
> static void tg3_enable_ints(struct tg3 *tp)
>@@ -577,7 +580,7 @@
> /* tg3_restart_ints
>  *  similar to tg3_enable_ints, but it accurately determines whether there
>  *  is new work pending and can return without flushing the PIO write
>- *  which reenables interrupts
>+ *  which reenables interrupts 
>  */
> static void tg3_restart_ints(struct tg3 *tp)
> {
>@@ -666,7 +669,7 @@
> 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
> 		      MI_COM_REG_ADDR_MASK);
> 	frame_val |= (MI_COM_CMD_READ | MI_COM_START);
>-
>+	
> 	tw32_f(MAC_MI_COM, frame_val);
> 
> 	loops = PHY_BUSY_LOOPS;
>@@ -702,10 +705,6 @@
> 	unsigned int loops;
> 	int ret;
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
>-	    (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
>-		return 0;
>-
> 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
> 		tw32_f(MAC_MI_MODE,
> 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
>@@ -718,7 +717,7 @@
> 		      MI_COM_REG_ADDR_MASK);
> 	frame_val |= (val & MI_COM_DATA_MASK);
> 	frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
>-
>+	
> 	tw32_f(MAC_MI_COM, frame_val);
> 
> 	loops = PHY_BUSY_LOOPS;
>@@ -969,8 +968,6 @@
> 	return err;
> }
> 
>-static void tg3_link_report(struct tg3 *);
>-
> /* This will reset the tigon3 PHY if there is no valid
>  * link unless the FORCE argument is non-zero.
>  */
>@@ -979,23 +976,11 @@
> 	u32 phy_status;
> 	int err;
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		u32 val;
>-
>-		val = tr32(GRC_MISC_CFG);
>-		tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
>-		udelay(40);
>-	}
> 	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
> 	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
> 	if (err != 0)
> 		return -EBUSY;
> 
>-	if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
>-		netif_carrier_off(tp->dev);
>-		tg3_link_report(tp);
>-	}
>-
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
>@@ -1032,17 +1017,6 @@
> 		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
> 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
> 	}
>-	else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
>-		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
>-		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
>-		if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
>-			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
>-			tg3_writephy(tp, MII_TG3_TEST1,
>-				     MII_TG3_TEST1_TRIM_EN | 0x4);
>-		} else
>-			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
>-		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
>-	}
> 	/* Set Extended packet length bit (bit 14) on all chips that */
> 	/* support jumbo frames */
> 	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
>@@ -1068,24 +1042,6 @@
> 				 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
> 	}
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		u32 phy_reg;
>-
>-		/* adjust output voltage */
>-		tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
>-
>-		if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
>-			u32 phy_reg2;
>-
>-			tg3_writephy(tp, MII_TG3_EPHY_TEST,
>-				     phy_reg | MII_TG3_EPHY_SHADOW_EN);
>-			/* Enable auto-MDIX */
>-			if (!tg3_readphy(tp, 0x10, &phy_reg2))
>-				tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
>-			tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
>-		}
>-	}
>-
> 	tg3_phy_set_wirespeed(tp);
> 	return 0;
> }
>@@ -1094,7 +1050,7 @@
> {
> 	struct tg3 *tp_peer = tp;
> 
>-	if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
>+	if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
> 		return;
> 
> 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
>@@ -1197,36 +1153,6 @@
> static int tg3_nvram_lock(struct tg3 *);
> static void tg3_nvram_unlock(struct tg3 *);
> 
>-static void tg3_power_down_phy(struct tg3 *tp)
>-{
>-	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
>-		return;
>-
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		u32 val;
>-
>-		tg3_bmcr_reset(tp);
>-		val = tr32(GRC_MISC_CFG);
>-		tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
>-		udelay(40);
>-		return;
>-	} else {
>-		tg3_writephy(tp, MII_TG3_EXT_CTRL,
>-			     MII_TG3_EXT_CTRL_FORCE_LED_OFF);
>-		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
>-	}
>-
>-	/* The PHY should not be powered down on some chips because
>-	 * of bugs.
>-	 */
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
>-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
>-	     (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
>-		return;
>-	tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
>-}
>-
> static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
> {
> 	u32 misc_host_ctrl;
>@@ -1254,7 +1180,7 @@
> 		udelay(100);	/* Delay after power state change */
> 
> 		/* Switch out of Vaux if it is not a LOM */
>-		if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
>+		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
> 			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
> 
> 		return 0;
>@@ -1298,12 +1224,7 @@
> 		tg3_setup_phy(tp, 0);
> 	}
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		u32 val;
>-
>-		val = tr32(GRC_VCPU_EXT_CTRL);
>-		tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
>-	} else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
>+	if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
> 		int i;
> 		u32 val;
> 
>@@ -1311,12 +1232,7 @@
> 			tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
> 			if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
> 				break;
>-#if (LINUX_VERSION_CODE < 0x20607)
>-			set_current_state(TASK_UNINTERRUPTIBLE);
>-			schedule_timeout(HZ / 1000);
>-#else
> 			msleep(1);
>-#endif
> 		}
> 	}
> 	tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
>@@ -1332,10 +1248,7 @@
> 			tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
> 			udelay(40);
> 
>-			if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
>-				mac_mode = MAC_MODE_PORT_MODE_GMII;
>-			else
>-				mac_mode = MAC_MODE_PORT_MODE_MII;
>+			mac_mode = MAC_MODE_PORT_MODE_MII;
> 
> 			if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
> 			    !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
>@@ -1369,8 +1282,7 @@
> 
> 		tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
> 			    CLOCK_CTRL_PWRDOWN_PLL133, 40);
>-	} else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
>-		   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
>+	} else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
> 		/* do nothing */
> 	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
> 		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
>@@ -1414,8 +1326,16 @@
> 	}
> 
> 	if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
>-	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
>-		tg3_power_down_phy(tp);
>+	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
>+		/* Turn off the PHY */
>+		if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
>+			tg3_writephy(tp, MII_TG3_EXT_CTRL,
>+				     MII_TG3_EXT_CTRL_FORCE_LED_OFF);
>+			tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
>+			if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
>+				tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
>+		}
>+	}
> 
> 	tg3_frob_aux_power(tp);
> 
>@@ -1436,22 +1356,20 @@
> 		}
> 	}
> 
>-	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
>-
> 	/* Finally, set the new power state. */
> 	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
> 	udelay(100);	/* Delay after power state change */
> 
>+	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
>+
> 	return 0;
> }
> 
> static void tg3_link_report(struct tg3 *tp)
> {
> 	if (!netif_carrier_ok(tp->dev)) {
>-		if (netif_msg_link(tp))
>-			printk(KERN_INFO PFX "%s: Link is down.\n",
>-			       tp->dev->name);
>-	} else if (netif_msg_link(tp)) {
>+		printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
>+	} else {
> 		printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
> 		       tp->dev->name,
> 		       (tp->link_config.active_speed == SPEED_1000 ?
>@@ -1530,7 +1448,7 @@
> 	if (old_rx_mode != tp->rx_mode) {
> 		tw32_f(MAC_RX_MODE, tp->rx_mode);
> 	}
>-
>+	
> 	if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
> 		tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
> 	else
>@@ -1575,13 +1493,6 @@
> 		break;
> 
> 	default:
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			*speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
>-				 SPEED_10;
>-			*duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
>-				  DUPLEX_HALF;
>-			break;
>-		}
> 		*speed = SPEED_INVALID;
> 		*duplex = DUPLEX_INVALID;
> 		break;
>@@ -1606,6 +1517,12 @@
> 
> 		tg3_writephy(tp, MII_ADVERTISE, new_adv);
> 	} else if (tp->link_config.speed == SPEED_INVALID) {
>+		tp->link_config.advertising =
>+			(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
>+			 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
>+			 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
>+			 ADVERTISED_Autoneg | ADVERTISED_MII);
>+
> 		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
> 			tp->link_config.advertising &=
> 				~(ADVERTISED_1000baseT_Half |
>@@ -1749,36 +1666,25 @@
> 	return err;
> }
> 
>-static int tg3_copper_is_advertising_right(struct tg3 *tp, u32 mask)
>+static int tg3_copper_is_advertising_all(struct tg3 *tp)
> {
>-	u32 adv_reg, all_mask = 0;
>-
>-	if (mask & ADVERTISED_10baseT_Half)
>-		all_mask |= ADVERTISE_10HALF;
>-	if (mask & ADVERTISED_10baseT_Full)
>-		all_mask |= ADVERTISE_10FULL;
>-	if (mask & ADVERTISED_100baseT_Half)
>-		all_mask |= ADVERTISE_100HALF;
>-	if (mask & ADVERTISED_100baseT_Full)
>-		all_mask |= ADVERTISE_100FULL;
>+	u32 adv_reg, all_mask;
> 
> 	if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
> 		return 0;
> 
>+	all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
>+		    ADVERTISE_100HALF | ADVERTISE_100FULL);
> 	if ((adv_reg & all_mask) != all_mask)
> 		return 0;
> 	if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
> 		u32 tg3_ctrl;
> 
>-		all_mask = 0;
>-		if (mask & ADVERTISED_1000baseT_Half)
>-			all_mask |= ADVERTISE_1000HALF;
>-		if (mask & ADVERTISED_1000baseT_Full)
>-			all_mask |= ADVERTISE_1000FULL;
>-
> 		if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
> 			return 0;
> 
>+		all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
>+			    MII_TG3_CTRL_ADV_1000_FULL);
> 		if ((tg3_ctrl & all_mask) != all_mask)
> 			return 0;
> 	}
>@@ -1869,7 +1775,7 @@
> 
> 	if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
> 		tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
>-	else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
>+	else
> 		tg3_writephy(tp, MII_TG3_IMASK, ~0);
> 
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
>@@ -1938,8 +1844,7 @@
> 				/* Force autoneg restart if we are exiting
> 				 * low power mode.
> 				 */
>-				if (!tg3_copper_is_advertising_right(tp,
>-						tp->link_config.advertising))
>+				if (!tg3_copper_is_advertising_all(tp))
> 					current_link_up = 0;
> 			} else {
> 				current_link_up = 0;
>@@ -2527,27 +2432,24 @@
> 	expected_sg_dig_ctrl |= (1 << 12);
> 
> 	if (sg_dig_ctrl != expected_sg_dig_ctrl) {
>-		if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
>-		    tp->serdes_counter &&
>-		    ((mac_status & (MAC_STATUS_PCS_SYNCED |
>-				    MAC_STATUS_RCVD_CFG)) ==
>-		     MAC_STATUS_PCS_SYNCED)) {
>-			tp->serdes_counter--;
>-			current_link_up = 1;
>-			goto out;
>-		}
>-restart_autoneg:
> 		if (workaround)
> 			tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
> 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
> 		udelay(5);
> 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
> 
>-		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
>-		tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
>+		tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
> 	} else if (mac_status & (MAC_STATUS_PCS_SYNCED |
> 				 MAC_STATUS_SIGNAL_DET)) {
>-		sg_dig_status = tr32(SG_DIG_STATUS);
>+		int i;
>+
>+		/* Giver time to negotiate (~200ms) */
>+		for (i = 0; i < 40000; i++) {
>+			sg_dig_status = tr32(SG_DIG_STATUS);
>+			if (sg_dig_status & (0x3))
>+				break;
>+			udelay(5);
>+		}
> 		mac_status = tr32(MAC_STATUS);
> 
> 		if ((sg_dig_status & (1 << 1)) &&
>@@ -2563,11 +2465,10 @@
> 
> 			tg3_setup_flow_control(tp, local_adv, remote_adv);
> 			current_link_up = 1;
>-			tp->serdes_counter = 0;
>-			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
>+			tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
> 		} else if (!(sg_dig_status & (1 << 1))) {
>-			if (tp->serdes_counter)
>-				tp->serdes_counter--;
>+			if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
>+				tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
> 			else {
> 				if (workaround) {
> 					u32 val = serdes_cfg;
>@@ -2591,17 +2492,9 @@
> 				    !(mac_status & MAC_STATUS_RCVD_CFG)) {
> 					tg3_setup_flow_control(tp, 0, 0);
> 					current_link_up = 1;
>-					tp->tg3_flags2 |=
>-						TG3_FLG2_PARALLEL_DETECT;
>-					tp->serdes_counter =
>-						SERDES_PARALLEL_DET_TIMEOUT;
>-				} else
>-					goto restart_autoneg;
>+				}
> 			}
> 		}
>-	} else {
>-		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
>-		tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
> 	}
> 
> out:
>@@ -2620,7 +2513,7 @@
> 	if (tp->link_config.autoneg == AUTONEG_ENABLE) {
> 		u32 flags;
> 		int i;
>-
>+  
> 		if (fiber_autoneg(tp, &flags)) {
> 			u32 local_adv, remote_adv;
> 
>@@ -2732,16 +2625,14 @@
> 				    MAC_STATUS_CFG_CHANGED));
> 		udelay(5);
> 		if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
>-					 MAC_STATUS_CFG_CHANGED |
>-					 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
>+					 MAC_STATUS_CFG_CHANGED)) == 0)
> 			break;
> 	}
> 
> 	mac_status = tr32(MAC_STATUS);
> 	if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
> 		current_link_up = 0;
>-		if (tp->link_config.autoneg == AUTONEG_ENABLE &&
>-		    tp->serdes_counter == 0) {
>+		if (tp->link_config.autoneg == AUTONEG_ENABLE) {
> 			tw32_f(MAC_MODE, (tp->mac_mode |
> 					  MAC_MODE_SEND_CONFIGS));
> 			udelay(1);
>@@ -2846,7 +2737,7 @@
> 			tg3_writephy(tp, MII_BMCR, bmcr);
> 
> 			tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
>-			tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
>+			tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
> 			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
> 
> 			return err;
>@@ -2951,9 +2842,9 @@
> 
> static void tg3_serdes_parallel_detect(struct tg3 *tp)
> {
>-	if (tp->serdes_counter) {
>+	if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
> 		/* Give autoneg time to complete. */
>-		tp->serdes_counter--;
>+		tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
> 		return;
> 	}
> 	if (!netif_carrier_ok(tp->dev) &&
>@@ -3043,34 +2934,6 @@
> 	return err;
> }
> 
>-/* This is called whenever we suspect that the system chipset is re-
>- * ordering the sequence of MMIO to the tx send mailbox. The symptom
>- * is bogus tx completions. We try to recover by setting the
>- * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
>- * in the workqueue.
>- */
>-static void tg3_tx_recover(struct tg3 *tp)
>-{
>-	BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
>-	       tp->write32_tx_mbox == tg3_write_indirect_mbox);
>-
>-	printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
>-	       "mapped I/O cycles to the network device, attempting to "
>-	       "recover. Please report the problem to the driver maintainer "
>-	       "and include system chipset information.\n", tp->dev->name);
>-
>-	spin_lock(&tp->lock);
>-	tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
>-	spin_unlock(&tp->lock);
>-}
>-
>-static inline u32 tg3_tx_avail(struct tg3 *tp)
>-{
>-	smp_mb();
>-	return (tp->tx_pending -
>-		((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
>-}
>-
> /* Tigon3 never reports partial packet sends.  So we do not
>  * need special logic to handle SKBs that have not had all
>  * of their frags sent yet, like SunGEM does.
>@@ -3083,12 +2946,10 @@
> 	while (sw_idx != hw_idx) {
> 		struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
> 		struct sk_buff *skb = ri->skb;
>-		int i, tx_bug = 0;
>+		int i;
> 
>-		if (unlikely(skb == NULL)) {
>-			tg3_tx_recover(tp);
>-			return;
>-		}
>+		if (unlikely(skb == NULL))
>+			BUG();
> 
> 		pci_unmap_single(tp->pdev,
> 				 pci_unmap_addr(ri, mapping),
>@@ -3100,9 +2961,12 @@
> 		sw_idx = NEXT_TX(sw_idx);
> 
> 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
>+			if (unlikely(sw_idx == hw_idx))
>+				BUG();
>+
> 			ri = &tp->tx_buffers[sw_idx];
>-			if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
>-				tx_bug = 1;
>+			if (unlikely(ri->skb != NULL))
>+				BUG();
> 
> 			pci_unmap_page(tp->pdev,
> 				       pci_unmap_addr(ri, mapping),
>@@ -3113,29 +2977,16 @@
> 		}
> 
> 		dev_kfree_skb(skb);
>-
>-		if (unlikely(tx_bug)) {
>-			tg3_tx_recover(tp);
>-			return;
>-		}
> 	}
> 
> 	tp->tx_cons = sw_idx;
> 
>-	/* Need to make the tx_cons update visible to tg3_start_xmit()
>-	 * before checking for netif_queue_stopped().  Without the
>-	 * memory barrier, there is a small possibility that tg3_start_xmit()
>-	 * will miss it and cause the queue to be stopped forever.
>-	 */
>-	smp_mb();
>-
>-	if (unlikely(netif_queue_stopped(tp->dev) &&
>-		     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
>-		netif_tx_lock(tp->dev);
>+	if (unlikely(netif_queue_stopped(tp->dev))) {
>+		spin_lock(&tp->tx_lock);
> 		if (netif_queue_stopped(tp->dev) &&
>-		    (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
>+		    (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
> 			netif_wake_queue(tp->dev);
>-		netif_tx_unlock(tp->dev);
>+		spin_unlock(&tp->tx_lock);
> 	}
> }
> 
>@@ -3189,10 +3040,11 @@
> 	 * Callers depend upon this behavior and assume that
> 	 * we leave everything unchanged if we fail.
> 	 */
>-	skb = netdev_alloc_skb(tp->dev, skb_size);
>+	skb = dev_alloc_skb(skb_size);
> 	if (skb == NULL)
> 		return -ENOMEM;
> 
>+	skb->dev = tp->dev;
> 	skb_reserve(skb, tp->rx_offset);
> 
> 	mapping = pci_map_single(tp->pdev, skb->data,
>@@ -3285,7 +3137,7 @@
>  */
> static int tg3_rx(struct tg3 *tp, int budget)
> {
>-	u32 work_mask, rx_std_posted = 0;
>+	u32 work_mask;
> 	u32 sw_idx = tp->rx_rcb_ptr;
> 	u16 hw_idx;
> 	int received;
>@@ -3312,7 +3164,6 @@
> 						  mapping);
> 			skb = tp->rx_std_buffers[desc_idx].skb;
> 			post_ptr = &tp->rx_std_ptr;
>-			rx_std_posted++;
> 		} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
> 			dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
> 						  mapping);
>@@ -3338,7 +3189,7 @@
> 
> 		len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
> 
>-		if (len > RX_COPY_THRESHOLD
>+		if (len > RX_COPY_THRESHOLD 
> 			&& tp->rx_offset == 2
> 			/* rx_offset != 2 iff this is a 5701 card running
> 			 * in PCI-X mode [see tg3_get_invariants()] */
>@@ -3361,10 +3212,11 @@
> 			tg3_recycle_rx(tp, opaque_key,
> 				       desc_idx, *post_ptr);
> 
>-			copy_skb = netdev_alloc_skb(tp->dev, len + 2);
>+			copy_skb = dev_alloc_skb(len + 2);
> 			if (copy_skb == NULL)
> 				goto drop_it_no_recycle;
> 
>+			copy_skb->dev = tp->dev;
> 			skb_reserve(copy_skb, 2);
> 			skb_put(copy_skb, len);
> 			pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
>@@ -3399,15 +3251,6 @@
> 
> next_pkt:
> 		(*post_ptr)++;
>-
>-		if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
>-			u32 idx = *post_ptr % TG3_RX_RING_SIZE;
>-
>-			tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
>-				     TG3_64BIT_REG_LOW, idx);
>-			work_mask &= ~RXD_OPAQUE_RING_STD;
>-			rx_std_posted = 0;
>-		}
> next_pkt_nopost:
> 		sw_idx++;
> 		sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
>@@ -3464,11 +3307,6 @@
> 	/* run TX completion thread */
> 	if (sblk->idx[0].tx_consumer != tp->tx_cons) {
> 		tg3_tx(tp);
>-		if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
>-			netif_rx_complete(netdev);
>-			schedule_work(&tp->reset_task);
>-			return 0;
>-		}
> 	}
> 
> 	/* run RX thread, within the bounds set by NAPI.
>@@ -3511,11 +3349,7 @@
> 	tp->irq_sync = 1;
> 	smp_mb();
> 
>-#if (LINUX_VERSION_CODE >= 0x2051c)
> 	synchronize_irq(tp->pdev->irq);
>-#else
>-	synchronize_irq();
>-#endif
> }
> 
> static inline int tg3_irq_sync(struct tg3 *tp)
>@@ -3533,21 +3367,19 @@
> 	if (irq_sync)
> 		tg3_irq_quiesce(tp);
> 	spin_lock_bh(&tp->lock);
>+	spin_lock(&tp->tx_lock);
> }
> 
> static inline void tg3_full_unlock(struct tg3 *tp)
> {
>+	spin_unlock(&tp->tx_lock);
> 	spin_unlock_bh(&tp->lock);
> }
> 
> /* One-shot MSI handler - Chip automatically disables interrupt
>  * after sending MSI so driver doesn't have to do it.
>  */
>-#if (LINUX_VERSION_CODE < 0x20613)
> static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
>-#else
>-static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
>-#endif
> {
> 	struct net_device *dev = dev_id;
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -3565,11 +3397,7 @@
>  * flush status block and interrupt mailbox. PCI ordering rules
>  * guarantee that MSI will arrive after the status block.
>  */
>-#if (LINUX_VERSION_CODE < 0x20613)
> static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
>-#else
>-static irqreturn_t tg3_msi(int irq, void *dev_id)
>-#endif
> {
> 	struct net_device *dev = dev_id;
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -3590,11 +3418,7 @@
> 	return IRQ_RETVAL(1);
> }
> 
>-#if (LINUX_VERSION_CODE < 0x20613)
> static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
>-#else
>-static irqreturn_t tg3_interrupt(int irq, void *dev_id)
>-#endif
> {
> 	struct net_device *dev = dev_id;
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -3637,11 +3461,7 @@
> 	return IRQ_RETVAL(handled);
> }
> 
>-#if (LINUX_VERSION_CODE < 0x20613)
> static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
>-#else
>-static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
>-#endif
> {
> 	struct net_device *dev = dev_id;
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -3684,11 +3504,8 @@
> }
> 
> /* ISR for interrupt test */
>-#if (LINUX_VERSION_CODE < 0x020613)
>-static irqreturn_t tg3_test_isr(int irq, void *dev_id, struct pt_regs *regs)
>-#else
>-static irqreturn_t tg3_test_isr(int irq, void *dev_id)
>-#endif
>+static irqreturn_t tg3_test_isr(int irq, void *dev_id,
>+		struct pt_regs *regs)
> {
> 	struct net_device *dev = dev_id;
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -3696,58 +3513,22 @@
> 
> 	if ((sblk->status & SD_STATUS_UPDATED) ||
> 	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
>-		tg3_disable_ints(tp);
>+		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
>+			     0x00000001);
> 		return IRQ_RETVAL(1);
> 	}
> 	return IRQ_RETVAL(0);
> }
> 
>-static int tg3_init_hw(struct tg3 *, int);
>+static int tg3_init_hw(struct tg3 *);
> static int tg3_halt(struct tg3 *, int, int);
> 
>-/* Restart hardware after configuration changes, self-test, etc.
>- * Invoked with tp->lock held.
>- */
>-static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
>-{
>-	int err;
>-
>-	err = tg3_init_hw(tp, reset_phy);
>-	if (err) {
>-		printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
>-		       "aborting.\n", tp->dev->name);
>-		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>-		tg3_full_unlock(tp);
>-		del_timer_sync(&tp->timer);
>-		tp->irq_sync = 0;
>-		netif_poll_enable(tp->dev);
>-		dev_close(tp->dev);
>-		tg3_full_lock(tp, 0);
>-	}
>-	return err;
>-}
>-
>-#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
>+#ifdef CONFIG_NET_POLL_CONTROLLER
> static void tg3_poll_controller(struct net_device *dev)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 
>-#if defined(RED_HAT_LINUX_KERNEL) && (LINUX_VERSION_CODE < 0x20600)
>-	if (netdump_mode) {
>-		tg3_interrupt(tp->pdev->irq, dev, NULL);
>-		if (dev->poll_list.prev) {
>-			int budget = 64;
>-
>-			tg3_poll(dev, &budget);
>-		}
>-	}
>-	else
>-#endif
>-#if (LINUX_VERSION_CODE < 0x020613)
> 	tg3_interrupt(tp->pdev->irq, dev, NULL);
>-#else
>-	tg3_interrupt(tp->pdev->irq, dev);
>-#endif
> }
> #endif
> 
>@@ -3774,23 +3555,14 @@
> 	restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
> 	tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
> 
>-	if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
>-		tp->write32_tx_mbox = tg3_write32_tx_mbox;
>-		tp->write32_rx_mbox = tg3_write_flush_reg32;
>-		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
>-		tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
>-	}
>-
> 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
>-	if (tg3_init_hw(tp, 1))
>-		goto out;
>+	tg3_init_hw(tp);
> 
> 	tg3_netif_start(tp);
> 
> 	if (restart_timer)
> 		mod_timer(&tp->timer, jiffies + 1);
> 
>-out:
> 	tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
> 
> 	tg3_full_unlock(tp);
>@@ -3800,9 +3572,8 @@
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 
>-	if (netif_msg_tx_err(tp))
>-		printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
>-		       dev->name);
>+	printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
>+	       dev->name);
> 
> 	schedule_work(&tp->reset_task);
> }
>@@ -3821,7 +3592,7 @@
> 					  int len)
> {
> #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
>-	if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
>+	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
> 		return (((u64) mapping + len) > DMA_40BIT_MASK);
> 	return 0;
> #else
>@@ -3923,12 +3694,15 @@
> 
> 	len = skb_headlen(skb);
> 
>-	/* We are running in BH disabled context with netif_tx_lock
>-	 * and TX reclaim runs via tp->poll inside of a software
>+	/* No BH disabling for tx_lock here.  We are running in BH disabled
>+	 * context and TX reclaim runs via tp->poll inside of a software
> 	 * interrupt.  Furthermore, IRQ processing runs lockless so we have
> 	 * no IRQ context deadlocks to worry about either.  Rejoice!
> 	 */
>-	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
>+	if (!spin_trylock(&tp->tx_lock))
>+		return NETDEV_TX_LOCKED;
>+
>+	if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
> 		if (!netif_queue_stopped(dev)) {
> 			netif_stop_queue(dev);
> 
>@@ -3936,6 +3710,7 @@
> 			printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
> 			       "queue awake!\n", dev->name);
> 		}
>+		spin_unlock(&tp->tx_lock);
> 		return NETDEV_TX_BUSY;
> 	}
> 
>@@ -3944,7 +3719,7 @@
> #if TG3_TSO_SUPPORT != 0
> 	mss = 0;
> 	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
>-	    (mss = skb_shinfo(skb)->gso_size) != 0) {
>+	    (mss = skb_shinfo(skb)->tso_size) != 0) {
> 		int tcp_opt_len, ip_tcp_len;
> 
> 		if (skb_header_cloned(skb) &&
>@@ -3953,33 +3728,24 @@
> 			goto out_unlock;
> 		}
> 
>-#ifdef NETIF_F_GSO
>-		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
>-			mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
>-		else
>-#endif
>-		{
>-			tcp_opt_len = ((skb->h.th->doff - 5) * 4);
>-			ip_tcp_len = (skb->nh.iph->ihl * 4) +
>-				     sizeof(struct tcphdr);
>-
>-			skb->nh.iph->check = 0;
>-			skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
>-						     tcp_opt_len);
>-			mss |= (ip_tcp_len + tcp_opt_len) << 9;
>-		}
>+		tcp_opt_len = ((skb->h.th->doff - 5) * 4);
>+		ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
> 
> 		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
> 			       TXD_FLAG_CPU_POST_DMA);
> 
>+		skb->nh.iph->check = 0;
>+		skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
>+
> 		skb->h.th->check = 0;
> 
>+		mss |= (ip_tcp_len + tcp_opt_len) << 9;
> 	}
>-	else if (skb->ip_summed == CHECKSUM_PARTIAL)
>+	else if (skb->ip_summed == CHECKSUM_HW)
> 		base_flags |= TXD_FLAG_TCPUDP_CSUM;
> #else
> 	mss = 0;
>-	if (skb->ip_summed == CHECKSUM_PARTIAL)
>+	if (skb->ip_summed == CHECKSUM_HW)
> 		base_flags |= TXD_FLAG_TCPUDP_CSUM;
> #endif
> #if TG3_VLAN_TAG_USED
>@@ -4023,65 +3789,25 @@
> 		}
> 	}
> 
>-	/* Some platforms need to sync memory here */
>-	wmb();
>-
> 	/* Packets are ready, update Tx producer idx local and on card. */
> 	tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
> 
> 	tp->tx_prod = entry;
>-	if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
>+	if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
> 		netif_stop_queue(dev);
>-		if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
>+		if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
> 			netif_wake_queue(tp->dev);
> 	}
> 
>-#if TG3_TSO_SUPPORT != 0
> out_unlock:
>-#endif
>     	mmiowb();
>+	spin_unlock(&tp->tx_lock);
> 
> 	dev->trans_start = jiffies;
> 
> 	return NETDEV_TX_OK;
> }
> 
>-#if TG3_TSO_SUPPORT != 0
>-#ifdef NETIF_F_GSO
>-static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
>-
>-/* Use GSO to workaround a rare TSO bug that may be triggered when the
>- * TSO header is greater than 80 bytes.
>- */
>-static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
>-{
>-	struct sk_buff *segs, *nskb;
>-
>-	/* Estimate the number of fragments in the worst case */
>-	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
>-		netif_stop_queue(tp->dev);
>-		return NETDEV_TX_BUSY;
>-	}
>-
>-	segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
>-	if (unlikely(IS_ERR(segs)))
>-		goto tg3_tso_bug_end;
>-
>-	do {
>-		nskb = segs;
>-		segs = segs->next;
>-		nskb->next = NULL;
>-		tg3_start_xmit_dma_bug(nskb, tp->dev);
>-	} while (segs);
>-
>-tg3_tso_bug_end:
>-	dev_kfree_skb(skb);
>-
>-	return NETDEV_TX_OK;
>-}
>-#endif
>-#endif
>-
> /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
>  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
>  */
>@@ -4094,12 +3820,15 @@
> 
> 	len = skb_headlen(skb);
> 
>-	/* We are running in BH disabled context with netif_tx_lock
>-	 * and TX reclaim runs via tp->poll inside of a software
>+	/* No BH disabling for tx_lock here.  We are running in BH disabled
>+	 * context and TX reclaim runs via tp->poll inside of a software
> 	 * interrupt.  Furthermore, IRQ processing runs lockless so we have
> 	 * no IRQ context deadlocks to worry about either.  Rejoice!
> 	 */
>-	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
>+	if (!spin_trylock(&tp->tx_lock))
>+		return NETDEV_TX_LOCKED; 
>+
>+	if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
> 		if (!netif_queue_stopped(dev)) {
> 			netif_stop_queue(dev);
> 
>@@ -4107,18 +3836,19 @@
> 			printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
> 			       "queue awake!\n", dev->name);
> 		}
>+		spin_unlock(&tp->tx_lock);
> 		return NETDEV_TX_BUSY;
> 	}
> 
> 	entry = tp->tx_prod;
> 	base_flags = 0;
>-	if (skb->ip_summed == CHECKSUM_PARTIAL)
>+	if (skb->ip_summed == CHECKSUM_HW)
> 		base_flags |= TXD_FLAG_TCPUDP_CSUM;
> #if TG3_TSO_SUPPORT != 0
> 	mss = 0;
> 	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
>-	    (mss = skb_shinfo(skb)->gso_size) != 0) {
>-		int tcp_opt_len, ip_tcp_len, hdr_len;
>+	    (mss = skb_shinfo(skb)->tso_size) != 0) {
>+		int tcp_opt_len, ip_tcp_len;
> 
> 		if (skb_header_cloned(skb) &&
> 		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
>@@ -4129,18 +3859,11 @@
> 		tcp_opt_len = ((skb->h.th->doff - 5) * 4);
> 		ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
> 
>-		hdr_len = ip_tcp_len + tcp_opt_len;
>-#ifdef NETIF_F_GSO
>-		if (unlikely((ETH_HLEN + hdr_len) > 80) &&
>-			     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
>-			return (tg3_tso_bug(tp, skb));
>-#endif
>-
> 		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
> 			       TXD_FLAG_CPU_POST_DMA);
> 
> 		skb->nh.iph->check = 0;
>-		skb->nh.iph->tot_len = htons(mss + hdr_len);
>+		skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
> 		if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
> 			skb->h.th->check = 0;
> 			base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
>@@ -4254,14 +3977,15 @@
> 	tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
> 
> 	tp->tx_prod = entry;
>-	if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
>+	if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
> 		netif_stop_queue(dev);
>-		if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
>+		if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
> 			netif_wake_queue(tp->dev);
> 	}
> 
> out_unlock:
>     	mmiowb();
>+	spin_unlock(&tp->tx_lock);
> 
> 	dev->trans_start = jiffies;
> 
>@@ -4276,9 +4000,7 @@
> 	if (new_mtu > ETH_DATA_LEN) {
> 		if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
> 			tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
>-#if TG3_TSO_SUPPORT != 0
> 			ethtool_op_set_tso(dev, 0);
>-#endif
> 		}
> 		else
> 			tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
>@@ -4292,7 +4014,6 @@
> static int tg3_change_mtu(struct net_device *dev, int new_mtu)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-	int err;
> 
> 	if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
> 		return -EINVAL;
>@@ -4313,14 +4034,13 @@
> 
> 	tg3_set_mtu(dev, tp, new_mtu);
> 
>-	err = tg3_restart_hw(tp, 0);
>+	tg3_init_hw(tp);
> 
>-	if (!err)
>-		tg3_netif_start(tp);
>+	tg3_netif_start(tp);
> 
> 	tg3_full_unlock(tp);
> 
>-	return err;
>+	return 0;
> }
> 
> /* Free up pending packets in all rx/tx rings.
>@@ -4402,7 +4122,7 @@
>  * end up in the driver.  tp->{tx,}lock are held and thus
>  * we may not sleep.
>  */
>-static int tg3_init_rings(struct tg3 *tp)
>+static void tg3_init_rings(struct tg3 *tp)
> {
> 	u32 i;
> 
>@@ -4451,38 +4171,18 @@
> 
> 	/* Now allocate fresh SKBs for each rx ring. */
> 	for (i = 0; i < tp->rx_pending; i++) {
>-		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
>-			printk(KERN_WARNING PFX
>-			       "%s: Using a smaller RX standard ring, "
>-			       "only %d out of %d buffers were allocated "
>-			       "successfully.\n",
>-			       tp->dev->name, i, tp->rx_pending);
>-			if (i == 0)
>-				return -ENOMEM;
>-			tp->rx_pending = i;
>+		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
>+				     -1, i) < 0)
> 			break;
>-		}
> 	}
> 
> 	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
> 		for (i = 0; i < tp->rx_jumbo_pending; i++) {
> 			if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
>-					     -1, i) < 0) {
>-				printk(KERN_WARNING PFX
>-				       "%s: Using a smaller RX jumbo ring, "
>-				       "only %d out of %d buffers were "
>-				       "allocated successfully.\n",
>-				       tp->dev->name, i, tp->rx_jumbo_pending);
>-				if (i == 0) {
>-					tg3_free_rings(tp);
>-					return -ENOMEM;
>-				}
>-				tp->rx_jumbo_pending = i;
>+					     -1, i) < 0)
> 				break;
>-			}
> 		}
> 	}
>-	return 0;
> }
> 
> /*
>@@ -4764,8 +4464,9 @@
> /* tp->lock is held. */
> static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
> {
>-	tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
>-		      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
>+	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
>+		tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
>+			      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
> 
> 	if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
> 		switch (kind) {
>@@ -4837,45 +4538,6 @@
> 	}
> }
> 
>-static int tg3_poll_fw(struct tg3 *tp)
>-{
>-	int i;
>-	u32 val;
>-
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		/* Wait up to 20ms for init done. */
>-		for (i = 0; i < 200; i++) {
>-			if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
>-				return 0;
>-			udelay(100);
>-		}
>-		return -ENODEV;
>-	}
>-
>-	/* Wait for firmware initialization to complete. */
>-	for (i = 0; i < 100000; i++) {
>-		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
>-		if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
>-			break;
>-		udelay(10);
>-	}
>-
>-	/* Chip might not be fitted with firmware.  Some Sun onboard
>-	 * parts are configured like that.  So don't signal the timeout
>-	 * of the above loop as an error, but do report the lack of
>-	 * running firmware once.
>-	 */
>-	if (i >= 100000 &&
>-	    !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
>-		tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
>-
>-		printk(KERN_INFO PFX "%s: No firmware running.\n",
>-		       tp->dev->name);
>-	}
>-
>-	return 0;
>-}
>-
> static void tg3_stop_fw(struct tg3 *);
> 
> /* tp->lock is held. */
>@@ -4883,14 +4545,15 @@
> {
> 	u32 val;
> 	void (*write_op)(struct tg3 *, u32, u32);
>-	int err;
>+	int i;
> 
>-	tg3_nvram_lock(tp);
>-
>-	/* No matching tg3_nvram_unlock() after this because
>-	 * chip reset below will undo the nvram lock.
>-	 */
>-	tp->nvram_lock_cnt = 0;
>+	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
>+		tg3_nvram_lock(tp);
>+		/* No matching tg3_nvram_unlock() after this because
>+		 * chip reset below will undo the nvram lock.
>+		 */
>+		tp->nvram_lock_cnt = 0;
>+	}
> 
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
>@@ -4920,12 +4583,6 @@
> 		}
> 	}
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
>-		tw32(GRC_VCPU_EXT_CTRL,
>-		     tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
>-	}
>-
> 	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
> 		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
> 	tw32(GRC_MISC_CFG, val);
>@@ -4986,11 +4643,7 @@
> 		val |= PCISTATE_RETRY_SAME_DMA;
> 	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
> 
>-#if (LINUX_VERSION_CODE < 0x2060a)
> 	pci_restore_state(tp->pdev, tp->pci_cfg_state);
>-#else
>-	pci_restore_state(tp->pdev);
>-#endif
> 
> 	/* Make sure PCI-X relaxed ordering bit is clear. */
> 	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
>@@ -5053,9 +4706,21 @@
> 		tw32_f(MAC_MODE, 0);
> 	udelay(40);
> 
>-	err = tg3_poll_fw(tp);
>-	if (err)
>-		return err;
>+	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
>+		/* Wait for firmware initialization to complete. */
>+		for (i = 0; i < 100000; i++) {
>+			tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
>+			if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
>+				break;
>+			udelay(10);
>+		}
>+		if (i >= 100000) {
>+			printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
>+			       "firmware will not restart magic=%08x\n",
>+			       tp->dev->name, val);
>+			return -ENODEV;
>+		}
>+	}
> 
> 	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
> 	    tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
>@@ -5139,7 +4804,7 @@
> #define TG3_FW_BSS_ADDR		0x08000a70
> #define TG3_FW_BSS_LEN		0x10
> 
>-static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
>+static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
> 	0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
> 	0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
> 	0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
>@@ -5233,7 +4898,7 @@
> 	0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
> };
> 
>-static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
>+static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
> 	0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
> 	0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
> 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
>@@ -5258,15 +4923,10 @@
> {
> 	int i;
> 
>-	BUG_ON(offset == TX_CPU_BASE &&
>-	    (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
>+	if (offset == TX_CPU_BASE &&
>+	    (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
>+		BUG();
> 
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		u32 val = tr32(GRC_VCPU_EXT_CTRL);
>-
>-		tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
>-		return 0;
>-	}
> 	if (offset == RX_CPU_BASE) {
> 		for (i = 0; i < 10000; i++) {
> 			tw32(offset + CPU_STATE, 0xffffffff);
>@@ -5304,13 +4964,13 @@
> struct fw_info {
> 	unsigned int text_base;
> 	unsigned int text_len;
>-	const u32 *text_data;
>+	u32 *text_data;
> 	unsigned int rodata_base;
> 	unsigned int rodata_len;
>-	const u32 *rodata_data;
>+	u32 *rodata_data;
> 	unsigned int data_base;
> 	unsigned int data_len;
>-	const u32 *data_data;
>+	u32 *data_data;
> };
> 
> /* tp->lock is held. */
>@@ -5442,7 +5102,7 @@
> #define TG3_TSO_FW_BSS_ADDR		0x08001b80
> #define TG3_TSO_FW_BSS_LEN		0x894
> 
>-static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
>+static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
> 	0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
> 	0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
> 	0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
>@@ -5729,7 +5389,7 @@
> 	0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
> };
> 
>-static const u32 tg3TsoFwRodata[] = {
>+static u32 tg3TsoFwRodata[] = {
> 	0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
> 	0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
> 	0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
>@@ -5737,7 +5397,7 @@
> 	0x00000000,
> };
> 
>-static const u32 tg3TsoFwData[] = {
>+static u32 tg3TsoFwData[] = {
> 	0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
> 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
> 	0x00000000,
>@@ -5759,7 +5419,7 @@
> #define TG3_TSO5_FW_BSS_ADDR		0x00010f50
> #define TG3_TSO5_FW_BSS_LEN		0x88
> 
>-static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
>+static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
> 	0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
> 	0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
> 	0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
>@@ -5918,14 +5578,14 @@
> 	0x00000000, 0x00000000, 0x00000000,
> };
> 
>-static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
>+static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
> 	0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
> 	0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
> 	0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
> 	0x00000000, 0x00000000, 0x00000000,
> };
> 
>-static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
>+static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
> 	0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
> 	0x00000000, 0x00000000, 0x00000000,
> };
>@@ -6043,7 +5703,6 @@
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 	struct sockaddr *addr = p;
>-	int err = 0;
> 
> 	if (!is_valid_ether_addr(addr->sa_data))
> 		return -EINVAL;
>@@ -6053,25 +5712,11 @@
> 	if (!netif_running(dev))
> 		return 0;
> 
>-	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
>-		/* Reset chip so that ASF can re-init any MAC addresses it
>-		 * needs.
>-		 */
>-		tg3_netif_stop(tp);
>-		tg3_full_lock(tp, 1);
>-
>-		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>-		err = tg3_restart_hw(tp, 0);
>-		if (!err)
>-			tg3_netif_start(tp);
>-		tg3_full_unlock(tp);
>-	} else {
>-		spin_lock_bh(&tp->lock);
>-		__tg3_set_mac_addr(tp);
>-		spin_unlock_bh(&tp->lock);
>-	}
>+	spin_lock_bh(&tp->lock);
>+	__tg3_set_mac_addr(tp);
>+	spin_unlock_bh(&tp->lock);
> 
>-	return err;
>+	return 0;
> }
> 
> /* tp->lock is held. */
>@@ -6119,7 +5764,7 @@
> }
> 
> /* tp->lock is held. */
>-static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
>+static int tg3_reset_hw(struct tg3 *tp)
> {
> 	u32 val, rdmac_mode;
> 	int i, err, limit;
>@@ -6134,7 +5779,7 @@
> 		tg3_abort_hw(tp, 1);
> 	}
> 
>-	if (reset_phy)
>+	if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
> 		tg3_phy_reset(tp);
> 
> 	err = tg3_chip_reset(tp);
>@@ -6171,9 +5816,7 @@
> 	 * can only do this after the hardware has been
> 	 * successfully reset.
> 	 */
>-	err = tg3_init_rings(tp);
>-	if (err)
>-		return err;
>+	tg3_init_rings(tp);
> 
> 	/* This value is determined during the probe time DMA
> 	 * engine test, tg3_test_dma.
>@@ -6185,14 +5828,10 @@
> 			  GRC_MODE_NO_TX_PHDR_CSUM |
> 			  GRC_MODE_NO_RX_PHDR_CSUM);
> 	tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
>-
>-	/* Pseudo-header checksum is done by hardware logic and not
>-	 * the offload processers, so make the chip do the pseudo-
>-	 * header checksums on receive.  For transmit it is more
>-	 * convenient to do the pseudo-header checksum in software
>-	 * as Linux does that on transmit for us in all cases.
>-	 */
>-	tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
>+	if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
>+		tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
>+	if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
>+		tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
> 
> 	tw32(GRC_MODE,
> 	     tp->grc_mode |
>@@ -6266,20 +5905,7 @@
> 	}
> 
> 	/* Setup replenish threshold. */
>-	val = tp->rx_pending / 8;
>-	if (val == 0)
>-		val = 1;
>-	else if (val > tp->rx_std_max_post)
>-		val = tp->rx_std_max_post;
>-	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
>-			tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
>-
>-		if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
>-			val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
>-	}
>-
>-	tw32(RCVBDI_STD_THRESH, val);
>+	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
> 
> 	/* Initialize TG3_BDINFO's at:
> 	 *  RCVDBDI_STD_BD:	standard eth size rx ring
>@@ -6439,12 +6065,8 @@
> #endif
> 
> 	/* Receive/send statistics. */
>-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
>-		val = tr32(RCVLPC_STATS_ENABLE);
>-		val &= ~RCVLPC_STATSENAB_DACK_FIX;
>-		tw32(RCVLPC_STATS_ENABLE, val);
>-	} else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
>-		   (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
>+	if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
>+	    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
> 		val = tr32(RCVLPC_STATS_ENABLE);
> 		val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
> 		tw32(RCVLPC_STATS_ENABLE, val);
>@@ -6515,17 +6137,16 @@
> 	udelay(40);
> 
> 	/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
>-	 * If TG3_FLG2_IS_NIC is zero, we should read the
>+	 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
> 	 * register to preserve the GPIO settings for LOMs. The GPIOs,
> 	 * whether used as inputs or outputs, are set by boot code after
> 	 * reset.
> 	 */
>-	if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
>+	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
> 		u32 gpio_mask;
> 
>-		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
>-			    GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
>-			    GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
>+		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
>+			    GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
> 
> 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
> 			gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
>@@ -6537,9 +6158,8 @@
> 		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
> 
> 		/* GPIO1 must be driven high for eeprom write protect */
>-		if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
>-			tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
>-					       GRC_LCLCTRL_GPIO_OUTPUT1);
>+		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
>+				       GRC_LCLCTRL_GPIO_OUTPUT1);
> 	}
> 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
> 	udelay(100);
>@@ -6696,18 +6316,16 @@
> 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
> 	}
> 
>-	err = tg3_setup_phy(tp, 0);
>+	err = tg3_setup_phy(tp, 1);
> 	if (err)
> 		return err;
> 
>-	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
>+	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
> 		u32 tmp;
> 
> 		/* Clear CRC stats. */
>-		if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
>-			tg3_writephy(tp, MII_TG3_TEST1,
>-				     tmp | MII_TG3_TEST1_CRC_EN);
>+		if (!tg3_readphy(tp, 0x1e, &tmp)) {
>+			tg3_writephy(tp, 0x1e, tmp | 0x8000);
> 			tg3_readphy(tp, 0x14, &tmp);
> 		}
> 	}
>@@ -6771,7 +6389,7 @@
> /* Called at device open time to get the chip ready for
>  * packet processing.  Invoked with tp->lock held.
>  */
>-static int tg3_init_hw(struct tg3 *tp, int reset_phy)
>+static int tg3_init_hw(struct tg3 *tp)
> {
> 	int err;
> 
>@@ -6784,7 +6402,7 @@
> 
> 	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
> 
>-	err = tg3_reset_hw(tp, reset_phy);
>+	err = tg3_reset_hw(tp);
> 
> out:
> 	return err;
>@@ -6832,19 +6450,12 @@
> 	TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
> 	TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
> 	TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
>-
>-	TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
>-	TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
>-	TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
> }
> 
> static void tg3_timer(unsigned long __opaque)
> {
> 	struct tg3 *tp = (struct tg3 *) __opaque;
> 
>-	if (tp->irq_sync)
>-		goto restart_timer;
>-
> 	spin_lock(&tp->lock);
> 
> 	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
>@@ -6902,14 +6513,12 @@
> 				need_setup = 1;
> 			}
> 			if (need_setup) {
>-				if (!tp->serdes_counter) {
>-					tw32_f(MAC_MODE,
>-					     (tp->mac_mode &
>-					      ~MAC_MODE_PORT_MODE_MASK));
>-					udelay(40);
>-					tw32_f(MAC_MODE, tp->mac_mode);
>-					udelay(40);
>-				}
>+				tw32_f(MAC_MODE,
>+				     (tp->mac_mode &
>+				      ~MAC_MODE_PORT_MODE_MASK));
>+				udelay(40);
>+				tw32_f(MAC_MODE, tp->mac_mode);
>+				udelay(40);
> 				tg3_setup_phy(tp, 0);
> 			}
> 		} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
>@@ -6918,32 +6527,16 @@
> 		tp->timer_counter = tp->timer_multiplier;
> 	}
> 
>-	/* Heartbeat is only sent once every 2 seconds.
>-	 *
>-	 * The heartbeat is to tell the ASF firmware that the host
>-	 * driver is still alive.  In the event that the OS crashes,
>-	 * ASF needs to reset the hardware to free up the FIFO space
>-	 * that may be filled with rx packets destined for the host.
>-	 * If the FIFO is full, ASF will no longer function properly.
>-	 *
>-	 * Unintended resets have been reported on real time kernels
>-	 * where the timer doesn't run on time.  Netpoll will also have
>-	 * same problem.
>-	 *
>-	 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
>-	 * to check the ring condition when the heartbeat is expiring
>-	 * before doing the reset.  This will prevent most unintended
>-	 * resets.
>-	 */
>+	/* Heartbeat is only sent once every 2 seconds.  */
> 	if (!--tp->asf_counter) {
> 		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
> 			u32 val;
> 
>-			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
>-				      FWCMD_NICDRV_ALIVE3);
>-			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
>+			tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
>+					   FWCMD_NICDRV_ALIVE2);
>+			tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
> 			/* 5 seconds timeout */
>-			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
>+			tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
> 			val = tr32(GRC_RX_CPU_EVENT);
> 			val |= (1 << 14);
> 			tw32(GRC_RX_CPU_EVENT, val);
>@@ -6953,18 +6546,13 @@
> 
> 	spin_unlock(&tp->lock);
> 
>-restart_timer:
> 	tp->timer.expires = jiffies + tp->timer_offset;
> 	add_timer(&tp->timer);
> }
> 
>-static int tg3_request_irq(struct tg3 *tp)
>+int tg3_request_irq(struct tg3 *tp)
> {
>-#if (LINUX_VERSION_CODE < 0x020613)
> 	irqreturn_t (*fn)(int, void *, struct pt_regs *);
>-#else
>-	irq_handler_t fn;
>-#endif
> 	unsigned long flags;
> 	struct net_device *dev = tp->dev;
> 
>@@ -6972,12 +6560,12 @@
> 		fn = tg3_msi;
> 		if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
> 			fn = tg3_msi_1shot;
>-		flags = IRQF_SAMPLE_RANDOM;
>+		flags = SA_SAMPLE_RANDOM;
> 	} else {
> 		fn = tg3_interrupt;
> 		if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
> 			fn = tg3_interrupt_tagged;
>-		flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
>+		flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
> 	}
> 	return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
> }
>@@ -6985,7 +6573,8 @@
> static int tg3_test_interrupt(struct tg3 *tp)
> {
> 	struct net_device *dev = tp->dev;
>-	int err, i, intr_ok = 0;
>+	int err, i;
>+	u32 int_mbox = 0;
> 
> 	if (!netif_running(dev))
> 		return -ENODEV;
>@@ -6995,7 +6584,7 @@
> 	free_irq(tp->pdev->irq, dev);
> 
> 	err = request_irq(tp->pdev->irq, tg3_test_isr,
>-			  IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
>+			  SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
> 	if (err)
> 		return err;
> 
>@@ -7006,36 +6595,23 @@
> 	       HOSTCC_MODE_NOW);
> 
> 	for (i = 0; i < 5; i++) {
>-		u32 int_mbox, misc_host_ctrl;
>-
> 		int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
> 					TG3_64BIT_REG_LOW);
>-		misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
>-
>-		if ((int_mbox != 0) ||
>-		    (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
>-			intr_ok = 1;
>+		if (int_mbox != 0)
> 			break;
>-		}
>-
>-#if (LINUX_VERSION_CODE < 0x20607)
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(10);
>-#else
> 		msleep(10);
>-#endif
> 	}
> 
> 	tg3_disable_ints(tp);
> 
> 	free_irq(tp->pdev->irq, dev);
>-
>+	
> 	err = tg3_request_irq(tp);
> 
> 	if (err)
> 		return err;
> 
>-	if (intr_ok)
>+	if (int_mbox != 0)
> 		return 0;
> 
> 	return -EIO;
>@@ -7078,9 +6654,7 @@
> 		       tp->dev->name);
> 
> 	free_irq(tp->pdev->irq, dev);
>-#ifdef CONFIG_PCI_MSI
> 	pci_disable_msi(tp->pdev);
>-#endif
> 
> 	tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
> 
>@@ -7094,7 +6668,7 @@
> 	tg3_full_lock(tp, 1);
> 
> 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>-	err = tg3_init_hw(tp, 1);
>+	err = tg3_init_hw(tp);
> 
> 	tg3_full_unlock(tp);
> 
>@@ -7109,15 +6683,11 @@
> 	struct tg3 *tp = netdev_priv(dev);
> 	int err;
> 
>-	netif_carrier_off(tp->dev);
>-
> 	tg3_full_lock(tp, 0);
> 
> 	err = tg3_set_power_state(tp, PCI_D0);
>-	if (err) {
>-		tg3_full_unlock(tp);
>+	if (err)
> 		return err;
>-	}
> 
> 	tg3_disable_ints(tp);
> 	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
>@@ -7131,7 +6701,6 @@
> 	if (err)
> 		return err;
> 
>-#ifdef CONFIG_PCI_MSI
> 	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
> 	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
> 	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
>@@ -7151,14 +6720,11 @@
> 			tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
> 		}
> 	}
>-#endif
> 	err = tg3_request_irq(tp);
> 
> 	if (err) {
> 		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
>-#ifdef CONFIG_PCI_MSI
> 			pci_disable_msi(tp->pdev);
>-#endif
> 			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
> 		}
> 		tg3_free_consistent(tp);
>@@ -7167,7 +6733,7 @@
> 
> 	tg3_full_lock(tp, 0);
> 
>-	err = tg3_init_hw(tp, 1);
>+	err = tg3_init_hw(tp);
> 	if (err) {
> 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
> 		tg3_free_rings(tp);
>@@ -7194,9 +6760,7 @@
> 	if (err) {
> 		free_irq(tp->pdev->irq, dev);
> 		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
>-#ifdef CONFIG_PCI_MSI
> 			pci_disable_msi(tp->pdev);
>-#endif
> 			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
> 		}
> 		tg3_free_consistent(tp);
>@@ -7210,9 +6774,7 @@
> 			tg3_full_lock(tp, 0);
> 
> 			if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
>-#ifdef CONFIG_PCI_MSI
> 				pci_disable_msi(tp->pdev);
>-#endif
> 				tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
> 			}
> 			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>@@ -7226,10 +6788,9 @@
> 
> 		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
> 			if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
>-				u32 val = tr32(PCIE_TRANSACTION_CFG);
>+				u32 val = tr32(0x7c04);
> 
>-				tw32(PCIE_TRANSACTION_CFG,
>-				     val | PCIE_TRANS_CFG_1SHOT_MSI);
>+				tw32(0x7c04, val | (1 << 29));
> 			}
> 		}
> 	}
>@@ -7486,14 +7047,8 @@
> 	 * linkwatch_event() may be on the workqueue and it will try to get
> 	 * the rtnl_lock which we are holding.
> 	 */
>-	while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK) {
>-#if (LINUX_VERSION_CODE < 0x20607)
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(1);
>-#else
>+	while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
> 		msleep(1);
>-#endif
>-	}
> 
> 	netif_stop_queue(dev);
> 
>@@ -7516,9 +7071,7 @@
> 
> 	free_irq(tp->pdev->irq, dev);
> 	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
>-#ifdef CONFIG_PCI_MSI
> 		pci_disable_msi(tp->pdev);
>-#endif
> 		tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
> 	}
> 
>@@ -7558,9 +7111,8 @@
> 		u32 val;
> 
> 		spin_lock_bh(&tp->lock);
>-		if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
>-			tg3_writephy(tp, MII_TG3_TEST1,
>-				     val | MII_TG3_TEST1_CRC_EN);
>+		if (!tg3_readphy(tp, 0x1e, &val)) {
>+			tg3_writephy(tp, 0x1e, val | 0x8000);
> 			tg3_readphy(tp, 0x14, &val);
> 		} else
> 			val = 0;
>@@ -7680,7 +7232,7 @@
> 		get_stat64(&hw_stats->rx_ucast_packets) +
> 		get_stat64(&hw_stats->rx_mcast_packets) +
> 		get_stat64(&hw_stats->rx_bcast_packets);
>-
>+		
> 	stats->tx_packets = old_stats->tx_packets +
> 		get_stat64(&hw_stats->tx_ucast_packets) +
> 		get_stat64(&hw_stats->tx_mcast_packets) +
>@@ -7916,19 +7468,16 @@
> 	tg3_full_unlock(tp);
> }
> 
>-#if (LINUX_VERSION_CODE >= 0x20418)
> static int tg3_get_eeprom_len(struct net_device *dev)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 
> 	return tp->nvram_size;
> }
>-#endif
> 
> static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
> static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
> 
>-#ifdef ETHTOOL_GEEPROM
> static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -7990,11 +7539,9 @@
> 	}
> 	return 0;
> }
>-#endif
> 
>-static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
>+static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); 
> 
>-#ifdef ETHTOOL_SEEPROM
> static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -8053,35 +7600,32 @@
> 
> 	return ret;
> }
>-#endif
> 
> static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
> {
>   	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	cmd->supported = (SUPPORTED_Autoneg);
> 
> 	if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
> 		cmd->supported |= (SUPPORTED_1000baseT_Half |
> 				   SUPPORTED_1000baseT_Full);
> 
>-	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
>+	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
> 		cmd->supported |= (SUPPORTED_100baseT_Half |
> 				  SUPPORTED_100baseT_Full |
> 				  SUPPORTED_10baseT_Half |
> 				  SUPPORTED_10baseT_Full |
> 				  SUPPORTED_MII);
>-		cmd->port = PORT_TP;
>-	} else {
>+	else
> 		cmd->supported |= SUPPORTED_FIBRE;
>-		cmd->port = PORT_FIBRE;
>-	}
>-
>+  
> 	cmd->advertising = tp->link_config.advertising;
> 	if (netif_running(dev)) {
> 		cmd->speed = tp->link_config.active_speed;
> 		cmd->duplex = tp->link_config.active_duplex;
> 	}
>+	cmd->port = 0;
> 	cmd->phy_address = PHY_ADDR;
> 	cmd->transceiver = 0;
> 	cmd->autoneg = tp->link_config.autoneg;
>@@ -8089,12 +7633,12 @@
> 	cmd->maxrxpkt = 0;
> 	return 0;
> }
>-
>+  
> static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>-	if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
>+  
>+	if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { 
> 		/* These are the only valid advertisement bits allowed.  */
> 		if (cmd->autoneg == AUTONEG_ENABLE &&
> 		    (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
>@@ -8126,73 +7670,69 @@
> 		tp->link_config.speed = cmd->speed;
> 		tp->link_config.duplex = cmd->duplex;
>   	}
>-
>-	tp->link_config.orig_speed = tp->link_config.speed;
>-	tp->link_config.orig_duplex = tp->link_config.duplex;
>-	tp->link_config.orig_autoneg = tp->link_config.autoneg;
>-
>+  
> 	if (netif_running(dev))
> 		tg3_setup_phy(tp, 1);
> 
> 	tg3_full_unlock(tp);
>-
>+  
> 	return 0;
> }
>-
>+  
> static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	strcpy(info->driver, DRV_MODULE_NAME);
> 	strcpy(info->version, DRV_MODULE_VERSION);
> 	strcpy(info->fw_version, tp->fw_ver);
> 	strcpy(info->bus_info, pci_name(tp->pdev));
> }
>-
>+  
> static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	wol->supported = WAKE_MAGIC;
> 	wol->wolopts = 0;
> 	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
> 		wol->wolopts = WAKE_MAGIC;
> 	memset(&wol->sopass, 0, sizeof(wol->sopass));
> }
>-
>+  
> static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	if (wol->wolopts & ~WAKE_MAGIC)
> 		return -EINVAL;
> 	if ((wol->wolopts & WAKE_MAGIC) &&
>-	    tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
>+	    tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
> 	    !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
> 		return -EINVAL;
>-
>+  
> 	spin_lock_bh(&tp->lock);
> 	if (wol->wolopts & WAKE_MAGIC)
> 		tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
> 	else
> 		tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
> 	spin_unlock_bh(&tp->lock);
>-
>+  
> 	return 0;
> }
>-
>+  
> static u32 tg3_get_msglevel(struct net_device *dev)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 	return tp->msg_enable;
> }
>-
>+  
> static void tg3_set_msglevel(struct net_device *dev, u32 value)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 	tp->msg_enable = value;
> }
>-
>+  
> #if TG3_TSO_SUPPORT != 0
> static int tg3_set_tso(struct net_device *dev, u32 value)
> {
>@@ -8203,23 +7743,16 @@
> 			return -EINVAL;
> 		return 0;
> 	}
>-	if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
>-	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
>-		if (value)
>-			dev->features |= NETIF_F_TSO6;
>-		else
>-			dev->features &= ~NETIF_F_TSO6;
>-	}
> 	return ethtool_op_set_tso(dev, value);
> }
> #endif
>-
>+  
> static int tg3_nway_reset(struct net_device *dev)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 	u32 bmcr;
> 	int r;
>-
>+  
> 	if (!netif_running(dev))
> 		return -EAGAIN;
> 
>@@ -8237,14 +7770,14 @@
> 		r = 0;
> 	}
> 	spin_unlock_bh(&tp->lock);
>-
>+  
> 	return r;
> }
>-
>+  
> static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
> 	ering->rx_mini_max_pending = 0;
> 	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
>@@ -8263,27 +7796,24 @@
> 
> 	ering->tx_pending = tp->tx_pending;
> }
>-
>+  
> static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-	int irq_sync = 0, err = 0;
>-
>+	int irq_sync = 0;
>+  
> 	if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
> 	    (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
>-	    (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
>-	    (ering->tx_pending <= MAX_SKB_FRAGS) ||
>-	    ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
>-	     (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
>+	    (ering->tx_pending > TG3_TX_RING_SIZE - 1))
> 		return -EINVAL;
>-
>+  
> 	if (netif_running(dev)) {
> 		tg3_netif_stop(tp);
> 		irq_sync = 1;
> 	}
> 
> 	tg3_full_lock(tp, irq_sync);
>-
>+  
> 	tp->rx_pending = ering->rx_pending;
> 
> 	if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
>@@ -8294,30 +7824,29 @@
> 
> 	if (netif_running(dev)) {
> 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>-		err = tg3_restart_hw(tp, 1);
>-		if (!err)
>-			tg3_netif_start(tp);
>+		tg3_init_hw(tp);
>+		tg3_netif_start(tp);
> 	}
> 
> 	tg3_full_unlock(tp);
>-
>-	return err;
>+  
>+	return 0;
> }
>-
>+  
> static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
> 	epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
> 	epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
> }
>-
>+  
> static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-	int irq_sync = 0, err = 0;
>-
>+	int irq_sync = 0;
>+  
> 	if (netif_running(dev)) {
> 		tg3_netif_stop(tp);
> 		irq_sync = 1;
>@@ -8340,66 +7869,59 @@
> 
> 	if (netif_running(dev)) {
> 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
>-		err = tg3_restart_hw(tp, 1);
>-		if (!err)
>-			tg3_netif_start(tp);
>+		tg3_init_hw(tp);
>+		tg3_netif_start(tp);
> 	}
> 
> 	tg3_full_unlock(tp);
>-
>-	return err;
>+  
>+	return 0;
> }
>-
>+  
> static u32 tg3_get_rx_csum(struct net_device *dev)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 	return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
> }
>-
>+  
> static int tg3_set_rx_csum(struct net_device *dev, u32 data)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
> 		if (data != 0)
> 			return -EINVAL;
>   		return 0;
>   	}
>-
>+  
> 	spin_lock_bh(&tp->lock);
> 	if (data)
> 		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
> 	else
> 		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
> 	spin_unlock_bh(&tp->lock);
>-
>+  
> 	return 0;
> }
>-
>-#if (LINUX_VERSION_CODE >= 0x20418)
>+  
> static int tg3_set_tx_csum(struct net_device *dev, u32 data)
> {
> 	struct tg3 *tp = netdev_priv(dev);
>-
>+  
> 	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
> 		if (data != 0)
> 			return -EINVAL;
>   		return 0;
>   	}
>-
>+  
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
>-#if (LINUX_VERSION_CODE >= 0x20418) && (LINUX_VERSION_CODE < 0x2060c)
>-		tg3_set_tx_hw_csum(dev, data);
>-#else
> 		ethtool_op_set_tx_hw_csum(dev, data);
>-#endif
> 	else
> 		ethtool_op_set_tx_csum(dev, data);
> 
> 	return 0;
> }
>-#endif
> 
> static int tg3_get_stats_count (struct net_device *dev)
> {
>@@ -8446,16 +7968,12 @@
> 					   LED_CTRL_TRAFFIC_OVERRIDE |
> 					   LED_CTRL_TRAFFIC_BLINK |
> 					   LED_CTRL_TRAFFIC_LED);
>-
>+	
> 		else
> 			tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
> 					   LED_CTRL_TRAFFIC_OVERRIDE);
>-#if (LINUX_VERSION_CODE < 0x20607)
>-		set_current_state(TASK_INTERRUPTIBLE);
>-		if (schedule_timeout(HZ / 2))
>-#else
>+
> 		if (msleep_interruptible(500))
>-#endif
> 			break;
> 	}
> 	tw32(MAC_LED_CTRL, tp->led_ctrl);
>@@ -8471,8 +7989,6 @@
> 
> #define NVRAM_TEST_SIZE 0x100
> #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
>-#define NVRAM_SELFBOOT_HW_SIZE 0x20
>-#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
> 
> static int tg3_test_nvram(struct tg3 *tp)
> {
>@@ -8484,14 +8000,12 @@
> 
> 	if (magic == TG3_EEPROM_MAGIC)
> 		size = NVRAM_TEST_SIZE;
>-	else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
>+	else if ((magic & 0xff000000) == 0xa5000000) {
> 		if ((magic & 0xe00000) == 0x200000)
> 			size = NVRAM_SELFBOOT_FORMAT1_SIZE;
> 		else
> 			return 0;
>-	} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
>-		size = NVRAM_SELFBOOT_HW_SIZE;
>-	else
>+	} else
> 		return -EIO;
> 
> 	buf = kmalloc(size, GFP_KERNEL);
>@@ -8510,65 +8024,15 @@
> 		goto out;
> 
> 	/* Selfboot format */
>-	if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
>-	    TG3_EEPROM_MAGIC_FW) {
>+	if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
> 		u8 *buf8 = (u8 *) buf, csum8 = 0;
> 
> 		for (i = 0; i < size; i++)
> 			csum8 += buf8[i];
> 
>-		if (csum8 == 0) {
>-			err = 0;
>-			goto out;
>-		}
>-
>-		err = -EIO;
>-		goto out;
>-	}
>-
>-	if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
>-	    TG3_EEPROM_MAGIC_HW) {
>-		u8 data[NVRAM_SELFBOOT_DATA_SIZE];
>-	       	u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
>-		u8 *buf8 = (u8 *) buf;
>-		int j, k;
>-
>-		/* Separate the parity bits and the data bytes.  */
>-		for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
>-			if ((i == 0) || (i == 8)) {
>-				int l;
>-				u8 msk;
>-
>-				for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
>-					parity[k++] = buf8[i] & msk;
>-				i++;
>-			}
>-			else if (i == 16) {
>-				int l;
>-				u8 msk;
>-
>-				for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
>-					parity[k++] = buf8[i] & msk;
>-				i++;
>-
>-				for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
>-					parity[k++] = buf8[i] & msk;
>-				i++;
>-			}
>-			data[j++] = buf8[i];
>-		}
>-
>-		err = -EIO;
>-		for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
>-			u8 hw8 = hweight8(data[i]);
>-
>-			if ((hw8 & 0x1) && parity[i])
>-				goto out;
>-			else if (!(hw8 & 0x1) && !parity[i])
>-				goto out;
>-		}
>-		err = 0;
>-		goto out;
>+		if (csum8 == 0)
>+			return 0;
>+		return -EIO;
> 	}
> 
> 	/* Bootstrap checksum at offset 0x10 */
>@@ -8589,7 +8053,7 @@
> }
> 
> #define TG3_SERDES_TIMEOUT_SEC	2
>-#define TG3_COPPER_TIMEOUT_SEC	7
>+#define TG3_COPPER_TIMEOUT_SEC	6
> 
> static int tg3_test_link(struct tg3 *tp)
> {
>@@ -8607,12 +8071,7 @@
> 		if (netif_carrier_ok(tp->dev))
> 			return 0;
> 
>-#if (LINUX_VERSION_CODE < 0x20607)
>-		set_current_state(TASK_INTERRUPTIBLE);
>-		if (schedule_timeout(HZ))
>-#else
> 		if (msleep_interruptible(1000))
>-#endif
> 			break;
> 	}
> 
>@@ -8622,7 +8081,7 @@
> /* Only test the commonly used registers */
> static int tg3_test_registers(struct tg3 *tp)
> {
>-	int i, is_5705, is_5750;
>+	int i, is_5705;
> 	u32 offset, read_mask, write_mask, val, save_val, read_val;
> 	static struct {
> 		u16 offset;
>@@ -8630,7 +8089,6 @@
> #define TG3_FL_5705	0x1
> #define TG3_FL_NOT_5705	0x2
> #define TG3_FL_NOT_5788	0x4
>-#define TG3_FL_NOT_5750	0x8
> 		u32 read_mask;
> 		u32 write_mask;
> 	} reg_tbl[] = {
>@@ -8683,7 +8141,7 @@
> 			0x00000000, 0xffff0002 },
> 		{ RCVDBDI_STD_BD+0xc, 0x0000,
> 			0x00000000, 0xffffffff },
>-
>+	
> 		/* Receive BD Initiator Control Registers. */
> 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
> 			0x00000000, 0xffffffff },
>@@ -8691,7 +8149,7 @@
> 			0x00000000, 0x000003ff },
> 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
> 			0x00000000, 0xffffffff },
>-
>+	
> 		/* Host Coalescing Control Registers. */
> 		{ HOSTCC_MODE, TG3_FL_NOT_5705,
> 			0x00000000, 0x00000004 },
>@@ -8741,9 +8199,9 @@
> 			0xffffffff, 0x00000000 },
> 
> 		/* Buffer Manager Control Registers. */
>-		{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
>+		{ BUFMGR_MB_POOL_ADDR, 0x0000,
> 			0x00000000, 0x007fff80 },
>-		{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
>+		{ BUFMGR_MB_POOL_SIZE, 0x0000,
> 			0x00000000, 0x007fffff },
> 		{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
> 			0x00000000, 0x0000003f },
>@@ -8755,7 +8213,7 @@
> 			0xffffffff, 0x00000000 },
> 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
> 			0xffffffff, 0x00000000 },
>-
>+	
> 		/* Mailbox Registers */
> 		{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
> 			0x00000000, 0x000001ff },
>@@ -8769,12 +8227,10 @@
> 		{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
> 	};
> 
>-	is_5705 = is_5750 = 0;
>-	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
>+	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
> 		is_5705 = 1;
>-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
>-			is_5750 = 1;
>-	}
>+	else
>+		is_5705 = 0;
> 
> 	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
> 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
>@@ -8787,9 +8243,6 @@
> 		    (reg_tbl[i].flags & TG3_FL_NOT_5788))
> 			continue;
> 
>-		if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
>-			continue;
>-
> 		offset = (u32) reg_tbl[i].offset;
> 		read_mask = reg_tbl[i].read_mask;
> 		write_mask = reg_tbl[i].write_mask;
>@@ -8833,16 +8286,14 @@
> 	return 0;
> 
> out:
>-	if (netif_msg_hw(tp))
>-		printk(KERN_ERR PFX "Register test failed at offset %x\n",
>-		       offset);
>+	printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
> 	tw32(offset, save_val);
> 	return -EIO;
> }
> 
> static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
> {
>-	static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
>+	static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
> 	int i;
> 	u32 j;
> 
>@@ -8883,13 +8334,6 @@
> 		{ 0x00008000, 0x02000},
> 		{ 0x00010000, 0x0c000},
> 		{ 0xffffffff, 0x00000}
>-	}, mem_tbl_5906[] = {
>-		{ 0x00000200, 0x00008},
>-		{ 0x00004000, 0x00400},
>-		{ 0x00006000, 0x00400},
>-		{ 0x00008000, 0x01000},
>-		{ 0x00010000, 0x01000},
>-		{ 0xffffffff, 0x00000}
> 	};
> 	struct mem_entry *mem_tbl;
> 	int err = 0;
>@@ -8899,8 +8343,6 @@
> 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
> 		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
> 			mem_tbl = mem_tbl_5755;
>-		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>-			mem_tbl = mem_tbl_5906;
> 		else
> 			mem_tbl = mem_tbl_5705;
> 	} else
>@@ -8911,7 +8353,7 @@
> 		    mem_tbl[i].len)) != 0)
> 			break;
> 	}
>-
>+	
> 	return err;
> }
> 
>@@ -8937,55 +8379,23 @@
> 			return 0;
> 
> 		mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
>-			   MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
>-		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
>-			mac_mode |= MAC_MODE_PORT_MODE_MII;
>-		else
>-			mac_mode |= MAC_MODE_PORT_MODE_GMII;
>+			   MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
>+			   MAC_MODE_PORT_MODE_GMII;
> 		tw32(MAC_MODE, mac_mode);
> 	} else if (loopback_mode == TG3_PHY_LOOPBACK) {
>-		u32 val;
>-
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			u32 phytest;
>-
>-			if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
>-				u32 phy;
>-
>-				tg3_writephy(tp, MII_TG3_EPHY_TEST,
>-					     phytest | MII_TG3_EPHY_SHADOW_EN);
>-				if (!tg3_readphy(tp, 0x1b, &phy))
>-					tg3_writephy(tp, 0x1b, phy & ~0x20);
>-				if (!tg3_readphy(tp, 0x10, &phy))
>-					tg3_writephy(tp, 0x10, phy & ~0x4000);
>-				tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
>-			}
>-			val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
>-		} else
>-			val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
>-
>-		tg3_writephy(tp, MII_BMCR, val);
>+		tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
>+					   BMCR_SPEED1000);
> 		udelay(40);
>-
>-		mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
>-			   MAC_MODE_LINK_POLARITY;
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
>-			mac_mode |= MAC_MODE_PORT_MODE_MII;
>-		} else
>-			mac_mode |= MAC_MODE_PORT_MODE_GMII;
>-
> 		/* reset to prevent losing 1st rx packet intermittently */
> 		if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
> 			tw32_f(MAC_RX_MODE, RX_MODE_RESET);
> 			udelay(10);
> 			tw32_f(MAC_RX_MODE, tp->rx_mode);
> 		}
>-		if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
>+		mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
>+			   MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
>+		if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
> 			mac_mode &= ~MAC_MODE_LINK_POLARITY;
>-			tg3_writephy(tp, MII_TG3_EXT_CTRL,
>-				     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
>-		}
> 		tw32(MAC_MODE, mac_mode);
> 	}
> 	else
>@@ -8994,10 +8404,7 @@
> 	err = -EIO;
> 
> 	tx_len = 1514;
>-	skb = netdev_alloc_skb(tp->dev, tx_len);
>-	if (!skb)
>-		return -ENOMEM;
>-
>+	skb = dev_alloc_skb(tx_len);
> 	tx_data = skb_put(skb, tx_len);
> 	memcpy(tx_data, tp->dev->dev_addr, 6);
> 	memset(tx_data + 6, 0x0, 8);
>@@ -9032,8 +8439,7 @@
> 
> 	udelay(10);
> 
>-	/* 250 usec to allow enough time on some 10/100 Mbps devices.  */
>-	for (i = 0; i < 25; i++) {
>+	for (i = 0; i < 10; i++) {
> 		tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
> 		       HOSTCC_MODE_NOW);
> 
>@@ -9079,7 +8485,7 @@
> 			goto out;
> 	}
> 	err = 0;
>-
>+	
> 	/* tg3_free_rings will unmap and free the rx_skb */
> out:
> 	return err;
>@@ -9097,9 +8503,7 @@
> 	if (!netif_running(tp->dev))
> 		return TG3_LOOPBACK_FAILED;
> 
>-	err = tg3_reset_hw(tp, 1);
>-	if (err)
>-		return TG3_LOOPBACK_FAILED;
>+	tg3_reset_hw(tp);
> 
> 	if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
> 		err |= TG3_MAC_LOOPBACK_FAILED;
>@@ -9173,8 +8577,8 @@
> 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
> 		if (netif_running(dev)) {
> 			tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
>-			if (!tg3_restart_hw(tp, 1))
>-				tg3_netif_start(tp);
>+			tg3_init_hw(tp);
>+			tg3_netif_start(tp);
> 		}
> 
> 		tg3_full_unlock(tp);
>@@ -9186,11 +8590,7 @@
> 
> static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
> {
>-#if (LINUX_VERSION_CODE >= 0x020607)
> 	struct mii_ioctl_data *data = if_mii(ifr);
>-#else
>-	struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_ifru;
>-#endif
> 	struct tg3 *tp = netdev_priv(dev);
> 	int err;
> 
>@@ -9245,9 +8645,6 @@
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 
>-	if (netif_running(dev))
>-		tg3_netif_stop(tp);
>-
> 	tg3_full_lock(tp, 0);
> 
> 	tp->vlgrp = grp;
>@@ -9256,25 +8653,16 @@
> 	__tg3_set_rx_mode(dev);
> 
> 	tg3_full_unlock(tp);
>-
>-	if (netif_running(dev))
>-		tg3_netif_start(tp);
> }
> 
> static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
> {
> 	struct tg3 *tp = netdev_priv(dev);
> 
>-	if (netif_running(dev))
>-		tg3_netif_stop(tp);
>-
> 	tg3_full_lock(tp, 0);
> 	if (tp->vlgrp)
> 		tp->vlgrp->vlan_devices[vid] = NULL;
> 	tg3_full_unlock(tp);
>-
>-	if (netif_running(dev))
>-		tg3_netif_start(tp);
> }
> #endif
> 
>@@ -9352,15 +8740,9 @@
> 	.set_msglevel		= tg3_set_msglevel,
> 	.nway_reset		= tg3_nway_reset,
> 	.get_link		= ethtool_op_get_link,
>-#if (LINUX_VERSION_CODE >= 0x20418)
> 	.get_eeprom_len		= tg3_get_eeprom_len,
>-#endif
>-#ifdef ETHTOOL_GEEPROM
> 	.get_eeprom		= tg3_get_eeprom,
>-#endif
>-#ifdef ETHTOOL_SEEPROM
> 	.set_eeprom		= tg3_set_eeprom,
>-#endif
> 	.get_ringparam		= tg3_get_ringparam,
> 	.set_ringparam		= tg3_set_ringparam,
> 	.get_pauseparam		= tg3_get_pauseparam,
>@@ -9368,9 +8750,7 @@
> 	.get_rx_csum		= tg3_get_rx_csum,
> 	.set_rx_csum		= tg3_set_rx_csum,
> 	.get_tx_csum		= ethtool_op_get_tx_csum,
>-#if (LINUX_VERSION_CODE >= 0x20418)
> 	.set_tx_csum		= tg3_set_tx_csum,
>-#endif
> 	.get_sg			= ethtool_op_get_sg,
> 	.set_sg			= ethtool_op_set_sg,
> #if TG3_TSO_SUPPORT != 0
>@@ -9385,7 +8765,7 @@
> 	.get_ethtool_stats	= tg3_get_ethtool_stats,
> 	.get_coalesce		= tg3_get_coalesce,
> 	.set_coalesce		= tg3_set_coalesce,
>-#ifdef ETHTOOL_GPERMADDR
>+#if 0 /* Not in RHEL4... */
> 	.get_perm_addr		= ethtool_op_get_perm_addr,
> #endif
> };
>@@ -9399,9 +8779,7 @@
> 	if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
> 		return;
> 
>-	if ((magic != TG3_EEPROM_MAGIC) &&
>-	    ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
>-	    ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
>+	if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
> 		return;
> 
> 	/*
>@@ -9423,7 +8801,7 @@
> 
> 	tp->nvram_size = cursize;
> }
>-
>+		
> static void __devinit tg3_get_nvram_size(struct tg3 *tp)
> {
> 	u32 val;
>@@ -9639,27 +9017,22 @@
> 	}
> }
> 
>-static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
>-{
>-	tp->nvram_jedecnum = JEDEC_ATMEL;
>-	tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
>-	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
>-}
>-
> /* Chips other than 5700/5701 use the NVRAM for fetching info. */
> static void __devinit tg3_nvram_init(struct tg3 *tp)
> {
>+	int j;
>+
>+	if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
>+		return;
>+
> 	tw32_f(GRC_EEPROM_ADDR,
> 	     (EEPROM_ADDR_FSM_RESET |
> 	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
> 	       EEPROM_ADDR_CLKPERD_SHIFT)));
> 
>-#if (LINUX_VERSION_CODE < 0x20607)
>-	set_current_state(TASK_UNINTERRUPTIBLE);
>-	schedule_timeout(HZ / 1000);
>-#else
>-	msleep(1);
>-#endif
>+	/* XXX schedule_timeout() ... */
>+	for (j = 0; j < 100; j++)
>+		udelay(10);
> 
> 	/* Enable seeprom accesses. */
> 	tw32_f(GRC_LOCAL_CTRL,
>@@ -9683,8 +9056,6 @@
> 			tg3_get_5755_nvram_info(tp);
> 		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
> 			tg3_get_5787_nvram_info(tp);
>-		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>-			tg3_get_5906_nvram_info(tp);
> 		else
> 			tg3_get_nvram_info(tp);
> 
>@@ -9720,17 +9091,12 @@
> 	      EEPROM_ADDR_ADDR_MASK) |
> 	     EEPROM_ADDR_READ | EEPROM_ADDR_START);
> 
>-	for (i = 0; i < 1000; i++) {
>+	for (i = 0; i < 10000; i++) {
> 		tmp = tr32(GRC_EEPROM_ADDR);
> 
> 		if (tmp & EEPROM_ADDR_COMPLETE)
> 			break;
>-#if (LINUX_VERSION_CODE < 0x20607)
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 1000);
>-#else
>-		msleep(1);
>-#endif
>+		udelay(100);
> 	}
> 	if (!(tmp & EEPROM_ADDR_COMPLETE))
> 		return -EBUSY;
>@@ -9791,6 +9157,11 @@
> {
> 	int ret;
> 
>+	if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
>+		printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
>+		return -EINVAL;
>+	}
>+
> 	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
> 		return tg3_nvram_read_using_eeprom(tp, offset, val);
> 
>@@ -9854,18 +9225,13 @@
> 			(addr & EEPROM_ADDR_ADDR_MASK) |
> 			EEPROM_ADDR_START |
> 			EEPROM_ADDR_WRITE);
>-
>-		for (j = 0; j < 1000; j++) {
>+		
>+		for (j = 0; j < 10000; j++) {
> 			val = tr32(GRC_EEPROM_ADDR);
> 
> 			if (val & EEPROM_ADDR_COMPLETE)
> 				break;
>-#if (LINUX_VERSION_CODE < 0x20607)
>-			set_current_state(TASK_UNINTERRUPTIBLE);
>-			schedule_timeout(HZ / 1000);
>-#else
>-			msleep(1);
>-#endif
>+			udelay(100);
> 		}
> 		if (!(val & EEPROM_ADDR_COMPLETE)) {
> 			rc = -EBUSY;
>@@ -9895,7 +9261,7 @@
> 		u32 phy_addr, page_off, size;
> 
> 		phy_addr = offset & ~pagemask;
>-
>+	
> 		for (j = 0; j < pagesize; j += 4) {
> 			if ((ret = tg3_nvram_read(tp, phy_addr + j,
> 						(u32 *) (tmp + j))))
>@@ -9994,7 +9360,7 @@
> 
> 	        if ((page_off == 0) || (i == 0))
> 			nvram_cmd |= NVRAM_CMD_FIRST;
>-		if (page_off == (tp->nvram_pagesize - 4))
>+		else if (page_off == (tp->nvram_pagesize - 4))
> 			nvram_cmd |= NVRAM_CMD_LAST;
> 
> 		if (i == (len - 4))
>@@ -10028,6 +9394,11 @@
> {
> 	int ret;
> 
>+	if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
>+		printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
>+		return -EINVAL;
>+	}
>+
> 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
> 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
> 		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
>@@ -10135,23 +9506,12 @@
> 	return NULL;
> }
> 
>+/* Since this function may be called in D3-hot power state during
>+ * tg3_init_one(), only config cycles are allowed.
>+ */
> static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
> {
> 	u32 val;
>-	u16 pmcsr;
>-
>-	/* On some early chips the SRAM cannot be accessed in D3hot state,
>-	 * so need make sure we're in D0.
>-	 */
>-	pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
>-	pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
>-	pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
>-#if (LINUX_VERSION_CODE < 0x20607)
>-	set_current_state(TASK_UNINTERRUPTIBLE);
>-	schedule_timeout(HZ / 1000);
>-#else
>-	msleep(1);
>-#endif
> 
> 	/* Make sure register accesses (indirect or otherwise)
> 	 * will function correctly.
>@@ -10159,28 +9519,9 @@
> 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
> 			       tp->misc_host_ctrl);
> 
>-	/* The memory arbiter has to be enabled in order for SRAM accesses
>-	 * to succeed.  Normally on powerup the tg3 chip firmware will make
>-	 * sure it is enabled, but other entities such as system netboot
>-	 * code might disable it.
>-	 */
>-	val = tr32(MEMARB_MODE);
>-	tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
>-
> 	tp->phy_id = PHY_ID_INVALID;
> 	tp->led_ctrl = LED_CTRL_MODE_PHY_1;
> 
>-	/* Assume an onboard device by default.  */
>-	tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
>-
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
>-			tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
>-			tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
>-		}
>-		return;
>-	}
>-
> 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
> 	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
> 		u32 nic_cfg, led_cfg;
>@@ -10277,17 +9618,10 @@
> 		    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
> 			tp->led_ctrl = LED_CTRL_MODE_PHY_2;
> 
>-		if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
>+		if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
>+		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
>+		    (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
> 			tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
>-			if ((tp->pdev->subsystem_vendor ==
>-			     PCI_VENDOR_ID_ARIMA) &&
>-			    (tp->pdev->subsystem_device == 0x205a ||
>-			     tp->pdev->subsystem_device == 0x2063))
>-				tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
>-		} else {
>-			tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
>-			tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
>-		}
> 
> 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
> 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
>@@ -10365,13 +9699,13 @@
> 
> 	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
> 	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
>-		u32 bmsr, adv_reg, tg3_ctrl, mask;
>+		u32 bmsr, adv_reg, tg3_ctrl;
> 
> 		tg3_readphy(tp, MII_BMSR, &bmsr);
> 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
> 		    (bmsr & BMSR_LSTATUS))
> 			goto skip_phy_reset;
>-
>+		    
> 		err = tg3_phy_reset(tp);
> 		if (err)
> 			return err;
>@@ -10389,10 +9723,7 @@
> 					     MII_TG3_CTRL_ENABLE_AS_MASTER);
> 		}
> 
>-		mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
>-			ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
>-			ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
>-		if (!tg3_copper_is_advertising_right(tp, mask)) {
>+		if (!tg3_copper_is_advertising_all(tp)) {
> 			tg3_writephy(tp, MII_ADVERTISE, adv_reg);
> 
> 			if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
>@@ -10436,11 +9767,19 @@
> static void __devinit tg3_read_partno(struct tg3 *tp)
> {
> 	unsigned char vpd_data[256];
>-	unsigned int i;
>+	int i;
> 	u32 magic;
> 
>+	if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
>+		/* Sun decided not to put the necessary bits in the
>+		 * NVRAM of their onboard tg3 parts :(
>+		 */
>+		strcpy(tp->board_part_number, "Sun 570X");
>+		return;
>+	}
>+
> 	if (tg3_nvram_read_swab(tp, 0x0, &magic))
>-		goto out_not_found;
>+		return;
> 
> 	if (magic == TG3_EEPROM_MAGIC) {
> 		for (i = 0; i < 256; i += 4) {
>@@ -10469,16 +9808,8 @@
> 						     PCI_VPD_ADDR, &tmp16);
> 				if (tmp16 & 0x8000)
> 					break;
>-#if (LINUX_VERSION_CODE < 0x20607)
>-				set_current_state(TASK_UNINTERRUPTIBLE);
>-				schedule_timeout(1);
>-#else
> 				msleep(1);
>-#endif
> 			}
>-			if (!(tmp16 & 0x8000))
>-				goto out_not_found;
>-
> 			pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
> 					      &tmp);
> 			tmp = cpu_to_le32(tmp);
>@@ -10487,9 +9818,9 @@
> 	}
> 
> 	/* Now parse and find the part number. */
>-	for (i = 0; i < 254; ) {
>+	for (i = 0; i < 256; ) {
> 		unsigned char val = vpd_data[i];
>-		unsigned int block_end;
>+		int block_end;
> 
> 		if (val == 0x82 || val == 0x91) {
> 			i = (i + 3 +
>@@ -10505,26 +9836,21 @@
> 			     (vpd_data[i + 1] +
> 			      (vpd_data[i + 2] << 8)));
> 		i += 3;
>-
>-		if (block_end > 256)
>-			goto out_not_found;
>-
>-		while (i < (block_end - 2)) {
>+		while (i < block_end) {
> 			if (vpd_data[i + 0] == 'P' &&
> 			    vpd_data[i + 1] == 'N') {
> 				int partno_len = vpd_data[i + 2];
> 
>-				i += 3;
>-				if (partno_len > 24 || (partno_len + i) > 256)
>+				if (partno_len > 24)
> 					goto out_not_found;
> 
> 				memcpy(tp->board_part_number,
>-				       &vpd_data[i], partno_len);
>+				       &vpd_data[i + 3],
>+				       partno_len);
> 
> 				/* Success. */
> 				return;
> 			}
>-			i += 3 + vpd_data[i + 2];
> 		}
> 
> 		/* Part number not found. */
>@@ -10532,10 +9858,7 @@
> 	}
> 
> out_not_found:
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>-		strcpy(tp->board_part_number, "BCM95906");
>-	else
>-		strcpy(tp->board_part_number, "none");
>+	strcpy(tp->board_part_number, "none");
> }
> 
> static void __devinit tg3_read_fw_ver(struct tg3 *tp)
>@@ -10578,25 +9901,59 @@
> 	}
> }
> 
>+#ifdef CONFIG_SPARC64
>+static int __devinit tg3_is_sun_570X(struct tg3 *tp)
>+{
>+	struct pci_dev *pdev = tp->pdev;
>+	struct pcidev_cookie *pcp = pdev->sysdata;
>+
>+	if (pcp != NULL) {
>+		int node = pcp->prom_node;
>+		u32 venid;
>+		int err;
>+
>+		err = prom_getproperty(node, "subsystem-vendor-id",
>+				       (char *) &venid, sizeof(venid));
>+		if (err == 0 || err == -1)
>+			return 0;
>+		if (venid == PCI_VENDOR_ID_SUN)
>+			return 1;
>+
>+		/* TG3 chips onboard the SunBlade-2500 don't have the
>+		 * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
>+		 * are distinguishable from non-Sun variants by being
>+		 * named "network" by the firmware.  Non-Sun cards will
>+		 * show up as being named "ethernet".
>+		 */
>+		if (!strcmp(pcp->prom_name, "network"))
>+			return 1;
>+	}
>+	return 0;
>+}
>+#endif
>+
> static int __devinit tg3_get_invariants(struct tg3 *tp)
> {
>-#if (LINUX_VERSION_CODE >= 0x2060a)
> 	static struct pci_device_id write_reorder_chipsets[] = {
> 		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
> 		             PCI_DEVICE_ID_AMD_FE_GATE_700C) },
> 		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
>-		             PCI_DEVICE_ID_AMD_8131_BRIDGE) },
>+		             0x7450) },
> 		{ PCI_DEVICE(PCI_VENDOR_ID_VIA,
> 			     PCI_DEVICE_ID_VIA_8385_0) },
> 		{ },
> 	};
>-#endif
> 	u32 misc_ctrl_reg;
> 	u32 cacheline_sz_reg;
> 	u32 pci_state_reg, grc_misc_cfg;
> 	u32 val;
> 	u16 pci_cmd;
>-	int err, pcie_cap;
>+	int err;
>+
>+#ifdef CONFIG_SPARC64
>+	if (tg3_is_sun_570X(tp))
>+		tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
>+#endif
> 
> 	/* Force memory write invalidate off.  If we leave it on,
> 	 * then on 5700_BX chips we have to enable a workaround.
>@@ -10690,36 +10047,12 @@
> 		}
> 	}
> 
>-	/* The EPB bridge inside 5714, 5715, and 5780 cannot support
>-	 * DMA addresses > 40-bit. This bridge may have other additional
>-	 * 57xx devices behind it in some 4-port NIC designs for example.
>-	 * Any tg3 device found behind the bridge will also need the 40-bit
>-	 * DMA workaround.
>-	 */
>+	/* Find msi capability. */
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
> 		tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
>-		tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
> 		tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
> 	}
>-	else {
>-		struct pci_dev *bridge = NULL;
>-
>-		do {
>-			bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
>-						PCI_DEVICE_ID_SERVERWORKS_EPB,
>-						bridge);
>-			if (bridge && bridge->subordinate &&
>-			    (bridge->subordinate->number <=
>-			     tp->pdev->bus->number) &&
>-			    (bridge->subordinate->subordinate >=
>-			     tp->pdev->bus->number)) {
>-				tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
>-				pci_dev_put(bridge);
>-				break;
>-			}
>-		} while (bridge);
>-	}
> 
> 	/* Initialize misc host control in PCI block. */
> 	tp->misc_host_ctrl |= (misc_ctrl_reg &
>@@ -10739,7 +10072,6 @@
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
> 	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
> 		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
> 
>@@ -10749,42 +10081,22 @@
> 
> 	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
> 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
>-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
>-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5906M)
>-				tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
>+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
>+			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
> 			tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
>-		} else {
>-			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
>-					  TG3_FLG2_HW_TSO_1_BUG;
>-			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
>-				ASIC_REV_5750 &&
>-	     		    tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
>-				tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
>-		}
>+		} else
>+			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
> 	}
> 
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
>+	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
> 		tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
> 
>-	pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
>-	if (pcie_cap != 0) {
>+	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
> 		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			u16 lnkctl;
>-
>-			pci_read_config_word(tp->pdev,
>-					     pcie_cap + PCI_EXP_LNKCTL,
>-					     &lnkctl);
>-			if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
>-				tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
>-		}
>-	}
> 
> 	/* If we have an AMD 762 or VIA K8T800 chipset, write
> 	 * reordering to the mailbox registers done by the host
>@@ -10792,16 +10104,7 @@
> 	 * every mailbox register write to force the writes to be
> 	 * posted to the chip in order.
> 	 */
>-#if (LINUX_VERSION_CODE < 0x2060a)
>-	if ((pci_find_device(PCI_VENDOR_ID_AMD,
>-			     PCI_DEVICE_ID_AMD_FE_GATE_700C, NULL) ||
>-	     pci_find_device(PCI_VENDOR_ID_AMD,
>-			     PCI_DEVICE_ID_AMD_8131_BRIDGE, NULL) ||
>-	     pci_find_device(PCI_VENDOR_ID_VIA,
>-			     PCI_DEVICE_ID_VIA_8385_0, NULL)) &&
>-#else
> 	if (pci_dev_present(write_reorder_chipsets) &&
>-#endif
> 	    !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
> 		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
> 
>@@ -10919,27 +10222,15 @@
> 		pci_cmd &= ~PCI_COMMAND_MEMORY;
> 		pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
> 	}
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-		tp->read32_mbox = tg3_read32_mbox_5906;
>-		tp->write32_mbox = tg3_write32_mbox_5906;
>-		tp->write32_tx_mbox = tg3_write32_mbox_5906;
>-		tp->write32_rx_mbox = tg3_write32_mbox_5906;
>-	}
>-
>-	if (tp->write32 == tg3_write_indirect_reg32 ||
>-	    ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
>-	     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
>-	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
>-		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
> 
> 	/* Get eeprom hw config before calling tg3_set_power_state().
>-	 * In particular, the TG3_FLG2_IS_NIC flag must be
>+	 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
> 	 * determined before calling tg3_set_power_state() so that
> 	 * we know whether or not to switch out of Vaux power.
> 	 * When the flag is set, it means that GPIO1 is used for eeprom
> 	 * write protect and also implies that it is a LOM where GPIOs
> 	 * are not used to switch power.
>-	 */
>+	 */ 
> 	tg3_get_eeprom_hw_cfg(tp);
> 
> 	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
>@@ -10974,6 +10265,15 @@
> 	if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
> 		tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
> 
>+	/* Pseudo-header checksum is done by hardware logic and not
>+	 * the offload processers, so make the chip do the pseudo-
>+	 * header checksums on receive.  For transmit it is more
>+	 * convenient to do the pseudo-header checksum in software
>+	 * as Linux does that on transmit for us in all cases.
>+	 */
>+	tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
>+	tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
>+
> 	/* Derive initial jumbo mode from MTU assigned in
> 	 * ether_setup() via the alloc_etherdev() call
> 	 */
>@@ -10996,7 +10296,6 @@
> 	    ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
> 	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
> 	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
>-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
> 	    (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
> 		tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
> 
>@@ -11006,15 +10305,10 @@
> 	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
> 		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
> 
>-	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
>-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
>-			tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
>-			if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
>-				tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
>-		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
>-			tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
>-	}
>+	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
>+	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
>+	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))
>+		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
> 
> 	tp->coalesce_mode = 0;
> 	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
>@@ -11102,9 +10396,7 @@
> 	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
> 	    (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
> 	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
>-	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
>-	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>+	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
> 		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
> 
> 	err = tg3_phy_probe(tp);
>@@ -11155,8 +10447,7 @@
> 	 * straddle the 4GB address boundary in some cases.
> 	 */
> 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
> 		tp->dev->hard_start_xmit = tg3_start_xmit;
> 	else
> 		tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
>@@ -11166,16 +10457,6 @@
> 	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
> 		tp->rx_offset = 0;
> 
>-	tp->rx_std_max_post = TG3_RX_RING_SIZE;
>-
>-	/* Increment the rx prod index on the rx std ring by at most
>-	 * 8 for these chips to workaround hw errata.
>-	 */
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
>-		tp->rx_std_max_post = 8;
>-
> 	/* By default, disable wake-on-lan.  User can change this
> 	 * using ETHTOOL_SWOL.
> 	 */
>@@ -11192,14 +10473,14 @@
> 	struct pcidev_cookie *pcp = pdev->sysdata;
> 
> 	if (pcp != NULL) {
>-		unsigned char *addr;
>-		int len;
>+		int node = pcp->prom_node;
> 
>-		addr = of_get_property(pcp->prom_node, "local-mac-address",
>-					&len);
>-		if (addr && len == 6) {
>-			memcpy(dev->dev_addr, addr, 6);
>+		if (prom_getproplen(node, "local-mac-address") == 6) {
>+			prom_getproperty(node, "local-mac-address",
>+					 dev->dev_addr, 6);
>+#if 0 /* Not in RHEL4... */
> 			memcpy(dev->perm_addr, dev->dev_addr, 6);
>+#endif
> 			return 0;
> 		}
> 	}
>@@ -11211,7 +10492,9 @@
> 	struct net_device *dev = tp->dev;
> 
> 	memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
>+#if 0 /* Not in RHEL4... */
> 	memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
>+#endif
> 	return 0;
> }
> #endif
>@@ -11220,7 +10503,6 @@
> {
> 	struct net_device *dev = tp->dev;
> 	u32 hi, lo, mac_offset;
>-	int addr_ok = 0;
> 
> #ifdef CONFIG_SPARC64
> 	if (!tg3_get_macaddr_sparc(tp))
>@@ -11228,7 +10510,8 @@
> #endif
> 
> 	mac_offset = 0x7c;
>-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
>+	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
>+	     !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
> 	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
> 		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
> 			mac_offset = 0xcc;
>@@ -11237,8 +10520,6 @@
> 		else
> 			tg3_nvram_unlock(tp);
> 	}
>-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
>-		mac_offset = 0x10;
> 
> 	/* First try to get it from MAC address mailbox. */
> 	tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
>@@ -11251,33 +10532,29 @@
> 		dev->dev_addr[3] = (lo >> 16) & 0xff;
> 		dev->dev_addr[4] = (lo >>  8) & 0xff;
> 		dev->dev_addr[5] = (lo >>  0) & 0xff;
>-
>-		/* Some old bootcode may report a 0 MAC address in SRAM */
>-		addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
> 	}
>-	if (!addr_ok) {
>-		/* Next, try NVRAM. */
>-		if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
>-		    !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
>-			dev->dev_addr[0] = ((hi >> 16) & 0xff);
>-			dev->dev_addr[1] = ((hi >> 24) & 0xff);
>-			dev->dev_addr[2] = ((lo >>  0) & 0xff);
>-			dev->dev_addr[3] = ((lo >>  8) & 0xff);
>-			dev->dev_addr[4] = ((lo >> 16) & 0xff);
>-			dev->dev_addr[5] = ((lo >> 24) & 0xff);
>-		}
>-		/* Finally just fetch it out of the MAC control regs. */
>-		else {
>-			hi = tr32(MAC_ADDR_0_HIGH);
>-			lo = tr32(MAC_ADDR_0_LOW);
>+	/* Next, try NVRAM. */
>+	else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
>+		 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
>+		 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
>+		dev->dev_addr[0] = ((hi >> 16) & 0xff);
>+		dev->dev_addr[1] = ((hi >> 24) & 0xff);
>+		dev->dev_addr[2] = ((lo >>  0) & 0xff);
>+		dev->dev_addr[3] = ((lo >>  8) & 0xff);
>+		dev->dev_addr[4] = ((lo >> 16) & 0xff);
>+		dev->dev_addr[5] = ((lo >> 24) & 0xff);
>+	}
>+	/* Finally just fetch it out of the MAC control regs. */
>+	else {
>+		hi = tr32(MAC_ADDR_0_HIGH);
>+		lo = tr32(MAC_ADDR_0_LOW);
> 
>-			dev->dev_addr[5] = lo & 0xff;
>-			dev->dev_addr[4] = (lo >> 8) & 0xff;
>-			dev->dev_addr[3] = (lo >> 16) & 0xff;
>-			dev->dev_addr[2] = (lo >> 24) & 0xff;
>-			dev->dev_addr[1] = hi & 0xff;
>-			dev->dev_addr[0] = (hi >> 8) & 0xff;
>-		}
>+		dev->dev_addr[5] = lo & 0xff;
>+		dev->dev_addr[4] = (lo >> 8) & 0xff;
>+		dev->dev_addr[3] = (lo >> 16) & 0xff;
>+		dev->dev_addr[2] = (lo >> 24) & 0xff;
>+		dev->dev_addr[1] = hi & 0xff;
>+		dev->dev_addr[0] = (hi >> 8) & 0xff;
> 	}
> 
> 	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
>@@ -11287,7 +10564,7 @@
> #endif
> 		return -EINVAL;
> 	}
>-#ifdef ETHTOOL_GPERMADDR
>+#if 0 /* Not in RHEL4... */
> 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
> #endif
> 	return 0;
>@@ -11547,14 +10824,7 @@
> 		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
> 			u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
> 
>-			/* If the 5704 is behind the EPB bridge, we can
>-			 * do the less restrictive ONE_DMA workaround for
>-			 * better performance.
>-			 */
>-			if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
>-			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
>-				tp->dma_rwctrl |= 0x8000;
>-			else if (ccval == 0x6 || ccval == 0x7)
>+			if (ccval == 0x6 || ccval == 0x7)
> 				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
> 
> 			/* Set bit 23 to enable PCIX hw bug fix */
>@@ -11670,25 +10940,17 @@
> 	}
> 	if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
> 	    DMA_RWCTRL_WRITE_BNDRY_16) {
>-#if (LINUX_VERSION_CODE >= 0x2060a)
> 		static struct pci_device_id dma_wait_state_chipsets[] = {
> 			{ PCI_DEVICE(PCI_VENDOR_ID_APPLE,
> 				     PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
> 			{ },
> 		};
>-#endif
> 
> 		/* DMA test passed without adjusting DMA boundary,
> 		 * now look for chipsets that are known to expose the
> 		 * DMA bug without failing the test.
> 		 */
>-#if (LINUX_VERSION_CODE < 0x2060a)
>-		if (pci_find_device(PCI_VENDOR_ID_APPLE,
>-			PCI_DEVICE_ID_APPLE_UNI_N_PCI15, NULL))
>-#else
>-		if (pci_dev_present(dma_wait_state_chipsets))
>-#endif
>-		{
>+		if (pci_dev_present(dma_wait_state_chipsets)) {
> 			tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
> 			tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
> 		}
>@@ -11732,12 +10994,6 @@
> 			DEFAULT_MB_MACRX_LOW_WATER_5705;
> 		tp->bufmgr_config.mbuf_high_water =
> 			DEFAULT_MB_HIGH_WATER_5705;
>-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
>-			tp->bufmgr_config.mbuf_mac_rx_low_water =
>-				DEFAULT_MB_MACRX_LOW_WATER_5906;
>-			tp->bufmgr_config.mbuf_high_water =
>-				DEFAULT_MB_HIGH_WATER_5906;
>-		}
> 
> 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
> 			DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
>@@ -11781,8 +11037,6 @@
> 	case PHY_ID_BCM5780:	return "5780";
> 	case PHY_ID_BCM5755:	return "5755";
> 	case PHY_ID_BCM5787:	return "5787";
>-	case PHY_ID_BCM5756:	return "5722/5756";
>-	case PHY_ID_BCM5906:	return "5906";
> 	case PHY_ID_BCM8002:	return "8002/serdes";
> 	case 0:			return "serdes";
> 	default:		return "unknown";
>@@ -11811,6 +11065,8 @@
> 			strcat(str, "66MHz");
> 		else if (clock_ctrl == 6)
> 			strcat(str, "100MHz");
>+		else if (clock_ctrl == 7)
>+			strcat(str, "133MHz");
> 	} else {
> 		strcpy(str, "PCI:");
> 		if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
>@@ -11941,10 +11197,9 @@
> 	}
> 
> 	SET_MODULE_OWNER(dev);
>-#if (LINUX_VERSION_CODE >= 0x20419)
> 	SET_NETDEV_DEV(dev, &pdev->dev);
>-#endif
> 
>+	dev->features |= NETIF_F_LLTX;
> #if TG3_VLAN_TAG_USED
> 	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
> 	dev->vlan_rx_register = tg3_vlan_rx_register;
>@@ -11986,6 +11241,7 @@
> 	tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
> #endif
> 	spin_lock_init(&tp->lock);
>+	spin_lock_init(&tp->tx_lock);
> 	spin_lock_init(&tp->indirect_lock);
> 	INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
> 
>@@ -12016,7 +11272,7 @@
> 	dev->watchdog_timeo = TG3_TX_TIMEOUT;
> 	dev->change_mtu = tg3_change_mtu;
> 	dev->irq = pdev->irq;
>-#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
>+#ifdef CONFIG_NET_POLL_CONTROLLER
> 	dev->poll_controller = tg3_poll_controller;
> #endif
> 
>@@ -12027,20 +11283,19 @@
> 		goto err_out_iounmap;
> 	}
> 
>-	/* The EPB bridge inside 5714, 5715, and 5780 and any
>-	 * device behind the EPB cannot support DMA addresses > 40-bit.
>+	/* 5714, 5715 and 5780 cannot support DMA addresses > 40-bit.
> 	 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
> 	 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
> 	 * do DMA address check in tg3_start_xmit().
> 	 */
>-	if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
>-		persist_dma_mask = dma_mask = DMA_32BIT_MASK;
>-	else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
>+	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
> 		persist_dma_mask = dma_mask = DMA_40BIT_MASK;
> #ifdef CONFIG_HIGHMEM
> 		dma_mask = DMA_64BIT_MASK;
> #endif
>-	} else
>+	} else if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
>+		persist_dma_mask = dma_mask = DMA_32BIT_MASK;
>+	else
> 		persist_dma_mask = dma_mask = DMA_64BIT_MASK;
> 
> 	/* Configure DMA attributes. */
>@@ -12075,7 +11330,6 @@
> 	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
> 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
> 	    tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
>-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
> 	    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
> 		tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
> 	} else {
>@@ -12086,12 +11340,8 @@
> 	 * Firmware TSO on older chips gives lower performance, so it
> 	 * is off by default, but can be enabled using ethtool.
> 	 */
>-	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
>+	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
> 		dev->features |= NETIF_F_TSO;
>-		if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
>-		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
>-			dev->features |= NETIF_F_TSO6;
>-	}
> 
> #endif
> 
>@@ -12120,11 +11370,7 @@
> 	 */
> 	if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
> 	    (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
>-#if (LINUX_VERSION_CODE < 0x2060a)
> 		pci_save_state(tp->pdev, tp->pci_cfg_state);
>-#else
>-		pci_save_state(tp->pdev);
>-#endif
> 		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
> 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
> 	}
>@@ -12158,12 +11404,7 @@
> 	 * of the PCI config space.  We need to restore this after
> 	 * GRC_MISC_CFG core clock resets and some resume events.
> 	 */
>-#if (LINUX_VERSION_CODE < 0x2060a)
> 	pci_save_state(tp->pdev, tp->pci_cfg_state);
>-#else
>-	pci_save_state(tp->pdev);
>-#endif
>-	pci_set_drvdata(pdev, dev);
> 
> 	err = register_netdev(dev);
> 	if (err) {
>@@ -12172,15 +11413,15 @@
> 		goto err_out_iounmap;
> 	}
> 
>-	printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
>+	pci_set_drvdata(pdev, dev);
>+
>+	printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
> 	       dev->name,
> 	       tp->board_part_number,
> 	       tp->pci_chip_rev_id,
> 	       tg3_phy_string(tp),
> 	       tg3_bus_string(tp, str),
>-	       ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
>-		((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
>-		 "10/100/1000Base-T")));
>+	       (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
> 
> 	for (i = 0; i < 6; i++)
> 		printk("%2.2x%c", dev->dev_addr[i],
>@@ -12197,10 +11438,10 @@
> 	       (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
> 	       (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
> 	       (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
>-	printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
>-	       dev->name, tp->dma_rwctrl,
>-	       (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
>-	        (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
>+	printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
>+	       dev->name, tp->dma_rwctrl);
>+
>+	netif_carrier_off(tp->dev);
> 
> 	return 0;
> 
>@@ -12211,11 +11452,7 @@
> 	}
> 
> err_out_free_dev:
>-#if (LINUX_VERSION_CODE >= 0x20418)
> 	free_netdev(dev);
>-#else
>-	kfree(dev);
>-#endif
> 
> err_out_free_res:
> 	pci_release_regions(pdev);
>@@ -12233,30 +11470,20 @@
> 	if (dev) {
> 		struct tg3 *tp = netdev_priv(dev);
> 
>-#if (LINUX_VERSION_CODE >= 0x20600)
> 		flush_scheduled_work();
>-#endif
> 		unregister_netdev(dev);
> 		if (tp->regs) {
> 			iounmap(tp->regs);
> 			tp->regs = NULL;
> 		}
>-#if (LINUX_VERSION_CODE >= 0x20418)
> 		free_netdev(dev);
>-#else
>-		kfree(dev);
>-#endif
> 		pci_release_regions(pdev);
> 		pci_disable_device(pdev);
> 		pci_set_drvdata(pdev, NULL);
> 	}
> }
> 
>-#if (LINUX_VERSION_CODE < 0x2060b)
>-static int tg3_suspend(struct pci_dev *pdev, u32 state)
>-#else
> static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
>-#endif
> {
> 	struct net_device *dev = pci_get_drvdata(pdev);
> 	struct tg3 *tp = netdev_priv(dev);
>@@ -12265,9 +11492,7 @@
> 	if (!netif_running(dev))
> 		return 0;
> 
>-#if (LINUX_VERSION_CODE >= 0x20600)
> 	flush_scheduled_work();
>-#endif
> 	tg3_netif_stop(tp);
> 
> 	del_timer_sync(&tp->timer);
>@@ -12283,17 +11508,12 @@
> 	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
> 	tg3_full_unlock(tp);
> 
>-#if (LINUX_VERSION_CODE < 0x2060b)
>-	err = tg3_set_power_state(tp, state);
>-#else
> 	err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
>-#endif
> 	if (err) {
> 		tg3_full_lock(tp, 0);
> 
> 		tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
>-		if (tg3_restart_hw(tp, 1))
>-			goto out;
>+		tg3_init_hw(tp);
> 
> 		tp->timer.expires = jiffies + tp->timer_offset;
> 		add_timer(&tp->timer);
>@@ -12301,7 +11521,6 @@
> 		netif_device_attach(dev);
> 		tg3_netif_start(tp);
> 
>-out:
> 		tg3_full_unlock(tp);
> 	}
> 
>@@ -12317,11 +11536,7 @@
> 	if (!netif_running(dev))
> 		return 0;
> 
>-#if (LINUX_VERSION_CODE < 0x2060a)
> 	pci_restore_state(tp->pdev, tp->pci_cfg_state);
>-#else
>-	pci_restore_state(tp->pdev);
>-#endif
> 
> 	err = tg3_set_power_state(tp, PCI_D0);
> 	if (err)
>@@ -12332,19 +11547,16 @@
> 	tg3_full_lock(tp, 0);
> 
> 	tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
>-	err = tg3_restart_hw(tp, 1);
>-	if (err)
>-		goto out;
>+	tg3_init_hw(tp);
> 
> 	tp->timer.expires = jiffies + tp->timer_offset;
> 	add_timer(&tp->timer);
> 
> 	tg3_netif_start(tp);
> 
>-out:
> 	tg3_full_unlock(tp);
> 
>-	return err;
>+	return 0;
> }
> 
> static struct pci_driver tg3_driver = {
>@@ -12358,11 +11570,7 @@
> 
> static int __init tg3_init(void)
> {
>-#if (LINUX_VERSION_CODE < 0x020613)
> 	return pci_module_init(&tg3_driver);
>-#else
>-	return pci_register_driver(&tg3_driver);
>-#endif
> }
> 
> static void __exit tg3_cleanup(void)

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Attachments on bug 216895: 148312 | 149677 | 151555 | 151687 | 151755 | 151756