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Red Hat Bugzilla – Attachment 151496 Details for
Bug 223901
[RHEL5] kernel: MCA occurs during ext3 stress test on ia64
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[patch]
Debug patch
mca-trap7.patch (text/plain), 8.17 KB, created by
Kiyoshi Ueda
on 2007-04-03 00:31:29 UTC
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Description:
Debug patch
Filename:
MIME Type:
Creator:
Kiyoshi Ueda
Created:
2007-04-03 00:31:29 UTC
Size:
8.17 KB
patch
obsolete
>diff -rupN 2.6.18-4.el5/arch/ia64/kernel/entry.S trap/arch/ia64/kernel/entry.S >--- 2.6.18-4.el5/arch/ia64/kernel/entry.S 2007-02-23 12:05:25.000000000 -0500 >+++ trap/arch/ia64/kernel/entry.S 2007-03-14 08:58:39.000000000 -0400 >@@ -229,6 +229,12 @@ GLOBAL_ENTRY(__ia64_switch_to) > mov r25=IA64_TR_CURRENT_STACK > mov IA64_KR(CURRENT_STACK)=r26 // remember last page we mapped... > ;; >+ movl r26=0x0000001100000000 // set 68 GB >+ ;; >+ cmp.ge p7,p0=r20,r26 // check the address >+ ;; >+(p7) st8 [r0]=r0 >+ ;; > itr.d dtr[r25]=r23 // wire in new mapping... > ssm psr.ic // reenable the psr.ic bit > ;; >diff -rupN 2.6.18-4.el5/arch/ia64/kernel/ivt.S trap/arch/ia64/kernel/ivt.S >--- 2.6.18-4.el5/arch/ia64/kernel/ivt.S 2006-09-19 23:42:06.000000000 -0400 >+++ trap/arch/ia64/kernel/ivt.S 2007-03-05 14:13:01.000000000 -0500 >@@ -145,6 +145,11 @@ ENTRY(vhpt_miss) > #else > shr.u r18=r22,PMD_SHIFT // shift pmd index into position > #endif >+ movl r27=0x0000001100000000 // set 68 GB into r27 >+ ;; >+ cmp.ge p9,p0=r17,r27 // check the address >+ ;; >+(p9) br.cond.spnt page_fault > ;; > ld8 r17=[r17] // get *pgd (may be 0) > ;; >@@ -161,12 +166,20 @@ ENTRY(vhpt_miss) > dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr) > #endif > ;; >+(p7) cmp.ge p9,p7=r17,r27 // check the address >+ ;; >+(p9) br.cond.spnt page_fault >+ ;; > (p7) ld8 r20=[r17] // get *pmd (may be 0) > shr.u r19=r22,PAGE_SHIFT // shift pte index into position > ;; > (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL? > dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr) > ;; >+(p7) cmp.ge p9,p7=r21,r27 // check the address >+ ;; >+(p9) br.cond.spnt page_fault >+ ;; > (p7) ld8 r18=[r21] // read *pte > mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss > ;; >@@ -175,6 +188,13 @@ ENTRY(vhpt_miss) > ;; // avoid RAW on p7 > (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? > dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address >+(p7) movl r28=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+(p7) and r28=r18,r28 // extract ppn of r18 >+ ;; >+(p7) cmp.ge p9,p0=r28,r27 // check the ppn >+ ;; >+(p9) br.cond.spnt page_fault > ;; > (p10) itc.i r18 // insert the instruction TLB entry > (p11) itc.d r18 // insert the data TLB entry >@@ -191,6 +211,13 @@ ENTRY(vhpt_miss) > * bit. > */ > adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23 >+(p7) movl r28=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+(p7) and r28=r24,r28 // extract ppn of r24 >+ ;; >+(p7) cmp.ge p9,p0=r28,r27 // check the ppn >+ ;; >+(p9) br.cond.spnt page_fault > ;; > (p7) itc.d r24 > ;; >@@ -214,6 +241,13 @@ ENTRY(vhpt_miss) > * r20 = *pmd > * r18 = *pte > */ >+ cmp.ge p7,p0=r21,r27 // check the address >+ cmp.ge p6,p0=r17,r27 // check the address >+ ;; >+(p7) br.cond.spnt page_fault >+ ;; >+(p6) br.cond.spnt page_fault >+ ;; > ld8 r25=[r21] // read *pte again > ld8 r26=[r17] // read *pmd again > #ifdef CONFIG_PGTABLE_4 >@@ -261,6 +295,15 @@ ENTRY(itlb_miss) > tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? > (p6) br.cond.spnt page_fault > ;; >+ movl r19=0x0000001100000000 // set 68 GB >+ movl r20=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+ and r20=r18,r20 // extract ppn of r18 >+ ;; >+ cmp.ge p6,p0=r20,r19 // chech the ppn >+ ;; >+(p6) br.cond.spnt page_fault >+ ;; > itc.i r18 > ;; > #ifdef CONFIG_SMP >@@ -305,6 +348,15 @@ dtlb_fault: > tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? > (p6) br.cond.spnt page_fault > ;; >+ movl r19=0x0000001100000000 // set 68 GB >+ movl r20=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+ and r20=r18,r20 // extract ppn of r18 >+ ;; >+ cmp.ge p6,p0=r20,r19 // chech the ppn >+ ;; >+(p6) br.cond.spnt page_fault >+ ;; > itc.d r18 > ;; > #ifdef CONFIG_SMP >@@ -358,6 +410,19 @@ ENTRY(alt_itlb_miss) > or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 > (p8) br.cond.spnt page_fault > ;; >+ shr.u r22=r16,61 >+ ;; >+ cmp.gt p0,p8=6,r22 // p0=1 if reg 0-5, p8=1 if reg 6-7 >+ ;; >+(p8) movl r22=((1 << IA64_MAX_PHYS_BITS) - 1) >+(p8) movl r23=0x0000001100000000 // set 68 GB into r23 >+ ;; >+(p8) and r22=r22,r16 // get physical address into r22 >+ ;; >+(p8) cmp.ge p8,p0=r22,r23 // check the physical address >+ ;; >+(p8) br.cond.spnt page_fault // if access to unpresent memory, panic >+ ;; > itc.i r19 // insert the TLB entry > mov pr=r31,-1 > rfi >@@ -404,6 +469,24 @@ ENTRY(alt_dtlb_miss) > or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 > (p6) mov cr.ipsr=r21 > ;; >+ cmp.eq.and p6,p9=1,r0 // set p6=0, p9=0. already p8=0 here. >+(p7) shr.u r22=r16,61 // get region number >+ ;; >+(p7) cmp.gt p7,p8=6,r22 // p7=1 if reg 0-5, p8=1 if reg 6-7 >+ ;; >+(p8) cmp.eq p6,p9=6,r22 // p6=1 if reg 6, p9=1 if reg 7 >+ ;; >+(p8) movl r22=((1 << IA64_MAX_PHYS_BITS) - 1) >+(p6) movl r23=0x0000100000000000 // set 16 TB into r23 for reg 6 >+ ;; >+(p9) movl r23=0x0000001100000000 // set 68 GB into r23 for reg 7 >+ ;; >+(p8) and r22=r22,r16 // get physical address into r22 >+ ;; >+(p8) cmp.ge p8,p7=r22,r23 // check the physical address >+ ;; >+(p8) br.cond.spnt page_fault // if access to unpresent memory, panic >+ ;; > (p7) itc.d r19 // insert the TLB entry > mov pr=r31,-1 > rfi >@@ -460,14 +543,22 @@ ENTRY(nested_dtlb_miss) > ;; > (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 > (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4] >- cmp.eq p7,p6=0,r21 // unused address bits all zeroes? >+// cmp.eq p7,p6=0,r21 // unused address bits all zeroes? > #ifdef CONFIG_PGTABLE_4 > shr.u r18=r22,PUD_SHIFT // shift pud index into position > #else > shr.u r18=r22,PMD_SHIFT // shift pmd index into position > #endif > ;; >- ld8 r17=[r17] // get *pgd (may be 0) >+ movl r19=0x0000001100000000 // set 68 GB into r19 >+ ;; >+ cmp.ge p6,p7=r17,r19 // check the address >+ ;; >+(p6) br.cond.spnt page_fault >+ ;; >+(p7) ld8 r17=[r17] // get *pgd (may be 0) >+ ;; >+ cmp.eq p7,p6=0,r21 // unused address bits all zeroes? > ;; > (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL? > dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr) >@@ -480,6 +571,15 @@ ENTRY(nested_dtlb_miss) > dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr) > ;; > #endif >+(p7) cmp.ge p7,p0=r17,r19 // check the address >+ ;; >+(p7) br.cond.spnt page_fault // panic >+ ;; >+(p6) br.cond.spnt 1f // no need to set p7 if p6 == 1 >+ ;; >+ cmp.eq p7,p0=0,r0 // the check above was false. so recover the original value (1) to p7. >+ ;; >+1: > (p7) ld8 r17=[r17] // get *pmd (may be 0) > shr.u r19=r22,PAGE_SHIFT // shift pte index into position > ;; >@@ -567,6 +667,20 @@ ENTRY(dirty_bit) > ;; > (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present > ;; >+(p6) movl r26=0x0000001100000000 // set 68 GB >+(p6) movl r18=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+(p6) and r18=r25,r18 // extract ppn of r25 >+ ;; >+(p6) cmp.ge p6,p0=r18,r26 // check the ppn >+ ;; >+(p6) br.cond.spnt page_fault // panic >+ ;; >+(p7) br.cond.spnt 2f // no need to set p6 if p7 == 1 >+ ;; >+ cmp.eq p6,p0=0,r0 // the check above was false, so recover the original value (1) to p6. >+ ;; >+2: > (p6) itc.d r25 // install updated PTE > ;; > /* >@@ -633,6 +747,20 @@ ENTRY(iaccess_bit) > ;; > (p6) cmp.eq p6,p7=r26,r18 // Only if page present > ;; >+(p6) movl r26=0x0000001100000000 // set 68 GB >+(p6) movl r18=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+(p6) and r18=r25,r18 // extract ppn of r25 >+ ;; >+(p6) cmp.ge p6,p0=r18,r26 // check the ppn >+ ;; >+(p6) br.cond.spnt page_fault // panic >+ ;; >+(p7) br.cond.spnt 2f // no need to set p6 if p7 == 1 >+ ;; >+ cmp.eq p6,p0=0,r0 // the check above was false, so recover the original value (1) to p6. >+ ;; >+2: > (p6) itc.i r25 // install updated PTE > ;; > /* >@@ -688,6 +816,20 @@ ENTRY(daccess_bit) > ;; > (p6) cmp.eq p6,p7=r26,r18 // Only if page is present > ;; >+(p6) movl r26=0x0000001100000000 // set 68 GB >+(p6) movl r18=((1 << IA64_MAX_PHYS_BITS) - 1) >+ ;; >+(p6) and r18=r25,r18 // extract ppn of r25 >+ ;; >+(p6) cmp.ge p6,p0=r18,r26 // check the ppn >+ ;; >+(p6) br.cond.spnt page_fault // panic >+ ;; >+(p7) br.cond.spnt 2f // no need to set p6 if p7 == 1 >+ ;; >+ cmp.eq p6,p0=0,r0 // the check above was false, so recover the original value (1) to p6. >+ ;; >+2: > (p6) itc.d r25 // install updated PTE > /* > * Tell the assemblers dependency-violation checker that the above "itc" instructions
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Attachments on
bug 223901
: 151496