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Red Hat Bugzilla – Attachment 161265 Details for
Bug 228733
sky2 module (ver 1.6) kernel panic
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[patch]
correct patch for sky2 from cvs
linux-kernel-test.patch (text/plain), 100.77 KB, created by
Neil Horman
on 2007-08-14 12:47:01 UTC
(
hide
)
Description:
correct patch for sky2 from cvs
Filename:
MIME Type:
Creator:
Neil Horman
Created:
2007-08-14 12:47:01 UTC
Size:
100.77 KB
patch
obsolete
>--- linux-2.6.9/drivers/net/sky2_compat.h.orig 2007-08-13 15:42:41.000000000 -0400 >+++ linux-2.6.9/drivers/net/sky2_compat.h 2007-08-13 15:45:08.000000000 -0400 >@@ -33,4 +33,36 @@ > init_timer(timer); > } > >+static inline void netif_tx_lock(struct net_device *dev) >+{ >+ spin_lock(&dev->xmit_lock); >+ dev->xmit_lock_owner = smp_processor_id(); >+} >+ >+static inline void netif_tx_lock_bh(struct net_device *dev) >+{ >+ spin_lock_bh(&dev->xmit_lock); >+ dev->xmit_lock_owner = smp_processor_id(); >+} >+ >+static inline void netif_tx_unlock(struct net_device *dev) >+{ >+ dev->xmit_lock_owner = -1; >+ spin_unlock(&dev->xmit_lock); >+} >+ >+static inline void netif_tx_unlock_bh(struct net_device *dev) >+{ >+ dev->xmit_lock_owner = -1; >+ spin_unlock_bh(&dev->xmit_lock); >+} >+ >+#ifndef NET_SKB_PAD >+#define NET_SKB_PAD 16 >+#endif >+ >+#ifndef IRQF_SHARED >+#define IRQF_SHARED SA_SHIRQ >+#endif >+ > #endif /* __SKY2_COMPAT_H__ */ >--- linux-2.6.9/drivers/net/sky2.h.orig 2007-08-13 15:42:41.000000000 -0400 >+++ linux-2.6.9/drivers/net/sky2.h 2007-08-13 15:45:08.000000000 -0400 >@@ -4,6 +4,8 @@ > #ifndef _SKY2_H > #define _SKY2_H > >+#define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ >+ > /* PCI config registers */ > enum { > PCI_DEV_REG1 = 0x40, >@@ -285,6 +287,9 @@ > | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, > Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 > | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, >+ Y2_IS_ERROR = Y2_IS_HW_ERR | >+ Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | >+ Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, > }; > > /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ >@@ -368,12 +373,9 @@ > > /* B2_CHIP_ID 8 bit Chip Identification Number */ > enum { >- CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */ >- CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */ >- CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */ >- CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */ > CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ > CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ >+ CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */ > CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ > CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ > >@@ -381,8 +383,13 @@ > CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ > CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ > >- CHIP_REV_YU_EC_U_A0 = 0, >- CHIP_REV_YU_EC_U_A1 = 1, >+ CHIP_REV_YU_EC_U_A0 = 1, >+ CHIP_REV_YU_EC_U_A1 = 2, >+ CHIP_REV_YU_EC_U_B0 = 3, >+ >+ CHIP_REV_YU_FE_A1 = 1, >+ CHIP_REV_YU_FE_A2 = 2, >+ > }; > > /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ >@@ -601,7 +608,7 @@ > PHY_ADDR_MARV = 0, > }; > >-#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) >+#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) > > > enum { >@@ -673,6 +680,7 @@ > BMU_FIFO_ENA | BMU_OP_ON, > > BMU_WM_DEFAULT = 0x600, >+ BMU_WM_PEX = 0x80, > }; > > /* Tx BMU Control / Status Registers (Yukon-2) */ >@@ -732,6 +740,11 @@ > TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ > TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ > TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ >+ >+ /* Threshold values for Yukon-EC Ultra and Extreme */ >+ ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ >+ ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ >+ ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ > }; > > /* Descriptor Poll Timer Registers */ >@@ -759,6 +772,24 @@ > POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ > }; > >+enum { >+ SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ >+ SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ >+}; >+ >+enum { >+ CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ >+ CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ >+ CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ >+ CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ >+ CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ >+ CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ >+ HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ >+ CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ >+ HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ >+ HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ >+}; >+ > /* ASF Subsystem Registers (Yukon-2 only) */ > enum { > B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ >@@ -1053,7 +1084,7 @@ > PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ > }; > >-#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) >+#define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) > > enum { > PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ >@@ -1149,13 +1180,13 @@ > PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ > PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; > >-#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK) >+#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) > /* 00=1x; 01=2x; 10=3x; 11=4x */ >-#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK) >+#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) > /* 00=dis; 01=1x; 10=2x; 11=3x */ >-#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2) >+#define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) > /* 000=1x; 001=2x; 010=3x; 011=4x */ >-#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK) >+#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) > /* 01X=0; 110=2.5; 111=25 (MHz) */ > > /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ >@@ -1166,7 +1197,7 @@ > }; > /* !!! Errata in spec. (1 = disable) */ > >-#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK) >+#define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) > /* 100=5x; 101=6x; 110=7x; 111=8x */ > enum { > MAC_TX_CLK_0_MHZ = 2, >@@ -1196,7 +1227,7 @@ > PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ > }; > >-#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK) >+#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) > > /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ > enum { >@@ -1226,7 +1257,7 @@ > PULS_1300MS = 7,/* 1.3 s to 2.7 s */ > }; > >-#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK) >+#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) > > enum { > BLINK_42MS = 0,/* 42 ms */ >@@ -1236,21 +1267,18 @@ > BLINK_670MS = 4,/* 670 ms */ > }; > >-/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ >-#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ >- /* Bit 13..12: reserved */ >-#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ >-#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ >-#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ >-#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ >-#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ >-#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ >- >+/**** PHY_MARV_LED_OVER 16 bit r/w LED control */ > enum { >- MO_LED_NORM = 0, >- MO_LED_BLINK = 1, >- MO_LED_OFF = 2, >- MO_LED_ON = 3, >+ PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */ >+ PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */ >+ PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */ >+ PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */ >+ PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */ >+ PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */ >+ >+ PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 >+ | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000 >+ | PHY_M_LED_MO_RX, > }; > > /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ >@@ -1287,9 +1315,9 @@ > PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ > }; > >-#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK) >-#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK) >-#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK) >+#define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) >+#define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) >+#define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) > > enum { > LED_PAR_CTRL_COLX = 0x00, >@@ -1318,6 +1346,14 @@ > }; > > /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ >+/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ >+enum { >+ PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */ >+ PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */ >+ PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */ >+}; >+ >+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ > /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ > enum { > PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ >@@ -1537,8 +1573,8 @@ > GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ > }; > >-#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) >-#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) >+#define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) >+#define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) > > /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ > enum { >@@ -1566,7 +1602,7 @@ > > GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | > GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | >- GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | >+ GMR_FS_MII_ERR | GMR_FS_BAD_FC | > GMR_FS_UN_SIZE | GMR_FS_JABBER, > }; > >@@ -1608,6 +1644,9 @@ > TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ > TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ > >+ TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ >+ TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ >+ > GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ > GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ > GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ >@@ -1641,6 +1680,39 @@ > Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ > Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ > }; >+/* HCU_CCSR CPU Control and Status Register */ >+enum { >+ HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */ >+ HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */ >+ /* Clock Stretching Timeout */ >+ HCU_CCSR_CS_TO = 1<<25, >+ HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ >+ >+ HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */ >+ HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */ >+ >+ HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ >+ HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ >+ >+ HCU_CCSR_SET_SYNC_CPU = 1<<5, >+ HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */ >+ HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3, >+ HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */ >+/* Microcontroller State */ >+ HCU_CCSR_UC_STATE_MSK = 3, >+ HCU_CCSR_UC_STATE_BASE = 1<<0, >+ HCU_CCSR_ASF_RESET = 0, >+ HCU_CCSR_ASF_HALTED = 1<<1, >+ HCU_CCSR_ASF_RUNNING = 1<<0, >+}; >+ >+/* HCU_HCSR Host Control and Status Register */ >+enum { >+ HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */ >+ >+ HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */ >+ HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */ >+}; > > /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ > enum { >@@ -1748,7 +1820,6 @@ > INIT_SUM= 1<<3, > LOCK_SUM= 1<<4, > INS_VLAN= 1<<5, >- FRC_STAT= 1<<6, > EOP = 1<<7, > }; > >@@ -1784,21 +1855,9 @@ > OP_TXINDEXLE = 0x68, > }; > >-/* Yukon 2 hardware interface >- * Not tested on big endian >- */ >+/* Yukon 2 hardware interface */ > struct sky2_tx_le { >- union { >- __le32 addr; >- struct { >- __le16 offset; >- __le16 start; >- } csum __attribute((packed)); >- struct { >- __le16 size; >- __le16 rsvd; >- } tso __attribute((packed)); >- } tx; >+ __le32 addr; > __le16 length; /* also vlan tag or checksum start */ > u8 ctrl; > u8 opcode; >@@ -1821,12 +1880,21 @@ > struct tx_ring_info { > struct sk_buff *skb; > DECLARE_PCI_UNMAP_ADDR(mapaddr); >- u16 idx; >+ DECLARE_PCI_UNMAP_ADDR(maplen); > }; > >-struct ring_info { >+struct rx_ring_info { > struct sk_buff *skb; >- dma_addr_t mapaddr; >+ dma_addr_t data_addr; >+ DECLARE_PCI_UNMAP_ADDR(data_size); >+ dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; >+}; >+ >+enum flow_control { >+ FC_NONE = 0, >+ FC_TX = 1, >+ FC_RX = 2, >+ FC_BOTH = 3, > }; > > struct sky2_port { >@@ -1836,7 +1904,6 @@ > u32 msg_enable; > spinlock_t phy_lock; > >- spinlock_t tx_lock ____cacheline_aligned_in_smp; > struct tx_ring_info *tx_ring; > struct sky2_tx_le *tx_le; > u16 tx_cons; /* next le to check */ >@@ -1844,14 +1911,17 @@ > u32 tx_addr64; > u16 tx_pending; > u16 tx_last_mss; >+ u32 tx_tcpsum; > >- struct ring_info *rx_ring ____cacheline_aligned_in_smp; >+ struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp; > struct sky2_rx_le *rx_le; > u32 rx_addr64; > u16 rx_next; /* next re to check */ > u16 rx_put; /* next le index to use */ > u16 rx_pending; >- u16 rx_bufsize; >+ u16 rx_data_size; >+ u16 rx_nfrags; >+ > #ifdef SKY2_VLAN_TAG_USED > u16 rx_tag; > struct vlan_group *vlgrp; >@@ -1863,9 +1933,9 @@ > u16 speed; /* SPEED_1000, SPEED_100, ... */ > u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ > u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ >- u8 rx_pause; >- u8 tx_pause; > u8 rx_csum; >+ enum flow_control flow_mode; >+ enum flow_control flow_status; > > struct net_device_stats net_stats; > >@@ -1876,10 +1946,9 @@ > struct pci_dev *pdev; > struct net_device *dev[2]; > >- int pm_cap; > u8 chip_id; > u8 chip_rev; >- u8 copper; >+ u8 pmd_type; > u8 ports; > > struct sky2_status_le *st_le; >@@ -1887,12 +1956,18 @@ > dma_addr_t st_dma; > > struct timer_list idle_timer; >- int msi_detected; >+ struct work_struct restart_work; >+ int msi; > wait_queue_head_t msi_wait; > > u32 pci_cfg_state[64 / sizeof(u32)]; > }; > >+static inline int sky2_is_copper(const struct sky2_hw *hw) >+{ >+ return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P'); >+} >+ > /* Register accessor for memory mapped device */ > static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) > { >--- linux-2.6.9/drivers/net/sky2.c.orig 2007-08-13 15:42:41.000000000 -0400 >+++ linux-2.6.9/drivers/net/sky2.c 2007-08-13 15:46:30.000000000 -0400 >@@ -10,8 +10,7 @@ > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by >- * the Free Software Foundation; either version 2 of the License, or >- * (at your option) any later version. >+ * the Free Software Foundation; either version 2 of the License. > * > * This program is distributed in the hope that it will be useful, > * but WITHOUT ANY WARRANTY; without even the implied warranty of >@@ -33,6 +32,7 @@ > #include <linux/ethtool.h> > #include <linux/pci.h> > #include <linux/ip.h> >+#include <net/ip.h> > #include <linux/tcp.h> > #include <linux/in.h> > #include <linux/delay.h> >@@ -51,19 +51,18 @@ > #include "sky2.h" > > #define DRV_NAME "sky2" >-#define DRV_VERSION "1.6" >+#define DRV_VERSION "1.14" > #define PFX DRV_NAME " " > > /* > * The Yukon II chipset takes 64 bit command blocks (called list elements) > * that are organized into three (receive, transmit, status) different rings >- * similar to Tigon3. A transmit can require several elements; >- * a receive requires one (or two if using 64 bit dma). >+ * similar to Tigon3. > */ > >-#define RX_LE_SIZE 512 >+#define RX_LE_SIZE 1024 > #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) >-#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) >+#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) > #define RX_DEF_PENDING RX_MAX_PENDING > #define RX_SKB_ALIGN 8 > #define RX_BUF_WRITE 16 >@@ -75,7 +74,6 @@ > > #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ > #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) >-#define ETH_JUMBO_MTU 9000 > #define TX_WATCHDOG (5 * HZ) > #define NAPI_WEIGHT 64 > #define PHY_RETRIES 1000 >@@ -91,7 +89,7 @@ > module_param(debug, int, 0); > MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); > >-static int copybreak __read_mostly = 256; >+static int copybreak __read_mostly = 128; > module_param(copybreak, int, 0); > MODULE_PARM_DESC(copybreak, "Receive copy threshold"); > >@@ -99,34 +97,41 @@ > module_param(disable_msi, int, 0); > MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); > >-static int idle_timeout = 100; >+static int idle_timeout = 0; > module_param(idle_timeout, int, 0); >-MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); >+MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)"); > > static const struct pci_device_id sky2_id_table[] = { >- { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, >- { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, >+ { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ >+ { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ > { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, >- { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, >+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ >+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ >+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ >+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ >+// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ > { 0 } > }; > >@@ -141,7 +146,7 @@ > static const char *yukon2_name[] = { > "XL", /* 0xb3 */ > "EC Ultra", /* 0xb4 */ >- "UNKNOWN", /* 0xb5 */ >+ "Extreme", /* 0xb5 */ > "EC", /* 0xb6 */ > "FE", /* 0xb7 */ > }; >@@ -193,100 +198,55 @@ > return v; > } > >-static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) >-{ >- u16 power_control; >- u32 reg1; >- int vaux; >- >- pr_debug("sky2_set_power_state %d\n", state); >- sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); >- >- power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); >- vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && >- (power_control & PCI_PM_CAP_PME_D3cold); >- >- power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); >- >- power_control |= PCI_PM_CTRL_PME_STATUS; >- power_control &= ~(PCI_PM_CTRL_STATE_MASK); >- >- switch (state) { >- case PCI_D0: >- /* switch power to VCC (WA for VAUX problem) */ >- sky2_write8(hw, B0_POWER_CTRL, >- PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); >- >- /* disable Core Clock Division, */ >- sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); >- >- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >- /* enable bits are inverted */ >- sky2_write8(hw, B2_Y2_CLK_GATE, >- Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | >- Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | >- Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); >- else >- sky2_write8(hw, B2_Y2_CLK_GATE, 0); > >- /* Turn off phy power saving */ >- reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); >- reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); >- >- /* looks like this XL is back asswards .. */ >- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { >- reg1 |= PCI_Y2_PHY1_COMA; >- if (hw->ports > 1) >- reg1 |= PCI_Y2_PHY2_COMA; >- } >- sky2_pci_write32(hw, PCI_DEV_REG1, reg1); >- udelay(100); >- >- if (hw->chip_id == CHIP_ID_YUKON_EC_U) { >- sky2_pci_write32(hw, PCI_DEV_REG3, 0); >- reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); >- reg1 &= P_ASPM_CONTROL_MSK; >- sky2_pci_write32(hw, PCI_DEV_REG4, reg1); >- sky2_pci_write32(hw, PCI_DEV_REG5, 0); >- } >- >- break; >+static void sky2_power_on(struct sky2_hw *hw) >+{ >+ /* switch power to VCC (WA for VAUX problem) */ >+ sky2_write8(hw, B0_POWER_CTRL, >+ PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); >+ >+ /* disable Core Clock Division, */ >+ sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); >+ >+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >+ /* enable bits are inverted */ >+ sky2_write8(hw, B2_Y2_CLK_GATE, >+ Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | >+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | >+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); >+ else >+ sky2_write8(hw, B2_Y2_CLK_GATE, 0); > >- case PCI_D3hot: >- case PCI_D3cold: >- /* Turn on phy power saving */ >- reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); >- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >- reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); >- else >- reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); >- sky2_pci_write32(hw, PCI_DEV_REG1, reg1); >- udelay(100); >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { >+ u32 reg1; > >- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >- sky2_write8(hw, B2_Y2_CLK_GATE, 0); >- else >- /* enable bits are inverted */ >- sky2_write8(hw, B2_Y2_CLK_GATE, >- Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | >- Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | >- Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); >- >- /* switch power to VAUX */ >- if (vaux && state != PCI_D3cold) >- sky2_write8(hw, B0_POWER_CTRL, >- (PC_VAUX_ENA | PC_VCC_ENA | >- PC_VAUX_ON | PC_VCC_OFF)); >- break; >- default: >- printk(KERN_ERR PFX "Unknown power state %d\n", state); >+ sky2_pci_write32(hw, PCI_DEV_REG3, 0); >+ reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); >+ reg1 &= P_ASPM_CONTROL_MSK; >+ sky2_pci_write32(hw, PCI_DEV_REG4, reg1); >+ sky2_pci_write32(hw, PCI_DEV_REG5, 0); > } >+} > >- sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); >- sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); >+static void sky2_power_aux(struct sky2_hw *hw) >+{ >+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >+ sky2_write8(hw, B2_Y2_CLK_GATE, 0); >+ else >+ /* enable bits are inverted */ >+ sky2_write8(hw, B2_Y2_CLK_GATE, >+ Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | >+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | >+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); >+ >+ /* switch power to VAUX */ >+ if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) >+ sky2_write8(hw, B0_POWER_CTRL, >+ (PC_VAUX_ENA | PC_VCC_ENA | >+ PC_VAUX_ON | PC_VCC_OFF)); > } > >-static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) >+static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) > { > u16 reg; > >@@ -305,29 +265,59 @@ > gma_write16(hw, port, GM_RX_CTRL, reg); > } > >+/* flow control to advertise bits */ >+static const u16 copper_fc_adv[] = { >+ [FC_NONE] = 0, >+ [FC_TX] = PHY_M_AN_ASP, >+ [FC_RX] = PHY_M_AN_PC, >+ [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, >+}; >+ >+/* flow control to advertise bits when using 1000BaseX */ >+static const u16 fiber_fc_adv[] = { >+ [FC_BOTH] = PHY_M_P_BOTH_MD_X, >+ [FC_TX] = PHY_M_P_ASYM_MD_X, >+ [FC_RX] = PHY_M_P_SYM_MD_X, >+ [FC_NONE] = PHY_M_P_NO_PAUSE_X, >+}; >+ >+/* flow control to GMA disable bits */ >+static const u16 gm_fc_disable[] = { >+ [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, >+ [FC_TX] = GM_GPCR_FC_RX_DIS, >+ [FC_RX] = GM_GPCR_FC_TX_DIS, >+ [FC_BOTH] = 0, >+}; >+ >+ > static void sky2_phy_init(struct sky2_hw *hw, unsigned port) > { > struct sky2_port *sky2 = netdev_priv(hw->dev[port]); >- u16 ctrl, ct1000, adv, pg, ledctrl, ledover; >+ u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; > >- if (sky2->autoneg == AUTONEG_ENABLE && >- !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { >+ if (sky2->autoneg == AUTONEG_ENABLE >+ && !(hw->chip_id == CHIP_ID_YUKON_XL >+ || hw->chip_id == CHIP_ID_YUKON_EC_U >+ || hw->chip_id == CHIP_ID_YUKON_EX)) { > u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); > > ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | > PHY_M_EC_MAC_S_MSK); > ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); > >+ /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ > if (hw->chip_id == CHIP_ID_YUKON_EC) >+ /* set downshift counter to 3x and enable downshift */ > ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; > else >- ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); >+ /* set master & slave downshift counter to 1x */ >+ ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); > > gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); > } > > ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); >- if (hw->copper) { >+ if (sky2_is_copper(hw)) { > if (hw->chip_id == CHIP_ID_YUKON_FE) { > /* enable automatic crossover */ > ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; >@@ -338,48 +328,56 @@ > /* enable automatic crossover */ > ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); > >- if (sky2->autoneg == AUTONEG_ENABLE && >- (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { >+ /* downshift on PHY 88E1112 and 88E1149 is changed */ >+ if (sky2->autoneg == AUTONEG_ENABLE >+ && (hw->chip_id == CHIP_ID_YUKON_XL >+ || hw->chip_id == CHIP_ID_YUKON_EC_U >+ || hw->chip_id == CHIP_ID_YUKON_EX)) { >+ /* set downshift counter to 3x and enable downshift */ > ctrl &= ~PHY_M_PC_DSC_MSK; > ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; > } > } >- gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); > } else { > /* workaround for deviation #4.88 (CRC errors) */ > /* disable Automatic Crossover */ > > ctrl &= ~PHY_M_PC_MDIX_MSK; >- gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); >+ } > >- if (hw->chip_id == CHIP_ID_YUKON_XL) { >- /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ >- gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); >- ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); >- ctrl &= ~PHY_M_MAC_MD_MSK; >- ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); >- gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); >+ gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); >+ >+ /* special setup for PHY 88E1112 Fiber */ >+ if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) { >+ pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); > >+ /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ >+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); >+ ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); >+ ctrl &= ~PHY_M_MAC_MD_MSK; >+ ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); >+ gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); >+ >+ if (hw->pmd_type == 'P') { > /* select page 1 to access Fiber registers */ > gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); >- } >- } > >- ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); >- if (sky2->autoneg == AUTONEG_DISABLE) >- ctrl &= ~PHY_CT_ANE; >- else >- ctrl |= PHY_CT_ANE; >+ /* for SFP-module set SIGDET polarity to low */ >+ ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); >+ ctrl |= PHY_M_FIB_SIGD_POL; >+ gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); >+ } > >- ctrl |= PHY_CT_RESET; >- gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); >+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); >+ } > >- ctrl = 0; >+ ctrl = PHY_CT_RESET; > ct1000 = 0; > adv = PHY_AN_CSMA; >+ reg = 0; > > if (sky2->autoneg == AUTONEG_ENABLE) { >- if (hw->copper) { >+ if (sky2_is_copper(hw)) { > if (sky2->advertising & ADVERTISED_1000baseT_Full) > ct1000 |= PHY_M_1000C_AFD; > if (sky2->advertising & ADVERTISED_1000baseT_Half) >@@ -392,16 +390,16 @@ > adv |= PHY_M_AN_10_FD; > if (sky2->advertising & ADVERTISED_10baseT_Half) > adv |= PHY_M_AN_10_HD; >- } else /* special defines for FIBER (88E1011S only) */ >- adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; > >- /* Set Flow-control capabilities */ >- if (sky2->tx_pause && sky2->rx_pause) >- adv |= PHY_AN_PAUSE_CAP; /* symmetric */ >- else if (sky2->rx_pause && !sky2->tx_pause) >- adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; >- else if (!sky2->rx_pause && sky2->tx_pause) >- adv |= PHY_AN_PAUSE_ASYM; /* local */ >+ adv |= copper_fc_adv[sky2->flow_mode]; >+ } else { /* special defines for FIBER (88E1040S only) */ >+ if (sky2->advertising & ADVERTISED_1000baseT_Full) >+ adv |= PHY_M_AN_1000X_AFD; >+ if (sky2->advertising & ADVERTISED_1000baseT_Half) >+ adv |= PHY_M_AN_1000X_AHD; >+ >+ adv |= fiber_fc_adv[sky2->flow_mode]; >+ } > > /* Restart Auto-negotiation */ > ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; >@@ -409,21 +407,38 @@ > /* forced speed/duplex settings */ > ct1000 = PHY_M_1000C_MSE; > >- if (sky2->duplex == DUPLEX_FULL) >- ctrl |= PHY_CT_DUP_MD; >+ /* Disable auto update for duplex flow control and speed */ >+ reg |= GM_GPCR_AU_ALL_DIS; > > switch (sky2->speed) { > case SPEED_1000: > ctrl |= PHY_CT_SP1000; >+ reg |= GM_GPCR_SPEED_1000; > break; > case SPEED_100: > ctrl |= PHY_CT_SP100; >+ reg |= GM_GPCR_SPEED_100; > break; > } > >- ctrl |= PHY_CT_RESET; >+ if (sky2->duplex == DUPLEX_FULL) { >+ reg |= GM_GPCR_DUP_FULL; >+ ctrl |= PHY_CT_DUP_MD; >+ } else if (sky2->speed < SPEED_1000) >+ sky2->flow_mode = FC_NONE; >+ >+ >+ reg |= gm_fc_disable[sky2->flow_mode]; >+ >+ /* Forward pause packets to GMAC? */ >+ if (sky2->flow_mode & FC_RX) >+ sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); >+ else >+ sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); > } > >+ gma_write16(hw, port, GM_GP_CTRL, reg); >+ > if (hw->chip_id != CHIP_ID_YUKON_FE) > gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); > >@@ -473,7 +488,9 @@ > /* restore page register */ > gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); > break; >+ > case CHIP_ID_YUKON_EC_U: >+ case CHIP_ID_YUKON_EX: > pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); > > /* select page 3 to access LED control register */ >@@ -497,12 +514,12 @@ > /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ > ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; > /* turn off the Rx LED (LED_RX) */ >- ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); >+ ledover &= ~PHY_M_LED_MO_RX; > } > >- if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && >+ hw->chip_rev == CHIP_REV_YU_EC_U_A1) { > /* apply fixes in PHY AFE */ >- pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); > gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); > > /* increase differential signal amplitude in 10BASE-T */ >@@ -514,19 +531,20 @@ > gm_phy_write(hw, port, 0x17, 0x2002); > > /* set page register to 0 */ >- gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); >- } else { >+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); >+ } else if (hw->chip_id != CHIP_ID_YUKON_EX) { > gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); > > if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { > /* turn on 100 Mbps LED (LED_LINK100) */ >- ledover |= PHY_M_LED_MO_100(MO_LED_ON); >+ ledover |= PHY_M_LED_MO_100; > } > > if (ledover) > gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); > > } >+ > /* Enable phy interrupt on auto-negotiation complete (or link up) */ > if (sky2->autoneg == AUTONEG_ENABLE) > gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); >@@ -534,6 +552,30 @@ > gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); > } > >+static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) >+{ >+ u32 reg1; >+ static const u32 phy_power[] >+ = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; >+ >+ /* looks like this XL is back asswards .. */ >+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) >+ onoff = !onoff; >+ >+ sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); >+ reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); >+ if (onoff) >+ /* Turn off phy power saving */ >+ reg1 &= ~phy_power[port]; >+ else >+ reg1 |= phy_power[port]; >+ >+ sky2_pci_write32(hw, PCI_DEV_REG1, reg1); >+ sky2_pci_read32(hw, PCI_DEV_REG1); >+ sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); >+ udelay(100); >+} >+ > /* Force a renegotiation */ > static void sky2_phy_reinit(struct sky2_port *sky2) > { >@@ -566,49 +608,11 @@ > gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); > } > >- if (sky2->autoneg == AUTONEG_DISABLE) { >- reg = gma_read16(hw, port, GM_GP_CTRL); >- reg |= GM_GPCR_AU_ALL_DIS; >- gma_write16(hw, port, GM_GP_CTRL, reg); >- gma_read16(hw, port, GM_GP_CTRL); >- >- switch (sky2->speed) { >- case SPEED_1000: >- reg &= ~GM_GPCR_SPEED_100; >- reg |= GM_GPCR_SPEED_1000; >- break; >- case SPEED_100: >- reg &= ~GM_GPCR_SPEED_1000; >- reg |= GM_GPCR_SPEED_100; >- break; >- case SPEED_10: >- reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); >- break; >- } >- >- if (sky2->duplex == DUPLEX_FULL) >- reg |= GM_GPCR_DUP_FULL; >- >- /* turn off pause in 10/100mbps half duplex */ >- else if (sky2->speed != SPEED_1000 && >- hw->chip_id != CHIP_ID_YUKON_EC_U) >- sky2->tx_pause = sky2->rx_pause = 0; >- } else >- reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; >- >- if (!sky2->tx_pause && !sky2->rx_pause) { >- sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); >- reg |= >- GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; >- } else if (sky2->tx_pause && !sky2->rx_pause) { >- /* disable Rx flow-control */ >- reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; >- } >- >- gma_write16(hw, port, GM_GP_CTRL, reg); >- > sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); > >+ /* Enable Transmit FIFO Underrun */ >+ sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); >+ > spin_lock_bh(&sky2->phy_lock); > sky2_phy_init(hw, port); > spin_unlock_bh(&sky2->phy_lock); >@@ -666,38 +670,40 @@ > /* Flush Rx MAC FIFO on any flow control or error */ > sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); > >- /* Set threshold to 0xa (64 bytes) >- * ASF disabled so no need to do WA dev #4.30 >- */ >- sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); >+ /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ >+ sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); > > /* Configure Tx MAC FIFO */ > sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); > sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); > >- if (hw->chip_id == CHIP_ID_YUKON_EC_U) { >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { > sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); > sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); >- if (hw->dev[port]->mtu > ETH_DATA_LEN) { >- /* set Tx GMAC FIFO Almost Empty Threshold */ >- sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); >- /* Disable Store & Forward mode for TX */ >- sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); >- } >+ >+ /* set Tx GMAC FIFO Almost Empty Threshold */ >+ sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), >+ (ECU_JUMBO_WM << 16) | ECU_AE_THR); >+ >+ if (hw->dev[port]->mtu > ETH_DATA_LEN) >+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), >+ TX_JUMBO_ENA | TX_STFW_DIS); >+ else >+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), >+ TX_JUMBO_DIS | TX_STFW_ENA); > } > > } > >-/* Assign Ram Buffer allocation. >- * start and end are in units of 4k bytes >- * ram registers are in units of 64bit words >- */ >-static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) >+/* Assign Ram Buffer allocation to queue */ >+static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) > { >- u32 start, end; >+ u32 end; > >- start = startk * 4096/8; >- end = (endk * 4096/8) - 1; >+ /* convert from K bytes to qwords used for hw register */ >+ start *= 1024/8; >+ space *= 1024/8; >+ end = start + space - 1; > > sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); > sky2_write32(hw, RB_ADDR(q, RB_START), start); >@@ -706,7 +712,6 @@ > sky2_write32(hw, RB_ADDR(q, RB_RP), start); > > if (q == Q_R1 || q == Q_R2) { >- u32 space = (endk - startk) * 4096/8; > u32 tp = space - space/4; > > /* On receive queue's set the thresholds >@@ -760,14 +765,24 @@ > struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; > > sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); >+ le->ctrl = 0; > return le; > } > >+static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2, >+ struct sky2_tx_le *le) >+{ >+ return sky2->tx_ring + (le - sky2->tx_le); >+} >+ > /* Update chip's next pointer */ > static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) > { >+ /* Make sure write' to descriptors are complete before we tell hardware */ > wmb(); > sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); >+ >+ /* Synchronize I/O on since next processor may write to tail */ > mmiowb(); > } > >@@ -776,6 +791,7 @@ > { > struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; > sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); >+ le->ctrl = 0; > return le; > } > >@@ -785,17 +801,16 @@ > return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; > } > >-/* Build description to hardware about buffer */ >-static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) >+/* Build description to hardware for one receive segment */ >+static void sky2_rx_add(struct sky2_port *sky2, u8 op, >+ dma_addr_t map, unsigned len) > { > struct sky2_rx_le *le; > u32 hi = high32(map); >- u16 len = sky2->rx_bufsize; > > if (sky2->rx_addr64 != hi) { > le = sky2_next_rx(sky2); > le->addr = cpu_to_le32(hi); >- le->ctrl = 0; > le->opcode = OP_ADDR64 | HW_OWNER; > sky2->rx_addr64 = high32(map + len); > } >@@ -803,11 +818,53 @@ > le = sky2_next_rx(sky2); > le->addr = cpu_to_le32((u32) map); > le->length = cpu_to_le16(len); >- le->ctrl = 0; >- le->opcode = OP_PACKET | HW_OWNER; >+ le->opcode = op | HW_OWNER; >+} >+ >+/* Build description to hardware for one possibly fragmented skb */ >+static void sky2_rx_submit(struct sky2_port *sky2, >+ const struct rx_ring_info *re) >+{ >+ int i; >+ >+ sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); >+ >+ for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) >+ sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); > } > > >+static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, >+ unsigned size) >+{ >+ struct sk_buff *skb = re->skb; >+ int i; >+ >+ re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); >+ pci_unmap_len_set(re, data_size, size); >+ >+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) >+ re->frag_addr[i] = pci_map_page(pdev, >+ skb_shinfo(skb)->frags[i].page, >+ skb_shinfo(skb)->frags[i].page_offset, >+ skb_shinfo(skb)->frags[i].size, >+ PCI_DMA_FROMDEVICE); >+} >+ >+static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) >+{ >+ struct sk_buff *skb = re->skb; >+ int i; >+ >+ pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size), >+ PCI_DMA_FROMDEVICE); >+ >+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) >+ pci_unmap_page(pdev, re->frag_addr[i], >+ skb_shinfo(skb)->frags[i].size, >+ PCI_DMA_FROMDEVICE); >+} >+ > /* Tell chip where to start receive checksum. > * Actually has two checksums, but set both same to avoid possible byte > * order problems. >@@ -817,7 +874,7 @@ > struct sky2_rx_le *le; > > le = sky2_next_rx(sky2); >- le->addr = (ETH_HLEN << 16) | ETH_HLEN; >+ le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); > le->ctrl = 0; > le->opcode = OP_TCPSTART | HW_OWNER; > >@@ -858,6 +915,7 @@ > > /* reset the Rx prefetch unit */ > sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); >+ mmiowb(); > } > > /* Clean out receive buffer area, assumes receiver hardware stopped */ >@@ -867,12 +925,10 @@ > > memset(sky2->rx_le, 0, RX_LE_BYTES); > for (i = 0; i < sky2->rx_pending; i++) { >- struct ring_info *re = sky2->rx_ring + i; >+ struct rx_ring_info *re = sky2->rx_ring + i; > > if (re->skb) { >- pci_unmap_single(sky2->hw->pdev, >- re->mapaddr, sky2->rx_bufsize, >- PCI_DMA_FROMDEVICE); >+ sky2_rx_unmap_skb(sky2->hw->pdev, re); > kfree_skb(re->skb); > re->skb = NULL; > } >@@ -926,13 +982,13 @@ > struct sky2_hw *hw = sky2->hw; > u16 port = sky2->port; > >- spin_lock_bh(&sky2->tx_lock); >+ netif_tx_lock_bh(dev); > > sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); > sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); > sky2->vlgrp = grp; > >- spin_unlock_bh(&sky2->tx_lock); >+ netif_tx_unlock_bh(dev); > } > > static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) >@@ -941,80 +997,137 @@ > struct sky2_hw *hw = sky2->hw; > u16 port = sky2->port; > >- spin_lock_bh(&sky2->tx_lock); >+ netif_tx_lock_bh(dev); > > sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); > sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); > if (sky2->vlgrp) > sky2->vlgrp->vlan_devices[vid] = NULL; > >- spin_unlock_bh(&sky2->tx_lock); >+ netif_tx_unlock_bh(dev); > } > #endif > > /* >+ * Allocate an skb for receiving. If the MTU is large enough >+ * make the skb non-linear with a fragment list of pages. >+ * > * It appears the hardware has a bug in the FIFO logic that > * cause it to hang if the FIFO gets overrun and the receive buffer >- * is not aligned. ALso alloc_skb() won't align properly if slab >- * debugging is enabled. >+ * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is >+ * aligned except if slab debugging is enabled. > */ >-static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) >+static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2) > { > struct sk_buff *skb; >+ unsigned long p; >+ int i; > >- skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); >- if (likely(skb)) { >- unsigned long p = (unsigned long) skb->data; >- skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); >+ skb = alloc_skb(sky2->rx_data_size + RX_SKB_ALIGN, GFP_ATOMIC); >+ if (!skb) >+ goto nomem; >+ >+ p = (unsigned long) skb->data; >+ skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); >+ >+ for (i = 0; i < sky2->rx_nfrags; i++) { >+ struct page *page = alloc_page(GFP_ATOMIC); >+ >+ if (!page) >+ goto free_partial; >+ skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); > } > > return skb; >+free_partial: >+ kfree_skb(skb); >+nomem: >+ return NULL; > } > > /* > * Allocate and setup receiver buffer pool. >- * In case of 64 bit dma, there are 2X as many list elements >- * available as ring entries >- * and need to reserve one list element so we don't wrap around. >+ * Normal case this ends up creating one list element for skb >+ * in the receive ring. Worst case if using large MTU and each >+ * allocation falls on a different 64 bit region, that results >+ * in 6 list elements per ring entry. >+ * One element is used for checksum enable/disable, and one >+ * extra to avoid wrap. > */ > static int sky2_rx_start(struct sky2_port *sky2) > { > struct sky2_hw *hw = sky2->hw; >+ struct rx_ring_info *re; > unsigned rxq = rxqaddr[sky2->port]; >- int i; >- unsigned thresh; >+ unsigned i, size, space, thresh; > > sky2->rx_put = sky2->rx_next = 0; > sky2_qset(hw, rxq); > >- if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { >- /* MAC Rx RAM Read is controlled by hardware */ >+ /* On PCI express lowering the watermark gives better performance */ >+ if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) >+ sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); >+ >+ /* These chips have no ram buffer? >+ * MAC Rx RAM Read is controlled by hardware */ >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && >+ (hw->chip_rev == CHIP_REV_YU_EC_U_A1 >+ || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) > sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); >- } > > sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); > > rx_set_checksum(sky2); >+ >+ /* Space needed for frame data + headers rounded up */ >+ size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8) >+ + 8; >+ >+ /* Stopping point for hardware truncation */ >+ thresh = (size - 8) / sizeof(u32); >+ >+ /* Account for overhead of skb - to avoid order > 0 allocation */ >+ space = SKB_DATA_ALIGN(size) + NET_SKB_PAD >+ + sizeof(struct skb_shared_info); >+ >+ sky2->rx_nfrags = space >> PAGE_SHIFT; >+ BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); >+ >+ if (sky2->rx_nfrags != 0) { >+ /* Compute residue after pages */ >+ space = sky2->rx_nfrags << PAGE_SHIFT; >+ >+ if (space < size) >+ size -= space; >+ else >+ size = 0; >+ >+ /* Optimize to handle small packets and headers */ >+ if (size < copybreak) >+ size = copybreak; >+ if (size < ETH_HLEN) >+ size = ETH_HLEN; >+ } >+ sky2->rx_data_size = size; >+ >+ /* Fill Rx ring */ > for (i = 0; i < sky2->rx_pending; i++) { >- struct ring_info *re = sky2->rx_ring + i; >+ re = sky2->rx_ring + i; > >- re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); >+ re->skb = sky2_rx_alloc(sky2); > if (!re->skb) > goto nomem; > >- re->mapaddr = pci_map_single(hw->pdev, re->skb->data, >- sky2->rx_bufsize, PCI_DMA_FROMDEVICE); >- sky2_rx_add(sky2, re->mapaddr); >+ sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size); >+ sky2_rx_submit(sky2, re); > } > >- > /* > * The receiver hangs if it receives frames larger than the > * packet buffer. As a workaround, truncate oversize frames, but > * the register is limited to 9 bits, so if you do frames > 2052 > * you better get the MTU right! > */ >- thresh = (sky2->rx_bufsize - 8) / sizeof(u32); > if (thresh > 0x1ff) > sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); > else { >@@ -1022,9 +1135,8 @@ > sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); > } > >- > /* Tell chip about available buffers */ >- sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); >+ sky2_put_idx(hw, rxq, sky2->rx_put); > return 0; > nomem: > sky2_rx_clean(sky2); >@@ -1037,7 +1149,7 @@ > struct sky2_port *sky2 = netdev_priv(dev); > struct sky2_hw *hw = sky2->hw; > unsigned port = sky2->port; >- u32 ramsize, rxspace, imask; >+ u32 ramsize, imask; > int cap, err = -ENOMEM; > struct net_device *otherdev = hw->dev[sky2->port^1]; > >@@ -1081,36 +1193,41 @@ > goto err_out; > memset(sky2->rx_le, 0, RX_LE_BYTES); > >- sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), >+ sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), > GFP_KERNEL); > if (!sky2->rx_ring) > goto err_out; > >+ sky2_phy_power(hw, port, 1); >+ > sky2_mac_init(hw, port); > >- /* Determine available ram buffer space (in 4K blocks). >- * Note: not sure about the FE setting below yet >- */ >- if (hw->chip_id == CHIP_ID_YUKON_FE) >- ramsize = 4; >- else >- ramsize = sky2_read8(hw, B2_E_0); >+ /* Register is number of 4K blocks on internal RAM buffer. */ >+ ramsize = sky2_read8(hw, B2_E_0) * 4; >+ printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize); > >- /* Give transmitter one third (rounded up) */ >- rxspace = ramsize - (ramsize + 2) / 3; >+ if (ramsize > 0) { >+ u32 rxspace; > >- sky2_ramset(hw, rxqaddr[port], 0, rxspace); >- sky2_ramset(hw, txqaddr[port], rxspace, ramsize); >+ if (ramsize < 16) >+ rxspace = ramsize / 2; >+ else >+ rxspace = 8 + (2*(ramsize - 16))/3; > >- /* Make sure SyncQ is disabled */ >- sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), >- RB_RST_SET); >+ sky2_ramset(hw, rxqaddr[port], 0, rxspace); >+ sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); >+ >+ /* Make sure SyncQ is disabled */ >+ sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), >+ RB_RST_SET); >+ } > > sky2_qset(hw, txqaddr[port]); > > /* Set almost empty threshold */ >- if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) >- sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U >+ && hw->chip_rev == CHIP_REV_YU_EC_U_A0) >+ sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); > > sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, > TX_RING_SIZE - 1); >@@ -1180,8 +1297,6 @@ > * A single packet can generate multiple list elements, and > * the number of ring elements will probably be less than the number > * of list elements used. >- * >- * No BH disabling for tx_lock here (like tg3) > */ > static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) > { >@@ -1190,33 +1305,13 @@ > struct sky2_tx_le *le = NULL; > struct tx_ring_info *re; > unsigned i, len; >- int avail; > dma_addr_t mapping; > u32 addr64; > u16 mss; > u8 ctrl; > >- /* No BH disabling for tx_lock here. We are running in BH disabled >- * context and TX reclaim runs via poll inside of a software >- * interrupt, and no related locks in IRQ processing. >- */ >- if (!spin_trylock(&sky2->tx_lock)) >- return NETDEV_TX_LOCKED; >- >- if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { >- /* There is a known but harmless race with lockless tx >- * and netif_stop_queue. >- */ >- if (!netif_queue_stopped(dev)) { >- netif_stop_queue(dev); >- if (net_ratelimit()) >- printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", >- dev->name); >- } >- spin_unlock(&sky2->tx_lock); >- >- return NETDEV_TX_BUSY; >- } >+ if (unlikely(tx_avail(sky2) < tx_le_req(skb))) >+ return NETDEV_TX_BUSY; > > if (unlikely(netif_msg_tx_queued(sky2))) > printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", >@@ -1226,13 +1321,10 @@ > mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); > addr64 = high32(mapping); > >- re = sky2->tx_ring + sky2->tx_prod; >- > /* Send high bits if changed or crosses boundary */ > if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { > le = get_tx_le(sky2); >- le->tx.addr = cpu_to_le32(addr64); >- le->ctrl = 0; >+ le->addr = cpu_to_le32(addr64); > le->opcode = OP_ADDR64 | HW_OWNER; > sky2->tx_addr64 = high32(mapping + len); > } >@@ -1240,25 +1332,16 @@ > /* Check for TCP Segmentation Offload */ > mss = skb_shinfo(skb)->tso_size; > if (mss != 0) { >- /* just drop the packet if non-linear expansion fails */ >- if (skb_header_cloned(skb) && >- pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { >- dev_kfree_skb(skb); >- goto out_unlock; >- } >- >- mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ >- mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); >+ mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ >+ mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); > mss += ETH_HLEN; >- } > >- if (mss != sky2->tx_last_mss) { >- le = get_tx_le(sky2); >- le->tx.tso.size = cpu_to_le16(mss); >- le->tx.tso.rsvd = 0; >- le->opcode = OP_LRGLEN | HW_OWNER; >- le->ctrl = 0; >- sky2->tx_last_mss = mss; >+ if (mss != sky2->tx_last_mss) { >+ le = get_tx_le(sky2); >+ le->addr = cpu_to_le32(mss); >+ le->opcode = OP_LRGLEN | HW_OWNER; >+ sky2->tx_last_mss = mss; >+ } > } > > ctrl = 0; >@@ -1267,9 +1350,8 @@ > if (sky2->vlgrp && vlan_tx_tag_present(skb)) { > if (!le) { > le = get_tx_le(sky2); >- le->tx.addr = 0; >+ le->addr = 0; > le->opcode = OP_VLAN|HW_OWNER; >- le->ctrl = 0; > } else > le->opcode |= OP_VLAN; > le->length = cpu_to_be16(vlan_tx_tag_get(skb)); >@@ -1279,72 +1361,71 @@ > > /* Handle TCP checksum offload */ > if (skb->ip_summed == CHECKSUM_HW) { >- u16 hdr = skb->h.raw - skb->data; >- u16 offset = hdr + skb->csum; >+ u32 tcpsum; >+ unsigned offset = skb->h.raw - skb->data;; >+ >+ tcpsum = offset << 16; /* sum start */ >+ tcpsum |= offset + skb->csum; /* sum write */ > > ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; > if (skb->nh.iph->protocol == IPPROTO_UDP) > ctrl |= UDPTCP; > >- le = get_tx_le(sky2); >- le->tx.csum.start = cpu_to_le16(hdr); >- le->tx.csum.offset = cpu_to_le16(offset); >- le->length = 0; /* initial checksum value */ >- le->ctrl = 1; /* one packet */ >- le->opcode = OP_TCPLISW | HW_OWNER; >+ if (tcpsum != sky2->tx_tcpsum) { >+ sky2->tx_tcpsum = tcpsum; >+ >+ le = get_tx_le(sky2); >+ le->addr = cpu_to_le32(tcpsum); >+ le->length = 0; /* initial checksum value */ >+ le->ctrl = 1; /* one packet */ >+ le->opcode = OP_TCPLISW | HW_OWNER; >+ } > } > > le = get_tx_le(sky2); >- le->tx.addr = cpu_to_le32((u32) mapping); >+ le->addr = cpu_to_le32((u32) mapping); > le->length = cpu_to_le16(len); > le->ctrl = ctrl; > le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); > >- /* Record the transmit mapping info */ >+ re = tx_le_re(sky2, le); > re->skb = skb; > pci_unmap_addr_set(re, mapaddr, mapping); >+ pci_unmap_len_set(re, maplen, len); > > for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { >- skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; >- struct tx_ring_info *fre; >+ const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; > > mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, > frag->size, PCI_DMA_TODEVICE); > addr64 = high32(mapping); > if (addr64 != sky2->tx_addr64) { > le = get_tx_le(sky2); >- le->tx.addr = cpu_to_le32(addr64); >+ le->addr = cpu_to_le32(addr64); > le->ctrl = 0; > le->opcode = OP_ADDR64 | HW_OWNER; > sky2->tx_addr64 = addr64; > } > > le = get_tx_le(sky2); >- le->tx.addr = cpu_to_le32((u32) mapping); >+ le->addr = cpu_to_le32((u32) mapping); > le->length = cpu_to_le16(frag->size); > le->ctrl = ctrl; > le->opcode = OP_BUFFER | HW_OWNER; > >- fre = sky2->tx_ring >- + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); >- pci_unmap_addr_set(fre, mapaddr, mapping); >+ re = tx_le_re(sky2, le); >+ re->skb = skb; >+ pci_unmap_addr_set(re, mapaddr, mapping); >+ pci_unmap_len_set(re, maplen, frag->size); > } > >- re->idx = sky2->tx_prod; > le->ctrl |= EOP; > >- avail = tx_avail(sky2); >- if (mss != 0 || avail < TX_MIN_PENDING) { >- le->ctrl |= FRC_STAT; >- if (avail <= MAX_SKB_TX_LE) >- netif_stop_queue(dev); >- } >+ if (tx_avail(sky2) <= MAX_SKB_TX_LE) >+ netif_stop_queue(dev); > > sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); > >-out_unlock: >- spin_unlock(&sky2->tx_lock); >- > dev->trans_start = jiffies; > return NETDEV_TX_OK; > } >@@ -1353,59 +1434,64 @@ > * Free ring elements from starting at tx_cons until "done" > * > * NB: the hardware will tell us about partial completion of multi-part >- * buffers; these are deferred until completion. >+ * buffers so make sure not to free skb to early. > */ > static void sky2_tx_complete(struct sky2_port *sky2, u16 done) > { > struct net_device *dev = sky2->netdev; > struct pci_dev *pdev = sky2->hw->pdev; >- u16 nxt, put; >- unsigned i; >+ unsigned idx; > > BUG_ON(done >= TX_RING_SIZE); > >- if (unlikely(netif_msg_tx_done(sky2))) >- printk(KERN_DEBUG "%s: tx done, up to %u\n", >- dev->name, done); >- >- for (put = sky2->tx_cons; put != done; put = nxt) { >- struct tx_ring_info *re = sky2->tx_ring + put; >- struct sk_buff *skb = re->skb; >- >- nxt = re->idx; >- BUG_ON(nxt >= TX_RING_SIZE); >- prefetch(sky2->tx_ring + nxt); >- >- /* Check for partial status */ >- if (tx_dist(put, done) < tx_dist(put, nxt)) >+ for (idx = sky2->tx_cons; idx != done; >+ idx = RING_NEXT(idx, TX_RING_SIZE)) { >+ struct sky2_tx_le *le = sky2->tx_le + idx; >+ struct tx_ring_info *re = sky2->tx_ring + idx; >+ >+ switch(le->opcode & ~HW_OWNER) { >+ case OP_LARGESEND: >+ case OP_PACKET: >+ pci_unmap_single(pdev, >+ pci_unmap_addr(re, mapaddr), >+ pci_unmap_len(re, maplen), >+ PCI_DMA_TODEVICE); > break; >- >- skb = re->skb; >- pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), >- skb_headlen(skb), PCI_DMA_TODEVICE); >- >- for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { >- struct tx_ring_info *fre; >- fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE); >- pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), >- skb_shinfo(skb)->frags[i].size, >+ case OP_BUFFER: >+ pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr), >+ pci_unmap_len(re, maplen), > PCI_DMA_TODEVICE); >+ break; >+ } >+ >+ if (le->ctrl & EOP) { >+ if (unlikely(netif_msg_tx_done(sky2))) >+ printk(KERN_DEBUG "%s: tx done %u\n", >+ dev->name, idx); >+ sky2->net_stats.tx_packets++; >+ sky2->net_stats.tx_bytes += re->skb->len; >+ >+ dev_kfree_skb_any(re->skb); > } > >- dev_kfree_skb(skb); >+ le->opcode = 0; /* paranoia */ > } > >- sky2->tx_cons = put; >+ sky2->tx_cons = idx; >+ smp_mb(); >+ > if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) > netif_wake_queue(dev); > } > > /* Cleanup all untransmitted buffers, assume transmitter not running */ >-static void sky2_tx_clean(struct sky2_port *sky2) >+static void sky2_tx_clean(struct net_device *dev) > { >- spin_lock_bh(&sky2->tx_lock); >+ struct sky2_port *sky2 = netdev_priv(dev); >+ >+ netif_tx_lock_bh(dev); > sky2_tx_complete(sky2, sky2->tx_prod); >- spin_unlock_bh(&sky2->tx_lock); >+ netif_tx_unlock_bh(dev); > } > > /* Network shutdown */ >@@ -1426,8 +1512,14 @@ > > /* Stop more packets from being queued */ > netif_stop_queue(dev); >+ netif_carrier_off(dev); > >- sky2_phy_reset(hw, port); >+ /* Disable port IRQ */ >+ imask = sky2_read32(hw, B0_IMSK); >+ imask &= ~portirq_msk[port]; >+ sky2_write32(hw, B0_IMSK, imask); >+ >+ sky2_gmac_reset(hw, port); > > /* Stop transmitter */ > sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); >@@ -1470,17 +1562,14 @@ > sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); > sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); > >- /* Disable port IRQ */ >- imask = sky2_read32(hw, B0_IMSK); >- imask &= ~portirq_msk[port]; >- sky2_write32(hw, B0_IMSK, imask); >+ sky2_phy_power(hw, port, 0); > > /* turn off LED's */ > sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); > > synchronize_irq(hw->pdev->irq); > >- sky2_tx_clean(sky2); >+ sky2_tx_clean(dev); > sky2_rx_clean(sky2); > > pci_free_consistent(hw->pdev, RX_LE_BYTES, >@@ -1503,7 +1592,7 @@ > > static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) > { >- if (!hw->copper) >+ if (!sky2_is_copper(hw)) > return SPEED_1000; > > if (hw->chip_id == CHIP_ID_YUKON_FE) >@@ -1524,41 +1613,17 @@ > struct sky2_hw *hw = sky2->hw; > unsigned port = sky2->port; > u16 reg; >- >- /* Enable Transmit FIFO Underrun */ >- sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); >- >- reg = gma_read16(hw, port, GM_GP_CTRL); >- if (sky2->autoneg == AUTONEG_DISABLE) { >- reg |= GM_GPCR_AU_ALL_DIS; >- >- /* Is write/read necessary? Copied from sky2_mac_init */ >- gma_write16(hw, port, GM_GP_CTRL, reg); >- gma_read16(hw, port, GM_GP_CTRL); >- >- switch (sky2->speed) { >- case SPEED_1000: >- reg &= ~GM_GPCR_SPEED_100; >- reg |= GM_GPCR_SPEED_1000; >- break; >- case SPEED_100: >- reg &= ~GM_GPCR_SPEED_1000; >- reg |= GM_GPCR_SPEED_100; >- break; >- case SPEED_10: >- reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); >- break; >- } >- } else >- reg &= ~GM_GPCR_AU_ALL_DIS; >- >- if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) >- reg |= GM_GPCR_DUP_FULL; >+ static const char *fc_name[] = { >+ [FC_NONE] = "none", >+ [FC_TX] = "tx", >+ [FC_RX] = "rx", >+ [FC_BOTH] = "both", >+ }; > > /* enable Rx/Tx */ >+ reg = gma_read16(hw, port, GM_GP_CTRL); > reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; > gma_write16(hw, port, GM_GP_CTRL, reg); >- gma_read16(hw, port, GM_GP_CTRL); > > gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); > >@@ -1569,7 +1634,9 @@ > sky2_write8(hw, SK_REG(port, LNK_LED_REG), > LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); > >- if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) { >+ if (hw->chip_id == CHIP_ID_YUKON_XL >+ || hw->chip_id == CHIP_ID_YUKON_EC_U >+ || hw->chip_id == CHIP_ID_YUKON_EX) { > u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); > u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ > >@@ -1597,8 +1664,7 @@ > "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", > sky2->netdev->name, sky2->speed, > sky2->duplex == DUPLEX_FULL ? "full" : "half", >- (sky2->tx_pause && sky2->rx_pause) ? "both" : >- sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); >+ fc_name[sky2->flow_status]); > } > > static void sky2_link_down(struct sky2_port *sky2) >@@ -1612,14 +1678,6 @@ > reg = gma_read16(hw, port, GM_GP_CTRL); > reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); > gma_write16(hw, port, GM_GP_CTRL, reg); >- gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ >- >- if (sky2->rx_pause && !sky2->tx_pause) { >- /* restore Asymmetric Pause bit */ >- gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, >- gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) >- | PHY_M_AN_ASP); >- } > > netif_carrier_off(sky2->netdev); > netif_stop_queue(sky2->netdev); >@@ -1629,48 +1687,74 @@ > > if (netif_msg_link(sky2)) > printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); >+ > sky2_phy_init(hw, port); > } > >+static enum flow_control sky2_flow(int rx, int tx) >+{ >+ if (rx) >+ return tx ? FC_BOTH : FC_RX; >+ else >+ return tx ? FC_TX : FC_NONE; >+} >+ > static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) > { > struct sky2_hw *hw = sky2->hw; > unsigned port = sky2->port; >- u16 lpa; >+ u16 advert, lpa; > >+ advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); > lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); >- > if (lpa & PHY_M_AN_RF) { > printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); > return -1; > } > >- if (hw->chip_id != CHIP_ID_YUKON_FE && >- gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { >- printk(KERN_ERR PFX "%s: master/slave fault", >- sky2->netdev->name); >- return -1; >- } >- > if (!(aux & PHY_M_PS_SPDUP_RES)) { > printk(KERN_ERR PFX "%s: speed/duplex mismatch", > sky2->netdev->name); > return -1; > } > >- sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; >- > sky2->speed = sky2_phy_speed(hw, aux); >+ sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; > >- /* Pause bits are offset (9..8) */ >- if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) >- aux >>= 6; >- >- sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; >- sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; >+ /* Since the pause result bits seem to in different positions on >+ * different chips. look at registers. >+ */ >+ if (!sky2_is_copper(hw)) { >+ /* Shift for bits in fiber PHY */ >+ advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); >+ lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); >+ >+ if (advert & ADVERTISE_1000XPAUSE) >+ advert |= ADVERTISE_PAUSE_CAP; >+ if (advert & ADVERTISE_1000XPSE_ASYM) >+ advert |= ADVERTISE_PAUSE_ASYM; >+ if (lpa & LPA_1000XPAUSE) >+ lpa |= LPA_PAUSE_CAP; >+ if (lpa & LPA_1000XPAUSE_ASYM) >+ lpa |= LPA_PAUSE_ASYM; >+ } >+ >+ sky2->flow_status = FC_NONE; >+ if (advert & ADVERTISE_PAUSE_CAP) { >+ if (lpa & LPA_PAUSE_CAP) >+ sky2->flow_status = FC_BOTH; >+ else if (advert & ADVERTISE_PAUSE_ASYM) >+ sky2->flow_status = FC_RX; >+ } else if (advert & ADVERTISE_PAUSE_ASYM) { >+ if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) >+ sky2->flow_status = FC_TX; >+ } >+ >+ if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 >+ && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) >+ sky2->flow_status = FC_NONE; > >- if ((sky2->tx_pause || sky2->rx_pause) >- && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) >+ if (sky2->flow_status & FC_TX) > sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); > else > sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); >@@ -1685,18 +1769,18 @@ > struct sky2_port *sky2 = netdev_priv(dev); > u16 istatus, phystat; > >+ if (!netif_running(dev)) >+ return; >+ > spin_lock(&sky2->phy_lock); > istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); > phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); > >- if (!netif_running(dev)) >- goto out; >- > if (netif_msg_intr(sky2)) > printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", > sky2->netdev->name, istatus, phystat); > >- if (istatus & PHY_M_IS_AN_COMPL) { >+ if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) { > if (sky2_autoneg_done(sky2, phystat) == 0) > sky2_link_up(sky2); > goto out; >@@ -1719,64 +1803,31 @@ > spin_unlock(&sky2->phy_lock); > } > >- >-/* Transmit timeout is only called if we are running, carries is up >+/* Transmit timeout is only called if we are running, carrier is up > * and tx queue is full (stopped). > */ > static void sky2_tx_timeout(struct net_device *dev) > { > struct sky2_port *sky2 = netdev_priv(dev); > struct sky2_hw *hw = sky2->hw; >- unsigned txq = txqaddr[sky2->port]; >- u16 report, done; > > if (netif_msg_timer(sky2)) > printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); > >- report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); >- done = sky2_read16(hw, Q_ADDR(txq, Q_DONE)); >- > printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", >- dev->name, >- sky2->tx_cons, sky2->tx_prod, report, done); >- >- if (report != done) { >- printk(KERN_INFO PFX "status burst pending (irq moderation?)\n"); >- >- sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); >- sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); >- } else if (report != sky2->tx_cons) { >- printk(KERN_INFO PFX "status report lost?\n"); >- >- spin_lock_bh(&sky2->tx_lock); >- sky2_tx_complete(sky2, report); >- spin_unlock_bh(&sky2->tx_lock); >- } else { >- printk(KERN_INFO PFX "hardware hung? flushing\n"); >- >- sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); >- sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); >- >- sky2_tx_clean(sky2); >- >- sky2_qset(hw, txq); >- sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); >- } >-} >- >- >-/* Want receive buffer size to be multiple of 64 bits >- * and incl room for vlan and truncation >- */ >-static inline unsigned sky2_buf_size(int mtu) >-{ >- return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8; >+ dev->name, sky2->tx_cons, sky2->tx_prod, >+ sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), >+ sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); >+ >+ /* can't restart safely under softirq */ >+ schedule_work(&hw->restart_work); > } > > static int sky2_change_mtu(struct net_device *dev, int new_mtu) > { > struct sky2_port *sky2 = netdev_priv(dev); > struct sky2_hw *hw = sky2->hw; >+ unsigned port = sky2->port; > int err; > u16 ctl, mode; > u32 imask; >@@ -1784,7 +1835,7 @@ > if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) > return -EINVAL; > >- if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) >+ if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE) > return -EINVAL; > > if (!netif_running(dev)) { >@@ -1801,22 +1852,32 @@ > > synchronize_irq(hw->pdev->irq); > >- ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); >- gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); >+ if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) { >+ if (new_mtu > ETH_DATA_LEN) { >+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), >+ TX_JUMBO_ENA | TX_STFW_DIS); >+ dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM; >+ } else >+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), >+ TX_JUMBO_DIS | TX_STFW_ENA); >+ } >+ >+ ctl = gma_read16(hw, port, GM_GP_CTRL); >+ gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); > sky2_rx_stop(sky2); > sky2_rx_clean(sky2); > > dev->mtu = new_mtu; >- sky2->rx_bufsize = sky2_buf_size(new_mtu); >+ > mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | > GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); > > if (dev->mtu > ETH_DATA_LEN) > mode |= GM_SMOD_JUMBO_ENA; > >- gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); >+ gma_write16(hw, port, GM_SERIAL_MODE, mode); > >- sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); >+ sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); > > err = sky2_rx_start(sky2); > sky2_write32(hw, B0_IMSK, imask); >@@ -1824,7 +1885,7 @@ > if (err) > dev_close(dev); > else { >- gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); >+ gma_write16(hw, port, GM_GP_CTRL, ctl); > > netif_poll_enable(hw->dev[0]); > netif_wake_queue(dev); >@@ -1833,20 +1894,105 @@ > return err; > } > >+/* For small just reuse existing skb for next receive */ >+static struct sk_buff *receive_copy(struct sky2_port *sky2, >+ const struct rx_ring_info *re, >+ unsigned length) >+{ >+ struct sk_buff *skb; >+ >+ skb = alloc_skb(length + 2, GFP_ATOMIC); >+ if (likely(skb)) { >+ skb_reserve(skb, 2); >+ pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, >+ length, PCI_DMA_FROMDEVICE); >+ memcpy(skb->data, re->skb->data, length); >+ skb->ip_summed = re->skb->ip_summed; >+ skb->csum = re->skb->csum; >+ pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, >+ length, PCI_DMA_FROMDEVICE); >+ re->skb->ip_summed = CHECKSUM_NONE; >+ skb_put(skb, length); >+ } >+ return skb; >+} >+ >+/* Adjust length of skb with fragments to match received data */ >+static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, >+ unsigned int length) >+{ >+ int i, num_frags; >+ unsigned int size; >+ >+ /* put header into skb */ >+ size = min(length, hdr_space); >+ skb->tail += size; >+ skb->len += size; >+ length -= size; >+ >+ num_frags = skb_shinfo(skb)->nr_frags; >+ for (i = 0; i < num_frags; i++) { >+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; >+ >+ if (length == 0) { >+ /* don't need this page */ >+ __free_page(frag->page); >+ --skb_shinfo(skb)->nr_frags; >+ } else { >+ size = min(length, (unsigned) PAGE_SIZE); >+ >+ frag->size = size; >+ skb->data_len += size; >+ skb->truesize += size; >+ skb->len += size; >+ length -= size; >+ } >+ } >+} >+ >+/* Normal packet - take skb from ring element and put in a new one */ >+static struct sk_buff *receive_new(struct sky2_port *sky2, >+ struct rx_ring_info *re, >+ unsigned int length) >+{ >+ struct sk_buff *skb, *nskb; >+ unsigned hdr_space = sky2->rx_data_size; >+ >+ pr_debug(PFX "receive new length=%d\n", length); >+ >+ /* Don't be tricky about reusing pages (yet) */ >+ nskb = sky2_rx_alloc(sky2); >+ if (unlikely(!nskb)) >+ return NULL; >+ >+ skb = re->skb; >+ sky2_rx_unmap_skb(sky2->hw->pdev, re); >+ >+ prefetch(skb->data); >+ re->skb = nskb; >+ sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space); >+ >+ if (skb_shinfo(skb)->nr_frags) >+ skb_put_frags(skb, hdr_space, length); >+ else >+ skb_put(skb, length); >+ return skb; >+} >+ > /* > * Receive one packet. >- * For small packets or errors, just reuse existing skb. > * For larger packets, get new buffer. > */ >-static struct sk_buff *sky2_receive(struct sky2_port *sky2, >+static struct sk_buff *sky2_receive(struct net_device *dev, > u16 length, u32 status) > { >- struct ring_info *re = sky2->rx_ring + sky2->rx_next; >+ struct sky2_port *sky2 = netdev_priv(dev); >+ struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; > struct sk_buff *skb = NULL; > > if (unlikely(netif_msg_rx_status(sky2))) > printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", >- sky2->netdev->name, sky2->rx_next, status, length); >+ dev->name, sky2->rx_next, status, length); > > sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; > prefetch(sky2->rx_ring + sky2->rx_next); >@@ -1857,52 +2003,21 @@ > if (!(status & GMR_FS_RX_OK)) > goto resubmit; > >- if (length > sky2->netdev->mtu + ETH_HLEN) >- goto oversize; >- >- if (length < copybreak) { >- skb = alloc_skb(length + 2, GFP_ATOMIC); >- if (!skb) >- goto resubmit; >- >- skb_reserve(skb, 2); >- pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, >- length, PCI_DMA_FROMDEVICE); >- memcpy(skb->data, re->skb->data, length); >- skb->ip_summed = re->skb->ip_summed; >- skb->csum = re->skb->csum; >- pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, >- length, PCI_DMA_FROMDEVICE); >- } else { >- struct sk_buff *nskb; >- >- nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); >- if (!nskb) >- goto resubmit; >- >- skb = re->skb; >- re->skb = nskb; >- pci_unmap_single(sky2->hw->pdev, re->mapaddr, >- sky2->rx_bufsize, PCI_DMA_FROMDEVICE); >- prefetch(skb->data); >- >- re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, >- sky2->rx_bufsize, PCI_DMA_FROMDEVICE); >- } >- >- skb_put(skb, length); >+ if (length < copybreak) >+ skb = receive_copy(sky2, re, length); >+ else >+ skb = receive_new(sky2, re, length); > resubmit: >- re->skb->ip_summed = CHECKSUM_NONE; >- sky2_rx_add(sky2, re->mapaddr); >+ sky2_rx_submit(sky2, re); > > return skb; > >-oversize: >- ++sky2->net_stats.rx_over_errors; >- goto resubmit; >- > error: > ++sky2->net_stats.rx_errors; >+ if (status & GMR_FS_RX_FF_OV) { >+ sky2->net_stats.rx_over_errors++; >+ goto resubmit; >+ } > > if (netif_msg_rx_err(sky2) && net_ratelimit()) > printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", >@@ -1914,8 +2029,6 @@ > sky2->net_stats.rx_frame_errors++; > if (status & GMR_FS_CRC_ERR) > sky2->net_stats.rx_crc_errors++; >- if (status & GMR_FS_RX_FF_OV) >- sky2->net_stats.rx_fifo_errors++; > > goto resubmit; > } >@@ -1926,9 +2039,9 @@ > struct sky2_port *sky2 = netdev_priv(dev); > > if (netif_running(dev)) { >- spin_lock(&sky2->tx_lock); >+ netif_tx_lock(dev); > sky2_tx_complete(sky2, last); >- spin_unlock(&sky2->tx_lock); >+ netif_tx_unlock(dev); > } > } > >@@ -1955,17 +2068,22 @@ > dev = hw->dev[le->link]; > > sky2 = netdev_priv(dev); >- length = le->length; >- status = le->status; >+ length = le16_to_cpu(le->length); >+ status = le32_to_cpu(le->status); >+ > > switch (le->opcode & ~HW_OWNER) { > case OP_RXSTAT: >- skb = sky2_receive(sky2, length, status); >- if (!skb) >- break; >+ skb = sky2_receive(dev, length, status); >+ if (unlikely(!skb)) { >+ sky2->net_stats.rx_dropped++; >+ goto force_update; >+ } > > skb->dev = dev; > skb->protocol = eth_type_trans(skb, dev); >+ sky2->net_stats.rx_packets++; >+ sky2->net_stats.rx_bytes += skb->len; > dev->last_rx = jiffies; > > #ifdef SKY2_VLAN_TAG_USED >@@ -1979,8 +2097,8 @@ > > /* Update receiver after 16 frames */ > if (++buf_write[le->link] == RX_BUF_WRITE) { >- sky2_put_idx(hw, rxqaddr[le->link], >- sky2->rx_put); >+force_update: >+ sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put); > buf_write[le->link] = 0; > } > >@@ -1999,9 +2117,27 @@ > /* fall through */ > #endif > case OP_RXCHKS: >- skb = sky2->rx_ring[sky2->rx_next].skb; >- skb->ip_summed = CHECKSUM_HW; >- skb->csum = le16_to_cpu(status); >+ if (!sky2->rx_csum) >+ break; >+ >+ /* Both checksum counters are programmed to start at >+ * the same offset, so unless there is a problem they >+ * should match. This failure is an early indication that >+ * hardware receive checksumming won't work. >+ */ >+ if (likely(status >> 16 == (status & 0xffff))) { >+ skb = sky2->rx_ring[sky2->rx_next].skb; >+ skb->ip_summed = CHECKSUM_HW; >+ skb->csum = status & 0xffff; >+ } else { >+ printk(KERN_NOTICE PFX "%s: hardware receive " >+ "checksum problem (status = %#x)\n", >+ dev->name, status); >+ sky2->rx_csum = 0; >+ sky2_write32(sky2->hw, >+ Q_ADDR(rxqaddr[le->link], Q_CSR), >+ BMU_DIS_RX_CHKSUM); >+ } > break; > > case OP_TXINDEXLE: >@@ -2024,6 +2160,7 @@ > > /* Fully processed status ring so clear irq */ > sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); >+ mmiowb(); > > exit_loop: > if (buf_write[0]) { >@@ -2095,12 +2232,12 @@ > > pci_err = sky2_pci_read16(hw, PCI_STATUS); > if (net_ratelimit()) >- printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", >- pci_name(hw->pdev), pci_err); >+ dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n", >+ pci_err); > > sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); > sky2_pci_write16(hw, PCI_STATUS, >- pci_err | PCI_STATUS_ERROR_BITS); >+ pci_err | PCI_STATUS_ERROR_BITS); > sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); > } > >@@ -2111,8 +2248,8 @@ > pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); > > if (net_ratelimit()) >- printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", >- pci_name(hw->pdev), pex_err); >+ dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n", >+ pex_err); > > /* clear the interrupt */ > sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); >@@ -2144,6 +2281,12 @@ > printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", > dev->name, status); > >+ if (status & GM_IS_RX_CO_OV) >+ gma_read16(hw, port, GM_RX_IRQ_SRC); >+ >+ if (status & GM_IS_TX_CO_OV) >+ gma_read16(hw, port, GM_TX_IRQ_SRC); >+ > if (status & GM_IS_RX_FF_OR) { > ++sky2->net_stats.rx_fifo_errors; > sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); >@@ -2155,26 +2298,22 @@ > } > } > >-/* This should never happen it is a fatal situation */ >-static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port, >- const char *rxtx, u32 mask) >+/* This should never happen it is a bug. */ >+static void sky2_le_error(struct sky2_hw *hw, unsigned port, >+ u16 q, unsigned ring_size) > { > struct net_device *dev = hw->dev[port]; > struct sky2_port *sky2 = netdev_priv(dev); >- u32 imask; >- >- printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n", >- dev ? dev->name : "<not registered>", rxtx); >- >- imask = sky2_read32(hw, B0_IMSK); >- imask &= ~mask; >- sky2_write32(hw, B0_IMSK, imask); >+ unsigned idx; >+ const u64 *le = (q == Q_R1 || q == Q_R2) >+ ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le; >+ >+ idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); >+ printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n", >+ dev->name, (unsigned) q, idx, (unsigned long long) le[idx], >+ (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); > >- if (dev) { >- spin_lock(&sky2->phy_lock); >- sky2_link_down(sky2); >- spin_unlock(&sky2->phy_lock); >- } >+ sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); > } > > /* If idle then force a fake soft NAPI poll once a second >@@ -2198,23 +2337,15 @@ > mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout)); > } > >- >-static int sky2_poll(struct net_device *dev0, int *budget) >+/* Hardware/software error handling */ >+static void sky2_err_intr(struct sky2_hw *hw, u32 status) > { >- struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; >- int work_limit = min(dev0->quota, *budget); >- int work_done = 0; >- u32 status = sky2_read32(hw, B0_Y2_SP_EISR); >+ if (net_ratelimit()) >+ dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); > > if (status & Y2_IS_HW_ERR) > sky2_hw_intr(hw); > >- if (status & Y2_IS_IRQ_PHY1) >- sky2_phy_intr(hw, 0); >- >- if (status & Y2_IS_IRQ_PHY2) >- sky2_phy_intr(hw, 1); >- > if (status & Y2_IS_IRQ_MAC1) > sky2_mac_intr(hw, 0); > >@@ -2222,21 +2353,39 @@ > sky2_mac_intr(hw, 1); > > if (status & Y2_IS_CHK_RX1) >- sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); >+ sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE); > > if (status & Y2_IS_CHK_RX2) >- sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); >+ sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE); > > if (status & Y2_IS_CHK_TXA1) >- sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); >+ sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE); > > if (status & Y2_IS_CHK_TXA2) >- sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); >+ sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE); >+} >+ >+static int sky2_poll(struct net_device *dev0, int *budget) >+{ >+ struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; >+ int work_limit = min(dev0->quota, *budget); >+ int work_done = 0; >+ u32 status = sky2_read32(hw, B0_Y2_SP_EISR); >+ >+ if (unlikely(status & Y2_IS_ERROR)) >+ sky2_err_intr(hw, status); >+ >+ if (status & Y2_IS_IRQ_PHY1) >+ sky2_phy_intr(hw, 0); >+ >+ if (status & Y2_IS_IRQ_PHY2) >+ sky2_phy_intr(hw, 1); > > work_done = sky2_status_intr(hw, work_limit); > if (work_done < work_limit) { > netif_rx_complete(dev0); > >+ /* end of interrupt, re-enables also acts as I/O synchronization */ > sky2_read32(hw, B0_Y2_SP_LISR); > return 0; > } else { >@@ -2281,6 +2430,7 @@ > switch (hw->chip_id) { > case CHIP_ID_YUKON_EC: > case CHIP_ID_YUKON_EC_U: >+ case CHIP_ID_YUKON_EX: > return 125; /* 125 Mhz */ > case CHIP_ID_YUKON_FE: > return 100; /* 100 Mhz */ >@@ -2303,33 +2453,45 @@ > static int sky2_reset(struct sky2_hw *hw) > { > u16 status; >- u8 t8, pmd_type; >+ u8 t8; > int i; > > sky2_write8(hw, B0_CTST, CS_RST_CLR); > > hw->chip_id = sky2_read8(hw, B2_CHIP_ID); > if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { >- printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", >- pci_name(hw->pdev), hw->chip_id); >+ dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", >+ hw->chip_id); > return -EOPNOTSUPP; > } > >+ if (hw->chip_id == CHIP_ID_YUKON_EX) >+ dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n" >+ "Please report success or failure to <netdev@vger.kernel.org>\n"); >+ >+ /* Make sure and enable all clocks */ >+ if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U) >+ sky2_pci_write32(hw, PCI_DEV_REG3, 0); >+ > hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; > > /* This rev is really old, and requires untested workarounds */ > if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { >- printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n", >- pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], >- hw->chip_id, hw->chip_rev); >+ dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n", >+ yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], >+ hw->chip_id, hw->chip_rev); > return -EOPNOTSUPP; > } > > /* disable ASF */ >- if (hw->chip_id <= CHIP_ID_YUKON_EC) { >+ if (hw->chip_id == CHIP_ID_YUKON_EX) { >+ status = sky2_read16(hw, HCU_CCSR); >+ status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | >+ HCU_CCSR_UC_STATE_MSK); >+ sky2_write16(hw, HCU_CCSR, status); >+ } else > sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); >- sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); >- } >+ sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); > > /* do a SW reset */ > sky2_write8(hw, B0_CTST, CS_RST_SET); >@@ -2349,9 +2511,7 @@ > sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); > > >- pmd_type = sky2_read8(hw, B2_PMD_TYP); >- hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); >- >+ hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); > hw->ports = 1; > t8 = sky2_read8(hw, B2_Y2_HW_RES); > if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { >@@ -2359,7 +2519,7 @@ > ++hw->ports; > } > >- sky2_set_power_state(hw, PCI_D0); >+ sky2_power_on(hw); > > for (i = 0; i < hw->ports; i++) { > sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); >@@ -2409,7 +2569,7 @@ > sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); > > for (i = 0; i < hw->ports; i++) >- sky2_phy_reset(hw, i); >+ sky2_gmac_reset(hw, i); > > memset(hw->st_le, 0, STATUS_LE_BYTES); > hw->st_idx = 0; >@@ -2446,23 +2606,69 @@ > return 0; > } > >+static void sky2_restart(struct work_struct *work) >+{ >+ struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); >+ struct net_device *dev; >+ int i, err; >+ >+ dev_dbg(&hw->pdev->dev, "restarting\n"); >+ >+ del_timer_sync(&hw->idle_timer); >+ >+ rtnl_lock(); >+ sky2_write32(hw, B0_IMSK, 0); >+ sky2_read32(hw, B0_IMSK); >+ >+ netif_poll_disable(hw->dev[0]); >+ >+ for (i = 0; i < hw->ports; i++) { >+ dev = hw->dev[i]; >+ if (netif_running(dev)) >+ sky2_down(dev); >+ } >+ >+ sky2_reset(hw); >+ sky2_write32(hw, B0_IMSK, Y2_IS_BASE); >+ netif_poll_enable(hw->dev[0]); >+ >+ for (i = 0; i < hw->ports; i++) { >+ dev = hw->dev[i]; >+ if (netif_running(dev)) { >+ netif_device_detach(dev); >+ >+ err = sky2_up(dev); >+ if (err) { >+ printk(KERN_INFO PFX "%s: could not restart %d\n", >+ dev->name, err); >+ dev_close(dev); >+ } >+ } >+ } >+ >+ sky2_idle_start(hw); >+ >+ rtnl_unlock(); >+} >+ > static u32 sky2_supported_modes(const struct sky2_hw *hw) > { >- u32 modes; >- if (hw->copper) { >- modes = SUPPORTED_10baseT_Half >- | SUPPORTED_10baseT_Full >- | SUPPORTED_100baseT_Half >- | SUPPORTED_100baseT_Full >- | SUPPORTED_Autoneg | SUPPORTED_TP; >+ if (sky2_is_copper(hw)) { >+ u32 modes = SUPPORTED_10baseT_Half >+ | SUPPORTED_10baseT_Full >+ | SUPPORTED_100baseT_Half >+ | SUPPORTED_100baseT_Full >+ | SUPPORTED_Autoneg | SUPPORTED_TP; > > if (hw->chip_id != CHIP_ID_YUKON_FE) > modes |= SUPPORTED_1000baseT_Half >- | SUPPORTED_1000baseT_Full; >+ | SUPPORTED_1000baseT_Full; >+ return modes; > } else >- modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE >- | SUPPORTED_Autoneg; >- return modes; >+ return SUPPORTED_1000baseT_Half >+ | SUPPORTED_1000baseT_Full >+ | SUPPORTED_Autoneg >+ | SUPPORTED_FIBRE; > } > > static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) >@@ -2473,7 +2679,7 @@ > ecmd->transceiver = XCVR_INTERNAL; > ecmd->supported = sky2_supported_modes(hw); > ecmd->phy_address = PHY_ADDR_MARV; >- if (hw->copper) { >+ if (sky2_is_copper(hw)) { > ecmd->supported = SUPPORTED_10baseT_Half > | SUPPORTED_10baseT_Full > | SUPPORTED_100baseT_Half >@@ -2482,12 +2688,14 @@ > | SUPPORTED_1000baseT_Full > | SUPPORTED_Autoneg | SUPPORTED_TP; > ecmd->port = PORT_TP; >- } else >+ ecmd->speed = sky2->speed; >+ } else { >+ ecmd->speed = SPEED_1000; > ecmd->port = PORT_FIBRE; >+ } > > ecmd->advertising = sky2->advertising; > ecmd->autoneg = sky2->autoneg; >- ecmd->speed = sky2->speed; > ecmd->duplex = sky2->duplex; > return 0; > } >@@ -2635,7 +2843,7 @@ > { > struct sky2_port *sky2 = netdev_priv(dev); > >- if (sky2->autoneg != AUTONEG_ENABLE) >+ if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE) > return -EINVAL; > > sky2_phy_reinit(sky2); >@@ -2690,25 +2898,9 @@ > } > } > >-/* Use hardware MIB variables for critical path statistics and >- * transmit feedback not reported at interrupt. >- * Other errors are accounted for in interrupt handler. >- */ > static struct net_device_stats *sky2_get_stats(struct net_device *dev) > { > struct sky2_port *sky2 = netdev_priv(dev); >- u64 data[13]; >- >- sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); >- >- sky2->net_stats.tx_bytes = data[0]; >- sky2->net_stats.rx_bytes = data[1]; >- sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; >- sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; >- sky2->net_stats.multicast = data[3] + data[5]; >- sky2->net_stats.collisions = data[10]; >- sky2->net_stats.tx_aborted_errors = data[12]; >- > return &sky2->net_stats; > } > >@@ -2737,6 +2929,14 @@ > return 0; > } > >+static void inline sky2_add_filter(u8 filter[8], const u8 *addr) >+{ >+ u32 bit; >+ >+ bit = ether_crc(ETH_ALEN, addr) & 63; >+ filter[bit >> 3] |= 1 << (bit & 7); >+} >+ > static void sky2_set_multicast(struct net_device *dev) > { > struct sky2_port *sky2 = netdev_priv(dev); >@@ -2745,7 +2945,10 @@ > struct dev_mc_list *list = dev->mc_list; > u16 reg; > u8 filter[8]; >+ int rx_pause; >+ static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; > >+ rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); > memset(filter, 0, sizeof(filter)); > > reg = gma_read16(hw, port, GM_RX_CTRL); >@@ -2753,18 +2956,19 @@ > > if (dev->flags & IFF_PROMISC) /* promiscuous */ > reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); >- else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ >+ else if (dev->flags & IFF_ALLMULTI) > memset(filter, 0xff, sizeof(filter)); >- else if (dev->mc_count == 0) /* no multicast */ >+ else if (dev->mc_count == 0 && !rx_pause) > reg &= ~GM_RXCR_MCF_ENA; > else { > int i; > reg |= GM_RXCR_MCF_ENA; > >- for (i = 0; list && i < dev->mc_count; i++, list = list->next) { >- u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; >- filter[bit / 8] |= 1 << (bit % 8); >- } >+ if (rx_pause) >+ sky2_add_filter(filter, pause_mc_addr); >+ >+ for (i = 0; list && i < dev->mc_count; i++, list = list->next) >+ sky2_add_filter(filter, list->dmi_addr); > } > > gma_write16(hw, port, GM_MC_ADDR_H1, >@@ -2802,18 +3006,8 @@ > > default: > gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); >- gm_phy_write(hw, port, PHY_MARV_LED_OVER, >- on ? PHY_M_LED_MO_DUP(MO_LED_ON) | >- PHY_M_LED_MO_10(MO_LED_ON) | >- PHY_M_LED_MO_100(MO_LED_ON) | >- PHY_M_LED_MO_1000(MO_LED_ON) | >- PHY_M_LED_MO_RX(MO_LED_ON) >- : PHY_M_LED_MO_DUP(MO_LED_OFF) | >- PHY_M_LED_MO_10(MO_LED_OFF) | >- PHY_M_LED_MO_100(MO_LED_OFF) | >- PHY_M_LED_MO_1000(MO_LED_OFF) | >- PHY_M_LED_MO_RX(MO_LED_OFF)); >- >+ gm_phy_write(hw, port, PHY_MARV_LED_OVER, >+ on ? PHY_M_LED_ALL : 0); > } > } > >@@ -2877,8 +3071,20 @@ > { > struct sky2_port *sky2 = netdev_priv(dev); > >- ecmd->tx_pause = sky2->tx_pause; >- ecmd->rx_pause = sky2->rx_pause; >+ switch (sky2->flow_mode) { >+ case FC_NONE: >+ ecmd->tx_pause = ecmd->rx_pause = 0; >+ break; >+ case FC_TX: >+ ecmd->tx_pause = 1, ecmd->rx_pause = 0; >+ break; >+ case FC_RX: >+ ecmd->tx_pause = 0, ecmd->rx_pause = 1; >+ break; >+ case FC_BOTH: >+ ecmd->tx_pause = ecmd->rx_pause = 1; >+ } >+ > ecmd->autoneg = sky2->autoneg; > } > >@@ -2886,15 +3092,14 @@ > struct ethtool_pauseparam *ecmd) > { > struct sky2_port *sky2 = netdev_priv(dev); >- int err = 0; > > sky2->autoneg = ecmd->autoneg; >- sky2->tx_pause = ecmd->tx_pause != 0; >- sky2->rx_pause = ecmd->rx_pause != 0; >+ sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); > >- sky2_phy_reinit(sky2); >+ if (netif_running(dev)) >+ sky2_phy_reinit(sky2); > >- return err; >+ return 0; > } > > static int sky2_get_coalesce(struct net_device *dev, >@@ -3055,7 +3260,37 @@ > regs->len - B3_RI_WTO_R1); > } > >-static struct ethtool_ops sky2_ethtool_ops = { >+/* In order to do Jumbo packets on these chips, need to turn off the >+ * transmit store/forward. Therefore checksum offload won't work. >+ */ >+static int no_tx_offload(struct net_device *dev) >+{ >+ const struct sky2_port *sky2 = netdev_priv(dev); >+ const struct sky2_hw *hw = sky2->hw; >+ >+ return dev->mtu > ETH_DATA_LEN && >+ (hw->chip_id == CHIP_ID_YUKON_EX >+ || hw->chip_id == CHIP_ID_YUKON_EC_U); >+} >+ >+static int sky2_set_tx_csum(struct net_device *dev, u32 data) >+{ >+ if (data && no_tx_offload(dev)) >+ return -EINVAL; >+ >+ return ethtool_op_set_tx_csum(dev, data); >+} >+ >+ >+static int sky2_set_tso(struct net_device *dev, u32 data) >+{ >+ if (data && no_tx_offload(dev)) >+ return -EINVAL; >+ >+ return ethtool_op_set_tso(dev, data); >+} >+ >+static const struct ethtool_ops sky2_ethtool_ops = { > .get_settings = sky2_get_settings, > .set_settings = sky2_set_settings, > .get_drvinfo = sky2_get_drvinfo, >@@ -3068,9 +3303,9 @@ > .get_sg = ethtool_op_get_sg, > .set_sg = ethtool_op_set_sg, > .get_tx_csum = ethtool_op_get_tx_csum, >- .set_tx_csum = ethtool_op_set_tx_csum, >+ .set_tx_csum = sky2_set_tx_csum, > .get_tso = ethtool_op_get_tso, >- .set_tso = ethtool_op_set_tso, >+ .set_tso = sky2_set_tso, > .get_rx_csum = sky2_get_rx_csum, > .set_rx_csum = sky2_set_rx_csum, > .get_strings = sky2_get_strings, >@@ -3096,7 +3331,7 @@ > struct net_device *dev = alloc_etherdev(sizeof(*sky2)); > > if (!dev) { >- printk(KERN_ERR "sky2 etherdev alloc failed"); >+ dev_err(&hw->pdev->dev, "etherdev alloc failed"); > return NULL; > } > >@@ -3118,7 +3353,11 @@ > dev->poll = sky2_poll; > dev->weight = NAPI_WEIGHT; > #ifdef CONFIG_NET_POLL_CONTROLLER >- dev->poll_controller = sky2_netpoll; >+ /* Network console (only works on port 0) >+ * because netpoll makes assumptions about NAPI >+ */ >+ if (port == 0) >+ dev->poll_controller = sky2_netpoll; > #endif > > sky2 = netdev_priv(dev); >@@ -3126,11 +3365,10 @@ > sky2->hw = hw; > sky2->msg_enable = netif_msg_init(debug, default_msg); > >- spin_lock_init(&sky2->tx_lock); > /* Auto speed and flow control */ > sky2->autoneg = AUTONEG_ENABLE; >- sky2->tx_pause = 1; >- sky2->rx_pause = 1; >+ sky2->flow_mode = FC_BOTH; >+ > sky2->duplex = -1; > sky2->speed = -1; > sky2->advertising = sky2_supported_modes(hw); >@@ -3139,18 +3377,14 @@ > spin_lock_init(&sky2->phy_lock); > sky2->tx_pending = TX_DEF_PENDING; > sky2->rx_pending = RX_DEF_PENDING; >- sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); > > hw->dev[port] = dev; > > sky2->port = port; > >- dev->features |= NETIF_F_LLTX; >- if (hw->chip_id != CHIP_ID_YUKON_EC_U) >- dev->features |= NETIF_F_TSO; >+ dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG; > if (highmem) > dev->features |= NETIF_F_HIGHDMA; >- dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; > > #ifdef SKY2_VLAN_TAG_USED > dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; >@@ -3183,8 +3417,8 @@ > } > > /* Handle software interrupt used during MSI test */ >-static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, >- struct pt_regs *regs) >+static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, >+ struct pt_regs *regs) > { > struct sky2_hw *hw = dev_id; > u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); >@@ -3193,7 +3427,7 @@ > return IRQ_NONE; > > if (status & Y2_IS_IRQ_SW) { >- hw->msi_detected = 1; >+ hw->msi = 1; > wake_up(&hw->msi_wait); > sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); > } >@@ -3208,34 +3442,32 @@ > struct pci_dev *pdev = hw->pdev; > int err; > >+ init_waitqueue_head (&hw->msi_wait); >+ > sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); > >- err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw); >+ err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); > if (err) { >- printk(KERN_ERR PFX "%s: cannot assign irq %d\n", >- pci_name(pdev), pdev->irq); >+ dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); > return err; > } > >- init_waitqueue_head (&hw->msi_wait); >- > sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); >- wmb(); >+ sky2_read8(hw, B0_CTST); > >- wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); >+ wait_event_timeout(hw->msi_wait, hw->msi, HZ/10); > >- if (!hw->msi_detected) { >+ if (!hw->msi) { > /* MSI test failed, go back to INTx mode */ >- printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " >- "switching to INTx mode. Please report this failure to " >- "the PCI maintainer and include system chipset information.\n", >- pci_name(pdev)); >+ dev_info(&pdev->dev, "No interrupt generated using MSI, " >+ "switching to INTx mode.\n"); > > err = -EOPNOTSUPP; > sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); > } > > sky2_write32(hw, B0_IMSK, 0); >+ sky2_read32(hw, B0_IMSK); > > free_irq(pdev->irq, hw); > >@@ -3245,50 +3477,37 @@ > static int __devinit sky2_probe(struct pci_dev *pdev, > const struct pci_device_id *ent) > { >- struct net_device *dev, *dev1 = NULL; >+ struct net_device *dev; > struct sky2_hw *hw; >- int err, pm_cap, using_dac = 0; >+ int err, using_dac = 0; > > err = pci_enable_device(pdev); > if (err) { >- printk(KERN_ERR PFX "%s cannot enable PCI device\n", >- pci_name(pdev)); >+ dev_err(&pdev->dev, "cannot enable PCI device\n"); > goto err_out; > } > > err = pci_request_regions(pdev, DRV_NAME); > if (err) { >- printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", >- pci_name(pdev)); >- goto err_out; >+ dev_err(&pdev->dev, "cannot obtain PCI resources\n"); >+ goto err_out_disable; > } > > pci_set_master(pdev); > >- /* Find power-management capability. */ >- pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); >- if (pm_cap == 0) { >- printk(KERN_ERR PFX "Cannot find PowerManagement capability, " >- "aborting.\n"); >- err = -EIO; >- goto err_out_free_regions; >- } >- > if (sizeof(dma_addr_t) > sizeof(u32) && > !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { > using_dac = 1; > err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); > if (err < 0) { >- printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " >- "for consistent allocations\n", pci_name(pdev)); >+ dev_err(&pdev->dev, "unable to obtain 64 bit DMA " >+ "for consistent allocations\n"); > goto err_out_free_regions; > } >- > } else { > err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); > if (err) { >- printk(KERN_ERR PFX "%s no usable DMA configuration\n", >- pci_name(pdev)); >+ dev_err(&pdev->dev, "no usable DMA configuration\n"); > goto err_out_free_regions; > } > } >@@ -3296,8 +3515,7 @@ > err = -ENOMEM; > hw = kzalloc(sizeof(*hw), GFP_KERNEL); > if (!hw) { >- printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", >- pci_name(pdev)); >+ dev_err(&pdev->dev, "cannot allocate hardware struct\n"); > goto err_out_free_regions; > } > >@@ -3305,19 +3523,18 @@ > > hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); > if (!hw->regs) { >- printk(KERN_ERR PFX "%s: cannot map device registers\n", >- pci_name(pdev)); >+ dev_err(&pdev->dev, "cannot map device registers\n"); > goto err_out_free_hw; > } >- hw->pm_cap = pm_cap; > > #ifdef __BIG_ENDIAN >- /* byte swap descriptors in hardware */ >+ /* The sk98lin vendor driver uses hardware byte swapping but >+ * this driver uses software swapping. >+ */ > { > u32 reg; >- > reg = sky2_pci_read32(hw, PCI_DEV_REG2); >- reg |= PCI_REV_DESC; >+ reg &= ~PCI_REV_DESC; > sky2_pci_write32(hw, PCI_DEV_REG2, reg); > } > #endif >@@ -3332,34 +3549,15 @@ > if (err) > goto err_out_iounmap; > >- printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", >+ dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", > DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), > pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], > hw->chip_id, hw->chip_rev); > > dev = sky2_init_netdev(hw, 0, using_dac); >- if (!dev) >+ if (!dev) { >+ err = -ENOMEM; > goto err_out_free_pci; >- >- err = register_netdev(dev); >- if (err) { >- printk(KERN_ERR PFX "%s: cannot register net device\n", >- pci_name(pdev)); >- goto err_out_free_netdev; >- } >- >- sky2_show_addr(dev); >- >- if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { >- if (register_netdev(dev1) == 0) >- sky2_show_addr(dev1); >- else { >- /* Failure to register second port need not be fatal */ >- printk(KERN_WARNING PFX >- "register of second port failed\n"); >- hw->dev[1] = NULL; >- free_netdev(dev1); >- } > } > > if (!disable_msi && pci_enable_msi(pdev) == 0) { >@@ -3367,19 +3565,43 @@ > if (err == -EOPNOTSUPP) > pci_disable_msi(pdev); > else if (err) >- goto err_out_unregister; >+ goto err_out_free_netdev; > } > >- err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); >+ err = register_netdev(dev); >+ if (err) { >+ dev_err(&pdev->dev, "cannot register net device\n"); >+ goto err_out_free_netdev; >+ } >+ >+ err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED, >+ dev->name, hw); > if (err) { >- printk(KERN_ERR PFX "%s: cannot assign irq %d\n", >- pci_name(pdev), pdev->irq); >+ dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); > goto err_out_unregister; > } >- > sky2_write32(hw, B0_IMSK, Y2_IS_BASE); > >+ sky2_show_addr(dev); >+ >+ if (hw->ports > 1) { >+ struct net_device *dev1; >+ >+ dev1 = sky2_init_netdev(hw, 1, using_dac); >+ if (!dev1) >+ dev_warn(&pdev->dev, "allocation for second device failed\n"); >+ else if ((err = register_netdev(dev1))) { >+ dev_warn(&pdev->dev, >+ "register of second port failed (%d)\n", err); >+ hw->dev[1] = NULL; >+ free_netdev(dev1); >+ } else >+ sky2_show_addr(dev1); >+ } >+ > setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw); >+ INIT_WORK(&hw->restart_work, sky2_restart, &hw->restart_work); >+ > sky2_idle_start(hw); > > pci_set_drvdata(pdev, hw); >@@ -3387,11 +3609,8 @@ > return 0; > > err_out_unregister: >- pci_disable_msi(pdev); >- if (dev1) { >- unregister_netdev(dev1); >- free_netdev(dev1); >- } >+ if (hw->msi) >+ pci_disable_msi(pdev); > unregister_netdev(dev); > err_out_free_netdev: > free_netdev(dev); >@@ -3404,8 +3623,10 @@ > kfree(hw); > err_out_free_regions: > pci_release_regions(pdev); >+err_out_disable: > pci_disable_device(pdev); > err_out: >+ pci_set_drvdata(pdev, NULL); > return err; > } > >@@ -3419,6 +3640,8 @@ > > del_timer_sync(&hw->idle_timer); > >+ flush_scheduled_work(); >+ > sky2_write32(hw, B0_IMSK, 0); > synchronize_irq(hw->pdev->irq); > >@@ -3428,13 +3651,15 @@ > unregister_netdev(dev1); > unregister_netdev(dev0); > >- sky2_set_power_state(hw, PCI_D3hot); >+ sky2_power_aux(hw); >+ > sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); > sky2_write8(hw, B0_CTST, CS_RST_SET); > sky2_read8(hw, B0_CTST); > > free_irq(pdev->irq, hw); >- pci_disable_msi(pdev); >+ if (hw->msi) >+ pci_disable_msi(pdev); > pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); > pci_release_regions(pdev); > pci_disable_device(pdev); >@@ -3453,10 +3678,9 @@ > { > struct sky2_hw *hw = pci_get_drvdata(pdev); > int i; >- pci_power_t pstate = pci_choose_state(pdev, state); > >- if (!(pstate == PCI_D3hot || pstate == PCI_D3cold)) >- return -EINVAL; >+ if (!hw) >+ return 0; > > del_timer_sync(&hw->idle_timer); > netif_poll_disable(hw->dev[0]); >@@ -3468,11 +3692,14 @@ > sky2_down(dev); > netif_device_detach(dev); > } >+ > } > > sky2_write32(hw, B0_IMSK, 0); >+ sky2_power_aux(hw); > pci_save_state(pdev, hw->pci_cfg_state); >- sky2_set_power_state(hw, pstate); >+ pci_set_power_state(pdev, pci_choose_state(pdev, state)); >+ > return 0; > } > >@@ -3481,21 +3708,29 @@ > struct sky2_hw *hw = pci_get_drvdata(pdev); > int i, err; > >- pci_restore_state(pdev, hw->pci_cfg_state); >- pci_enable_wake(pdev, PCI_D0, 0); >- sky2_set_power_state(hw, PCI_D0); >+ if (!hw) >+ return 0; > >- err = sky2_reset(hw); >+ err = pci_set_power_state(pdev, PCI_D0); >+ if (err) >+ goto out; >+ err = pci_restore_state(pdev, hw->pci_cfg_state); > if (err) > goto out; > >+ pci_enable_wake(pdev, PCI_D0, 0); >+ >+ /* Re-enable all clocks */ >+ if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U) >+ sky2_pci_write32(hw, PCI_DEV_REG3, 0); >+ >+ sky2_reset(hw); >+ > sky2_write32(hw, B0_IMSK, Y2_IS_BASE); > > for (i = 0; i < hw->ports; i++) { > struct net_device *dev = hw->dev[i]; > if (netif_running(dev)) { >- netif_device_attach(dev); >- > err = sky2_up(dev); > if (err) { > printk(KERN_ERR PFX "%s: could not up: %d\n", >@@ -3508,11 +3743,15 @@ > > netif_poll_enable(hw->dev[0]); > sky2_idle_start(hw); >+ return 0; > out: >+ dev_err(&pdev->dev, "resume failed (%d)\n", err); >+ pci_disable_device(pdev); > return err; > } > #endif > >+ > static struct pci_driver sky2_driver = { > .name = DRV_NAME, > .id_table = sky2_id_table, >@@ -3538,6 +3777,6 @@ > module_exit(sky2_cleanup_module); > > MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); >-MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); >+MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); > MODULE_LICENSE("GPL"); > MODULE_VERSION(DRV_VERSION);
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