Attachment 192911 Details for Bug 224373 – kernel-2.6.18-45.el5.bz224373.2 x86_64 kexec boot log

kernel-2.6.18-45.el5.bz224373.2 x86_64 kexec boot log

es7000-kexec.log (text/plain), 105.66 KB, created by Jeff Burke on 2007-09-11 19:19:10 UTC

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Creator: Jeff Burke

Created: 2007-09-11 19:19:10 UTC

Size: 105.66 KB

patch

obsolete

><Sep/11 01:51 pm>es7000-01.lab.boston.redhat.com login: Synchronizing SCSI cache for disk sdb: 
><Sep/11 01:51 pm>Synchronizing SCSI cache for disk sda: 
><Sep/11 01:51 pm>Starting new kernel
><Sep/11 01:51 pm>Linux version 2.6.18-45.el5.bz224373.2 (brewbuilder@hs20-bc1-7.build.redhat.com) (gcc version 4.1.1 20070105 (Red Hat 4.1.1-52)) #1 SMP Mon Sep 10 16:53:08 EDT 2007
><Sep/11 01:51 pm>Command line: ro root=/dev/VolGroup00/LogVol00 crashkernel=128M@16M console=ttyS0,115200 kexecboot
><Sep/11 01:51 pm>BIOS-provided physical RAM map:
><Sep/11 01:51 pm> BIOS-e820: 0000000000000100 - 000000000009d800 (usable)
><Sep/11 01:51 pm> BIOS-e820: 000000000009d800 - 00000000000a0000 (reserved)
><Sep/11 01:51 pm> BIOS-e820: 0000000000100000 - 0000000037e70000 (usable)
><Sep/11 01:51 pm> BIOS-e820: 0000000037e70000 - 0000000037ed6000 (ACPI data)
><Sep/11 01:51 pm> BIOS-e820: 0000000037ed6000 - 0000000037f00000 (ACPI NVS)
><Sep/11 01:51 pm> BIOS-e820: 0000000037f00000 - 00000000d8000000 (usable)
><Sep/11 01:51 pm> BIOS-e820: 00000000f8000000 - 00000000fec00000 (reserved)
><Sep/11 01:51 pm> BIOS-e820: 00000000fffc0000 - 0000000100000000 (reserved)
><Sep/11 01:51 pm> BIOS-e820: 0000000100000000 - 0000002020000000 (usable)
><Sep/11 01:51 pm>DMI present.
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 63 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 59 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 55 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 51 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 62 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 58 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 54 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 50 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 61 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 57 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 53 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 49 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 60 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 56 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 52 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 4 -> APIC 48 -> Node 0
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 47 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 43 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 39 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 35 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 46 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 42 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 38 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 34 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 45 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 41 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 37 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 33 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 44 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 40 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 36 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 3 -> APIC 32 -> Node 1
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 31 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 27 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 23 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 19 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 30 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 26 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 22 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 18 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 29 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 25 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 21 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 17 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 28 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 24 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 20 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 2 -> APIC 16 -> Node 2
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 15 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 11 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 7 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 3 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 14 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 10 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 6 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 2 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 13 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 9 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 5 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 1 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 12 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 8 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 4 -> Node 3
><Sep/11 01:51 pm>SRAT: PXM 1 -> APIC 0 -> Node 3
><Sep/11 01:51 pm>SRAT: Node 3 PXM 1 0-100000
><Sep/11 01:51 pm>SRAT: Node 3 PXM 1 0-810000000
><Sep/11 01:51 pm>SRAT: Node 2 PXM 2 810000000-1020000000
><Sep/11 01:51 pm>SRAT: Node 1 PXM 3 1020000000-1820000000
><Sep/11 01:51 pm>SRAT: Node 0 PXM 4 1820000000-2020000000
><Sep/11 01:51 pm>Bootmem setup node 0 0000001820000000-0000002020000000
><Sep/11 01:51 pm>Bootmem setup node 1 0000001020000000-0000001820000000
><Sep/11 01:51 pm>Bootmem setup node 2 0000000810000000-0000001020000000
><Sep/11 01:51 pm>Bootmem setup node 3 0000000000000000-0000000810000000
><Sep/11 01:51 pm>ACPI: PM-Timer IO Port: 0xd08
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
><Sep/11 01:51 pm>Processor #0 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x04] enabled)
><Sep/11 01:51 pm>Processor #4 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x02] lapic_id[0x08] enabled)
><Sep/11 01:51 pm>Processor #8 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x03] lapic_id[0x0c] enabled)
><Sep/11 01:51 pm>Processor #12 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x04] lapic_id[0x02] enabled)
><Sep/11 01:51 pm>Processor #2 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x05] lapic_id[0x06] enabled)
><Sep/11 01:51 pm>Processor #6 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x06] lapic_id[0x0a] enabled)
><Sep/11 01:51 pm>Processor #10 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x07] lapic_id[0x0e] enabled)
><Sep/11 01:51 pm>Processor #14 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x08] lapic_id[0x10] enabled)
><Sep/11 01:51 pm>Processor #16 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x09] lapic_id[0x14] enabled)
><Sep/11 01:51 pm>Processor #20 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x18] enabled)
><Sep/11 01:51 pm>Processor #24 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x1c] enabled)
><Sep/11 01:51 pm>Processor #28 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x12] enabled)
><Sep/11 01:51 pm>Processor #18 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x16] enabled)
><Sep/11 01:51 pm>Processor #22 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x1a] enabled)
><Sep/11 01:51 pm>Processor #26 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x1e] enabled)
><Sep/11 01:51 pm>Processor #30 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x10] lapic_id[0x20] enabled)
><Sep/11 01:51 pm>Processor #32 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x11] lapic_id[0x24] enabled)
><Sep/11 01:51 pm>Processor #36 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x12] lapic_id[0x28] enabled)
><Sep/11 01:51 pm>Processor #40 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x13] lapic_id[0x2c] enabled)
><Sep/11 01:51 pm>Processor #44 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x14] lapic_id[0x22] enabled)
><Sep/11 01:51 pm>Processor #34 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x15] lapic_id[0x26] enabled)
><Sep/11 01:51 pm>Processor #38 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x16] lapic_id[0x2a] enabled)
><Sep/11 01:51 pm>Processor #42 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x17] lapic_id[0x2e] enabled)
><Sep/11 01:51 pm>Processor #46 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x18] lapic_id[0x30] enabled)
><Sep/11 01:51 pm>Processor #48 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x19] lapic_id[0x34] enabled)
><Sep/11 01:51 pm>Processor #52 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1a] lapic_id[0x38] enabled)
><Sep/11 01:51 pm>Processor #56 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1b] lapic_id[0x3c] enabled)
><Sep/11 01:51 pm>Processor #60 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1c] lapic_id[0x32] enabled)
><Sep/11 01:51 pm>Processor #50 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1d] lapic_id[0x36] enabled)
><Sep/11 01:51 pm>Processor #54 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1e] lapic_id[0x3a] enabled)
><Sep/11 01:51 pm>Processor #58 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x1f] lapic_id[0x3e] enabled)
><Sep/11 01:51 pm>Processor #62 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x20] lapic_id[0x01] enabled)
><Sep/11 01:51 pm>Processor #1 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x21] lapic_id[0x05] enabled)
><Sep/11 01:51 pm>Processor #5 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x22] lapic_id[0x09] enabled)
><Sep/11 01:51 pm>Processor #9 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x23] lapic_id[0x0d] enabled)
><Sep/11 01:51 pm>Processor #13 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x24] lapic_id[0x03] enabled)
><Sep/11 01:51 pm>Processor #3 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x25] lapic_id[0x07] enabled)
><Sep/11 01:51 pm>Processor #7 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x26] lapic_id[0x0b] enabled)
><Sep/11 01:51 pm>Processor #11 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x27] lapic_id[0x0f] enabled)
><Sep/11 01:51 pm>Processor #15 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x28] lapic_id[0x11] enabled)
><Sep/11 01:51 pm>Processor #17 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x29] lapic_id[0x15] enabled)
><Sep/11 01:51 pm>Processor #21 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2a] lapic_id[0x19] enabled)
><Sep/11 01:51 pm>Processor #25 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2b] lapic_id[0x1d] enabled)
><Sep/11 01:51 pm>Processor #29 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2c] lapic_id[0x13] enabled)
><Sep/11 01:51 pm>Processor #19 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2d] lapic_id[0x17] enabled)
><Sep/11 01:51 pm>Processor #23 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2e] lapic_id[0x1b] enabled)
><Sep/11 01:51 pm>Processor #27 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x2f] lapic_id[0x1f] enabled)
><Sep/11 01:51 pm>Processor #31 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x30] lapic_id[0x21] enabled)
><Sep/11 01:51 pm>Processor #33 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x31] lapic_id[0x25] enabled)
><Sep/11 01:51 pm>Processor #37 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x32] lapic_id[0x29] enabled)
><Sep/11 01:51 pm>Processor #41 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x33] lapic_id[0x2d] enabled)
><Sep/11 01:51 pm>Processor #45 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x34] lapic_id[0x23] enabled)
><Sep/11 01:51 pm>Processor #35 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x35] lapic_id[0x27] enabled)
><Sep/11 01:51 pm>Processor #39 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x36] lapic_id[0x2b] enabled)
><Sep/11 01:51 pm>Processor #43 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x37] lapic_id[0x2f] enabled)
><Sep/11 01:51 pm>Processor #47 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x38] lapic_id[0x31] enabled)
><Sep/11 01:51 pm>Processor #49 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x39] lapic_id[0x35] enabled)
><Sep/11 01:51 pm>Processor #53 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3a] lapic_id[0x39] enabled)
><Sep/11 01:51 pm>Processor #57 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3b] lapic_id[0x3d] enabled)
><Sep/11 01:51 pm>Processor #61 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3c] lapic_id[0x33] enabled)
><Sep/11 01:51 pm>Processor #51 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3d] lapic_id[0x37] enabled)
><Sep/11 01:51 pm>Processor #55 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3e] lapic_id[0x3b] enabled)
><Sep/11 01:51 pm>Processor #59 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC (acpi_id[0x3f] lapic_id[0x3f] enabled)
><Sep/11 01:51 pm>Processor #63 15:6 APIC version 20
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x11] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x12] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x13] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x14] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x15] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x16] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x17] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x18] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x19] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1a] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1b] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1c] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1d] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1e] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x1f] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x20] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x21] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x22] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x23] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x24] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x25] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x26] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x27] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x28] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x29] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2a] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2b] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2c] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2d] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2e] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x2f] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x30] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x31] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x32] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x33] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x34] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x35] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x36] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x37] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x38] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x39] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3a] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3b] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3c] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3d] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3e] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: LAPIC_NMI (acpi_id[0x3f] high edge lint[0x1])
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0])
><Sep/11 01:51 pm>IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x08] address[0xfec02000] gsi_base[24])
><Sep/11 01:51 pm>IOAPIC[1]: apic_id 8, version 32, address 0xfec02000, GSI 24-47
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x09] address[0xfec03000] gsi_base[48])
><Sep/11 01:51 pm>IOAPIC[2]: apic_id 9, version 32, address 0xfec03000, GSI 48-71
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0a] address[0xfec04000] gsi_base[72])
><Sep/11 01:51 pm>IOAPIC[3]: apic_id 10, version 32, address 0xfec04000, GSI 72-95
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0b] address[0xfec05000] gsi_base[96])
><Sep/11 01:51 pm>IOAPIC[4]: apic_id 11, version 32, address 0xfec05000, GSI 96-119
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0c] address[0xfec06000] gsi_base[120])
><Sep/11 01:51 pm>IOAPIC[5]: apic_id 12, version 32, address 0xfec06000, GSI 120-143
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0d] address[0xfec07000] gsi_base[144])
><Sep/11 01:51 pm>IOAPIC[6]: apic_id 13, version 32, address 0xfec07000, GSI 144-167
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0e] address[0xfec08000] gsi_base[168])
><Sep/11 01:51 pm>IOAPIC[7]: apic_id 14, version 32, address 0xfec08000, GSI 168-191
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x0f] address[0xfec09000] gsi_base[192])
><Sep/11 01:51 pm>IOAPIC[8]: apic_id 15, version 32, address 0xfec09000, GSI 192-215
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x18] address[0xfec12000] gsi_base[408])
><Sep/11 01:51 pm>IOAPIC[9]: apic_id 24, version 32, address 0xfec12000, GSI 408-431
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x19] address[0xfec13000] gsi_base[432])
><Sep/11 01:51 pm>IOAPIC[10]: apic_id 25, version 32, address 0xfec13000, GSI 432-455
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1a] address[0xfec14000] gsi_base[456])
><Sep/11 01:51 pm>IOAPIC[11]: apic_id 26, version 32, address 0xfec14000, GSI 456-479
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1b] address[0xfec15000] gsi_base[480])
><Sep/11 01:51 pm>IOAPIC[12]: apic_id 27, version 32, address 0xfec15000, GSI 480-503
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1c] address[0xfec16000] gsi_base[504])
><Sep/11 01:51 pm>IOAPIC[13]: apic_id 28, version 32, address 0xfec16000, GSI 504-527
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1d] address[0xfec17000] gsi_base[528])
><Sep/11 01:51 pm>IOAPIC[14]: apic_id 29, version 32, address 0xfec17000, GSI 528-551
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1e] address[0xfec18000] gsi_base[552])
><Sep/11 01:51 pm>IOAPIC[15]: apic_id 30, version 32, address 0xfec18000, GSI 552-575
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x1f] address[0xfec19000] gsi_base[576])
><Sep/11 01:51 pm>IOAPIC[16]: apic_id 31, version 32, address 0xfec19000, GSI 576-599
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x28] address[0xfec1a000] gsi_base[600])
><Sep/11 01:51 pm>IOAPIC[17]: apic_id 40, version 32, address 0xfec1a000, GSI 600-623
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x29] address[0xfec1b000] gsi_base[624])
><Sep/11 01:51 pm>IOAPIC[18]: apic_id 41, version 32, address 0xfec1b000, GSI 624-647
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2a] address[0xfec1c000] gsi_base[648])
><Sep/11 01:51 pm>IOAPIC[19]: apic_id 42, version 32, address 0xfec1c000, GSI 648-671
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2b] address[0xfec1d000] gsi_base[672])
><Sep/11 01:51 pm>IOAPIC[20]: apic_id 43, version 32, address 0xfec1d000, GSI 672-695
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2c] address[0xfec1e000] gsi_base[696])
><Sep/11 01:51 pm>IOAPIC[21]: apic_id 44, version 32, address 0xfec1e000, GSI 696-719
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2d] address[0xfec1f000] gsi_base[720])
><Sep/11 01:51 pm>IOAPIC[22]: apic_id 45, version 32, address 0xfec1f000, GSI 720-743
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2e] address[0xfec20000] gsi_base[744])
><Sep/11 01:51 pm>IOAPIC[23]: apic_id 46, version 32, address 0xfec20000, GSI 744-767
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x2f] address[0xfec21000] gsi_base[768])
><Sep/11 01:51 pm>IOAPIC[24]: apic_id 47, version 32, address 0xfec21000, GSI 768-791
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x38] address[0xfec22000] gsi_base[792])
><Sep/11 01:51 pm>IOAPIC[25]: apic_id 56, version 32, address 0xfec22000, GSI 792-815
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x39] address[0xfec23000] gsi_base[816])
><Sep/11 01:51 pm>IOAPIC[26]: apic_id 57, version 32, address 0xfec23000, GSI 816-839
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3a] address[0xfec24000] gsi_base[840])
><Sep/11 01:51 pm>IOAPIC[27]: apic_id 58, version 32, address 0xfec24000, GSI 840-863
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3b] address[0xfec25000] gsi_base[864])
><Sep/11 01:51 pm>IOAPIC[28]: apic_id 59, version 32, address 0xfec25000, GSI 864-887
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3c] address[0xfec26000] gsi_base[888])
><Sep/11 01:51 pm>IOAPIC[29]: apic_id 60, version 32, address 0xfec26000, GSI 888-911
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3d] address[0xfec27000] gsi_base[912])
><Sep/11 01:51 pm>IOAPIC[30]: apic_id 61, version 32, address 0xfec27000, GSI 912-935
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3e] address[0xfec28000] gsi_base[936])
><Sep/11 01:51 pm>IOAPIC[31]: apic_id 62, version 32, address 0xfec28000, GSI 936-959
><Sep/11 01:51 pm>ACPI: IOAPIC (id[0x3f] address[0xfec29000] gsi_base[960])
><Sep/11 01:51 pm>IOAPIC[32]: apic_id 63, version 32, address 0xfec29000, GSI 960-983
><Sep/11 01:51 pm>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge)
><Sep/11 01:51 pm>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
><Sep/11 01:51 pm>Setting APIC routing to clustered
><Sep/11 01:51 pm>Using ACPI (MADT) for SMP configuration information
><Sep/11 01:51 pm>Nosave address range: 000000000009d000 - 000000000009e000
><Sep/11 01:51 pm>Nosave address range: 000000000009e000 - 00000000000a0000
><Sep/11 01:51 pm>Nosave address range: 00000000000a0000 - 0000000000100000
><Sep/11 01:51 pm>Nosave address range: 0000000037e70000 - 0000000037ed6000
><Sep/11 01:51 pm>Nosave address range: 0000000037ed6000 - 0000000037f00000
><Sep/11 01:51 pm>Nosave address range: 00000000d8000000 - 00000000f8000000
><Sep/11 01:51 pm>Nosave address range: 00000000f8000000 - 00000000fec00000
><Sep/11 01:51 pm>Nosave address range: 00000000fec00000 - 00000000fffc0000
><Sep/11 01:51 pm>Nosave address range: 00000000fffc0000 - 0000000100000000
><Sep/11 01:51 pm>Allocating PCI resources starting at da000000 (gap: d8000000:20000000)
><Sep/11 01:51 pm>SMP: Allowing 64 CPUs, 0 hotplug CPUs
><Sep/11 01:51 pm>Built 4 zonelists.  Total pages: 33059503
><Sep/11 01:51 pm>Kernel command line: ro root=/dev/VolGroup00/LogVol00 crashkernel=128M@16M console=ttyS0,115200 kexecboot
><Sep/11 01:51 pm>Initializing CPU#0
><Sep/11 01:51 pm>PID hash table entries: 4096 (order: 12, 32768 bytes)
><Sep/11 01:51 pm>Console: colour VGA+ 80x25
><Sep/11 01:51 pm>Dentry cache hash table entries: 16777216 (order: 15, 134217728 bytes)
><Sep/11 01:51 pm>Inode-cache hash table entries: 8388608 (order: 14, 67108864 bytes)
><Sep/11 01:51 pm>Checking aperture...
><Sep/11 01:51 pm>PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
><Sep/11 01:51 pm>Placing software IO TLB between 0x1509a000 - 0x1909a000
><Sep/11 01:51 pm>Memory: 131838320k/134742016k available (2435k kernel code, 2247360k reserved, 1235k data, 192k init)
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6803.51 BogoMIPS (lpj=3401757)
><Sep/11 01:51 pm>Security Framework v1.0.0 initialized
><Sep/11 01:51 pm>SELinux:  Initializing.
><Sep/11 01:51 pm>selinux_register_security:  Registering secondary module capability
><Sep/11 01:51 pm>Capability LSM initialized as secondary
><Sep/11 01:51 pm>Mount-cache hash table entries: 256
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 0/0 -> Node 3
><Sep/11 01:51 pm>using mwait in idle threads.
><Sep/11 01:51 pm>CPU: Physical Processor ID: 0
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>SMP alternatives: switching to UP code
><Sep/11 01:51 pm>ACPI: Core revision 20060707
><Sep/11 01:51 pm>Using local APIC timer interrupts.
><Sep/11 01:51 pm>result 12500243
><Sep/11 01:51 pm>Detected 12.500 MHz APIC timer.
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 1/64 APIC 0x4
><Sep/11 01:51 pm>Initializing CPU#1
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.30 BogoMIPS (lpj=3399651)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 1/4 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 1
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU1: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 1: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 1: synchronized TSC with CPU 0 (last diff 10 cycles, maxerr 1751 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 2/64 APIC 0x8
><Sep/11 01:51 pm>Initializing CPU#2
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6798.82 BogoMIPS (lpj=3399412)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 2/8 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 2
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU2: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 2: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 2: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 3/64 APIC 0xc
><Sep/11 01:51 pm>Initializing CPU#3
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.32 BogoMIPS (lpj=3399663)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 3/c -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 3
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU3: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 3: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 3: synchronized TSC with CPU 0 (last diff -8 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 4/64 APIC 0x2
><Sep/11 01:51 pm>Initializing CPU#4
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6798.75 BogoMIPS (lpj=3399376)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 4/2 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 0
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU4: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 4: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 4: synchronized TSC with CPU 0 (last diff 9 cycles, maxerr 1003 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 5/64 APIC 0x6
><Sep/11 01:51 pm>Initializing CPU#5
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6798.83 BogoMIPS (lpj=3399416)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 5/6 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 1
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU5: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 5: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 5: synchronized TSC with CPU 0 (last diff 17 cycles, maxerr 1734 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 6/64 APIC 0xa
><Sep/11 01:51 pm>Initializing CPU#6
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.32 BogoMIPS (lpj=3399662)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 6/a -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 2
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU6: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 6: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 6: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 2193 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 7/64 APIC 0xe
><Sep/11 01:51 pm>Initializing CPU#7
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.32 BogoMIPS (lpj=3399660)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 7/e -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 3
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU7: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 7: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 7: synchronized TSC with CPU 0 (last diff -8 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 8/64 APIC 0x10
><Sep/11 01:51 pm>Initializing CPU#8
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.03 BogoMIPS (lpj=3399515)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 8/10 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 4
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU8: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 8: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 8: synchronized TSC with CPU 0 (last diff -9 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 9/64 APIC 0x14
><Sep/11 01:51 pm>Initializing CPU#9
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.48 BogoMIPS (lpj=3399740)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 9/14 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 5
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU9: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 9: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 9: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 6324 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 10/64 APIC 0x18
><Sep/11 01:51 pm>Initializing CPU#10
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.52 BogoMIPS (lpj=3399760)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 10/18 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 6
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU10: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 10: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 10: synchronized TSC with CPU 0 (last diff 135 cycles, maxerr 6511 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 11/64 APIC 0x1c
><Sep/11 01:51 pm>Initializing CPU#11
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.48 BogoMIPS (lpj=3399744)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 11/1c -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 7
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU11: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 11: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 11: synchronized TSC with CPU 0 (last diff 133 cycles, maxerr 6494 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 12/64 APIC 0x12
><Sep/11 01:51 pm>Initializing CPU#12
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.47 BogoMIPS (lpj=3399736)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 12/12 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 4
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU12: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 12: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 12: synchronized TSC with CPU 0 (last diff -9 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 13/64 APIC 0x16
><Sep/11 01:51 pm>Initializing CPU#13
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.47 BogoMIPS (lpj=3399739)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 13/16 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 5
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU13: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 13: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 13: synchronized TSC with CPU 0 (last diff -9 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 14/64 APIC 0x1a
><Sep/11 01:51 pm>Initializing CPU#14
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.48 BogoMIPS (lpj=3399742)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 14/1a -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 6
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU14: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 14: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 14: synchronized TSC with CPU 0 (last diff 71 cycles, maxerr 6596 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 15/64 APIC 0x1e
><Sep/11 01:51 pm>Initializing CPU#15
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.49 BogoMIPS (lpj=3399748)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 15/1e -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 7
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU15: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 15: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 15: synchronized TSC with CPU 0 (last diff 145 cycles, maxerr 6494 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 16/64 APIC 0x20
><Sep/11 01:51 pm>Initializing CPU#16
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.55 BogoMIPS (lpj=3399776)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 16/20 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 8
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU16: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 16: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 16: synchronized TSC with CPU 0 (last diff 26 cycles, maxerr 7786 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 17/64 APIC 0x24
><Sep/11 01:51 pm>Initializing CPU#17
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.54 BogoMIPS (lpj=3399774)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 17/24 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 9
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU17: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 17: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 17: synchronized TSC with CPU 0 (last diff 4 cycles, maxerr 7786 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 18/64 APIC 0x28
><Sep/11 01:51 pm>Initializing CPU#18
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.56 BogoMIPS (lpj=3399782)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 18/28 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 10
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU18: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 18: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 18: synchronized TSC with CPU 0 (last diff 1 cycles, maxerr 7378 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 19/64 APIC 0x2c
><Sep/11 01:51 pm>Initializing CPU#19
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.55 BogoMIPS (lpj=3399778)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 19/2c -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 11
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU19: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 19: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 19: synchronized TSC with CPU 0 (last diff 2 cycles, maxerr 7361 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 20/64 APIC 0x22
><Sep/11 01:51 pm>Initializing CPU#20
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.54 BogoMIPS (lpj=3399770)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 20/22 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 8
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU20: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 20: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 20: synchronized TSC with CPU 0 (last diff -3 cycles, maxerr 7803 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 21/64 APIC 0x26
><Sep/11 01:51 pm>Initializing CPU#21
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.07 BogoMIPS (lpj=3399536)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 21/26 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 9
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU21: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 21: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 21: synchronized TSC with CPU 0 (last diff 5 cycles, maxerr 7786 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 22/64 APIC 0x2a
><Sep/11 01:51 pm>Initializing CPU#22
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.52 BogoMIPS (lpj=3399762)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 22/2a -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 10
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU22: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 22: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 22: synchronized TSC with CPU 0 (last diff -136 cycles, maxerr 7378 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 23/64 APIC 0x2e
><Sep/11 01:51 pm>Initializing CPU#23
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.56 BogoMIPS (lpj=3399781)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 23/2e -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 11
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU23: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 23: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 23: synchronized TSC with CPU 0 (last diff 168 cycles, maxerr 7072 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 24/64 APIC 0x30
><Sep/11 01:51 pm>Initializing CPU#24
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.55 BogoMIPS (lpj=3399778)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 24/30 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 12
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU24: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 24: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 24: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 8143 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 25/64 APIC 0x34
><Sep/11 01:51 pm>Initializing CPU#25
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.55 BogoMIPS (lpj=3399778)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 25/34 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 13
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU25: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 25: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 25: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 8143 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 26/64 APIC 0x38
><Sep/11 01:51 pm>Initializing CPU#26
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.58 BogoMIPS (lpj=3399791)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 26/38 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 14
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU26: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 26: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 26: synchronized TSC with CPU 0 (last diff -35 cycles, maxerr 7429 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 27/64 APIC 0x3c
><Sep/11 01:51 pm>Initializing CPU#27
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.07 BogoMIPS (lpj=3399536)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 27/3c -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 15
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU27: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 27: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 27: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7429 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 28/64 APIC 0x32
><Sep/11 01:51 pm>Initializing CPU#28
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.56 BogoMIPS (lpj=3399781)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 28/32 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 12
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU28: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 28: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 28: synchronized TSC with CPU 0 (last diff -33 cycles, maxerr 7956 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 29/64 APIC 0x36
><Sep/11 01:51 pm>Initializing CPU#29
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.08 BogoMIPS (lpj=3399540)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 29/36 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 13
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU29: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 29: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 29: synchronized TSC with CPU 0 (last diff 8 cycles, maxerr 8041 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 30/64 APIC 0x3a
><Sep/11 01:51 pm>Initializing CPU#30
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.58 BogoMIPS (lpj=3399794)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 30/3a -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 14
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU30: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 30: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 30: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7429 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 31/64 APIC 0x3e
><Sep/11 01:51 pm>Initializing CPU#31
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.10 BogoMIPS (lpj=3399552)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 31/3e -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 15
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU31: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 31: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 31: synchronized TSC with CPU 0 (last diff 3 cycles, maxerr 7429 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 32/64 APIC 0x1
><Sep/11 01:51 pm>Initializing CPU#32
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.61 BogoMIPS (lpj=3399808)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 32/1 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 0
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU32: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 32: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 32: synchronized TSC with CPU 0 (last diff -110 cycles, maxerr 952 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 33/64 APIC 0x5
><Sep/11 01:51 pm>Initializing CPU#33
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.50 BogoMIPS (lpj=3399754)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 33/5 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 1
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU33: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 33: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 33: synchronized TSC with CPU 0 (last diff 8 cycles, maxerr 1751 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 34/64 APIC 0x9
><Sep/11 01:51 pm>Initializing CPU#34
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.17 BogoMIPS (lpj=3399588)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 34/9 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 2
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU34: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 34: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 34: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 35/64 APIC 0xd
><Sep/11 01:51 pm>Initializing CPU#35
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.16 BogoMIPS (lpj=3399584)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 35/d -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 3
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU35: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 35: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 35: synchronized TSC with CPU 0 (last diff 8 cycles, maxerr 2193 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 36/64 APIC 0x3
><Sep/11 01:51 pm>Initializing CPU#36
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.11 BogoMIPS (lpj=3399558)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 36/3 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 0
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU36: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 36: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 36: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 1020 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 37/64 APIC 0x7
><Sep/11 01:51 pm>Initializing CPU#37
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.86 BogoMIPS (lpj=3399934)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 37/7 -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 1
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU37: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 37: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 37: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 1751 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 38/64 APIC 0xb
><Sep/11 01:51 pm>Initializing CPU#38
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.64 BogoMIPS (lpj=3399822)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 38/b -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 2
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU38: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 38: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 38: synchronized TSC with CPU 0 (last diff -17 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 39/64 APIC 0xf
><Sep/11 01:51 pm>Initializing CPU#39
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.64 BogoMIPS (lpj=3399821)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 39/f -> Node 3
><Sep/11 01:51 pm>CPU: Physical Processor ID: 3
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU39: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 39: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 39: synchronized TSC with CPU 0 (last diff -8 cycles, maxerr 2210 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 40/64 APIC 0x11
><Sep/11 01:51 pm>Initializing CPU#40
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.61 BogoMIPS (lpj=3399806)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 40/11 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 4
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU40: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 40: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 40: synchronized TSC with CPU 0 (last diff 8 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 41/64 APIC 0x15
><Sep/11 01:51 pm>Initializing CPU#41
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.58 BogoMIPS (lpj=3399793)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 41/15 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 5
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU41: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 41: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 41: synchronized TSC with CPU 0 (last diff -19 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 42/64 APIC 0x19
><Sep/11 01:51 pm>Initializing CPU#42
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.11 BogoMIPS (lpj=3399558)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 42/19 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 6
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU42: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 42: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 42: synchronized TSC with CPU 0 (last diff 108 cycles, maxerr 6783 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 43/64 APIC 0x1d
><Sep/11 01:51 pm>Initializing CPU#43
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.62 BogoMIPS (lpj=3399812)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 43/1d -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 7
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU43: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 43: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 43: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 6766 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 44/64 APIC 0x13
><Sep/11 01:51 pm>Initializing CPU#44
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.61 BogoMIPS (lpj=3399805)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 44/13 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 4
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU44: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 44: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 44: synchronized TSC with CPU 0 (last diff 8 cycles, maxerr 6341 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 45/64 APIC 0x17
><Sep/11 01:51 pm>Initializing CPU#45
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.49 BogoMIPS (lpj=3399749)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 45/17 -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 5
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU45: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 45: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 45: synchronized TSC with CPU 0 (last diff 72 cycles, maxerr 6324 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 46/64 APIC 0x1b
><Sep/11 01:51 pm>Initializing CPU#46
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.60 BogoMIPS (lpj=3399803)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 46/1b -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 6
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU46: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 46: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 46: synchronized TSC with CPU 0 (last diff -33 cycles, maxerr 6783 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 47/64 APIC 0x1f
><Sep/11 01:51 pm>Initializing CPU#47
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.66 BogoMIPS (lpj=3399831)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 47/1f -> Node 2
><Sep/11 01:51 pm>CPU: Physical Processor ID: 7
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU47: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 47: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 47: synchronized TSC with CPU 0 (last diff -22 cycles, maxerr 6766 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 48/64 APIC 0x21
><Sep/11 01:51 pm>Initializing CPU#48
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.17 BogoMIPS (lpj=3399587)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 48/21 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 8
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU48: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 48: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 48: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7803 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 49/64 APIC 0x25
><Sep/11 01:51 pm>Initializing CPU#49
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.57 BogoMIPS (lpj=3399787)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 49/25 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 9
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU49: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 49: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 49: synchronized TSC with CPU 0 (last diff 47 cycles, maxerr 7310 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 50/64 APIC 0x29
><Sep/11 01:51 pm>Initializing CPU#50
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.11 BogoMIPS (lpj=3399559)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 50/29 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 10
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU50: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 50: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 50: synchronized TSC with CPU 0 (last diff 85 cycles, maxerr 7344 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 51/64 APIC 0x2d
><Sep/11 01:51 pm>Initializing CPU#51
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.57 BogoMIPS (lpj=3399788)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 51/2d -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 11
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU51: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 51: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 51: synchronized TSC with CPU 0 (last diff -2 cycles, maxerr 7089 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 52/64 APIC 0x23
><Sep/11 01:51 pm>Initializing CPU#52
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.13 BogoMIPS (lpj=3399567)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 52/23 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 8
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU52: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 52: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 52: synchronized TSC with CPU 0 (last diff 21 cycles, maxerr 7803 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 53/64 APIC 0x27
><Sep/11 01:51 pm>Initializing CPU#53
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.54 BogoMIPS (lpj=3399774)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 53/27 -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 9
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU53: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 53: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 53: synchronized TSC with CPU 0 (last diff 145 cycles, maxerr 7514 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 54/64 APIC 0x2b
><Sep/11 01:51 pm>Initializing CPU#54
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.35 BogoMIPS (lpj=3399679)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 54/2b -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 10
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU54: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 54: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 54: synchronized TSC with CPU 0 (last diff 3 cycles, maxerr 7361 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 55/64 APIC 0x2f
><Sep/11 01:51 pm>Initializing CPU#55
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.49 BogoMIPS (lpj=3399749)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 55/2f -> Node 1
><Sep/11 01:51 pm>CPU: Physical Processor ID: 11
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU55: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 55: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 55: synchronized TSC with CPU 0 (last diff 184 cycles, maxerr 7072 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 56/64 APIC 0x31
><Sep/11 01:51 pm>Initializing CPU#56
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.48 BogoMIPS (lpj=3399743)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 56/31 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 12
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU56: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 56: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 56: synchronized TSC with CPU 0 (last diff -9 cycles, maxerr 7973 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 57/64 APIC 0x35
><Sep/11 01:51 pm>Initializing CPU#57
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.32 BogoMIPS (lpj=3399661)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 57/35 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 13
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU57: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 57: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 57: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 8143 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 58/64 APIC 0x39
><Sep/11 01:51 pm>Initializing CPU#58
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.68 BogoMIPS (lpj=3399840)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 58/39 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 14
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU58: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 58: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 58: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7531 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 59/64 APIC 0x3d
><Sep/11 01:51 pm>Initializing CPU#59
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.14 BogoMIPS (lpj=3399572)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 59/3d -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 15
><Sep/11 01:51 pm>CPU: Processor Core ID: 0
><Sep/11 01:51 pm>CPU59: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 59: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 59: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7531 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 60/64 APIC 0x33
><Sep/11 01:51 pm>Initializing CPU#60
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.55 BogoMIPS (lpj=3399777)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 60/33 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 12
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU60: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 60: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 60: synchronized TSC with CPU 0 (last diff -34 cycles, maxerr 7990 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 61/64 APIC 0x37
><Sep/11 01:51 pm>Initializing CPU#61
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.09 BogoMIPS (lpj=3399545)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 61/37 -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 13
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU61: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 61: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 61: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 8041 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 62/64 APIC 0x3b
><Sep/11 01:51 pm>Initializing CPU#62
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.60 BogoMIPS (lpj=3399804)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 62/3b -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 14
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU62: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 62: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 62: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 7531 cycles)
><Sep/11 01:51 pm>SMP alternatives: switching to SMP code
><Sep/11 01:51 pm>Booting processor 63/64 APIC 0x3f
><Sep/11 01:51 pm>Initializing CPU#63
><Sep/11 01:51 pm>Calibrating delay using timer specific routine.. 6799.48 BogoMIPS (lpj=3399741)
><Sep/11 01:51 pm>CPU: Trace cache: 12K uops, L1 D cache: 16K
><Sep/11 01:51 pm>CPU: L2 cache: 1024K
><Sep/11 01:51 pm>CPU: L3 cache: 16384K
><Sep/11 01:51 pm>CPU 63/3f -> Node 0
><Sep/11 01:51 pm>CPU: Physical Processor ID: 15
><Sep/11 01:51 pm>CPU: Processor Core ID: 1
><Sep/11 01:51 pm>CPU63: Thermal monitoring enabled (TM1)
><Sep/11 01:51 pm>                   Genuine Intel(R) CPU 3.40GHz stepping 08
><Sep/11 01:51 pm>CPU 63: Syncing TSC to CPU 0.
><Sep/11 01:51 pm>CPU 63: synchronized TSC with CPU 0 (last diff -76 cycles, maxerr 7378 cycles)
><Sep/11 01:51 pm>Brought up 64 CPUs
><Sep/11 01:51 pm>testing NMI watchdog ... OK.
><Sep/11 01:51 pm>Disabling vsyscall due to use of PM timer
><Sep/11 01:51 pm>time.c: Using 3.579545 MHz WALL PM GTOD PM timer.
><Sep/11 01:51 pm>time.c: Detected 3400.042 MHz processor.
><Sep/11 01:51 pm>migration_cost=11,107,7348,42542
><Sep/11 01:51 pm>checking if image is initramfs... it is
><Sep/11 01:51 pm>Freeing initrd memory: 3268k freed
><Sep/11 01:51 pm>NET: Registered protocol family 16
><Sep/11 01:51 pm>ACPI: bus type pci registered
><Sep/11 01:51 pm>PCI: Using configuration type 1
><Sep/11 01:51 pm>ACPI: Interpreter enabled
><Sep/11 01:51 pm>ACPI: Using IOAPIC for interrupt routing
><Sep/11 01:51 pm>ACPI: Device [MBDV] status [00000008]: functional but not present; setting present
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [MBDV] (0000:ff)
><Sep/11 01:51 pm>ACPI: Device [MEDV] status [00000008]: functional but not present; setting present
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [MEDV] (0000:fe)
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S0H0] (0000:00)
><Sep/11 01:51 pm>PCI quirk: region 0d00-0d7f claimed by ICH4 ACPI/GPIO/TCO
><Sep/11 01:51 pm>PCI quirk: region 0e80-0ebf claimed by ICH4 GPIO
><Sep/11 01:51 pm>PCI: Ignoring BAR0-3 of IDE controller 0000:00:1f.1
><Sep/11 01:51 pm>PCI: Transparent bridge - 0000:00:1e.0
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKA] (IRQs 3 10 *11 14 15), disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKB] (IRQs 3 *10 11 14 15), disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKC] (IRQs 3 10 *11 14 15), disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKD] (IRQs 3 10 *11 14 15), disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKE] (IRQs 3 10 11 14 15) *0, disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKF] (IRQs 3 10 11 14 15) *12, disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKG] (IRQs 3 10 11 14 15) *12, disabled.
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKH] (IRQs 3 *6 10 11 14 15), disabled.
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S0H1] (0000:02)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S0H2] (0000:0f)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S0H3] (0000:1c)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S0H4] (0000:28)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S1H1] (0000:67)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S1H2] (0000:74)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S1H3] (0000:80)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S1H4] (0000:8c)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S2H1] (0000:99)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S2H2] (0000:a6)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S2H3] (0000:b2)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S2H4] (0000:be)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S3H1] (0000:cb)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S3H2] (0000:d8)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S3H3] (0000:e5)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Root Bridge [S3H4] (0000:f2)
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>PCI: Enable I/O Space to 1 KB Granularity
><Sep/11 01:51 pm>ACPI: PCI Interrupt Link [LNKA] (IRQs *10)
><Sep/11 01:51 pm>Linux Plug and Play Support v0.97 (c) Adam Belay
><Sep/11 01:51 pm>pnp: PnP ACPI init
><Sep/11 01:51 pm>pnp: PnP ACPI: found 23 devices
><Sep/11 01:51 pm>usbcore: registered new driver usbfs
><Sep/11 01:51 pm>usbcore: registered new driver hub
><Sep/11 01:51 pm>PCI: Using ACPI for IRQ routing
><Sep/11 01:51 pm>PCI: If a device doesn't work, try "pci=routeirq".  If it helps, post a report
><Sep/11 01:51 pm>NetLabel: Initializing
><Sep/11 01:51 pm>NetLabel:  domain hash size = 128
><Sep/11 01:51 pm>NetLabel:  protocols = UNLABELED CIPSOv4
><Sep/11 01:51 pm>NetLabel:  unlabeled traffic allowed by default
><Sep/11 01:51 pm>PCI-GART: No AMD northbridge found.
><Sep/11 01:51 pm>PCI: Bridge: 0000:00:1e.0
><Sep/11 01:51 pm>  IO window: 1000-1fff
><Sep/11 01:51 pm>  MEM window: f6000000-f7efffff
><Sep/11 01:51 pm>  PREFETCH window: da000000-da0fffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:02:1d.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:02:1f.0
><Sep/11 01:51 pm>  IO window: 2000-23ff
><Sep/11 01:51 pm>  MEM window: f4f00000-f4ffffff
><Sep/11 01:51 pm>  PREFETCH window: da200000-da3fffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:0f:1d.0
><Sep/11 01:51 pm>  IO window: 2800-2bff
><Sep/11 01:51 pm>  MEM window: f3f00000-f3ffffff
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:16:01.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: f3d00000-f3dfffff
><Sep/11 01:51 pm>  PREFETCH window: f2d00000-f2dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:0f:1f.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: f3d00000-f3efffff
><Sep/11 01:51 pm>  PREFETCH window: f2d00000-f2ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:1c:1d.0
><Sep/11 01:51 pm>  IO window: 3000-33ff
><Sep/11 01:51 pm>  MEM window: f1f00000-f1ffffff
><Sep/11 01:51 pm>  PREFETCH window: f0e00000-f0ffffff
><Sep/11 01:51 pm>PCI: Failed to allocate mem resource #6:100000@f0e00000 for 0000:23:01.1
><Sep/11 01:51 pm>PCI: Bridge: 0000:1c:1f.0
><Sep/11 01:51 pm>  IO window: 3400-37ff
><Sep/11 01:51 pm>  MEM window: f1d00000-f1efffff
><Sep/11 01:51 pm>  PREFETCH window: f0c00000-f0dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:28:1d.0
><Sep/11 01:51 pm>  IO window: 3800-3bff
><Sep/11 01:51 pm>  MEM window: eff00000-efffffff
><Sep/11 01:51 pm>  PREFETCH window: eee00000-eeffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:28:1f.0
><Sep/11 01:51 pm>  IO window: 3c00-3fff
><Sep/11 01:51 pm>  MEM window: efd00000-efefffff
><Sep/11 01:51 pm>  PREFETCH window: eec00000-eedfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:67:1d.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:67:1f.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:74:1d.0
><Sep/11 01:51 pm>  IO window: 4000-43ff
><Sep/11 01:51 pm>  MEM window: ecf00000-ecffffff
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:74:1f.0
><Sep/11 01:51 pm>  IO window: 4400-47ff
><Sep/11 01:51 pm>  MEM window: ecd00000-ecefffff
><Sep/11 01:51 pm>  PREFETCH window: ebe00000-ebffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:80:1d.0
><Sep/11 01:51 pm>  IO window: 4800-4bff
><Sep/11 01:51 pm>  MEM window: eae00000-eaffffff
><Sep/11 01:51 pm>  PREFETCH window: e9e00000-e9ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:80:1f.0
><Sep/11 01:51 pm>  IO window: 4c00-4fff
><Sep/11 01:51 pm>  MEM window: eac00000-eadfffff
><Sep/11 01:51 pm>  PREFETCH window: e9c00000-e9dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:8c:1d.0
><Sep/11 01:51 pm>  IO window: 5000-53ff
><Sep/11 01:51 pm>  MEM window: e8f00000-e8ffffff
><Sep/11 01:51 pm>  PREFETCH window: e7e00000-e7ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:8c:1f.0
><Sep/11 01:51 pm>  IO window: 5400-57ff
><Sep/11 01:51 pm>  MEM window: e8d00000-e8efffff
><Sep/11 01:51 pm>  PREFETCH window: e7c00000-e7dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:99:1d.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:99:1f.0
><Sep/11 01:51 pm>  IO window: 5800-5bff
><Sep/11 01:51 pm>  MEM window: e6f00000-e6ffffff
><Sep/11 01:51 pm>  PREFETCH window: da400000-da5fffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:a6:1d.0
><Sep/11 01:51 pm>  IO window: 6000-63ff
><Sep/11 01:51 pm>  MEM window: e5f00000-e5ffffff
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:a6:1f.0
><Sep/11 01:51 pm>  IO window: 6400-67ff
><Sep/11 01:51 pm>  MEM window: e5e00000-e5efffff
><Sep/11 01:51 pm>  PREFETCH window: e4e00000-e4ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:b2:1d.0
><Sep/11 01:51 pm>  IO window: 6800-6bff
><Sep/11 01:51 pm>  MEM window: e3f00000-e3ffffff
><Sep/11 01:51 pm>  PREFETCH window: e2e00000-e2ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:b2:1f.0
><Sep/11 01:51 pm>  IO window: 6c00-6fff
><Sep/11 01:51 pm>  MEM window: e3e00000-e3efffff
><Sep/11 01:51 pm>  PREFETCH window: e2c00000-e2dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:be:1d.0
><Sep/11 01:51 pm>  IO window: 7000-73ff
><Sep/11 01:51 pm>  MEM window: e1f00000-e1ffffff
><Sep/11 01:51 pm>  PREFETCH window: e0e00000-e0ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:be:1f.0
><Sep/11 01:51 pm>  IO window: 7400-77ff
><Sep/11 01:51 pm>  MEM window: e1e00000-e1efffff
><Sep/11 01:51 pm>  PREFETCH window: e0c00000-e0dfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:cb:1d.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:cb:1f.0
><Sep/11 01:51 pm>  IO window: disabled.
><Sep/11 01:51 pm>  MEM window: disabled.
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:d8:1d.0
><Sep/11 01:51 pm>  IO window: 7800-7bff
><Sep/11 01:51 pm>  MEM window: def00000-deffffff
><Sep/11 01:51 pm>  PREFETCH window: disabled.
><Sep/11 01:51 pm>PCI: Bridge: 0000:d8:1f.0
><Sep/11 01:51 pm>  IO window: 7c00-7fff
><Sep/11 01:51 pm>  MEM window: dee00000-deefffff
><Sep/11 01:51 pm>  PREFETCH window: dde00000-ddffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:e5:1d.0
><Sep/11 01:51 pm>  IO window: 8000-83ff
><Sep/11 01:51 pm>  MEM window: dcf00000-dcffffff
><Sep/11 01:51 pm>  PREFETCH window: dbe00000-dbffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:e5:1f.0
><Sep/11 01:51 pm>  IO window: 8400-87ff
><Sep/11 01:51 pm>  MEM window: dce00000-dcefffff
><Sep/11 01:51 pm>  PREFETCH window: dbc00000-dbdfffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:f2:1d.0
><Sep/11 01:51 pm>  IO window: 8800-8bff
><Sep/11 01:51 pm>  MEM window: daf00000-daffffff
><Sep/11 01:51 pm>  PREFETCH window: d9e00000-d9ffffff
><Sep/11 01:51 pm>PCI: Bridge: 0000:f2:1f.0
><Sep/11 01:51 pm>  IO window: 8c00-8fff
><Sep/11 01:51 pm>  MEM window: dae00000-daefffff
><Sep/11 01:51 pm>  PREFETCH window: d9c00000-d9dfffff
><Sep/11 01:51 pm>NET: Registered protocol family 2
><Sep/11 01:51 pm>IP route cache hash table entries: 524288 (order: 10, 4194304 bytes)
><Sep/11 01:51 pm>TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
><Sep/11 01:51 pm>TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
><Sep/11 01:51 pm>TCP: Hash tables configured (established 262144 bind 65536)
><Sep/11 01:51 pm>TCP reno registered
><Sep/11 01:51 pm>audit: initializing netlink socket (disabled)
><Sep/11 01:51 pm>audit(1189536719.293:1): initialized
><Sep/11 01:51 pm>Total HugeTLB memory allocated, 0
><Sep/11 01:51 pm>VFS: Disk quotas dquot_6.5.1
><Sep/11 01:51 pm>Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
><Sep/11 01:51 pm>Initializing Cryptographic API
><Sep/11 01:51 pm>ksign: Installing public key data
><Sep/11 01:51 pm>Loading keyring
><Sep/11 01:51 pm>- Added public key B46A116AA5438BDE
><Sep/11 01:51 pm>- User ID: Red Hat, Inc. (Kernel Module GPG key)
><Sep/11 01:51 pm>io scheduler noop registered
><Sep/11 01:51 pm>io scheduler anticipatory registered
><Sep/11 01:51 pm>io scheduler deadline registered
><Sep/11 01:51 pm>io scheduler cfq registered (default)
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x2020 to 0x2828 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x3030 to 0x3434 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x3030 to 0x3838 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x3030 to 0x3c3c for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x4040 to 0x4444 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x4040 to 0x4848 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x4040 to 0x4c4c for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x5050 to 0x5454 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x5050 to 0x5858 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x6060 to 0x6464 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x6060 to 0x6868 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x6060 to 0x6c6c for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x7070 to 0x7474 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x7070 to 0x7878 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x7070 to 0x7c7c for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x8080 to 0x8484 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x8080 to 0x8888 for 1 KB Granularity
><Sep/11 01:51 pm>PCI: Fixing P64H2 IOBL_ADR from 0x8080 to 0x8c8c for 1 KB Granularity
><Sep/11 01:51 pm>pci_hotplug: PCI Hot Plug PCI Core version: 0.5
><Sep/11 01:51 pm>Real Time Clock Driver v1.12ac
><Sep/11 01:51 pm>Non-volatile memory driver v1.2
><Sep/11 01:51 pm>Linux agpgart interface v0.101 (c) Dave Jones
><Sep/11 01:51 pm>Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
><Sep/11 01:51 pm>%GÃ¯Â¿Â½%@serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
><Sep/11 01:51 pm>00:06: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
><Sep/11 01:51 pm>RAMDISK driver initialized: 16 RAM disks of 16384K size 4096 blocksize
><Sep/11 01:51 pm>Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
><Sep/11 01:51 pm>ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
><Sep/11 01:51 pm>ICH4: IDE controller at PCI slot 0000:00:1f.1
><Sep/11 01:51 pm>GSI 16 sharing vector 0xA9 and IRQ 16
><Sep/11 01:51 pm>ACPI: PCI Interrupt 0000:00:1f.1[A] -> GSI 18 (level, low) -> IRQ 169
><Sep/11 01:51 pm>ICH4: chipset revision 2
><Sep/11 01:51 pm>ICH4: not 100% native mode: will probe irqs later
><Sep/11 01:51 pm>    ide0: BM-DMA at 0x0880-0x0887, BIOS settings: hda:DMA, hdb:pio
><Sep/11 01:51 pm>    ide1: BM-DMA at 0x0888-0x088f, BIOS settings: hdc:pio, hdd:pio
><Sep/11 01:51 pm>hda: _NEC DVD_RW ND-6750A, ATAPI CD/DVD-ROM drive
><Sep/11 01:51 pm>ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
><Sep/11 01:51 pm>ide-floppy driver 0.99.newide
><Sep/11 01:51 pm>usbcore: registered new driver hiddev
><Sep/11 01:51 pm>usbcore: registered new driver usbhid
><Sep/11 01:51 pm>drivers/usb/input/hid-core.c: v2.6:USB HID core driver
><Sep/11 01:51 pm>PNP: No PS/2 controller found. Probing ports directly.
><Sep/11 01:51 pm>serio: i8042 KBD port at 0x60,0x64 irq 1
><Sep/11 01:51 pm>serio: i8042 AUX port at 0x60,0x64 irq 12
><Sep/11 01:51 pm>mice: PS/2 mouse device common for all mice
><Sep/11 01:51 pm>md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
><Sep/11 01:51 pm>md: bitmap version 4.39
><Sep/11 01:51 pm>TCP bic registered
><Sep/11 01:51 pm>Initializing IPsec netlink socket
><Sep/11 01:51 pm>NET: Registered protocol family 1
><Sep/11 01:51 pm>NET: Registered protocol family 17
><Sep/11 01:51 pm>ACPI: (supports S0)
><Sep/11 01:51 pm>Freeing unused kernel memory: 192k freed
><Sep/11 01:51 pm>Write protecting the kernel read-only data: 469k
><Sep/11 01:51 pm>Red Hat nash version 5.1.19.6 starting
><Sep/11 01:51 pm>Mounting proc filesystem
><Sep/11 01:51 pm>Mounting sysfs filesystem
><Sep/11 01:51 pm>Creating /dev
><Sep/11 01:51 pm>Creating initial device nodes
><Sep/11 01:51 pm>Setting up hotplug.
><Sep/11 01:52 pm>Creating block device nodes.
><Sep/11 01:52 pm>Loading uhci-hcd.ko module
><Sep/11 01:52 pm>USB Universal Host Controller Interface driver v3.0
><Sep/11 01:52 pm>GSI 17 sharing vector 0xB1 and IRQ 17
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:00:1d.0[A] -> GSI 16 (level, low) -> IRQ 177
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.0: UHCI Host Controller
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 1
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.0: irq 177, io base 0x00000800
><Sep/11 01:52 pm>usb usb1: configuration #1 chosen from 1 choice
><Sep/11 01:52 pm>hub 1-0:1.0: USB hub found
><Sep/11 01:52 pm>hub 1-0:1.0: 2 ports detected
><Sep/11 01:52 pm>GSI 18 sharing vector 0xB9 and IRQ 18
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:00:1d.1[B] -> GSI 19 (level, low) -> IRQ 185
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.1: UHCI Host Controller
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 2
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.1: irq 185, io base 0x00000820
><Sep/11 01:52 pm>usb usb2: configuration #1 chosen from 1 choice
><Sep/11 01:52 pm>hub 2-0:1.0: USB hub found
><Sep/11 01:52 pm>hub 2-0:1.0: 2 ports detected
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:00:1d.2[C] -> GSI 18 (level, low) -> IRQ 169
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.2: UHCI Host Controller
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 3
><Sep/11 01:52 pm>uhci_hcd 0000:00:1d.2: irq 169, io base 0x00000840
><Sep/11 01:52 pm>usb usb3: configuration #1 chosen from 1 choice
><Sep/11 01:52 pm>hub 3-0:1.0: USB hub found
><Sep/11 01:52 pm>hub 3-0:1.0: 2 ports detected
><Sep/11 01:52 pm>Loading ohci-hcd.ko module
><Sep/11 01:52 pm>Loading ehci-hcd.ko module
><Sep/11 01:52 pm>GSI 19 sharing vector 0xC1 and IRQ 19
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:00:1d.7[D] -> GSI 23 (level, low) -> IRQ 193
><Sep/11 01:52 pm>ehci_hcd 0000:00:1d.7: EHCI Host Controller
><Sep/11 01:52 pm>ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 4
><Sep/11 01:52 pm>ehci_hcd 0000:00:1d.7: debug port 1
><Sep/11 01:52 pm>ehci_hcd 0000:00:1d.7: irq 193, io mem 0xf7fffc00
><Sep/11 01:52 pm>ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004
><Sep/11 01:52 pm>usb usb4: configuration #1 chosen from 1 choice
><Sep/11 01:52 pm>hub 4-0:1.0: USB hub found
><Sep/11 01:52 pm>hub 4-0:1.0: 6 ports detected
><Sep/11 01:52 pm>usb 2-1: new full speed USB device using uhci_hcd and address 2
><Sep/11 01:52 pm>Loading jbd.ko module
><Sep/11 01:52 pm>Loading ext3.ko module
><Sep/11 01:52 pm>Loading scsi_mod.ko module
><Sep/11 01:52 pm>SCSI subsystem initialized
><Sep/11 01:52 pm>Loading sd_mod.ko module
><Sep/11 01:52 pm>Loading scsi_transport_sas.ko module
><Sep/11 01:52 pm>Loading mptbase.ko module
><Sep/11 01:52 pm>Fusion MPT base driver 3.04.04
><Sep/11 01:52 pm>Copyright (c) 1999-2007 LSI Logic Corporation
><Sep/11 01:52 pm>Loading mptscsih.ko module
><Sep/11 01:52 pm>Loading mptsas.ko module
><Sep/11 01:52 pm>Fusion MPT SAS Host driver 3.04.04
><Sep/11 01:52 pm>PCI: Enabling device 0000:09:01.0 (0156 -> 0157)
><Sep/11 01:52 pm>GSI 20 sharing vector 0xC9 and IRQ 20
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:09:01.0[A] -> GSI 48 (level, low) -> IRQ 201
><Sep/11 01:52 pm>mptbase: Initiating ioc0 bringup
><Sep/11 01:52 pm>ioc0: SAS1068: Capabilities={Initiator}
><Sep/11 01:52 pm>usb 2-1: new full speed USB device using uhci_hcd and address 3
><Sep/11 01:52 pm>usb 2-1: no configuration chosen from 1 choice
><Sep/11 01:52 pm>usb 3-1: new low speed USB device using uhci_hcd and address 2
><Sep/11 01:52 pm>usb 3-1: configuration #1 chosen from 1 choice
><Sep/11 01:52 pm>input: Cherry GmbH Cherry TouchBoard as /class/input/input0
><Sep/11 01:52 pm>input: USB HID v1.11 Keyboard [Cherry GmbH Cherry TouchBoard] on usb-0000:00:1d.2-1
><Sep/11 01:52 pm>input: Cherry GmbH Cherry TouchBoard as /class/input/input1
><Sep/11 01:52 pm>input: USB HID v1.11 Mouse [Cherry GmbH Cherry TouchBoard] on usb-0000:00:1d.2-1
><Sep/11 01:52 pm>scsi0 : ioc0: LSISAS1068, FwRev=010a0000h, Ports=1, MaxQ=511, IRQ=201
><Sep/11 01:52 pm>  Vendor: FUJITSU   Model: MAV2073RC         Rev: 0109
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 03
><Sep/11 01:52 pm>  Vendor: FUJITSU   Model: MAV2073RC         Rev: 0109
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 03
><Sep/11 01:52 pm>  Vendor: LSILOGIC  Model: Logical Volume    Rev: 3000
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 02
><Sep/11 01:52 pm>SCSI device sda: 138670080 512-byte hdwr sectors (70999 MB)
><Sep/11 01:52 pm>sda: Write Protect is off
><Sep/11 01:52 pm>SCSI device sda: drive cache: write back
><Sep/11 01:52 pm>SCSI device sda: 138670080 512-byte hdwr sectors (70999 MB)
><Sep/11 01:52 pm>sda: Write Protect is off
><Sep/11 01:52 pm>SCSI device sda: drive cache: write back
><Sep/11 01:52 pm> sda: sda1 sda2
><Sep/11 01:52 pm>sd 0:1:0:0: Attached scsi disk sda
><Sep/11 01:52 pm>PCI: Enabling device 0000:a0:01.0 (0156 -> 0157)
><Sep/11 01:52 pm>GSI 21 sharing vector 0xD1 and IRQ 21
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:a0:01.0[A] -> GSI 624 (level, low) -> IRQ 209
><Sep/11 01:52 pm>mptbase: Initiating ioc1 bringup
><Sep/11 01:52 pm>ioc1: SAS1068: Capabilities={Initiator}
><Sep/11 01:52 pm>scsi1 : ioc1: LSISAS1068, FwRev=010a0000h, Ports=1, MaxQ=511, IRQ=209
><Sep/11 01:52 pm>  Vendor: FUJITSU   Model: MAV2073RC         Rev: 0109
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 03
><Sep/11 01:52 pm>  Vendor: FUJITSU   Model: MAV2073RC         Rev: 0109
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 03
><Sep/11 01:52 pm>  Vendor: LSILOGIC  Model: Logical Volume    Rev: 3000
><Sep/11 01:52 pm>  Type:   Direct-Access                      ANSI SCSI revision: 02
><Sep/11 01:52 pm>SCSI device sdb: 138670080 512-byte hdwr sectors (70999 MB)
><Sep/11 01:52 pm>sdb: Write Protect is off
><Sep/11 01:52 pm>SCSI device sdb: drive cache: write back
><Sep/11 01:52 pm>SCSI device sdb: 138670080 512-byte hdwr sectors (70999 MB)
><Sep/11 01:52 pm>sdb: Write Protect is off
><Sep/11 01:52 pm>SCSI device sdb: drive cache: write back
><Sep/11 01:52 pm> sdb: sdb1
><Sep/11 01:52 pm>sd 1:1:0:0: Attached scsi disk sdb
><Sep/11 01:52 pm>Loading megaraid_mm.ko module
><Sep/11 01:52 pm>megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
><Sep/11 01:52 pm>Loading megaraid_mbox.ko module
><Sep/11 01:52 pm>megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
><Sep/11 01:52 pm>megaraid: probe new device 0x1000:0x0407:0x1000:0x0532: bus 23:slot 0:func 0
><Sep/11 01:52 pm>GSI 22 sharing vector 0xD9 and IRQ 22
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:17:00.0[A] -> GSI 96 (level, low) -> IRQ 217
><Sep/11 01:52 pm>megaraid: fw version:[413Z] bios version:[H424]
><Sep/11 01:52 pm>scsi2 : LSI Logic MegaRAID driver
><Sep/11 01:52 pm>scsi[2]: scanning scsi channel 0 [Phy 0] for non-raid devices
><Sep/11 01:52 pm>scsi[2]: scanning scsi channel 1 [Phy 1] for non-raid devices
><Sep/11 01:52 pm>scsi[2]: scanning scsi channel 2 [virtual] for logical drives
><Sep/11 01:52 pm>Loading scsi_transport_spi.ko module
><Sep/11 01:52 pm>Loading mptspi.ko module
><Sep/11 01:52 pm>Fusion MPT SPI Host driver 3.04.04
><Sep/11 01:52 pm>GSI 23 sharing vector 0xE1 and IRQ 23
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:23:01.0[A] -> GSI 144 (level, low) -> IRQ 225
><Sep/11 01:52 pm>mptbase: Initiating ioc2 bringup
><Sep/11 01:52 pm>ioc2: 53C1030: Capabilities={Initiator,Target}
><Sep/11 01:52 pm>scsi3 : ioc2: LSI53C1030, FwRev=01032700h, Ports=1, MaxQ=255, IRQ=225
><Sep/11 01:52 pm>GSI 24 sharing vector 0xE9 and IRQ 24
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:23:01.1[B] -> GSI 145 (level, low) -> IRQ 233
><Sep/11 01:52 pm>mptbase: Initiating ioc3 bringup
><Sep/11 01:52 pm>ioc3: 53C1030: Capabilities={Initiator,Target}
><Sep/11 01:52 pm>scsi4 : ioc3: LSI53C1030, FwRev=01032700h, Ports=1, MaxQ=255, IRQ=233
><Sep/11 01:52 pm>Loading libata.ko module
><Sep/11 01:52 pm>Loading ata_piix.ko module
><Sep/11 01:52 pm>Loading scsi_transport_fc.ko module
><Sep/11 01:52 pm>Loading lpfc.ko module
><Sep/11 01:52 pm>Emulex LightPulse Fibre Channel SCSI driver 8.1.10.9
><Sep/11 01:52 pm>Copyright(c) 2004-2007 Emulex.  All rights reserved.
><Sep/11 01:52 pm>GSI 25 sharing vector 0x32 and IRQ 25
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:2f:01.0[A] -> GSI 192 (level, low) -> IRQ 50
><Sep/11 01:52 pm>scsi5 :  on PCI bus 2f device 08 irq 50
><Sep/11 01:52 pm>GSI 26 sharing vector 0x3A and IRQ 26
><Sep/11 01:52 pm>ACPI: PCI Interrupt 0000:2f:01.1[B] -> GSI 193 (level, low) -> IRQ 58
><Sep/11 01:52 pm>scsi6 :  on PCI bus 2f device 09 irq 58
><Sep/11 01:53 pm>GSI 27 sharing vector 0x42 and IRQ 27
><Sep/11 01:53 pm>ACPI: PCI Interrupt 0000:7b:01.0[A] -> GSI 480 (level, low) -> IRQ 66
><Sep/11 01:53 pm>scsi7 :  on PCI bus 7b device 08 irq 66
><Sep/11 01:53 pm>GSI 28 sharing vector 0x4A and IRQ 28
><Sep/11 01:53 pm>ACPI: PCI Interrupt 0000:7b:01.1[B] -> GSI 481 (level, low) -> IRQ 74
><Sep/11 01:53 pm>scsi8 :  on PCI bus 7b device 09 irq 74
><Sep/11 01:53 pm>GSI 29 sharing vector 0x52 and IRQ 29
><Sep/11 01:53 pm>ACPI: PCI Interrupt 0000:93:01.0[A] -> GSI 576 (level, low) -> IRQ 82
><Sep/11 01:53 pm>scsi9 :  on PCI bus 93 device 08 irq 82
><Sep/11 01:54 pm>Loading dm-mod.ko module
><Sep/11 01:54 pm>device-mapper: ioctl: 4.11.0-ioctl (2006-09-14) initialised: dm-devel@redhat.com
><Sep/11 01:54 pm>Loading dm-mirror.ko module
><Sep/11 01:54 pm>Loading dm-zero.ko module
><Sep/11 01:54 pm>Loading dm-snapshot.ko module
><Sep/11 01:54 pm>Waiting for driver initialization.
><Sep/11 01:54 pm>Scanning and configuring dmraid supported devices
><Sep/11 01:54 pm>Scanning logical volumes
><Sep/11 01:54 pm>  Reading all physical volumes.  This may take a while...
><Sep/11 01:54 pm>  Found volume group "VolGroup00" using metadata type lvm2
><Sep/11 01:54 pm>Activating logical volumes
><Sep/11 01:54 pm>  2 logical volume(s) in volume group "VolGroup00" now active
><Sep/11 01:54 pm>Trying to resume from /dev/VolGroup00/LogVol01
><Sep/11 01:54 pm>No suspend signature on swap, not resuming.
><Sep/11 01:54 pm>Creating root device.
><Sep/11 01:54 pm>Mounting root filesystem.
><Sep/11 01:54 pm>EXT3-fs: INFO: recovery required on readonly filesystem.
><Sep/11 01:54 pm>EXT3-fs: write access will be enabled during recovery.
><Sep/11 01:54 pm>kjournald starting.  Commit interval 5 seconds
><Sep/11 01:54 pm>Setting up otherEXT3-fs: recovery complete.
><Sep/11 01:54 pm> filesystems.
><Sep/11 01:54 pm>EXT3-fs: mounted filesystem with ordered data mode.
><Sep/11 01:54 pm>Setting up new root fs
><Sep/11 01:54 pm>no fstab.sys, mounting internal defaults
><Sep/11 01:54 pm>Switching to new root and running init.
><Sep/11 01:54 pm>unmounting old /dev
><Sep/11 01:54 pm>unmounting old /proc
><Sep/11 01:54 pm>unmounting old /sys
><Sep/11 01:54 pm>audit(1189536861.793:2): enforcing=1 old_enforcing=0 auid=4294967295
><Sep/11 01:54 pm>audit(1189536862.104:3): policy loaded auid=4294967295
><Sep/11 01:54 pm>INIT: version 2.86 booting
><Sep/11 01:54 pm>               Welcome to Red Hat Enterprise Linux Server
><Sep/11 01:54 pm>               Press 'I' to enter interactive startup.
><Sep/11 01:54 pm>Setting clock  (utc): Tue Sep 11 14:54:22 EDT 2007 [  OK  ]
><Sep/11 01:54 pm>Starting udev: [  OK  ]
><Sep/11 01:54 pm>Loading default keymap (us): [  OK  ]
><Sep/11 01:54 pm>Setting hostname es7000-01.lab.boston.redhat.com:  [  OK  ]
><Sep/11 01:54 pm>Setting up Logical Volume Management:   2 logical volume(s) in volume group "VolGroup00" now active
><Sep/11 01:54 pm>[  OK  ]
><Sep/11 01:54 pm>Checking filesystems
><Sep/11 01:54 pm>Checking all file systems.
><Sep/11 01:54 pm>[/sbin/fsck.ext3 (1) -- /] fsck.ext3 -a /dev/VolGroup00/LogVol00 
><Sep/11 01:54 pm>/dev/VolGroup00/LogVol00: clean, 70539/34144256 files, 1577904/34119680 blocks
><Sep/11 01:54 pm>[/sbin/fsck.ext3 (1) -- /boot] fsck.ext3 -a /dev/sda1 
><Sep/11 01:54 pm>/boot: recovering journal
><Sep/11 01:54 pm>/boot: clean, 39/26104 files, 21939/104388 blocks
><Sep/11 01:54 pm>[  OK  ]
><Sep/11 01:54 pm>Remounting root filesystem in read-write mode:  [  OK  ]
><Sep/11 01:54 pm>Mounting local filesystems:  [  OK  ]
><Sep/11 01:54 pm>Enabling local filesystem quotas:  [  OK  ]
><Sep/11 01:54 pm>Enabling /etc/fstab swaps:  [  OK  ]
><Sep/11 01:54 pm>INIT: Entering runlevel: 3
><Sep/11 01:54 pm>Entering non-interactive startup
><Sep/11 01:54 pm>Applying Intel CPU microcode update: [  OK  ]
><Sep/11 01:54 pm>Starting monitoring for VG VolGroup00:   2 logical volume(s) in volume group "VolGroup00" monitored
><Sep/11 01:54 pm>[  OK  ]
><Sep/11 01:54 pm>Starting background readahead: [  OK  ]
><Sep/11 01:54 pm>Checking for hardware changes [  OK  ]
><Sep/11 01:54 pm>Bringing up loopback interface:  [  OK  ]
><Sep/11 01:54 pm>Bringing up interface eth0:  
><Sep/11 01:54 pm>Determining IP information for eth0... done.
><Sep/11 01:54 pm>[  OK  ]
><Sep/11 01:54 pm>Bringing up interface eth1:  
><Sep/11 01:54 pm>Determining IP information for eth1... failed; no link present.  Check cable?
><Sep/11 01:54 pm>[FAILED]
><Sep/11 01:54 pm>Bringing up interface eth2:  
><Sep/11 01:54 pm>Determining IP information for eth2... failed; no link present.  Check cable?
><Sep/11 01:54 pm>[FAILED]
><Sep/11 01:54 pm>Bringing up interface eth3:  
><Sep/11 01:54 pm>Determining IP information for eth3... failed; no link present.  Check cable?
><Sep/11 01:54 pm>[FAILED]
><Sep/11 01:54 pm>Bringing up interface eth4:  
><Sep/11 01:54 pm>Determining IP information for eth4... failed; no link present.  Check cable?
><Sep/11 01:54 pm>[FAILED]
><Sep/11 01:54 pm>Bringing up interface eth5:  
><Sep/11 01:55 pm>Determining IP information for eth5... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Bringing up interface eth6:  
><Sep/11 01:55 pm>Determining IP information for eth6... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Bringing up interface eth7:  
><Sep/11 01:55 pm>Determining IP information for eth7... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Bringing up interface eth8:  
><Sep/11 01:55 pm>Determining IP information for eth8... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Bringing up interface eth9:  
><Sep/11 01:55 pm>Determining IP information for eth9... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Bringing up interface eth10:  
><Sep/11 01:55 pm>Determining IP information for eth10... failed; no link present.  Check cable?
><Sep/11 01:55 pm>[FAILED]
><Sep/11 01:55 pm>Starting auditd: [  OK  ]
><Sep/11 01:55 pm>Starting restorecond: [  OK  ]
><Sep/11 01:55 pm>Starting system logger: [  OK  ]
><Sep/11 01:55 pm>Starting kernel logger: [  OK  ]
><Sep/11 01:55 pm>Starting irqbalance: [  OK  ]
><Sep/11 01:55 pm>Starting mcstransd: [  OK  ]
><Sep/11 01:55 pm>Starting portmap: [  OK  ]
><Sep/11 01:55 pm>Starting NFS statd: [  OK  ]
><Sep/11 01:55 pm>Starting RPC idmapd: [  OK  ]
><Sep/11 01:55 pm>Starting system message bus: [  OK  ]
><Sep/11 01:55 pm>[  OK  ] Bluetooth services:[  OK  ]
><Sep/11 01:55 pm>Mounting other filesystems:  [  OK  ]
><Sep/11 01:55 pm>Starting PC/SC smart card daemon (pcscd): [  OK  ]
><Sep/11 01:55 pm>Starting hidd: [  OK  ]
><Sep/11 01:55 pm>Starting autofs:  Loading autofs4: [  OK  ]
><Sep/11 01:55 pm>Starting automount: [  OK  ]
><Sep/11 01:55 pm>[  OK  ]
><Sep/11 01:55 pm>Starting acpi daemon: [  OK  ]
><Sep/11 01:55 pm>Starting sshd: [  OK  ]
><Sep/11 01:55 pm>Starting cups: [  OK  ]
><Sep/11 01:55 pm>Starting ntpd: [  OK  ]
><Sep/11 01:55 pm>Starting sendmail: [  OK  ]
><Sep/11 01:55 pm>Starting sm-client: [  OK  ]
><Sep/11 01:55 pm>Starting console mouse services: [  OK  ]
><Sep/11 01:55 pm>Starting crond: [  OK  ]
><Sep/11 01:55 pm>Starting xfs: [  OK  ]
><Sep/11 01:55 pm>Starting anacron: [  OK  ]
><Sep/11 01:55 pm>Starting atd: [  OK  ]
><Sep/11 01:55 pm>Starting yum-updatesd: [  OK  ]
><Sep/11 01:55 pm>Starting Avahi daemon... [  OK  ]
><Sep/11 01:55 pm>Starting HAL daemon: [  OK  ]
><Sep/11 01:55 pm>09/11/07 14:55:48  recipeID:21036 start:
><Sep/11 01:55 pm>Collecting all rpm packages...
><Sep/11 01:55 pm>Sending rpm info to http://rhts.lab.boston.redhat.com/cgi-bin/rhts/scheduler_xmlrpc.cgi
><Sep/11 01:55 pm>resp = client.results.allRpms(recipeid, pkg_list)
><Sep/11 01:55 pm>160862:/distribution/install has already run..
><Sep/11 01:55 pm>160863:/distribution/reservesys has already run..
><Sep/11 01:55 pm>09/11/07 14:55:55  recipeID:21036 finish:
><Sep/11 01:55 pm>Starting smartd: [  OK  ]
><Sep/11 01:55 pm>
><Sep/11 01:55 pm>Red Hat Enterprise Linux Server release 5.1 Beta (Tikanga)
><Sep/11 01:55 pm>Kernel 2.6.18-45.el5.bz224373.2 on an x86_64

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Attachments on bug 224373: 146542 | 190441 | 191881 | 192911