Attachment 1979895 Details for Bug 2226521 – build.log

build.log

build.log (text/plain), 32.00 KB, created by Fedora Release Engineering on 2023-07-25 20:29:32 UTC

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Creator: Fedora Release Engineering

Created: 2023-07-25 20:29:32 UTC

Size: 32.00 KB

patch

obsolete

>0 -> ok
>Test: t_wide_write_a7r4w0b0 -> ok
>Test: t_wide_read_a7r5w0b0 -> ok
>Test: t_wide_write_a7r5w0b0 -> ok
>Test: t_wide_read_a7r0w1b0 -> ok
>Test: t_wide_write_a7r0w1b0 -> ok
>Test: t_wide_read_a7r0w1b1 -> ok
>Test: t_wide_write_a7r0w1b1 -> ok
>Test: t_wide_read_a7r0w2b0 -> ok
>Test: t_wide_write_a7r0w2b0 -> ok
>Test: t_wide_read_a7r0w2b2 -> ok
>Test: t_wide_write_a7r0w2b2 -> ok
>Test: t_wide_read_a7r0w3b2 -> ok
>Test: t_wide_write_a7r0w3b2 -> ok
>Test: t_wide_read_a7r0w4b2 -> ok
>Test: t_wide_write_a7r0w4b2 -> ok
>Test: t_wide_read_a7r0w5b2 -> ok
>Test: t_wide_write_a7r0w5b2 -> ok
>Test: t_quad_port_a2d2 -> ok
>Test: t_quad_port_a4d2 -> ok
>Test: t_quad_port_a5d2 -> ok
>Test: t_quad_port_a4d4 -> ok
>Test: t_quad_port_a6d2 -> ok
>Test: t_quad_port_a4d8 -> ok
>Test: t_wide_quad_a4w2r1 -> ok
>Test: t_wide_oct_a4w2r1 -> ok
>Test: t_wide_quad_a4w2r2 -> ok
>Test: t_wide_oct_a4w2r2 -> ok
>Test: t_wide_quad_a4w2r3 -> ok
>Test: t_wide_oct_a4w2r3 -> ok
>Test: t_wide_quad_a4w2r4 -> ok
>Test: t_wide_oct_a4w2r4 -> ok
>Test: t_wide_quad_a4w2r5 -> ok
>Test: t_wide_oct_a4w2r5 -> ok
>Test: t_wide_quad_a4w2r6 -> ok
>Test: t_wide_oct_a4w2r6 -> ok
>Test: t_wide_quad_a4w2r7 -> ok
>Test: t_wide_oct_a4w2r7 -> ok
>Test: t_wide_quad_a4w2r8 -> ok
>Test: t_wide_oct_a4w2r8 -> ok
>Test: t_wide_quad_a4w2r9 -> ok
>Test: t_wide_oct_a4w2r9 -> ok
>Test: t_wide_quad_a4w4r1 -> ok
>Test: t_wide_oct_a4w4r1 -> ok
>Test: t_wide_quad_a4w4r4 -> ok
>Test: t_wide_oct_a4w4r4 -> ok
>Test: t_wide_quad_a4w4r6 -> ok
>Test: t_wide_oct_a4w4r6 -> ok
>Test: t_wide_quad_a4w4r9 -> ok
>Test: t_wide_oct_a4w4r9 -> ok
>Test: t_wide_quad_a5w2r1 -> ok
>Test: t_wide_oct_a5w2r1 -> ok
>Test: t_wide_quad_a5w2r4 -> ok
>Test: t_wide_oct_a5w2r4 -> ok
>Test: t_wide_quad_a5w2r9 -> ok
>Test: t_wide_oct_a5w2r9 -> ok
>Test: t_no_reset -> ok
>Test: t_gclken -> ok
>Test: t_ungated -> ok
>Test: t_gclken_ce -> ok
>Test: t_grden -> ok
>Test: t_grden_ce -> ok
>Test: t_exclwr -> ok
>Test: t_excl_rst -> ok
>Test: t_transwr -> ok
>Test: t_trans_rst -> ok
>Test: t_wr_byte -> ok
>Test: t_trans_byte -> ok
>Test: t_wr_rst_byte -> ok
>Test: t_rst_wr_byte -> ok
>Test: t_rdenrst_wr_byte -> ok
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/memlib'
>cd tests/bram && bash run-test.sh "-S 314159265359"
>generating tests..
>PRNG seed: 314159265359
>running tests..
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/bram'
>Passed memory_bram test 00_01.
>Passed memory_bram test 00_02.
>Passed memory_bram test 00_03.
>Passed memory_bram test 00_04.
>Passed memory_bram test 01_00.
>Passed memory_bram test 01_02.
>Passed memory_bram test 01_03.
>Passed memory_bram test 01_04.
>Passed memory_bram test 02_00.
>Passed memory_bram test 02_01.
>Passed memory_bram test 02_03.
>Passed memory_bram test 02_04.
>Passed memory_bram test 03_00.
>Passed memory_bram test 03_01.
>Passed memory_bram test 03_02.
>Passed memory_bram test 03_04.
>Passed memory_bram test 04_00.
>Passed memory_bram test 04_01.
>Passed memory_bram test 04_02.
>Passed memory_bram test 04_03.
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/bram'
>cd tests/various && bash run-test.sh
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/various'
>Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
>Passed abc9.ys
>Passed aiger_dff.ys
>Passed attrib05_port_conn.ys
>Passed attrib07_func_call.ys
>Passed autoname.ys
>Passed blackbox_wb.ys
>Passed bug1496.ys
>Passed bug1531.ys
>Passed bug1614.ys
>Passed bug1710.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
><<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
>Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
>Passed bug1745.ys
>Passed bug1781.ys
>Passed bug1876.ys
>Passed bug2014.ys
>Passed bug3462.ys
>Passed cellarray_array_connections.ys
>Passed chformal_coverenable.ys
>Passed const_arg_loop.ys
>Passed const_func.ys
>Passed const_func_block_var.ys
><<EOT:2: ERROR: syntax error, unexpected TOK_BASE
>Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
>Passed constcomment.ys
>Passed constmsk_test.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
>Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
>Passed countbits.ys
>Passed deminout_unused.ys
>Passed design.ys
>ERROR: No saved design 'foo' found!
>Expected error pattern 'No saved design 'foo' found!' found !!!
>Passed design1.ys
>ERROR: No saved design 'foo' found!
>Expected error pattern 'No saved design 'foo' found!' found !!!
>Passed design2.ys
>Passed dynamic_part_select.ys
>elab_sys_tasks.sv:8: Warning: X is 1.
>elab_sys_tasks.sv:22: Warning: 
>Passed elab_sys_tasks.ys
>Passed equiv_make_make_assert.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/simcells.v:456)
>Passed equiv_opt_multiclock.ys
>Passed equiv_opt_undef.ys
>ERROR: Command stdout did have a line matching given regex "giraffe".
>Expected error pattern 'stdout did have a line' found !!!
>Passed exec.ys
>Passed fib.ys
>Passed fib_tern.ys
>Passed func_port_implied_dir.ys
>Passed gen_if_null.ys
>Passed global_scope.ys
>Passed gzip_verilog.ys
>Passed help.ys
>Passed hierarchy_defer.ys
>Passed hierarchy_param.ys
>Passed ice40_mince_abc9.ys
><<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
>Expected error pattern 'syntax error, unexpected' found !!!
>Passed integer_range_bad_syntax.ys
><<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
>Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
>Passed integer_real_bad_syntax.ys
>attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
>Passed json_escape_chars.ys
>ERROR: Identifier `\b' is implicitly declared.
>Expected error pattern 'is implicitly declared.' found !!!
>Passed logger_error.ys
>Passed logger_nowarning.ys
>Warning: Found log message matching -W regex:
>Added regex 'Successfully finished Verilog frontend.' for warnings to expected warning list.
><<EOF:2: Warning: Identifier `\b' is implicitly declared.
><<EOF:2: Warning: Identifier `\w' is implicitly declared.
>Warning: Found log message matching -W regex:
>Successfully finished Verilog frontend.
>Passed logger_warn.ys
><<EOF:2: Warning: Identifier `\b' is implicitly declared.
><<EOF:2: Warning: Identifier `\w' is implicitly declared.
>Passed logger_warning.ys
>Passed logic_param_simple.ys
>Passed mem2reg.ys
>Passed memory_word_as_index.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/simcells.v:456)
>Passed muxcover.ys
>Passed muxpack.ys
>Passed param_struct.ys
>Passed peepopt.ys
>Passed pmgen_reduce.ys
>Passed pmux2shiftx.ys
>Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
>Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
>Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
>Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
>Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
>Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
>Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
>Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
>Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
>Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
>Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
>Passed port_sign_extend.ys
>Passed primitives.ys
>Passed printattr.ys
>Passed rand_const.ys
>Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
>Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
>Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
>Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
>Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
>Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
>Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
>Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
>Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
>Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
>Passed reg_wire_error.ys
>Passed rename_scramble_name.ys
>Passed rtlil_z_bits.ys
>Passed scratchpad.ys
>Passed script.ys
>Passed sformatf.ys
>Passed shregmap.ys
><<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
>Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
>Passed signed.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
>Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
>Passed signext.ys
>Passed sim_const.ys
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
>specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
>specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
>Warning: No SAT model available for cell B_0 ($specrule).
>Warning: No SAT model available for cell C_0 ($specrule).
>Warning: No SAT model available for cell A_0 ($specify3).
>Warning: No SAT model available for cell A_0 ($specify2).
>Warning: No SAT model available for cell B_0 ($specify2).
>Passed specify.ys
>Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
>Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
>Passed src.ys
>Warning: Critical-path does not terminate in a recognised endpoint.
>Warning: Cell type 'const0' not recognised! Ignoring.
>Passed sta.ys
>Passed struct_access.ys
>Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
>Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
>Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.
>Passed submod.ys
>Passed submod_extract.ys
>Passed sv_defines.ys
>ERROR: Duplicate macro arguments with name `x'.
>Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
>Passed sv_defines_dup.ys
>ERROR: Mismatched brackets in macro argument: [ and }.
>Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
>Passed sv_defines_mismatch.ys
>ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
>Expected error pattern 'Cannot expand macro `foo by giving only 1 argument $argument 2 has no default$.' found !!!
>Passed sv_defines_too_few.ys
>Passed wreduce.ys
>Passed write_gzip.ys
>Passed xaiger.ys
>Passed async.sh
>Passed chparam.sh
>Passed hierarchy.sh
>Passed logger_fail.sh
>Passed plugin.sh
>Passed smtlib2_module.sh
>Passed sv_implicit_ports.sh
>Passed svalways.sh
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/various'
>cd tests/select && bash run-test.sh
>Running blackboxes.ys..
>Running no_warn_assert.ys..
>Running no_warn_prefixed_arg_memb.ys..
>Running no_warn_prefixed_empty_select_arg.ys..
>Running unset.ys..
>ERROR: Selection '\foo' does not exist!
>Expected error pattern 'Selection '\\foo' does not exist!' found !!!
>Running unset2.ys..
>ERROR: Selection @foo is not defined!
>Expected error pattern 'Selection @foo is not defined!' found !!!
>Running warn_empty_select_arg.ys..
>Warning: Selection "foo" did not match any module.
>Warning: Selection "bar" did not match any object.
>cd tests/sat && bash run-test.sh
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/sat'
>Passed asserts.ys
>Passed asserts_seq.ys
>Passed bug2595.ys
>Warning: Complex async reset for dff `\q [12]'.
>Warning: Complex async reset for dff `\q [8]'.
>Passed clk2fflogic.ys
>Passed counters-repeat.ys
>Passed counters.ys
>Passed dff.ys
>Passed expose_dff.ys
>Passed grom.ys
>Passed initval.ys
>Passed share.ys
>Warning: Wire top.\cnt [7] is used but has no driver.
>Warning: Wire top.\cnt [6] is used but has no driver.
>Warning: Wire top.\cnt [5] is used but has no driver.
>Warning: Wire top.\cnt [4] is used but has no driver.
>Warning: Wire top.\cnt [3] is used but has no driver.
>Warning: Wire top.\cnt [2] is used but has no driver.
>Warning: Wire top.\cnt [1] is used but has no driver.
>Warning: Wire top.\cnt [0] is used but has no driver.
>Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000'
>ERROR: Signal difference
>Expected error pattern 'Signal difference' found !!!
>Passed sim_counter.ys
>Passed sizebits.ys
>Passed splice.ys
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/sat'
>cd tests/sim && bash run-test.sh
>Generate FST for sim models
>Test tb_adff
>FST info: dumpfile tb_adff.fst opened for output.
>tb/tb_adff.v:38: $finish called at 110 (1ns)
>Test tb_adffe
>FST info: dumpfile tb_adffe.fst opened for output.
>tb/tb_adffe.v:56: $finish called at 190 (1ns)
>Test tb_adlatch
>FST info: dumpfile tb_adlatch.fst opened for output.
>tb/tb_adlatch.v:68: $finish called at 250 (1ns)
>Test tb_aldff
>FST info: dumpfile tb_aldff.fst opened for output.
>tb/tb_aldff.v:71: $finish called at 270 (1ns)
>Test tb_aldffe
>FST info: dumpfile tb_aldffe.fst opened for output.
>tb/tb_aldffe.v:73: $finish called at 270 (1ns)
>Test tb_dff
>FST info: dumpfile tb_dff.fst opened for output.
>tb/tb_dff.v:45: $finish called at 150 (1ns)
>Test tb_dffe
>FST info: dumpfile tb_dffe.fst opened for output.
>tb/tb_dffe.v:40: $finish called at 120 (1ns)
>Test tb_dffsr
>FST info: dumpfile tb_dffsr.fst opened for output.
>tb/tb_dffsr.v:67: $finish called at 250 (1ns)
>Test tb_dlatch
>FST info: dumpfile tb_dlatch.fst opened for output.
>tb/tb_dlatch.v:48: $finish called at 160 (1ns)
>Test tb_dlatchsr
>FST info: dumpfile tb_dlatchsr.fst opened for output.
>tb/tb_dlatchsr.v:63: $finish called at 250 (1ns)
>Test tb_sdff
>FST info: dumpfile tb_sdff.fst opened for output.
>tb/tb_sdff.v:46: $finish called at 150 (1ns)
>Test tb_sdffce
>FST info: dumpfile tb_sdffce.fst opened for output.
>tb/tb_sdffce.v:77: $finish called at 300 (1ns)
>Test tb_sdffe
>FST info: dumpfile tb_sdffe.fst opened for output.
>tb/tb_sdffe.v:68: $finish called at 250 (1ns)
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/sim'
>Passed sim_adff.ys
>Passed sim_adffe.ys
>Passed sim_adlatch.ys
>Warning: Async reset value `\ad' is not constant!
>Passed sim_aldff.ys
>Warning: Async reset value `\ad' is not constant!
>Passed sim_aldffe.ys
>Passed sim_dff.ys
>Passed sim_dffe.ys
>Warning: Complex async reset for dff `\q'.
>Passed sim_dffsr.ys
>Passed sim_dlatch.ys
>Passed sim_dlatchsr.ys
>Passed sim_sdff.ys
>Passed sim_sdffce.ys
>Passed sim_sdffe.ys
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/sim'
>cd tests/svinterfaces && bash run-test.sh "-S 314159265359"
>Test: svinterface1 -> svinterface1_tb.v:50: $finish called at 420000 (10ps)
>svinterface1_tb.v:50: $finish called at 420000 (10ps)
>ok
>Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps)
>svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps)
>ERROR!
>Test: load_and_derive ->ok
>Test: resolve_types ->ok
>cd tests/svtypes && bash run-test.sh "-S 314159265359"
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/svtypes'
>Passed enum_simple.ys
>Passed logic_rom.ys
><<EOT:7: ERROR: Insufficient number of array indices for a.
>Expected error pattern 'Insufficient number of array indices for a.' found !!!
>Passed multirange_subarray_access.ys
><<EOT:1: ERROR: Static cast with zero or negative size!
>Expected error pattern 'Static cast with zero or negative size' found !!!
>Passed static_cast_negative.ys
><<EOT:1: ERROR: Static cast with non constant expression!
>Expected error pattern 'Static cast with non constant expression' found !!!
>Passed static_cast_nonconst.ys
><<EOT:1: ERROR: Static cast is only supported in SystemVerilog mode.
>Expected error pattern 'Static cast is only supported in SystemVerilog mode' found !!!
>Passed static_cast_verilog.ys
><<EOT:1: ERROR: Static cast with zero or negative size!
>Expected error pattern 'Static cast with zero or negative size' found !!!
>Passed static_cast_zero.ys
>Passed struct_dynamic_range.ys
>Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19.
>Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19.
>Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19.
>Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19.
>Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19.
>Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19.
>Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19.
>Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19.
>Passed typedef_initial_and_assign.ys
>Passed typedef_memory.ys
>Passed typedef_memory_2.ys
>Passed typedef_struct_port.ys
>Passed multirange_array.sv
>Passed static_cast_simple.sv
>struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef.
>struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef.
>struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef.
>struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef.
>Passed struct_array.sv
>Passed struct_simple.sv
>Passed struct_sizebits.sv
>Passed typedef_package.sv
>Passed typedef_param.sv
>Passed typedef_scopes.sv
>Passed typedef_simple.sv
>Passed typedef_struct.sv
>Passed union_simple.sv
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/svtypes'
>cd tests/proc && bash run-test.sh
>Running bug2619.ys..
>Running bug2656.ys..
>Warning: wire '\q1' is assigned in a block at <<EOT:8.3-8.11.
>Warning: wire '\q2' is assigned in a block at <<EOT:12.3-12.10.
>Warning: wire '\q2' is assigned in a block at <<EOT:14.3-14.11.
>Running bug2962.ys..
>Running bug_1268.ys..
>Running proc_rom.ys..
>Warning: wire '\d' is assigned in a block at <<EOT:7.10-7.20.
>Warning: wire '\d' is assigned in a block at <<EOT:8.10-8.20.
>Warning: wire '\d' is assigned in a block at <<EOT:9.10-9.20.
>Warning: wire '\d' is assigned in a block at <<EOT:10.10-10.20.
>Warning: wire '\d' is assigned in a block at <<EOT:11.10-11.20.
>Warning: wire '\d' is assigned in a block at <<EOT:12.10-12.20.
>Warning: wire '\d' is assigned in a block at <<EOT:13.10-13.20.
>Warning: wire '\d' is assigned in a block at <<EOT:14.10-14.20.
>Warning: wire '\d' is assigned in a block at <<EOT:15.10-15.20.
>Warning: wire '\d' is assigned in a block at <<EOT:16.10-16.20.
>Warning: wire '\d' is assigned in a block at <<EOT:17.10-17.20.
>Warning: wire '\d' is assigned in a block at <<EOT:18.10-18.20.
>Warning: wire '\d' is assigned in a block at <<EOT:19.10-19.20.
>Warning: wire '\d' is assigned in a block at <<EOT:20.10-20.20.
>Warning: wire '\d' is assigned in a block at <<EOT:21.10-21.20.
>Warning: wire '\d' is assigned in a block at <<EOT:22.10-22.20.
>Warning: wire '\d' is assigned in a block at <<EOT:25.3-25.9.
>Warning: wire '\d' is assigned in a block at <<EOT:20.13-20.23.
>Warning: wire '\d' is assigned in a block at <<EOT:23.3-23.9.
>Warning: wire '\d' is assigned in a block at <<EOT:7.7-7.17.
>Warning: wire '\d' is assigned in a block at <<EOT:8.7-8.17.
>Warning: wire '\d' is assigned in a block at <<EOT:9.7-9.17.
>Warning: wire '\d' is assigned in a block at <<EOT:10.7-10.17.
>Warning: wire '\d' is assigned in a block at <<EOT:11.7-11.17.
>Warning: wire '\d' is assigned in a block at <<EOT:12.7-12.17.
>Warning: wire '\d' is assigned in a block at <<EOT:13.7-13.17.
>Warning: wire '\d' is assigned in a block at <<EOT:14.7-14.17.
>Warning: wire '\d' is assigned in a block at <<EOT:15.7-15.17.
>Warning: wire '\d' is assigned in a block at <<EOT:16.7-16.17.
>Warning: wire '\d' is assigned in a block at <<EOT:17.8-17.18.
>Warning: wire '\d' is assigned in a block at <<EOT:18.8-18.18.
>Warning: wire '\d' is assigned in a block at <<EOT:19.8-19.18.
>Warning: wire '\d' is assigned in a block at <<EOT:7.9-7.19.
>Warning: wire '\d' is assigned in a block at <<EOT:8.9-8.19.
>Warning: wire '\d' is assigned in a block at <<EOT:9.9-9.19.
>Warning: wire '\d' is assigned in a block at <<EOT:10.9-10.19.
>Warning: wire '\d' is assigned in a block at <<EOT:11.9-11.19.
>Warning: wire '\d' is assigned in a block at <<EOT:12.9-12.19.
>Warning: wire '\d' is assigned in a block at <<EOT:13.9-13.19.
>Warning: wire '\d' is assigned in a block at <<EOT:14.9-14.19.
>Warning: wire '\d' is assigned in a block at <<EOT:15.9-15.19.
>Warning: wire '\d' is assigned in a block at <<EOT:16.9-16.19.
>Warning: wire '\d' is assigned in a block at <<EOT:17.9-17.19.
>Warning: wire '\d' is assigned in a block at <<EOT:18.9-18.19.
>Warning: wire '\d' is assigned in a block at <<EOT:19.9-19.19.
>Warning: wire '\d' is assigned in a block at <<EOT:20.9-20.19.
>Warning: wire '\d' is assigned in a block at <<EOT:21.9-21.19.
>Warning: wire '\d' is assigned in a block at <<EOT:22.9-22.19.
>Running rmdead.ys..
>cd tests/blif && bash run-test.sh
>Running bug2729.ys..
>Running bug3374.ys..
>ERROR: Syntax error in line 1!
>Expected error pattern 'Syntax error in line 1!' found !!!
>Running bug3385.ys..
>ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals.
>Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!!
>cd tests/opt && bash run-test.sh
>make[1]: Entering directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/opt'
>Passed bug1525.ys
>Passed bug1758.ys
>Passed bug1854.ys
>Passed bug2010.ys
>Passed bug2221.ys
>Passed bug2311.ys
>Passed bug2318.ys
>Passed bug2623.ys
>Passed bug2765.ys
>Passed bug2766.ys
>Passed bug2824.ys
>Passed bug2920.ys
>Passed bug3047.ys
>Passed bug3117.ys
>Passed memory_bmux2rom.ys
>Passed memory_dff_trans.ys
>Passed memory_map_offset.ys
>Passed opt_clean_init.ys
>Passed opt_clean_mem.ys
>Passed opt_dff_arst.ys
>Passed opt_dff_clk.ys
>Passed opt_dff_const.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:2)
>Passed opt_dff_dffmux.ys
><<EOT:19: Warning: Range select [13:12] out of bounds on signal `\Q': Setting all 2 result bits to undef.
><<EOT:20: Warning: Range select [15:14] out of bounds on signal `\Q': Setting all 2 result bits to undef.
>Passed opt_dff_en.ys
>Passed opt_dff_mux.ys
><<EOT:24: Warning: Range select [21:20] out of bounds on signal `\Q': Setting all 2 result bits to undef.
><<EOT:25: Warning: Range select [23:22] out of bounds on signal `\Q': Setting all 2 result bits to undef.
>Passed opt_dff_qd.ys
>Passed opt_dff_sr.ys
>Passed opt_dff_srst.ys
>Passed opt_expr.ys
>Passed opt_expr_alu.ys
>Passed opt_expr_and.ys
>Passed opt_expr_cmp.ys
>Warning: wire '\a' is assigned in a block at <<EOT:4.2-4.8.
>Warning: wire '\a' is assigned in a block at <<EOT:5.2-5.8.
>Warning: wire '\a' is assigned in a block at <<EOT:4.9-4.15.
>Warning: wire '\a' is assigned in a block at <<EOT:5.9-5.15.
>Passed opt_expr_combined_assign.ys
>Passed opt_expr_constconn.ys
>Passed opt_expr_consumex.ys
>Passed opt_expr_or.ys
>Passed opt_expr_xnor.ys
>Passed opt_expr_xor.ys
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:41)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:86)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:87)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2153)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2154)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2155)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2156)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2157)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2158)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2925)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2926)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2988)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2989)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:2990)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:3203)
>Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/share/ice40/cells_sim.v:3210)
>Passed opt_lut.ys
>Passed opt_lut_elim.ys
>Passed opt_lut_ins.ys
>Passed opt_lut_port.ys
>Passed opt_mem_feedback.ys
>Passed opt_mem_priority.ys
>Passed opt_merge_init.ys
>Passed opt_merge_keep.ys
>Passed opt_reduce_bmux.ys
>Passed opt_reduce_demux.ys
>Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver.
>Passed opt_rmdff.ys
>Passed opt_rmdff_sat.ys
>Passed opt_share_add_sub.ys
>Passed opt_share_bug2334.ys
>Passed opt_share_bug2335.ys
>Passed opt_share_bug2336.ys
>Passed opt_share_bug2538.ys
>Passed opt_share_cat.ys
>Passed opt_share_cat_multiuser.ys
>Passed opt_share_diff_port_widths.ys
>Passed opt_share_extend.ys
>Passed opt_share_large_pmux_cat.ys
>Passed opt_share_large_pmux_cat_multipart.ys
>Passed opt_share_large_pmux_multipart.ys
>Passed opt_share_large_pmux_part.ys
>Passed opt_share_mux_tree.ys
>make[1]: Leaving directory '/builddir/build/BUILD/yosys-5813809ad9afbe1c38f65c6aae7c3441d7614d0b/tests/opt'
>cd tests/aiger && bash run-test.sh "-A /usr/bin/abc"
>Checking and_.aag.
>Checking buffer.aag.
>Checking cnt1.aag.
>Warning: The new network has no primary inputs. It is recommended
>to add a dummy PI to make sure all commands work correctly.
>Checking cnt1e.aag.
>Checking empty.aag.
>Warning: The new network has no primary inputs. It is recommended
>to add a dummy PI to make sure all commands work correctly.
>Warning: The current network has no primary outputs. Some commands may not work correctly.
>Checking false.aag.
>run-test.sh: line 19: 31920 Segmentation fault      (core dumped) $abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
>make: *** [Makefile:864: test] Error 139
>RPM build errors:
>error: Bad exit status from /var/tmp/rpm-tmp.Hiuhg5 (%check)
>    Bad exit status from /var/tmp/rpm-tmp.Hiuhg5 (%check)
>Child return code was: 1
>EXCEPTION: [Error('Command failed: \n # /usr/bin/systemd-nspawn -q -M 9656fffec26f41fe9d8ef3f98db09d61 -D /var/lib/mock/f39-build-44382532-5277708/root -a -u mockbuild --capability=cap_ipc_lock --bind=/tmp/mock-resolv.ptrhrf8k:/etc/resolv.conf --bind=/dev/btrfs-control --bind=/dev/mapper/control --bind=/dev/loop-control --bind=/dev/loop0 --bind=/dev/loop1 --bind=/dev/loop2 --bind=/dev/loop3 --bind=/dev/loop4 --bind=/dev/loop5 --bind=/dev/loop6 --bind=/dev/loop7 --bind=/dev/loop8 --bind=/dev/loop9 --bind=/dev/loop10 --bind=/dev/loop11 --console=pipe --setenv=TERM=vt100 --setenv=SHELL=/bin/bash --setenv=HOME=/builddir --setenv=HOSTNAME=mock --setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin --setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007" --setenv=PS1=<mock-chroot> \\s-\\v\\$  --setenv=LANG=C.UTF-8 --resolv-conf=off bash --login -c /usr/bin/rpmbuild -bb --noclean --target aarch64 --nodeps /builddir/build/SPECS/yosys.spec\n', 1)]
>Traceback (most recent call last):
>  File "/usr/lib/python3.11/site-packages/mockbuild/trace_decorator.py", line 93, in trace
>    result = func(*args, **kw)
>             ^^^^^^^^^^^^^^^^^
>  File "/usr/lib/python3.11/site-packages/mockbuild/util.py", line 597, in do_with_status
>    raise exception.Error("Command failed: \n # %s\n%s" % (command, output), child.returncode)
>mockbuild.exception.Error: Command failed: 
> # /usr/bin/systemd-nspawn -q -M 9656fffec26f41fe9d8ef3f98db09d61 -D /var/lib/mock/f39-build-44382532-5277708/root -a -u mockbuild --capability=cap_ipc_lock --bind=/tmp/mock-resolv.ptrhrf8k:/etc/resolv.conf --bind=/dev/btrfs-control --bind=/dev/mapper/control --bind=/dev/loop-control --bind=/dev/loop0 --bind=/dev/loop1 --bind=/dev/loop2 --bind=/dev/loop3 --bind=/dev/loop4 --bind=/dev/loop5 --bind=/dev/loop6 --bind=/dev/loop7 --bind=/dev/loop8 --bind=/dev/loop9 --bind=/dev/loop10 --bind=/dev/loop11 --console=pipe --setenv=TERM=vt100 --setenv=SHELL=/bin/bash --setenv=HOME=/builddir --setenv=HOSTNAME=mock --setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin --setenv=PROMPT_COMMAND=printf "\033]0;<mock-chroot>\007" --setenv=PS1=<mock-chroot> \s-\v\$  --setenv=LANG=C.UTF-8 --resolv-conf=off bash --login -c /usr/bin/rpmbuild -bb --noclean --target aarch64 --nodeps /builddir/build/SPECS/yosys.spec
>

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Attachments on bug 2226521: 1979895 | 1979896 | 1979897