Attachment 290031 Details for Bug 421021 – AMD Family 10/11 fixes for HV

[patch] AMD Family 10/11 fixes for HV

AMD_Fam10-11_fixes.patch (text/plain), 7.70 KB, created by Bhavna Sarathy on 2007-12-19 15:23:18 UTC

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Creator: Bhavna Sarathy

Created: 2007-12-19 15:23:18 UTC

Size: 7.70 KB

patch

obsolete

>Signed-off-by: Jan Beulich <jbeulich@novell.com>
>
>Index: 2007-10-10/xen/arch/x86/apic.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/apic.c	2007-08-06 15:08:40.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/apic.c	2007-10-10 17:12:29.000000000 +0200
>@@ -737,7 +737,7 @@ static int __init detect_init_APIC (void
>     switch (boot_cpu_data.x86_vendor) {
>     case X86_VENDOR_AMD:
>         if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
>-            (boot_cpu_data.x86 == 15))        
>+            (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
>             break;
>         goto no_apic;
>     case X86_VENDOR_INTEL:
>Index: 2007-10-10/xen/arch/x86/cpu/amd.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/cpu/amd.c	2007-06-04 08:35:35.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/cpu/amd.c	2007-10-10 17:12:29.000000000 +0200
>@@ -278,7 +278,7 @@ static void __init init_amd(struct cpuin
> 	}
> 
> 	switch (c->x86) {
>-	case 15:
>+	case 15 ... 17:
> 		set_bit(X86_FEATURE_K8, c->x86_capability);
> 		break;
> 	case 6:
>@@ -303,11 +303,8 @@ static void __init init_amd(struct cpuin
> 
> 	display_cacheinfo(c);
> 
>-	if (cpuid_eax(0x80000000) >= 0x80000008) {
>+	if (cpuid_eax(0x80000000) >= 0x80000008)
> 		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
>-		if (c->x86_max_cores & (c->x86_max_cores - 1))
>-			c->x86_max_cores = 1;
>-	}
> 
> 	if (cpuid_eax(0x80000000) >= 0x80000007) {
> 		c->x86_power = cpuid_edx(0x80000007);
>@@ -317,15 +314,18 @@ static void __init init_amd(struct cpuin
> 
> #ifdef CONFIG_X86_HT
> 	/*
>-	 * On a AMD dual core setup the lower bits of the APIC id
>+	 * On a AMD multi core setup the lower bits of the APIC id
> 	 * distingush the cores.  Assumes number of cores is a power
> 	 * of two.
> 	 */
> 	if (c->x86_max_cores > 1) {
> 		int cpu = smp_processor_id();
>-		unsigned bits = 0;
>-		while ((1 << bits) < c->x86_max_cores)
>-			bits++;
>+		unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
>+
>+		if (bits == 0) {
>+			while ((1 << bits) < c->x86_max_cores)
>+				bits++;
>+		}
> 		cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
> 		phys_proc_id[cpu] >>= bits;
> 		printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
>Index: 2007-10-10/xen/arch/x86/cpu/mcheck/mce.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/cpu/mcheck/mce.c	2006-11-14 13:51:10.000000000 +0100
>+++ 2007-10-10/xen/arch/x86/cpu/mcheck/mce.c	2007-10-10 17:12:29.000000000 +0200
>@@ -34,7 +34,7 @@ void mcheck_init(struct cpuinfo_x86 *c)
> 
> 	switch (c->x86_vendor) {
> 		case X86_VENDOR_AMD:
>-			if (c->x86==6 || c->x86==15)
>+			if (c->x86 >= 6)
> 				amd_mcheck_init(c);
> 			break;
> 
>Index: 2007-10-10/xen/arch/x86/cpu/mtrr/main.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/cpu/mtrr/main.c	2007-09-10 09:59:36.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/cpu/mtrr/main.c	2007-10-10 17:12:29.000000000 +0200
>@@ -55,7 +55,7 @@ u32 num_var_ranges = 0;
> unsigned int *usage_table;
> static DECLARE_MUTEX(mtrr_sem);
> 
>-u32 size_or_mask, size_and_mask;
>+u64 size_or_mask, size_and_mask;
> 
> static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
> 
>@@ -587,8 +587,8 @@ void __init mtrr_bp_init(void)
> 			     boot_cpu_data.x86_mask == 0x4))
> 				phys_addr = 36;
> 
>-			size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
>-			size_and_mask = ~size_or_mask & 0xfff00000;
>+			size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
>+			size_and_mask = ~size_or_mask & 0xfffff00000ULL;
> 		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
> 			   boot_cpu_data.x86 == 6) {
> 			/* VIA C* family have Intel style MTRRs, but
>Index: 2007-10-10/xen/arch/x86/cpu/mtrr/mtrr.h
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/cpu/mtrr/mtrr.h	2006-02-15 15:07:25.000000000 +0100
>+++ 2007-10-10/xen/arch/x86/cpu/mtrr/mtrr.h	2007-10-10 17:12:29.000000000 +0200
>@@ -83,7 +83,7 @@ void get_mtrr_state(void);
> 
> extern void set_mtrr_ops(struct mtrr_ops * ops);
> 
>-extern u32 size_or_mask, size_and_mask;
>+extern u64 size_or_mask, size_and_mask;
> extern struct mtrr_ops * mtrr_if;
> 
> #define is_cpu(vnd)	(mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
>Index: 2007-10-10/xen/arch/x86/nmi.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/nmi.c	2007-08-06 15:08:41.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/nmi.c	2007-10-10 17:12:29.000000000 +0200
>@@ -314,9 +314,14 @@ void __pminit setup_apic_nmi_watchdog(vo
> 
>     switch (boot_cpu_data.x86_vendor) {
>     case X86_VENDOR_AMD:
>-        if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
>+        switch (boot_cpu_data.x86) {
>+	case 6:
>+	case 15 ... 17:
>+	        setup_k7_watchdog();
>+		break;
>+	default:
>             return;
>-        setup_k7_watchdog();
>+	}
>         break;
>     case X86_VENDOR_INTEL:
>         switch (boot_cpu_data.x86) {
>Index: 2007-10-10/xen/arch/x86/oprofile/nmi_int.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/oprofile/nmi_int.c	2007-08-06 15:08:41.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/oprofile/nmi_int.c	2007-10-10 17:12:29.000000000 +0200
>@@ -348,6 +348,14 @@ static int __init nmi_init(void)
> 				   give user space an consistent name. */
> 				cpu_type = "x86-64/hammer";
> 				break;
>+			case 0x10:
>+				model = &op_athlon_spec;
>+				cpu_type = "x86-64/family10";
>+				break;
>+			case 0x11:
>+				model = &op_athlon_spec;
>+				cpu_type = "x86-64/family11";
>+				break;
> 			}
> 			break;
>  
>Index: 2007-10-10/xen/arch/x86/oprofile/op_model_athlon.c
>===================================================================
>--- 2007-10-10.orig/xen/arch/x86/oprofile/op_model_athlon.c	2007-09-27 10:42:44.000000000 +0200
>+++ 2007-10-10/xen/arch/x86/oprofile/op_model_athlon.c	2007-10-10 17:12:29.000000000 +0200
>@@ -34,12 +34,15 @@
> #define CTRL_WRITE(l,h,msrs,c) do {wrmsr(msrs->controls[(c)].addr, (l), (h));} while (0)
> #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
> #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
>-#define CTRL_CLEAR(x) (x &= (1<<21))
>+#define CTRL_CLEAR(lo, hi) (lo &= (1<<21), hi = 0)
> #define CTRL_SET_ENABLE(val) (val |= 1<<20)
> #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16))
> #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17))
>-#define CTRL_SET_UM(val, m) (val |= (m << 8))
>-#define CTRL_SET_EVENT(val, e) (val |= e)
>+#define CTRL_SET_UM(val, m) (val |= ((m & 0xff) << 8))
>+#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
>+#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
>+#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
>+#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
> 
> static unsigned long reset_value[NUM_COUNTERS];
> 
>@@ -72,7 +75,7 @@ static void athlon_setup_ctrs(struct op_
> 	/* clear all counters */
> 	for (i = 0 ; i < NUM_CONTROLS; ++i) {
> 		CTRL_READ(low, high, msrs, i);
>-		CTRL_CLEAR(low);
>+		CTRL_CLEAR(low, high);
> 		CTRL_WRITE(low, high, msrs, i);
> 	}
> 	
>@@ -89,12 +92,15 @@ static void athlon_setup_ctrs(struct op_
> 			CTR_WRITE(counter_config[i].count, msrs, i);
> 
> 			CTRL_READ(low, high, msrs, i);
>-			CTRL_CLEAR(low);
>+			CTRL_CLEAR(low, high);
> 			CTRL_SET_ENABLE(low);
> 			CTRL_SET_USR(low, counter_config[i].user);
> 			CTRL_SET_KERN(low, counter_config[i].kernel);
> 			CTRL_SET_UM(low, counter_config[i].unit_mask);
>-			CTRL_SET_EVENT(low, counter_config[i].event);
>+			CTRL_SET_EVENT_LOW(low, counter_config[i].event);
>+			CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
>+			CTRL_SET_HOST_ONLY(high, 0);
>+			CTRL_SET_GUEST_ONLY(high, 0);
> 			CTRL_WRITE(low, high, msrs, i);
> 		} else {
> 			reset_value[i] = 0;
>
>
>
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>

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Attachments on bug 421021: 290031