Attachment 302651 Details for Bug 216799 – new sky2 backport

[patch] new sky2 backport

linux-kernel-test.patch (text/plain), 164.53 KB, created by Neil Horman on 2008-04-16 18:23:39 UTC

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Creator: Neil Horman

Created: 2008-04-16 18:23:39 UTC

Size: 164.53 KB

patch

obsolete

>--- linux-2.6.9/drivers/net/sky2_compat.h.orig	2008-04-16 09:50:40.000000000 -0400
>+++ linux-2.6.9/drivers/net/sky2_compat.h	2008-04-16 09:58:38.000000000 -0400
>@@ -33,4 +33,124 @@
> 	init_timer(timer);
> }
> 
>+static inline void netif_tx_lock_bh(struct net_device *dev)
>+{
>+	spin_lock_bh(&dev->xmit_lock);
>+	dev->xmit_lock_owner = smp_processor_id();
>+}
>+
>+static inline void netif_tx_unlock_bh(struct net_device *dev)
>+{
>+	dev->xmit_lock_owner = -1;
>+	spin_unlock_bh(&dev->xmit_lock);
>+}
>+
>+static inline void netif_tx_lock(struct net_device *dev)
>+{
>+	spin_lock(&dev->xmit_lock);
>+}
>+
>+static inline void netif_tx_unlock(struct net_device *dev)
>+{
>+	spin_unlock(&dev->xmit_lock);
>+}
>+
>+static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev,
>+                unsigned int length)
>+{
>+	struct sk_buff *skb = dev_alloc_skb(length);
>+
>+	if (likely(skb))
>+		skb->dev = dev;
>+	return skb;
>+}
>+
>+static inline int skb_is_gso(const struct sk_buff *skb)
>+{
>+	return skb_shinfo(skb)->tso_size;
>+}
>+
>+#define skb_network_header(skb) (skb->nh.raw)
>+#define skb_transport_header(skb) (skb->h.raw)
>+#define ip_hdr(skb) (skb->nh.iph)
>+#define tcp_hdrlen(skb) (skb->h.th->doff * 4)
>+
>+#define round_jiffies(jiffies)  jiffies
>+
>+static inline unsigned int ip_hdrlen(const struct sk_buff *skb)
>+{
>+	return ip_hdr(skb)->ihl * 4;
>+}
>+
>+static inline int skb_transport_offset(const struct sk_buff *skb)
>+{
>+	return skb_transport_header(skb) - skb->data;
>+}
>+
>+static inline void skb_copy_from_linear_data(const struct sk_buff *skb,
>+                                             void *to,
>+                                             const unsigned int len)
>+{
>+        memcpy(to, skb->data, len);
>+}
>+
>+
>+static inline int
>+backport_request_irq(unsigned int irq,
>+                     irqreturn_t (*handler)(int, void *),
>+                     unsigned long flags, const char *dev_name, void *dev_id)
>+{
>+        return request_irq(irq,
>+                           (irqreturn_t (*)(int, void *, struct pt_regs *))handler,
>+                           flags, dev_name, dev_id);
>+}
>+
>+#define request_irq backport_request_irq
>+#define IRQF_SHARED SA_SHIRQ
>+
>+#define MAC_BUF_SIZE 18
>+#define DECLARE_MAC_BUF(var) char var[MAC_BUF_SIZE] 
>+
>+static size_t _format_mac_addr(char *buf, int buflen,
>+                                const unsigned char *addr, int len)
>+{
>+        int i;
>+        char *cp = buf;
>+
>+        for (i = 0; i < len; i++) {
>+                cp += scnprintf(cp, buflen - (cp - buf), "%02x", addr[i]);
>+                if (i == len - 1)
>+                        break;
>+                cp += strlcpy(cp, ":", buflen - (cp - buf));
>+        }
>+        return cp - buf;
>+}
>+
>+static char *print_mac(char *buf, const unsigned char *addr)
>+{
>+        _format_mac_addr(buf, MAC_BUF_SIZE, addr, ETH_ALEN);
>+        return buf;
>+}
>+
>+
>+static inline void backport_INIT_WORK(struct work_struct *work, void *func)
>+{
>+        INIT_WORK(work, func, work);
>+}
>+
>+#undef INIT_WORK
>+#define INIT_WORK(_work, _func) backport_INIT_WORK(_work, _func)
>+
>+
>+#ifndef PTR_ALIGN
>+#define PTR_ALIGN(p, a)         ((typeof(p))ALIGN((unsigned long)(p), (a)))
>+#endif
>+
>+#ifndef roundup
>+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
>+#endif
>+
>+#define CHECKSUM_PARTIAL	CHECKSUM_HW
>+#define CHECKSUM_COMPLETE	CHECKSUM_HW
>+
> #endif /* __SKY2_COMPAT_H__ */
>--- linux-2.6.9/drivers/net/sky2.h.orig	2008-04-16 09:50:40.000000000 -0400
>+++ linux-2.6.9/drivers/net/sky2.h	2008-04-16 09:58:34.000000000 -0400
>@@ -4,6 +4,8 @@
> #ifndef _SKY2_H
> #define _SKY2_H
> 
>+#define ETH_JUMBO_MTU		9000	/* Maximum MTU supported */
>+
> /* PCI config registers */
> enum {
> 	PCI_DEV_REG1	= 0x40,
>@@ -12,24 +14,20 @@
> 	PCI_DEV_REG3	= 0x80,
> 	PCI_DEV_REG4	= 0x84,
> 	PCI_DEV_REG5    = 0x88,
>-};
>-
>-enum {
>-	PEX_DEV_CAP	= 0xe4,
>-	PEX_DEV_CTRL	= 0xe8,
>-	PEX_DEV_STA	= 0xea,
>-	PEX_LNK_STAT	= 0xf2,
>-	PEX_UNC_ERR_STAT= 0x104,
>+	PCI_CFG_REG_0	= 0x90,
>+	PCI_CFG_REG_1	= 0x94,
> };
> 
> /* Yukon-2 */
> enum pci_dev_reg_1 {
> 	PCI_Y2_PIG_ENA	 = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
> 	PCI_Y2_DLL_DIS	 = 1<<30, /* Disable PCI DLL (YUKON-2) */
>+	PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
> 	PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
> 	PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
> 	PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
> 	PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
>+	PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
> };
> 
> enum pci_dev_reg_2 {
>@@ -64,6 +62,80 @@
> 				  | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
> };
> 
>+/*	PCI_OUR_REG_5		32 bit	Our Register 5 (Yukon-ECU only) */
>+enum pci_dev_reg_5 {
>+					/* Bit 31..27:	for A3 & later */
>+	P_CTL_DIV_CORE_CLK_ENA	= 1<<31, /* Divide Core Clock Enable */
>+	P_CTL_SRESET_VMAIN_AV	= 1<<30, /* Soft Reset for Vmain_av De-Glitch */
>+	P_CTL_BYPASS_VMAIN_AV	= 1<<29, /* Bypass En. for Vmain_av De-Glitch */
>+	P_CTL_TIM_VMAIN_AV_MSK	= 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
>+					 /* Bit 26..16: Release Clock on Event */
>+	P_REL_PCIE_RST_DE_ASS	= 1<<26, /* PCIe Reset De-Asserted */
>+	P_REL_GPHY_REC_PACKET	= 1<<25, /* GPHY Received Packet */
>+	P_REL_INT_FIFO_N_EMPTY	= 1<<24, /* Internal FIFO Not Empty */
>+	P_REL_MAIN_PWR_AVAIL	= 1<<23, /* Main Power Available */
>+	P_REL_CLKRUN_REQ_REL	= 1<<22, /* CLKRUN Request Release */
>+	P_REL_PCIE_RESET_ASS	= 1<<21, /* PCIe Reset Asserted */
>+	P_REL_PME_ASSERTED	= 1<<20, /* PME Asserted */
>+	P_REL_PCIE_EXIT_L1_ST	= 1<<19, /* PCIe Exit L1 State */
>+	P_REL_LOADER_NOT_FIN	= 1<<18, /* EPROM Loader Not Finished */
>+	P_REL_PCIE_RX_EX_IDLE	= 1<<17, /* PCIe Rx Exit Electrical Idle State */
>+	P_REL_GPHY_LINK_UP	= 1<<16, /* GPHY Link Up */
>+
>+					/* Bit 10.. 0: Mask for Gate Clock */
>+	P_GAT_PCIE_RST_ASSERTED	= 1<<10,/* PCIe Reset Asserted */
>+	P_GAT_GPHY_N_REC_PACKET	= 1<<9, /* GPHY Not Received Packet */
>+	P_GAT_INT_FIFO_EMPTY	= 1<<8, /* Internal FIFO Empty */
>+	P_GAT_MAIN_PWR_N_AVAIL	= 1<<7, /* Main Power Not Available */
>+	P_GAT_CLKRUN_REQ_REL	= 1<<6, /* CLKRUN Not Requested */
>+	P_GAT_PCIE_RESET_ASS	= 1<<5, /* PCIe Reset Asserted */
>+	P_GAT_PME_DE_ASSERTED	= 1<<4, /* PME De-Asserted */
>+	P_GAT_PCIE_ENTER_L1_ST	= 1<<3, /* PCIe Enter L1 State */
>+	P_GAT_LOADER_FINISHED	= 1<<2, /* EPROM Loader Finished */
>+	P_GAT_PCIE_RX_EL_IDLE	= 1<<1, /* PCIe Rx Electrical Idle State */
>+	P_GAT_GPHY_LINK_DOWN	= 1<<0,	/* GPHY Link Down */
>+
>+	PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
>+				     P_REL_INT_FIFO_N_EMPTY |
>+				     P_REL_PCIE_EXIT_L1_ST |
>+				     P_REL_PCIE_RX_EX_IDLE |
>+				     P_GAT_GPHY_N_REC_PACKET |
>+				     P_GAT_INT_FIFO_EMPTY |
>+				     P_GAT_PCIE_ENTER_L1_ST |
>+				     P_GAT_PCIE_RX_EL_IDLE,
>+};
>+
>+#/*	PCI_CFG_REG_1			32 bit	Config Register 1 (Yukon-Ext only) */
>+enum pci_cfg_reg1 {
>+	P_CF1_DIS_REL_EVT_RST	= 1<<24, /* Dis. Rel. Event during PCIE reset */
>+										/* Bit 23..21: Release Clock on Event */
>+	P_CF1_REL_LDR_NOT_FIN	= 1<<23, /* EEPROM Loader Not Finished */
>+	P_CF1_REL_VMAIN_AVLBL	= 1<<22, /* Vmain available */
>+	P_CF1_REL_PCIE_RESET	= 1<<21, /* PCI-E reset */
>+										/* Bit 20..18: Gate Clock on Event */
>+	P_CF1_GAT_LDR_NOT_FIN	= 1<<20, /* EEPROM Loader Finished */
>+	P_CF1_GAT_PCIE_RX_IDLE	= 1<<19, /* PCI-E Rx Electrical idle */
>+	P_CF1_GAT_PCIE_RESET	= 1<<18, /* PCI-E Reset */
>+	P_CF1_PRST_PHY_CLKREQ	= 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
>+	P_CF1_PCIE_RST_CLKREQ	= 1<<16, /* Enable PCI-E rst generate CLKREQ */
>+
>+	P_CF1_ENA_CFG_LDR_DONE	= 1<<8, /* Enable core level Config loader done */
>+
>+	P_CF1_ENA_TXBMU_RD_IDLE	= 1<<1, /* Enable TX BMU Read  IDLE for ASPM */
>+	P_CF1_ENA_TXBMU_WR_IDLE	= 1<<0, /* Enable TX BMU Write IDLE for ASPM */
>+
>+	PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
>+					P_CF1_REL_LDR_NOT_FIN |
>+					P_CF1_REL_VMAIN_AVLBL |
>+					P_CF1_REL_PCIE_RESET |
>+					P_CF1_GAT_LDR_NOT_FIN |
>+					P_CF1_GAT_PCIE_RESET |
>+					P_CF1_PRST_PHY_CLKREQ |
>+					P_CF1_ENA_CFG_LDR_DONE |
>+					P_CF1_ENA_TXBMU_RD_IDLE |
>+					P_CF1_ENA_TXBMU_WR_IDLE,
>+};
>+
> 
> #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
> 			       PCI_STATUS_SIG_SYSTEM_ERROR | \
>@@ -71,38 +143,6 @@
> 			       PCI_STATUS_REC_TARGET_ABORT | \
> 			       PCI_STATUS_PARITY)
> 
>-enum pex_dev_ctrl {
>-	PEX_DC_MAX_RRS_MSK	= 7<<12, /* Bit 14..12:	Max. Read Request Size */
>-	PEX_DC_EN_NO_SNOOP	= 1<<11,/* Enable No Snoop */
>-	PEX_DC_EN_AUX_POW	= 1<<10,/* Enable AUX Power */
>-	PEX_DC_EN_PHANTOM	= 1<<9,	/* Enable Phantom Functions */
>-	PEX_DC_EN_EXT_TAG	= 1<<8,	/* Enable Extended Tag Field */
>-	PEX_DC_MAX_PLS_MSK	= 7<<5,	/* Bit  7.. 5:	Max. Payload Size Mask */
>-	PEX_DC_EN_REL_ORD	= 1<<4,	/* Enable Relaxed Ordering */
>-	PEX_DC_EN_UNS_RQ_RP	= 1<<3,	/* Enable Unsupported Request Reporting */
>-	PEX_DC_EN_FAT_ER_RP	= 1<<2,	/* Enable Fatal Error Reporting */
>-	PEX_DC_EN_NFA_ER_RP	= 1<<1,	/* Enable Non-Fatal Error Reporting */
>-	PEX_DC_EN_COR_ER_RP	= 1<<0,	/* Enable Correctable Error Reporting */
>-};
>-#define  PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
>-
>-/* PEX_UNC_ERR_STAT	 PEX Uncorrectable Errors Status Register (Yukon-2) */
>-enum pex_err {
>-	PEX_UNSUP_REQ 	= 1<<20, /* Unsupported Request Error */
>-
>-	PEX_MALFOR_TLP	= 1<<18, /* Malformed TLP */
>-
>-	PEX_UNEXP_COMP	= 1<<16, /* Unexpected Completion */
>-
>-	PEX_COMP_TO	= 1<<14, /* Completion Timeout */
>-	PEX_FLOW_CTRL_P	= 1<<13, /* Flow Control Protocol Error */
>-	PEX_POIS_TLP	= 1<<12, /* Poisoned TLP */
>-
>-	PEX_DATA_LINK_P = 1<<4,	/* Data Link Protocol Error */
>-	PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
>-};
>-
>-
> enum csr_regs {
> 	B0_RAP		= 0x0000,
> 	B0_CTST		= 0x0004,
>@@ -207,7 +247,8 @@
> 	B3_PA_CTRL	= 0x01f0,
> 	B3_PA_TEST	= 0x01f2,
> 
>-	Y2_CFG_SPC	= 0x1c00,
>+	Y2_CFG_SPC	= 0x1c00,	/* PCI config space region */
>+	Y2_CFG_AER      = 0x1d00,	/* PCI Advanced Error Report region */
> };
> 
> /*	B0_CTST			16 bit	Control/Status register */
>@@ -285,6 +326,9 @@
> 		          | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
> 	Y2_IS_PORT_2	= Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
> 			  | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
>+	Y2_IS_ERROR     = Y2_IS_HW_ERR |
>+			  Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
>+			  Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
> };
> 
> /*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
>@@ -336,7 +380,6 @@
> 			  Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
> 
> 	Y2_HWE_ALL_MASK	= Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
>-			  Y2_IS_PCI_EXP |
> 			  Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
> };
> 
>@@ -358,6 +401,20 @@
> 	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
> };
> 
>+/* 	B2_GPIO */
>+enum {
>+	GLB_GPIO_CLK_DEB_ENA = 1<<31,	/* Clock Debug Enable */
>+	GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
>+
>+	GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
>+	GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
>+	GLB_GPIO_STAT_RACE_DIS	= 1<<13, /* Status Race Disable */
>+	GLB_GPIO_TEST_SEL_MSK	= 3<<11, /* Testmode Select */
>+	GLB_GPIO_TEST_SEL_BASE	= 1<<11,
>+	GLB_GPIO_RAND_ENA	= 1<<10, /* Random Enable */
>+	GLB_GPIO_RAND_BIT_1	= 1<<9,  /* Random Bit 1 */
>+};
>+
> /*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
> enum {
> 	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
>@@ -368,23 +425,37 @@
> 
> /*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
> enum {
>-	CHIP_ID_GENESIS	   = 0x0a, /* Chip ID for GENESIS */
>-	CHIP_ID_YUKON	   = 0xb0, /* Chip ID for YUKON */
>-	CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
>-	CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
>-	CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
>-	CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
>-	CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
>- 	CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
>-
>+	CHIP_ID_YUKON_XL   = 0xb3, /* YUKON-2 XL */
>+	CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
>+	CHIP_ID_YUKON_EX   = 0xb5, /* YUKON-2 Extreme */
>+	CHIP_ID_YUKON_EC   = 0xb6, /* YUKON-2 EC */
>+ 	CHIP_ID_YUKON_FE   = 0xb7, /* YUKON-2 FE */
>+ 	CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
>+	CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
>+};
>+enum yukon_ec_rev {
> 	CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
> 	CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
> 	CHIP_REV_YU_EC_A3    = 2,  /* Chip Rev. for Yukon-EC A3 */
>-
>-	CHIP_REV_YU_EC_U_A0  = 0,
>-	CHIP_REV_YU_EC_U_A1  = 1,
>+};
>+enum yukon_ec_u_rev {
>+	CHIP_REV_YU_EC_U_A0  = 1,
>+	CHIP_REV_YU_EC_U_A1  = 2,
>+	CHIP_REV_YU_EC_U_B0  = 3,
>+};
>+enum yukon_fe_rev {
>+	CHIP_REV_YU_FE_A1    = 1,
>+	CHIP_REV_YU_FE_A2    = 2,
>+};
>+enum yukon_fe_p_rev {
>+	CHIP_REV_YU_FE2_A0   = 0,
>+};
>+enum yukon_ex_rev {
>+	CHIP_REV_YU_EX_A0    = 1,
>+	CHIP_REV_YU_EX_B0    = 2,
> };
> 
>+
> /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
> enum {
> 	Y2_STATUS_LNK2_INAC	= 1<<7, /* Status Link 2 inactive (0 = active) */
>@@ -507,23 +578,15 @@
> enum {
> 	B8_Q_REGS = 0x0400, /* base of Queue registers */
> 	Q_D	= 0x00,	/* 8*32	bit	Current Descriptor */
>-	Q_DA_L	= 0x20,	/* 32 bit	Current Descriptor Address Low dWord */
>-	Q_DA_H	= 0x24,	/* 32 bit	Current Descriptor Address High dWord */
>+	Q_VLAN  = 0x20, /* 16 bit	Current VLAN Tag */
>+	Q_DONE	= 0x24,	/* 16 bit	Done Index */
> 	Q_AC_L	= 0x28,	/* 32 bit	Current Address Counter Low dWord */
> 	Q_AC_H	= 0x2c,	/* 32 bit	Current Address Counter High dWord */
> 	Q_BC	= 0x30,	/* 32 bit	Current Byte Counter */
> 	Q_CSR	= 0x34,	/* 32 bit	BMU Control/Status Register */
>-	Q_F	= 0x38,	/* 32 bit	Flag Register */
>-	Q_T1	= 0x3c,	/* 32 bit	Test Register 1 */
>-	Q_T1_TR	= 0x3c,	/*  8 bit	Test Register 1 Transfer SM */
>-	Q_T1_WR	= 0x3d,	/*  8 bit	Test Register 1 Write Descriptor SM */
>-	Q_T1_RD	= 0x3e,	/*  8 bit	Test Register 1 Read Descriptor SM */
>-	Q_T1_SV	= 0x3f,	/*  8 bit	Test Register 1 Supervisor SM */
>-	Q_T2	= 0x40,	/* 32 bit	Test Register 2	*/
>-	Q_T3	= 0x44,	/* 32 bit	Test Register 3	*/
>+	Q_TEST	= 0x38,	/* 32 bit	Test/Control Register */
> 
> /* Yukon-2 */
>-	Q_DONE	= 0x24,	/* 16 bit	Done Index 		(Yukon-2 only) */
> 	Q_WM	= 0x40,	/* 16 bit	FIFO Watermark */
> 	Q_AL	= 0x42,	/*  8 bit	FIFO Alignment */
> 	Q_RSP	= 0x44,	/* 16 bit	FIFO Read Shadow Pointer */
>@@ -537,15 +600,16 @@
> };
> #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
> 
>-/*	Q_F				32 bit	Flag Register */
>+/*	Q_TEST				32 bit	Test Register */
> enum {
>-	F_ALM_FULL	= 1<<27, /* Rx FIFO: almost full */
>-	F_EMPTY		= 1<<27, /* Tx FIFO: empty flag */
>-	F_FIFO_EOF	= 1<<26, /* Tag (EOF Flag) bit in FIFO */
>-	F_WM_REACHED	= 1<<25, /* Watermark reached */
>+	/* Transmit */
>+	F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
>+	F_TX_CHK_AUTO_ON  = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
>+
>+	/* Receive */
> 	F_M_RX_RAM_DIS	= 1<<24, /* MAC Rx RAM Read Port disable */
>-	F_FIFO_LEVEL	= 0x1fL<<16, /* Bit 23..16:	# of Qwords in FIFO */
>-	F_WATER_MARK	= 0x0007ffL, /* Bit 10.. 0:	Watermark */
>+
>+	/* Hardware testbits not used */
> };
> 
> /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
>@@ -601,7 +665,7 @@
> 	PHY_ADDR_MARV	= 0,
> };
> 
>-#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
>+#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
> 
> 
> enum {
>@@ -673,6 +737,7 @@
> 			  BMU_FIFO_ENA | BMU_OP_ON,
> 
> 	BMU_WM_DEFAULT = 0x600,
>+	BMU_WM_PEX     = 0x80,
> };
> 
> /* Tx BMU Control / Status Registers (Yukon-2) */
>@@ -732,6 +797,11 @@
> 	TX_GMF_RP	= 0x0d70,/* 32 bit 	Tx GMAC FIFO Read Pointer */
> 	TX_GMF_RSTP	= 0x0d74,/* 32 bit 	Tx GMAC FIFO Restart Pointer */
> 	TX_GMF_RLEV	= 0x0d78,/* 32 bit 	Tx GMAC FIFO Read Level */
>+
>+	/* Threshold values for Yukon-EC Ultra and Extreme */
>+	ECU_AE_THR	= 0x0070, /* Almost Empty Threshold */
>+	ECU_TXFF_LEV	= 0x01a0, /* Tx BMU FIFO Level */
>+	ECU_JUMBO_WM	= 0x0080, /* Jumbo Mode Watermark */
> };
> 
> /* Descriptor Poll Timer Registers */
>@@ -759,6 +829,24 @@
> 	POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit	Poll. List Start Addr (high) */
> };
> 
>+enum {
>+	SMB_CFG		 = 0x0e40, /* 32 bit	SMBus Config Register */
>+	SMB_CSR		 = 0x0e44, /* 32 bit	SMBus Control/Status Register */
>+};
>+
>+enum {
>+	CPU_WDOG	 = 0x0e48, /* 32 bit	Watchdog Register  */
>+	CPU_CNTR	 = 0x0e4C, /* 32 bit	Counter Register  */
>+	CPU_TIM		 = 0x0e50,/* 32 bit	Timer Compare Register  */
>+	CPU_AHB_ADDR	 = 0x0e54, /* 32 bit	CPU AHB Debug  Register  */
>+	CPU_AHB_WDATA	 = 0x0e58, /* 32 bit	CPU AHB Debug  Register  */
>+	CPU_AHB_RDATA	 = 0x0e5C, /* 32 bit	CPU AHB Debug  Register  */
>+	HCU_MAP_BASE	 = 0x0e60, /* 32 bit	Reset Mapping Base */
>+	CPU_AHB_CTRL	 = 0x0e64, /* 32 bit	CPU AHB Debug  Register  */
>+	HCU_CCSR	 = 0x0e68, /* 32 bit	CPU Control and Status Register */
>+	HCU_HCSR	 = 0x0e6C, /* 32 bit	Host Control and Status Register */
>+};
>+
> /* ASF Subsystem Registers (Yukon-2 only) */
> enum {
> 	B28_Y2_SMB_CONFIG  = 0x0e40,/* 32 bit	ASF SMBus Config Register */
>@@ -829,33 +917,27 @@
> 	GMAC_LINK_CTRL	= 0x0f10,/* 16 bit	Link Control Reg */
> 
> /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
>-
>-	WOL_REG_OFFS	= 0x20,/* HW-Bug: Address is + 0x20 against spec. */
>-
> 	WOL_CTRL_STAT	= 0x0f20,/* 16 bit	WOL Control/Status Reg */
> 	WOL_MATCH_CTL	= 0x0f22,/*  8 bit	WOL Match Control Reg */
> 	WOL_MATCH_RES	= 0x0f23,/*  8 bit	WOL Match Result Reg */
> 	WOL_MAC_ADDR	= 0x0f24,/* 32 bit	WOL MAC Address */
>-	WOL_PATT_PME	= 0x0f2a,/*  8 bit	WOL PME Match Enable (Yukon-2) */
>-	WOL_PATT_ASFM	= 0x0f2b,/*  8 bit	WOL ASF Match Enable (Yukon-2) */
> 	WOL_PATT_RPTR	= 0x0f2c,/*  8 bit	WOL Pattern Read Pointer */
> 
> /* WOL Pattern Length Registers (YUKON only) */
>-
> 	WOL_PATT_LEN_LO	= 0x0f30,/* 32 bit	WOL Pattern Length 3..0 */
> 	WOL_PATT_LEN_HI	= 0x0f34,/* 24 bit	WOL Pattern Length 6..4 */
> 
> /* WOL Pattern Counter Registers (YUKON only) */
>-
>-
> 	WOL_PATT_CNT_0	= 0x0f38,/* 32 bit	WOL Pattern Counter 3..0 */
> 	WOL_PATT_CNT_4	= 0x0f3c,/* 24 bit	WOL Pattern Counter 6..4 */
> };
>+#define WOL_REGS(port, x)	(x + (port)*0x80)
> 
> enum {
> 	WOL_PATT_RAM_1	= 0x1000,/*  WOL Pattern RAM Link 1 */
> 	WOL_PATT_RAM_2	= 0x1400,/*  WOL Pattern RAM Link 2 */
> };
>+#define WOL_PATT_RAM_BASE(port)	(WOL_PATT_RAM_1 + (port)*0x400)
> 
> enum {
> 	BASE_GMAC_1	= 0x2800,/* GMAC 1 registers */
>@@ -1053,7 +1135,7 @@
> 	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */
> };
> 
>-#define PHY_M_PC_MDI_XMODE(x)	(((x)<<5) & PHY_M_PC_MDIX_MSK)
>+#define PHY_M_PC_MDI_XMODE(x)	(((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
> 
> enum {
> 	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */
>@@ -1123,7 +1205,7 @@
> 	PHY_M_IS_JABBER		= 1<<0, /* Jabber */
> 
> 	PHY_M_DEF_MSK		= PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
>-				 | PHY_M_IS_FIFO_ERROR,
>+				 | PHY_M_IS_DUP_CHANGE,
> 	PHY_M_AN_MSK	       = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
> };
> 
>@@ -1149,13 +1231,13 @@
> 	PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
> 	PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};
> 
>-#define PHY_M_EC_M_DSC(x)	((x)<<10 & PHY_M_EC_M_DSC_MSK)
>+#define PHY_M_EC_M_DSC(x)	((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
> 					/* 00=1x; 01=2x; 10=3x; 11=4x */
>-#define PHY_M_EC_S_DSC(x)	((x)<<8 & PHY_M_EC_S_DSC_MSK)
>+#define PHY_M_EC_S_DSC(x)	((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
> 					/* 00=dis; 01=1x; 10=2x; 11=3x */
>-#define PHY_M_EC_DSC_2(x)	((x)<<9 & PHY_M_EC_M_DSC_MSK2)
>+#define PHY_M_EC_DSC_2(x)	((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
> 					/* 000=1x; 001=2x; 010=3x; 011=4x */
>-#define PHY_M_EC_MAC_S(x)	((x)<<4 & PHY_M_EC_MAC_S_MSK)
>+#define PHY_M_EC_MAC_S(x)	((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
> 					/* 01X=0; 110=2.5; 111=25 (MHz) */
> 
> /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
>@@ -1166,7 +1248,7 @@
> };
> /* !!! Errata in spec. (1 = disable) */
> 
>-#define PHY_M_PC_DSC(x)			(((x)<<12) & PHY_M_PC_DSC_MSK)
>+#define PHY_M_PC_DSC(x)			(((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
> 											/* 100=5x; 101=6x; 110=7x; 111=8x */
> enum {
> 	MAC_TX_CLK_0_MHZ	= 2,
>@@ -1196,7 +1278,7 @@
> 	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */
> };
> 
>-#define PHY_M_LED_PULS_DUR(x)	(((x)<<12) & PHY_M_LEDC_PULS_MSK)
>+#define PHY_M_LED_PULS_DUR(x)	(((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
> 
> /*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w	Polarity Control Reg. *****/
> enum {
>@@ -1226,7 +1308,7 @@
> 	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */
> };
> 
>-#define PHY_M_LED_BLINK_RT(x)	(((x)<<8) & PHY_M_LEDC_BL_R_MSK)
>+#define PHY_M_LED_BLINK_RT(x)	(((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
> 
> enum {
> 	BLINK_42MS	= 0,/* 42 ms */
>@@ -1237,20 +1319,20 @@
> };
> 
> /*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/
>-#define PHY_M_LED_MO_SGMII(x)	((x)<<14) /* Bit 15..14:  SGMII AN Timer */
>-										/* Bit 13..12:	reserved */
>-#define PHY_M_LED_MO_DUP(x)	((x)<<10) /* Bit 11..10:  Duplex */
>-#define PHY_M_LED_MO_10(x)	((x)<<8) /* Bit  9.. 8:  Link 10 */
>-#define PHY_M_LED_MO_100(x)	((x)<<6) /* Bit  7.. 6:  Link 100 */
>-#define PHY_M_LED_MO_1000(x)	((x)<<4) /* Bit  5.. 4:  Link 1000 */
>-#define PHY_M_LED_MO_RX(x)	((x)<<2) /* Bit  3.. 2:  Rx */
>-#define PHY_M_LED_MO_TX(x)	((x)<<0) /* Bit  1.. 0:  Tx */
>+#define PHY_M_LED_MO_SGMII(x)	((x)<<14)	/* Bit 15..14:  SGMII AN Timer */
> 
>-enum {
>-	MO_LED_NORM	= 0,
>-	MO_LED_BLINK	= 1,
>-	MO_LED_OFF	= 2,
>-	MO_LED_ON	= 3,
>+#define PHY_M_LED_MO_DUP(x)	((x)<<10)	/* Bit 11..10:  Duplex */
>+#define PHY_M_LED_MO_10(x)	((x)<<8)	/* Bit  9.. 8:  Link 10 */
>+#define PHY_M_LED_MO_100(x)	((x)<<6)	/* Bit  7.. 6:  Link 100 */
>+#define PHY_M_LED_MO_1000(x)	((x)<<4)	/* Bit  5.. 4:  Link 1000 */
>+#define PHY_M_LED_MO_RX(x)	((x)<<2)	/* Bit  3.. 2:  Rx */
>+#define PHY_M_LED_MO_TX(x)	((x)<<0)	/* Bit  1.. 0:  Tx */
>+
>+enum led_mode {
>+	MO_LED_NORM  = 0,
>+	MO_LED_BLINK = 1,
>+	MO_LED_OFF   = 2,
>+	MO_LED_ON    = 3,
> };
> 
> /*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
>@@ -1287,9 +1369,9 @@
> 	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
> };
> 
>-#define PHY_M_FELP_LED2_CTRL(x)	(((x)<<8) & PHY_M_FELP_LED2_MSK)
>-#define PHY_M_FELP_LED1_CTRL(x)	(((x)<<4) & PHY_M_FELP_LED1_MSK)
>-#define PHY_M_FELP_LED0_CTRL(x)	(((x)<<0) & PHY_M_FELP_LED0_MSK)
>+#define PHY_M_FELP_LED2_CTRL(x)	(((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
>+#define PHY_M_FELP_LED1_CTRL(x)	(((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
>+#define PHY_M_FELP_LED0_CTRL(x)	(((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
> 
> enum {
> 	LED_PAR_CTRL_COLX	= 0x00,
>@@ -1318,6 +1400,14 @@
> };
> 
> /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
>+/*****  PHY_MARV_PHY_CTRL (page 1)		16 bit r/w	Fiber Specific Ctrl *****/
>+enum {
>+	PHY_M_FIB_FORCE_LNK	= 1<<10,/* Force Link Good */
>+	PHY_M_FIB_SIGD_POL	= 1<<9,	/* SIGDET Polarity */
>+	PHY_M_FIB_TX_DIS	= 1<<3,	/* Transmitter Disable */
>+};
>+
>+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
> /*****  PHY_MARV_PHY_CTRL (page 2)		16 bit r/w	MAC Specific Ctrl *****/
> enum {
> 	PHY_M_MAC_MD_MSK	= 7<<7, /* Bit  9.. 7: Mode Select Mask */
>@@ -1537,8 +1627,8 @@
> 	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */
> };
> 
>-#define GM_SMI_CT_PHY_AD(x)	(((x)<<11) & GM_SMI_CT_PHY_A_MSK)
>-#define GM_SMI_CT_REG_AD(x)	(((x)<<6) & GM_SMI_CT_REG_A_MSK)
>+#define GM_SMI_CT_PHY_AD(x)	(((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
>+#define GM_SMI_CT_REG_AD(x)	(((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
> 
> /*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */
> enum {
>@@ -1548,7 +1638,7 @@
> 
> /* Receive Frame Status Encoding */
> enum {
>-	GMR_FS_LEN	= 0xffff<<16, /* Bit 31..16:	Rx Frame Length */
>+	GMR_FS_LEN	= 0x7fff<<16, /* Bit 30..16:	Rx Frame Length */
> 	GMR_FS_VLAN	= 1<<13, /* VLAN Packet */
> 	GMR_FS_JABBER	= 1<<12, /* Jabber Packet */
> 	GMR_FS_UN_SIZE	= 1<<11, /* Undersize Packet */
>@@ -1566,7 +1656,7 @@
> 
> 	GMR_FS_ANY_ERR	= GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
> 			  GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
>-		  	  GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
>+		  	  GMR_FS_MII_ERR | GMR_FS_BAD_FC |
> 			  GMR_FS_UN_SIZE | GMR_FS_JABBER,
> };
> 
>@@ -1577,6 +1667,16 @@
> 	RX_VLAN_STRIP_ON = 1<<25,	/* enable  VLAN stripping */
> 	RX_VLAN_STRIP_OFF = 1<<24,	/* disable VLAN stripping */
> 
>+	RX_MACSEC_FLUSH_ON  = 1<<23,
>+	RX_MACSEC_FLUSH_OFF = 1<<22,
>+	RX_MACSEC_ASF_FLUSH_ON = 1<<21,
>+	RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
>+
>+	GMF_RX_OVER_ON      = 1<<19,	/* enable flushing on receive overrun */
>+	GMF_RX_OVER_OFF     = 1<<18,	/* disable flushing on receive overrun */
>+	GMF_ASF_RX_OVER_ON  = 1<<17,	/* enable flushing of ASF when overrun */
>+	GMF_ASF_RX_OVER_OFF = 1<<16,	/* disable flushing of ASF when overrun */
>+
> 	GMF_WP_TST_ON	= 1<<14,	/* Write Pointer Test On */
> 	GMF_WP_TST_OFF	= 1<<13,	/* Write Pointer Test Off */
> 	GMF_WP_STEP	= 1<<12,	/* Write Pointer Step/Increment */
>@@ -1599,6 +1699,10 @@
> 	GMF_RX_CTRL_DEF	= GMF_OPER_ON | GMF_RX_F_FL_ON,
> };
> 
>+/*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
>+enum {
>+	TX_DYN_WM_ENA	= 3,	/* Yukon-FE+ specific */
>+};
> 
> /*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test */
> enum {
>@@ -1608,6 +1712,9 @@
> 	TX_VLAN_TAG_ON	= 1<<25,/* enable  VLAN tagging */
> 	TX_VLAN_TAG_OFF	= 1<<24,/* disable VLAN tagging */
> 
>+	TX_JUMBO_ENA	= 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
>+	TX_JUMBO_DIS	= 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
>+
> 	GMF_WSP_TST_ON	= 1<<18,/* Write Shadow Pointer Test On */
> 	GMF_WSP_TST_OFF	= 1<<17,/* Write Shadow Pointer Test Off */
> 	GMF_WSP_STEP	= 1<<16,/* Write Shadow Pointer Step/Increment */
>@@ -1641,6 +1748,39 @@
> 	Y2_ASF_CLR_ASFI = 1<<1,	/* Clear host IRQ */
> 	Y2_ASF_HOST_IRQ = 1<<0,	/* Issue an IRQ to HOST system */
> };
>+/*	HCU_CCSR	CPU Control and Status Register */
>+enum {
>+	HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
>+	HCU_CCSR_CPU_SLEEP	= 1<<26, /* CPU sleep status */
>+	/* Clock Stretching Timeout */
>+	HCU_CCSR_CS_TO		= 1<<25,
>+	HCU_CCSR_WDOG		= 1<<24, /* Watchdog Reset */
>+
>+	HCU_CCSR_CLR_IRQ_HOST	= 1<<17, /* Clear IRQ_HOST */
>+	HCU_CCSR_SET_IRQ_HCU	= 1<<16, /* Set IRQ_HCU */
>+
>+	HCU_CCSR_AHB_RST	= 1<<9, /* Reset AHB bridge */
>+	HCU_CCSR_CPU_RST_MODE	= 1<<8, /* CPU Reset Mode */
>+
>+	HCU_CCSR_SET_SYNC_CPU	= 1<<5,
>+	HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
>+	HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
>+	HCU_CCSR_OS_PRSNT	= 1<<2, /* ASF OS Present */
>+/* Microcontroller State */
>+	HCU_CCSR_UC_STATE_MSK	= 3,
>+	HCU_CCSR_UC_STATE_BASE	= 1<<0,
>+	HCU_CCSR_ASF_RESET	= 0,
>+	HCU_CCSR_ASF_HALTED	= 1<<1,
>+	HCU_CCSR_ASF_RUNNING	= 1<<0,
>+};
>+
>+/*	HCU_HCSR	Host Control and Status Register */
>+enum {
>+	HCU_HCSR_SET_IRQ_CPU	= 1<<16, /* Set IRQ_CPU */
>+
>+	HCU_HCSR_CLR_IRQ_HCU	= 1<<1, /* Clear IRQ_HCU */
>+	HCU_HCSR_SET_IRQ_HOST	= 1<<0,	/* Set IRQ_HOST */
>+};
> 
> /*	STAT_CTRL		32 bit	Status BMU control register (Yukon-2 only) */
> enum {
>@@ -1653,6 +1793,15 @@
> 
> /*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
> enum {
>+	GMC_SET_RST	    = 1<<15,/* MAC SEC RST */
>+	GMC_SEC_RST_OFF     = 1<<14,/* MAC SEC RSt OFF */
>+	GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
>+	GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
>+	GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
>+	GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX  off*/
>+	GMC_BYP_RETR_ON	= 1<<9, /* Bypass retransmit FIFO On */
>+	GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
>+
> 	GMC_H_BURST_ON	= 1<<7,	/* Half Duplex Burst Mode On */
> 	GMC_H_BURST_OFF	= 1<<6,	/* Half Duplex Burst Mode Off */
> 	GMC_F_LOOPB_ON	= 1<<5,	/* FIFO Loopback On */
>@@ -1665,28 +1814,28 @@
> 
> /*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */
> enum {
>-	GPC_SEL_BDT	= 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
>-	GPC_INT_POL_HI	= 1<<27, /* IRQ Polarity is Active HIGH */
>-	GPC_75_OHM	= 1<<26, /* Use 75 Ohm Termination instead of 50 */
>-	GPC_DIS_FC	= 1<<25, /* Disable Automatic Fiber/Copper Detection */
>-	GPC_DIS_SLEEP	= 1<<24, /* Disable Energy Detect */
>-	GPC_HWCFG_M_3	= 1<<23, /* HWCFG_MODE[3] */
>-	GPC_HWCFG_M_2	= 1<<22, /* HWCFG_MODE[2] */
>-	GPC_HWCFG_M_1	= 1<<21, /* HWCFG_MODE[1] */
>-	GPC_HWCFG_M_0	= 1<<20, /* HWCFG_MODE[0] */
>-	GPC_ANEG_0	= 1<<19, /* ANEG[0] */
>-	GPC_ENA_XC	= 1<<18, /* Enable MDI crossover */
>-	GPC_DIS_125	= 1<<17, /* Disable 125 MHz clock */
>-	GPC_ANEG_3	= 1<<16, /* ANEG[3] */
>-	GPC_ANEG_2	= 1<<15, /* ANEG[2] */
>-	GPC_ANEG_1	= 1<<14, /* ANEG[1] */
>-	GPC_ENA_PAUSE	= 1<<13, /* Enable Pause (SYM_OR_REM) */
>-	GPC_PHYADDR_4	= 1<<12, /* Bit 4 of Phy Addr */
>-	GPC_PHYADDR_3	= 1<<11, /* Bit 3 of Phy Addr */
>-	GPC_PHYADDR_2	= 1<<10, /* Bit 2 of Phy Addr */
>-	GPC_PHYADDR_1	= 1<<9,	 /* Bit 1 of Phy Addr */
>-	GPC_PHYADDR_0	= 1<<8,	 /* Bit 0 of Phy Addr */
>-						/* Bits  7..2:	reserved */
>+	GPC_TX_PAUSE	= 1<<30, /* Tx pause enabled (ro) */
>+	GPC_RX_PAUSE	= 1<<29, /* Rx pause enabled (ro) */
>+	GPC_SPEED	= 3<<27, /* PHY speed (ro) */
>+	GPC_LINK	= 1<<26, /* Link up (ro) */
>+	GPC_DUPLEX	= 1<<25, /* Duplex (ro) */
>+	GPC_CLOCK	= 1<<24, /* 125Mhz clock stable (ro) */
>+
>+	GPC_PDOWN	= 1<<23, /* Internal regulator 2.5 power down */
>+	GPC_TSTMODE	= 1<<22, /* Test mode */
>+	GPC_REG18	= 1<<21, /* Reg18 Power down */
>+	GPC_REG12SEL	= 3<<19, /* Reg12 power setting */
>+	GPC_REG18SEL	= 3<<17, /* Reg18 power setting */
>+	GPC_SPILOCK	= 1<<16, /* SPI lock (ASF) */
>+
>+	GPC_LEDMUX	= 3<<14, /* LED Mux */
>+	GPC_INTPOL	= 1<<13, /* Interrupt polarity */
>+	GPC_DETECT	= 1<<12, /* Energy detect */
>+	GPC_1000HD	= 1<<11, /* Enable 1000Mbit HD */
>+	GPC_SLAVE	= 1<<10, /* Slave mode */
>+	GPC_PAUSE	= 1<<9, /* Pause enable */
>+	GPC_LEDCTL	= 3<<6, /* GPHY Leds */
>+
> 	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */
> 	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */
> };
>@@ -1702,14 +1851,17 @@
> 	GM_IS_RX_COMPL	= 1<<0,	/* Frame Reception Complete */
> 
> #define GMAC_DEF_MSK     GM_IS_TX_FF_UR
>+};
> 
> /*	GMAC_LINK_CTRL	16 bit	GMAC Link Control Reg (YUKON only) */
>-						/* Bits 15.. 2:	reserved */
>+enum {						/* Bits 15.. 2:	reserved */
> 	GMLC_RST_CLR	= 1<<1,	/* Clear GMAC Link Reset */
> 	GMLC_RST_SET	= 1<<0,	/* Set   GMAC Link Reset */
>+};
> 
> 
> /*	WOL_CTRL_STAT	16 bit	WOL Control/Status Reg */
>+enum {
> 	WOL_CTL_LINK_CHG_OCC		= 1<<15,
> 	WOL_CTL_MAGIC_PKT_OCC		= 1<<14,
> 	WOL_CTL_PATTERN_OCC		= 1<<13,
>@@ -1728,17 +1880,6 @@
> 	WOL_CTL_DIS_PATTERN_UNIT	= 1<<0,
> };
> 
>-#define WOL_CTL_DEFAULT				\
>-	(WOL_CTL_DIS_PME_ON_LINK_CHG |	\
>-	WOL_CTL_DIS_PME_ON_PATTERN |	\
>-	WOL_CTL_DIS_PME_ON_MAGIC_PKT |	\
>-	WOL_CTL_DIS_LINK_CHG_UNIT |		\
>-	WOL_CTL_DIS_PATTERN_UNIT |		\
>-	WOL_CTL_DIS_MAGIC_PKT_UNIT)
>-
>-/*	WOL_MATCH_CTL	 8 bit	WOL Match Control Reg */
>-#define WOL_CTL_PATT_ENA(x)	(1 << (x))
>-
> 
> /* Control flags */
> enum {
>@@ -1748,7 +1889,6 @@
> 	INIT_SUM= 1<<3,
> 	LOCK_SUM= 1<<4,
> 	INS_VLAN= 1<<5,
>-	FRC_STAT= 1<<6,
> 	EOP	= 1<<7,
> };
> 
>@@ -1769,9 +1909,13 @@
> 	OP_ADDR64VLAN	= OP_ADDR64 | OP_VLAN,
> 	OP_LRGLEN	= 0x24,
> 	OP_LRGLENVLAN	= OP_LRGLEN | OP_VLAN,
>+	OP_MSS		= 0x28,
>+	OP_MSSVLAN	= OP_MSS | OP_VLAN,
>+
> 	OP_BUFFER	= 0x40,
> 	OP_PACKET	= 0x41,
> 	OP_LARGESEND	= 0x43,
>+	OP_LSOV2	= 0x45,
> 
> /* YUKON-2 STATUS opcodes defines */
> 	OP_RXSTAT	= 0x60,
>@@ -1782,23 +1926,24 @@
> 	OP_RXTIMEVLAN	= OP_RXTIMESTAMP | OP_RXVLAN,
> 	OP_RSS_HASH	= 0x65,
> 	OP_TXINDEXLE	= 0x68,
>+	OP_MACSEC	= 0x6c,
>+	OP_PUTIDX	= 0x70,
> };
> 
>-/* Yukon 2 hardware interface
>- * Not tested on big endian
>- */
>+enum status_css {
>+	CSS_TCPUDPCSOK	= 1<<7,	/* TCP / UDP checksum is ok */
>+	CSS_ISUDP	= 1<<6, /* packet is a UDP packet */
>+	CSS_ISTCP	= 1<<5, /* packet is a TCP packet */
>+	CSS_ISIPFRAG	= 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
>+	CSS_ISIPV6	= 1<<3, /* packet is a IPv6 packet */
>+	CSS_IPV4CSUMOK	= 1<<2, /* IP v4: TCP header checksum is ok */
>+	CSS_ISIPV4	= 1<<1, /* packet is a IPv4 packet */
>+	CSS_LINK_BIT	= 1<<0, /* port number (legacy) */
>+};
>+
>+/* Yukon 2 hardware interface */
> struct sky2_tx_le {
>-	union {
>-		__le32	addr;
>-		struct {
>-			__le16	offset;
>-			__le16	start;
>-		} csum  __attribute((packed));
>-		struct {
>-			__le16	size;
>-			__le16	rsvd;
>-		} tso  __attribute((packed));
>-	} tx;
>+	__le32	addr;
> 	__le16	length;	/* also vlan tag or checksum start */
> 	u8	ctrl;
> 	u8	opcode;
>@@ -1814,19 +1959,28 @@
> struct sky2_status_le {
> 	__le32	status;	/* also checksum */
> 	__le16	length;	/* also vlan tag */
>-	u8	link;
>+	u8	css;
> 	u8	opcode;
> } __attribute((packed));
> 
> struct tx_ring_info {
> 	struct sk_buff	*skb;
> 	DECLARE_PCI_UNMAP_ADDR(mapaddr);
>-	u16		idx;
>+	DECLARE_PCI_UNMAP_ADDR(maplen);
> };
> 
>-struct ring_info {
>+struct rx_ring_info {
> 	struct sk_buff	*skb;
>-	dma_addr_t	mapaddr;
>+	dma_addr_t	data_addr;
>+	DECLARE_PCI_UNMAP_ADDR(data_size);
>+	dma_addr_t	frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
>+};
>+
>+enum flow_control {
>+	FC_NONE	= 0,
>+	FC_TX	= 1,
>+	FC_RX	= 2,
>+	FC_BOTH	= 3,
> };
> 
> struct sky2_port {
>@@ -1836,63 +1990,89 @@
> 	u32		     msg_enable;
> 	spinlock_t	     phy_lock;
> 
>-	spinlock_t	     tx_lock  ____cacheline_aligned_in_smp;
> 	struct tx_ring_info  *tx_ring;
> 	struct sky2_tx_le    *tx_le;
> 	u16		     tx_cons;		/* next le to check */
> 	u16		     tx_prod;		/* next le to use */
>-	u32		     tx_addr64;
>+	u16		     tx_next;		/* debug only */
>+
> 	u16		     tx_pending;
> 	u16		     tx_last_mss;
>+	u32		     tx_tcpsum;
> 
>-	struct ring_info     *rx_ring ____cacheline_aligned_in_smp;
>+	struct rx_ring_info  *rx_ring ____cacheline_aligned_in_smp;
> 	struct sky2_rx_le    *rx_le;
>-	u32		     rx_addr64;
>+
> 	u16		     rx_next;		/* next re to check */
> 	u16		     rx_put;		/* next le index to use */
> 	u16		     rx_pending;
>-	u16		     rx_bufsize;
>+	u16		     rx_data_size;
>+	u16		     rx_nfrags;
>+
> #ifdef SKY2_VLAN_TAG_USED
> 	u16		     rx_tag;
> 	struct vlan_group    *vlgrp;
> #endif
>+	struct {
>+		unsigned long last;
>+		u32	mac_rp;
>+		u8	mac_lev;
>+		u8	fifo_rp;
>+		u8	fifo_lev;
>+	} check;
>+
> 
> 	dma_addr_t	     rx_le_map;
> 	dma_addr_t	     tx_le_map;
>-	u32		     advertising;	/* ADVERTISED_ bits */
>+	u16		     advertising;	/* ADVERTISED_ bits */
> 	u16		     speed;	/* SPEED_1000, SPEED_100, ... */
> 	u8		     autoneg;	/* AUTONEG_ENABLE, AUTONEG_DISABLE */
> 	u8		     duplex;	/* DUPLEX_HALF, DUPLEX_FULL */
>-	u8		     rx_pause;
>-	u8		     tx_pause;
> 	u8		     rx_csum;
>+	u8		     wol;
>+ 	enum flow_control    flow_mode;
>+ 	enum flow_control    flow_status;
> 
> 	struct net_device_stats net_stats;
>-
>+#ifdef CONFIG_SKY2_DEBUG
>+	struct dentry	     *debugfs;
>+#endif
> };
> 
> struct sky2_hw {
> 	void __iomem  	     *regs;
> 	struct pci_dev	     *pdev;
> 	struct net_device    *dev[2];
>+	unsigned long	     flags;
>+#define SKY2_HW_USE_MSI		0x00000001
>+#define SKY2_HW_FIBRE_PHY	0x00000002
>+#define SKY2_HW_GIGABIT		0x00000004
>+#define SKY2_HW_NEWER_PHY	0x00000008
>+#define SKY2_HW_RAM_BUFFER	0x00000010
>+#define SKY2_HW_NEW_LE		0x00000020	/* new LSOv2 format */
>+#define SKY2_HW_AUTO_TX_SUM	0x00000040	/* new IP decode for Tx */
>+#define SKY2_HW_ADV_POWER_CTL	0x00000080	/* additional PHY power regs */
> 
>-	int		     pm_cap;
> 	u8	     	     chip_id;
> 	u8		     chip_rev;
>-	u8		     copper;
>+	u8		     pmd_type;
> 	u8		     ports;
> 
> 	struct sky2_status_le *st_le;
> 	u32		     st_idx;
> 	dma_addr_t   	     st_dma;
> 
>-	struct timer_list    idle_timer;
>-	int		     msi_detected;
>+	struct timer_list    watchdog_timer;
>+	struct work_struct   restart_work;
> 	wait_queue_head_t    msi_wait;
>-
> 	u32		     pci_cfg_state[64 / sizeof(u32)];
> };
> 
>+static inline int sky2_is_copper(const struct sky2_hw *hw)
>+{
>+	return !(hw->flags & SKY2_HW_FIBRE_PHY);
>+}
>+
> /* Register accessor for memory mapped device */
> static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
> {
>--- linux-2.6.9/drivers/net/sky2.c.orig	2008-04-16 09:50:40.000000000 -0400
>+++ linux-2.6.9/drivers/net/sky2.c	2008-04-16 09:58:31.000000000 -0400
>@@ -10,8 +10,7 @@
>  *
>  * This program is free software; you can redistribute it and/or modify
>  * it under the terms of the GNU General Public License as published by
>- * the Free Software Foundation; either version 2 of the License, or
>- * (at your option) any later version.
>+ * the Free Software Foundation; either version 2 of the License.
>  *
>  * This program is distributed in the hope that it will be useful,
>  * but WITHOUT ANY WARRANTY; without even the implied warranty of
>@@ -33,12 +32,14 @@
> #include <linux/ethtool.h>
> #include <linux/pci.h>
> #include <linux/ip.h>
>+#include <net/ip.h>
> #include <linux/tcp.h>
> #include <linux/in.h>
> #include <linux/delay.h>
> #include <linux/workqueue.h>
> #include <linux/if_vlan.h>
> #include <linux/prefetch.h>
>+#include <linux/debugfs.h>
> #include <linux/mii.h>
> 
> #include <asm/irq.h>
>@@ -46,27 +47,23 @@
> #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
> #define SKY2_VLAN_TAG_USED 1
> #endif
>-
> #include "sky2_compat.h"
> #include "sky2.h"
> 
> #define DRV_NAME		"sky2"
>-#define DRV_VERSION		"1.6"
>+#define DRV_VERSION		"1.21"
> #define PFX			DRV_NAME " "
> 
> /*
>  * The Yukon II chipset takes 64 bit command blocks (called list elements)
>  * that are organized into three (receive, transmit, status) different rings
>- * similar to Tigon3. A transmit can require several elements;
>- * a receive requires one (or two if using 64 bit dma).
>+ * similar to Tigon3.
>  */
> 
>-#define RX_LE_SIZE	    	512
>+#define RX_LE_SIZE	    	1024
> #define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
>-#define RX_MAX_PENDING		(RX_LE_SIZE/2 - 2)
>+#define RX_MAX_PENDING		(RX_LE_SIZE/6 - 2)
> #define RX_DEF_PENDING		RX_MAX_PENDING
>-#define RX_SKB_ALIGN		8
>-#define RX_BUF_WRITE		16
> 
> #define TX_RING_SIZE		512
> #define TX_DEF_PENDING		(TX_RING_SIZE - 1)
>@@ -75,11 +72,13 @@
> 
> #define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
> #define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))
>-#define ETH_JUMBO_MTU		9000
> #define TX_WATCHDOG		(5 * HZ)
> #define NAPI_WEIGHT		64
> #define PHY_RETRIES		1000
> 
>+#define SKY2_EEPROM_MAGIC	0x9955aabb
>+
>+
> #define RING_NEXT(x,s)	(((x)+1) & ((s)-1))
> 
> static const u32 default_msg =
>@@ -91,7 +90,7 @@
> module_param(debug, int, 0);
> MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
> 
>-static int copybreak __read_mostly = 256;
>+static int copybreak __read_mostly = 128;
> module_param(copybreak, int, 0);
> MODULE_PARM_DESC(copybreak, "Receive copy threshold");
> 
>@@ -99,34 +98,44 @@
> module_param(disable_msi, int, 0);
> MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
> 
>-static int idle_timeout = 100;
>-module_param(idle_timeout, int, 0);
>-MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
>-
> static const struct pci_device_id sky2_id_table[] = {
>-	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
>+	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
> 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },	/* DGE-560T */
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
>-	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
>+	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, 	/* DGE-550SX */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) },	/* DGE-560SX */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) },	/* DGE-550T */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
>+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
> 	{ 0 }
> };
> 
>@@ -141,12 +150,15 @@
> static const char *yukon2_name[] = {
> 	"XL",		/* 0xb3 */
> 	"EC Ultra", 	/* 0xb4 */
>-	"UNKNOWN",	/* 0xb5 */
>+	"Extreme",	/* 0xb5 */
> 	"EC",		/* 0xb6 */
> 	"FE",		/* 0xb7 */
>+	"FE+",		/* 0xb8 */
> };
> 
>-/* Access to external PHY */
>+static void sky2_set_multicast(struct net_device *dev);
>+
>+/* Access to PHY via serial interconnect */
> static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
> {
> 	int i;
>@@ -156,13 +168,22 @@
> 		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
> 
> 	for (i = 0; i < PHY_RETRIES; i++) {
>-		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
>+		u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
>+		if (ctrl == 0xffff)
>+			goto io_error;
>+
>+		if (!(ctrl & GM_SMI_CT_BUSY))
> 			return 0;
>-		udelay(1);
>+
>+		udelay(10);
> 	}
> 
>-	printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
>+	dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
> 	return -ETIMEDOUT;
>+
>+io_error:
>+	dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
>+	return -EIO;
> }
> 
> static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
>@@ -173,127 +194,101 @@
> 		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
> 
> 	for (i = 0; i < PHY_RETRIES; i++) {
>-		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
>+		u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
>+		if (ctrl == 0xffff)
>+			goto io_error;
>+
>+		if (ctrl & GM_SMI_CT_RD_VAL) {
> 			*val = gma_read16(hw, port, GM_SMI_DATA);
> 			return 0;
> 		}
> 
>-		udelay(1);
>+		udelay(10);
> 	}
> 
>+	dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
> 	return -ETIMEDOUT;
>+io_error:
>+	dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
>+	return -EIO;
> }
> 
>-static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
>+static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
> {
> 	u16 v;
>-
>-	if (__gm_phy_read(hw, port, reg, &v) != 0)
>-		printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
>+	__gm_phy_read(hw, port, reg, &v);
> 	return v;
> }
> 
>-static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
>-{
>-	u16 power_control;
>-	u32 reg1;
>-	int vaux;
> 
>-	pr_debug("sky2_set_power_state %d\n", state);
>-	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
>+static void sky2_power_on(struct sky2_hw *hw)
>+{
>+	/* switch power to VCC (WA for VAUX problem) */
>+	sky2_write8(hw, B0_POWER_CTRL,
>+		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
>+
>+	/* disable Core Clock Division, */
>+	sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
>+
>+	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>+		/* enable bits are inverted */
>+		sky2_write8(hw, B2_Y2_CLK_GATE,
>+			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
>+			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
>+			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
>+	else
>+		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
> 
>-	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
>-	vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
>-		(power_control & PCI_PM_CAP_PME_D3cold);
>-
>-	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
>-
>-	power_control |= PCI_PM_CTRL_PME_STATUS;
>-	power_control &= ~(PCI_PM_CTRL_STATE_MASK);
>-
>-	switch (state) {
>-	case PCI_D0:
>-		/* switch power to VCC (WA for VAUX problem) */
>-		sky2_write8(hw, B0_POWER_CTRL,
>-			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
>+	if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
>+		u32 reg;
> 
>-		/* disable Core Clock Division, */
>-		sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
>+		sky2_pci_write32(hw, PCI_DEV_REG3, 0);
> 
>-		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>-			/* enable bits are inverted */
>-			sky2_write8(hw, B2_Y2_CLK_GATE,
>-				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
>-				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
>-				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
>-		else
>-			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
>+		reg = sky2_pci_read32(hw, PCI_DEV_REG4);
>+		/* set all bits to 0 except bits 15..12 and 8 */
>+		reg &= P_ASPM_CONTROL_MSK;
>+		sky2_pci_write32(hw, PCI_DEV_REG4, reg);
> 
>-		/* Turn off phy power saving */
>-		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
>-		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
>-
>-		/* looks like this XL is back asswards .. */
>-		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
>-			reg1 |= PCI_Y2_PHY1_COMA;
>-			if (hw->ports > 1)
>-				reg1 |= PCI_Y2_PHY2_COMA;
>-		}
>-		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
>-		udelay(100);
>-
>-		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
>-			sky2_pci_write32(hw, PCI_DEV_REG3, 0);
>-			reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
>-			reg1 &= P_ASPM_CONTROL_MSK;
>-			sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
>-			sky2_pci_write32(hw, PCI_DEV_REG5, 0);
>-		}
>+		reg = sky2_pci_read32(hw, PCI_DEV_REG5);
>+		/* set all bits to 0 except bits 28 & 27 */
>+		reg &= P_CTL_TIM_VMAIN_AV_MSK;
>+		sky2_pci_write32(hw, PCI_DEV_REG5, reg);
> 
>-		break;
>+		sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
> 
>-	case PCI_D3hot:
>-	case PCI_D3cold:
>-		/* Turn on phy power saving */
>-		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
>-		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>-			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
>-		else
>-			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
>-		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
>-		udelay(100);
>+		/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
>+		reg = sky2_read32(hw, B2_GP_IO);
>+		reg |= GLB_GPIO_STAT_RACE_DIS;
>+		sky2_write32(hw, B2_GP_IO, reg);
> 
>-		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>-			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
>-		else
>-			/* enable bits are inverted */
>-			sky2_write8(hw, B2_Y2_CLK_GATE,
>-				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
>-				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
>-				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
>-
>-		/* switch power to VAUX */
>-		if (vaux && state != PCI_D3cold)
>-			sky2_write8(hw, B0_POWER_CTRL,
>-				    (PC_VAUX_ENA | PC_VCC_ENA |
>-				     PC_VAUX_ON | PC_VCC_OFF));
>-		break;
>-	default:
>-		printk(KERN_ERR PFX "Unknown power state %d\n", state);
>+		sky2_read32(hw, B2_GP_IO);
> 	}
>+}
> 
>-	sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
>-	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
>+static void sky2_power_aux(struct sky2_hw *hw)
>+{
>+	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>+		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
>+	else
>+		/* enable bits are inverted */
>+		sky2_write8(hw, B2_Y2_CLK_GATE,
>+			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
>+			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
>+			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
>+
>+	/* switch power to VAUX */
>+	if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
>+		sky2_write8(hw, B0_POWER_CTRL,
>+			    (PC_VAUX_ENA | PC_VCC_ENA |
>+			     PC_VAUX_ON | PC_VCC_OFF));
> }
> 
>-static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
>+static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
> {
> 	u16 reg;
> 
> 	/* disable all GMAC IRQ's */
> 	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
>-	/* disable PHY IRQs */
>-	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
> 
> 	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
> 	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
>@@ -305,32 +300,70 @@
> 	gma_write16(hw, port, GM_RX_CTRL, reg);
> }
> 
>+/* flow control to advertise bits */
>+static const u16 copper_fc_adv[] = {
>+	[FC_NONE]	= 0,
>+	[FC_TX]		= PHY_M_AN_ASP,
>+	[FC_RX]		= PHY_M_AN_PC,
>+	[FC_BOTH]	= PHY_M_AN_PC | PHY_M_AN_ASP,
>+};
>+
>+/* flow control to advertise bits when using 1000BaseX */
>+static const u16 fiber_fc_adv[] = {
>+	[FC_NONE] = PHY_M_P_NO_PAUSE_X,
>+	[FC_TX]   = PHY_M_P_ASYM_MD_X,
>+	[FC_RX]	  = PHY_M_P_SYM_MD_X,
>+	[FC_BOTH] = PHY_M_P_BOTH_MD_X,
>+};
>+
>+/* flow control to GMA disable bits */
>+static const u16 gm_fc_disable[] = {
>+	[FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
>+	[FC_TX]	  = GM_GPCR_FC_RX_DIS,
>+	[FC_RX]	  = GM_GPCR_FC_TX_DIS,
>+	[FC_BOTH] = 0,
>+};
>+
>+
> static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
> {
> 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
>-	u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
>+	u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
> 
> 	if (sky2->autoneg == AUTONEG_ENABLE &&
>-	    !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
>+	    !(hw->flags & SKY2_HW_NEWER_PHY)) {
> 		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
> 
> 		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
> 			   PHY_M_EC_MAC_S_MSK);
> 		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
> 
>+		/* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
> 		if (hw->chip_id == CHIP_ID_YUKON_EC)
>+			/* set downshift counter to 3x and enable downshift */
> 			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
> 		else
>-			ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
>+			/* set master & slave downshift counter to 1x */
>+			ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
> 
> 		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
> 	}
> 
> 	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>-	if (hw->copper) {
>-		if (hw->chip_id == CHIP_ID_YUKON_FE) {
>+	if (sky2_is_copper(hw)) {
>+		if (!(hw->flags & SKY2_HW_GIGABIT)) {
> 			/* enable automatic crossover */
> 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
>+
>+			if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+			    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
>+				u16 spec;
>+
>+				/* Enable Class A driver for FE+ A0 */
>+				spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
>+				spec |= PHY_M_FESC_SEL_CL_A;
>+				gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
>+			}
> 		} else {
> 			/* disable energy detect */
> 			ctrl &= ~PHY_M_PC_EN_DET_MSK;
>@@ -338,48 +371,54 @@
> 			/* enable automatic crossover */
> 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
> 
>-			if (sky2->autoneg == AUTONEG_ENABLE &&
>-			    (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
>+			/* downshift on PHY 88E1112 and 88E1149 is changed */
>+			if (sky2->autoneg == AUTONEG_ENABLE
>+			    && (hw->flags & SKY2_HW_NEWER_PHY)) {
>+				/* set downshift counter to 3x and enable downshift */
> 				ctrl &= ~PHY_M_PC_DSC_MSK;
> 				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
> 			}
> 		}
>-		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
> 	} else {
> 		/* workaround for deviation #4.88 (CRC errors) */
> 		/* disable Automatic Crossover */
> 
> 		ctrl &= ~PHY_M_PC_MDIX_MSK;
>-		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
>+	}
> 
>-		if (hw->chip_id == CHIP_ID_YUKON_XL) {
>-			/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
>-			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
>-			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>-			ctrl &= ~PHY_M_MAC_MD_MSK;
>-			ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
>-			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
>+	gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
>+
>+	/* special setup for PHY 88E1112 Fiber */
>+	if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
>+		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
>+
>+		/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
>+		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
>+		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>+		ctrl &= ~PHY_M_MAC_MD_MSK;
>+		ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
>+		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
> 
>+		if (hw->pmd_type  == 'P') {
> 			/* select page 1 to access Fiber registers */
> 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
>-		}
>-	}
> 
>-	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
>-	if (sky2->autoneg == AUTONEG_DISABLE)
>-		ctrl &= ~PHY_CT_ANE;
>-	else
>-		ctrl |= PHY_CT_ANE;
>+			/* for SFP-module set SIGDET polarity to low */
>+			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>+			ctrl |= PHY_M_FIB_SIGD_POL;
>+			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
>+		}
> 
>-	ctrl |= PHY_CT_RESET;
>-	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
>+		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>+	}
> 
>-	ctrl = 0;
>+	ctrl = PHY_CT_RESET;
> 	ct1000 = 0;
> 	adv = PHY_AN_CSMA;
>+	reg = 0;
> 
> 	if (sky2->autoneg == AUTONEG_ENABLE) {
>-		if (hw->copper) {
>+		if (sky2_is_copper(hw)) {
> 			if (sky2->advertising & ADVERTISED_1000baseT_Full)
> 				ct1000 |= PHY_M_1000C_AFD;
> 			if (sky2->advertising & ADVERTISED_1000baseT_Half)
>@@ -392,16 +431,16 @@
> 				adv |= PHY_M_AN_10_FD;
> 			if (sky2->advertising & ADVERTISED_10baseT_Half)
> 				adv |= PHY_M_AN_10_HD;
>-		} else		/* special defines for FIBER (88E1011S only) */
>-			adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
> 
>-		/* Set Flow-control capabilities */
>-		if (sky2->tx_pause && sky2->rx_pause)
>-			adv |= PHY_AN_PAUSE_CAP;	/* symmetric */
>-		else if (sky2->rx_pause && !sky2->tx_pause)
>-			adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
>-		else if (!sky2->rx_pause && sky2->tx_pause)
>-			adv |= PHY_AN_PAUSE_ASYM;	/* local */
>+			adv |= copper_fc_adv[sky2->flow_mode];
>+		} else {	/* special defines for FIBER (88E1040S only) */
>+			if (sky2->advertising & ADVERTISED_1000baseT_Full)
>+				adv |= PHY_M_AN_1000X_AFD;
>+			if (sky2->advertising & ADVERTISED_1000baseT_Half)
>+				adv |= PHY_M_AN_1000X_AHD;
>+
>+			adv |= fiber_fc_adv[sky2->flow_mode];
>+		}
> 
> 		/* Restart Auto-negotiation */
> 		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
>@@ -409,22 +448,39 @@
> 		/* forced speed/duplex settings */
> 		ct1000 = PHY_M_1000C_MSE;
> 
>-		if (sky2->duplex == DUPLEX_FULL)
>-			ctrl |= PHY_CT_DUP_MD;
>+		/* Disable auto update for duplex flow control and speed */
>+		reg |= GM_GPCR_AU_ALL_DIS;
> 
> 		switch (sky2->speed) {
> 		case SPEED_1000:
> 			ctrl |= PHY_CT_SP1000;
>+			reg |= GM_GPCR_SPEED_1000;
> 			break;
> 		case SPEED_100:
> 			ctrl |= PHY_CT_SP100;
>+			reg |= GM_GPCR_SPEED_100;
> 			break;
> 		}
> 
>-		ctrl |= PHY_CT_RESET;
>+		if (sky2->duplex == DUPLEX_FULL) {
>+			reg |= GM_GPCR_DUP_FULL;
>+			ctrl |= PHY_CT_DUP_MD;
>+		} else if (sky2->speed < SPEED_1000)
>+			sky2->flow_mode = FC_NONE;
>+
>+
>+ 		reg |= gm_fc_disable[sky2->flow_mode];
>+
>+		/* Forward pause packets to GMAC? */
>+		if (sky2->flow_mode & FC_RX)
>+			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
>+		else
>+			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
> 	}
> 
>-	if (hw->chip_id != CHIP_ID_YUKON_FE)
>+	gma_write16(hw, port, GM_GP_CTRL, reg);
>+
>+	if (hw->flags & SKY2_HW_GIGABIT)
> 		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
> 
> 	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
>@@ -448,6 +504,23 @@
> 		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
> 		break;
> 
>+	case CHIP_ID_YUKON_FE_P:
>+		/* Enable Link Partner Next Page */
>+		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>+		ctrl |= PHY_M_PC_ENA_LIP_NP;
>+
>+		/* disable Energy Detect and enable scrambler */
>+		ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
>+		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
>+
>+		/* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
>+		ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
>+			PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
>+			PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
>+
>+		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
>+		break;
>+
> 	case CHIP_ID_YUKON_XL:
> 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
> 
>@@ -473,7 +546,10 @@
> 		/* restore page register */
> 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
> 		break;
>+
> 	case CHIP_ID_YUKON_EC_U:
>+	case CHIP_ID_YUKON_EX:
>+	case CHIP_ID_YUKON_SUPR:
> 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
> 
> 		/* select page 3 to access LED control register */
>@@ -496,13 +572,14 @@
> 	default:
> 		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
> 		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
>+
> 		/* turn off the Rx LED (LED_RX) */
> 		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
> 	}
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
>+	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
>+	    hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
> 		/* apply fixes in PHY AFE */
>-		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
> 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
> 
> 		/* increase differential signal amplitude in 10BASE-T */
>@@ -514,8 +591,14 @@
> 		gm_phy_write(hw, port, 0x17, 0x2002);
> 
> 		/* set page register to 0 */
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>-	} else {
>+		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
>+	} else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+		   hw->chip_rev == CHIP_REV_YU_FE2_A0) {
>+		/* apply workaround for integrated resistors calibration */
>+		gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
>+		gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
>+	} else if (hw->chip_id != CHIP_ID_YUKON_EX) {
>+		/* no effect on Yukon-XL */
> 		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
> 
> 		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
>@@ -527,6 +610,7 @@
> 			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
> 
> 	}
>+
> 	/* Enable phy interrupt on auto-negotiation complete (or link up) */
> 	if (sky2->autoneg == AUTONEG_ENABLE)
> 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
>@@ -534,6 +618,30 @@
> 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
> }
> 
>+static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
>+{
>+	u32 reg1;
>+	static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
>+	static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
>+
>+	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
>+	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
>+	/* Turn on/off phy power saving */
>+	if (onoff)
>+		reg1 &= ~phy_power[port];
>+	else
>+		reg1 |= phy_power[port];
>+
>+	if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
>+		reg1 |= coma_mode[port];
>+
>+	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
>+	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
>+	sky2_pci_read32(hw, PCI_DEV_REG1);
>+
>+	udelay(100);
>+}
>+
> /* Force a renegotiation */
> static void sky2_phy_reinit(struct sky2_port *sky2)
> {
>@@ -542,15 +650,115 @@
> 	spin_unlock_bh(&sky2->phy_lock);
> }
> 
>+/* Put device in state to listen for Wake On Lan */
>+static void sky2_wol_init(struct sky2_port *sky2)
>+{
>+	struct sky2_hw *hw = sky2->hw;
>+	unsigned port = sky2->port;
>+	enum flow_control save_mode;
>+	u16 ctrl;
>+	u32 reg1;
>+
>+	/* Bring hardware out of reset */
>+	sky2_write16(hw, B0_CTST, CS_RST_CLR);
>+	sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
>+
>+	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
>+	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
>+
>+	/* Force to 10/100
>+	 * sky2_reset will re-enable on resume
>+	 */
>+	save_mode = sky2->flow_mode;
>+	ctrl = sky2->advertising;
>+
>+	sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
>+	sky2->flow_mode = FC_NONE;
>+	sky2_phy_power(hw, port, 1);
>+	sky2_phy_reinit(sky2);
>+
>+	sky2->flow_mode = save_mode;
>+	sky2->advertising = ctrl;
>+
>+	/* Set GMAC to no flow control and auto update for speed/duplex */
>+	gma_write16(hw, port, GM_GP_CTRL,
>+		    GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
>+		    GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
>+
>+	/* Set WOL address */
>+	memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
>+		    sky2->netdev->dev_addr, ETH_ALEN);
>+
>+	/* Turn on appropriate WOL control bits */
>+	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
>+	ctrl = 0;
>+	if (sky2->wol & WAKE_PHY)
>+		ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
>+	else
>+		ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
>+
>+	if (sky2->wol & WAKE_MAGIC)
>+		ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
>+	else
>+		ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
>+
>+	ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
>+	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
>+
>+	/* Turn on legacy PCI-Express PME mode */
>+	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
>+	reg1 |= PCI_Y2_PME_LEGACY;
>+	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
>+
>+	/* block receiver */
>+	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
>+
>+}
>+
>+static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
>+{
>+	struct net_device *dev = hw->dev[port];
>+
>+	if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
>+	      hw->chip_rev != CHIP_REV_YU_EX_A0) ||
>+	     hw->chip_id == CHIP_ID_YUKON_FE_P ||
>+	     hw->chip_id == CHIP_ID_YUKON_SUPR) {
>+		/* Yukon-Extreme B0 and further Extreme devices */
>+		/* enable Store & Forward mode for TX */
>+
>+		if (dev->mtu <= ETH_DATA_LEN)
>+			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
>+				     TX_JUMBO_DIS | TX_STFW_ENA);
>+
>+		else
>+			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
>+				     TX_JUMBO_ENA| TX_STFW_ENA);
>+	} else {
>+		if (dev->mtu <= ETH_DATA_LEN)
>+			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
>+		else {
>+			/* set Tx GMAC FIFO Almost Empty Threshold */
>+			sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
>+				     (ECU_JUMBO_WM << 16) | ECU_AE_THR);
>+
>+			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
>+
>+			/* Can't do offload because of lack of store/forward */
>+			dev->features &= ~(NETIF_F_TSO | NETIF_F_SG);
>+		}
>+	}
>+}
>+
> static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
> {
> 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
> 	u16 reg;
>+	u32 rx_reg;
> 	int i;
> 	const u8 *addr = hw->dev[port]->dev_addr;
> 
>-	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
>-	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
>+	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
>+	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
> 
> 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
> 
>@@ -566,49 +774,11 @@
> 			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
> 	}
> 
>-	if (sky2->autoneg == AUTONEG_DISABLE) {
>-		reg = gma_read16(hw, port, GM_GP_CTRL);
>-		reg |= GM_GPCR_AU_ALL_DIS;
>-		gma_write16(hw, port, GM_GP_CTRL, reg);
>-		gma_read16(hw, port, GM_GP_CTRL);
>-
>-		switch (sky2->speed) {
>-		case SPEED_1000:
>-			reg &= ~GM_GPCR_SPEED_100;
>-			reg |= GM_GPCR_SPEED_1000;
>-			break;
>-		case SPEED_100:
>-			reg &= ~GM_GPCR_SPEED_1000;
>-			reg |= GM_GPCR_SPEED_100;
>-			break;
>-		case SPEED_10:
>-			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
>-			break;
>-		}
>-
>-		if (sky2->duplex == DUPLEX_FULL)
>-			reg |= GM_GPCR_DUP_FULL;
>-
>-		/* turn off pause in 10/100mbps half duplex */
>-		else if (sky2->speed != SPEED_1000 &&
>-			 hw->chip_id != CHIP_ID_YUKON_EC_U)
>-			sky2->tx_pause = sky2->rx_pause = 0;
>-	} else
>-		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
>-
>-	if (!sky2->tx_pause && !sky2->rx_pause) {
>-		sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
>-		reg |=
>-		    GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
>-	} else if (sky2->tx_pause && !sky2->rx_pause) {
>-		/* disable Rx flow-control */
>-		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
>-	}
>-
>-	gma_write16(hw, port, GM_GP_CTRL, reg);
>-
> 	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
> 
>+	/* Enable Transmit FIFO Underrun */
>+	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
>+
> 	spin_lock_bh(&sky2->phy_lock);
> 	sky2_phy_init(hw, port);
> 	spin_unlock_bh(&sky2->phy_lock);
>@@ -660,44 +830,59 @@
> 
> 	/* Configure Rx MAC FIFO */
> 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
>-	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
>-		     GMF_OPER_ON | GMF_RX_F_FL_ON);
>+	rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
>+	if (hw->chip_id == CHIP_ID_YUKON_EX ||
>+	    hw->chip_id == CHIP_ID_YUKON_FE_P)
>+		rx_reg |= GMF_RX_OVER_ON;
> 
>-	/* Flush Rx MAC FIFO on any flow control or error */
>-	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
>+	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
> 
>-	/* Set threshold to 0xa (64 bytes)
>-	 *  ASF disabled so no need to do WA dev #4.30
>-	 */
>-	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
>+	if (hw->chip_id == CHIP_ID_YUKON_XL) {
>+		/* Hardware errata - clear flush mask */
>+		sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
>+	} else {
>+		/* Flush Rx MAC FIFO on any flow control or error */
>+		sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
>+	}
>+
>+	/* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug  */
>+	reg = RX_GMF_FL_THR_DEF + 1;
>+	/* Another magic mystery workaround from sk98lin */
>+	if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+	    hw->chip_rev == CHIP_REV_YU_FE2_A0)
>+		reg = 0x178;
>+	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
> 
> 	/* Configure Tx MAC FIFO */
> 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
> 	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
>+	/* On chips without ram buffer, pause is controled by MAC level */
>+	if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
> 		sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
> 		sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
>-		if (hw->dev[port]->mtu > ETH_DATA_LEN) {
>-			/* set Tx GMAC FIFO Almost Empty Threshold */
>-			sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
>-			/* Disable Store & Forward mode for TX */
>-			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
>-		}
>+
>+		sky2_set_tx_stfwd(hw, port);
> 	}
> 
>+	if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+	    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
>+		/* disable dynamic watermark */
>+		reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
>+		reg &= ~TX_DYN_WM_ENA;
>+		sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
>+	}
> }
> 
>-/* Assign Ram Buffer allocation.
>- * start and end are in units of 4k bytes
>- * ram registers are in units of 64bit words
>- */
>-static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
>+/* Assign Ram Buffer allocation to queue */
>+static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
> {
>-	u32 start, end;
>+	u32 end;
> 
>-	start = startk * 4096/8;
>-	end = (endk * 4096/8) - 1;
>+	/* convert from K bytes to qwords used for hw register */
>+	start *= 1024/8;
>+	space *= 1024/8;
>+	end = start + space - 1;
> 
> 	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
> 	sky2_write32(hw, RB_ADDR(q, RB_START), start);
>@@ -706,7 +891,6 @@
> 	sky2_write32(hw, RB_ADDR(q, RB_RP), start);
> 
> 	if (q == Q_R1 || q == Q_R2) {
>-		u32 space = (endk - startk) * 4096/8;
> 		u32 tp = space - space/4;
> 
> 		/* On receive queue's set the thresholds
>@@ -760,14 +944,37 @@
> 	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
> 
> 	sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
>+	le->ctrl = 0;
> 	return le;
> }
> 
>+static void tx_init(struct sky2_port *sky2)
>+{
>+	struct sky2_tx_le *le;
>+
>+	sky2->tx_prod = sky2->tx_cons = 0;
>+	sky2->tx_tcpsum = 0;
>+	sky2->tx_last_mss = 0;
>+
>+	le = get_tx_le(sky2);
>+	le->addr = 0;
>+	le->opcode = OP_ADDR64 | HW_OWNER;
>+}
>+
>+static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
>+					    struct sky2_tx_le *le)
>+{
>+	return sky2->tx_ring + (le - sky2->tx_le);
>+}
>+
> /* Update chip's next pointer */
> static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
> {
>+	/* Make sure write' to descriptors are complete before we tell hardware */
> 	wmb();
> 	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
>+
>+	/* Synchronize I/O on since next processor may write to tail */
> 	mmiowb();
> }
> 
>@@ -776,37 +983,77 @@
> {
> 	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
> 	sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
>+	le->ctrl = 0;
> 	return le;
> }
> 
> /* Return high part of DMA address (could be 32 or 64 bit) */
> static inline u32 high32(dma_addr_t a)
> {
>-	return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
>+        return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
> }
> 
>-/* Build description to hardware about buffer */
>-static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
>+/* Build description to hardware for one receive segment */
>+static void sky2_rx_add(struct sky2_port *sky2,  u8 op,
>+			dma_addr_t map, unsigned len)
> {
> 	struct sky2_rx_le *le;
>-	u32 hi = high32(map);
>-	u16 len = sky2->rx_bufsize;
> 
>-	if (sky2->rx_addr64 != hi) {
>+	if (sizeof(dma_addr_t) > sizeof(u32)) {
> 		le = sky2_next_rx(sky2);
>-		le->addr = cpu_to_le32(hi);
>-		le->ctrl = 0;
>+		le->addr = cpu_to_le32((u32)(map));
> 		le->opcode = OP_ADDR64 | HW_OWNER;
>-		sky2->rx_addr64 = high32(map + len);
> 	}
> 
> 	le = sky2_next_rx(sky2);
> 	le->addr = cpu_to_le32((u32) map);
> 	le->length = cpu_to_le16(len);
>-	le->ctrl = 0;
>-	le->opcode = OP_PACKET | HW_OWNER;
>+	le->opcode = op | HW_OWNER;
>+}
>+
>+/* Build description to hardware for one possibly fragmented skb */
>+static void sky2_rx_submit(struct sky2_port *sky2,
>+			   const struct rx_ring_info *re)
>+{
>+	int i;
>+
>+	sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
>+
>+	for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
>+		sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
>+}
>+
>+
>+static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
>+			    unsigned size)
>+{
>+	struct sk_buff *skb = re->skb;
>+	int i;
>+
>+	re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
>+	pci_unmap_len_set(re, data_size, size);
>+
>+	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
>+		re->frag_addr[i] = pci_map_page(pdev,
>+						skb_shinfo(skb)->frags[i].page,
>+						skb_shinfo(skb)->frags[i].page_offset,
>+						skb_shinfo(skb)->frags[i].size,
>+						PCI_DMA_FROMDEVICE);
> }
> 
>+static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
>+{
>+	struct sk_buff *skb = re->skb;
>+	int i;
>+
>+	pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
>+			 PCI_DMA_FROMDEVICE);
>+
>+	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
>+		pci_unmap_page(pdev, re->frag_addr[i],
>+			       skb_shinfo(skb)->frags[i].size,
>+			       PCI_DMA_FROMDEVICE);
>+}
> 
> /* Tell chip where to start receive checksum.
>  * Actually has two checksums, but set both same to avoid possible byte
>@@ -814,17 +1061,15 @@
>  */
> static void rx_set_checksum(struct sky2_port *sky2)
> {
>-	struct sky2_rx_le *le;
>+	struct sky2_rx_le *le = sky2_next_rx(sky2);
> 
>-	le = sky2_next_rx(sky2);
>-	le->addr = (ETH_HLEN << 16) | ETH_HLEN;
>+	le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
> 	le->ctrl = 0;
> 	le->opcode = OP_TCPSTART | HW_OWNER;
> 
> 	sky2_write32(sky2->hw,
> 		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
> 		     sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
>-
> }
> 
> /*
>@@ -858,6 +1103,7 @@
> 
> 	/* reset the Rx prefetch unit */
> 	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
>+	mmiowb();
> }
> 
> /* Clean out receive buffer area, assumes receiver hardware stopped */
>@@ -867,12 +1113,10 @@
> 
> 	memset(sky2->rx_le, 0, RX_LE_BYTES);
> 	for (i = 0; i < sky2->rx_pending; i++) {
>-		struct ring_info *re = sky2->rx_ring + i;
>+		struct rx_ring_info *re = sky2->rx_ring + i;
> 
> 		if (re->skb) {
>-			pci_unmap_single(sky2->hw->pdev,
>-					 re->mapaddr, sky2->rx_bufsize,
>-					 PCI_DMA_FROMDEVICE);
>+			sky2_rx_unmap_skb(sky2->hw->pdev, re);
> 			kfree_skb(re->skb);
> 			re->skb = NULL;
> 		}
>@@ -926,95 +1170,151 @@
> 	struct sky2_hw *hw = sky2->hw;
> 	u16 port = sky2->port;
> 
>-	spin_lock_bh(&sky2->tx_lock);
>+	netif_tx_lock_bh(dev);
>+	netif_poll_disable(sky2->hw->dev[0]);
> 
>-	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
>-	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
> 	sky2->vlgrp = grp;
>+	if (grp) {
>+		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
>+			     RX_VLAN_STRIP_ON);
>+		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
>+			     TX_VLAN_TAG_ON);
>+	} else {
>+		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
>+			     RX_VLAN_STRIP_OFF);
>+		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
>+			     TX_VLAN_TAG_OFF);
>+	}
> 
>-	spin_unlock_bh(&sky2->tx_lock);
>-}
>-
>-static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
>-{
>-	struct sky2_port *sky2 = netdev_priv(dev);
>-	struct sky2_hw *hw = sky2->hw;
>-	u16 port = sky2->port;
>-
>-	spin_lock_bh(&sky2->tx_lock);
>-
>-	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
>-	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
>-	if (sky2->vlgrp)
>-		sky2->vlgrp->vlan_devices[vid] = NULL;
>-
>-	spin_unlock_bh(&sky2->tx_lock);
>+	sky2_read32(hw, B0_Y2_SP_LISR);
>+	netif_poll_enable(hw->dev[0]);
>+	netif_tx_unlock_bh(dev);
> }
> #endif
> 
> /*
>- * It appears the hardware has a bug in the FIFO logic that
>- * cause it to hang if the FIFO gets overrun and the receive buffer
>- * is not aligned. ALso alloc_skb() won't align properly if slab
>- * debugging is enabled.
>+ * Allocate an skb for receiving. If the MTU is large enough
>+ * make the skb non-linear with a fragment list of pages.
>  */
>-static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
>+static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
> {
> 	struct sk_buff *skb;
>+	int i;
> 
>-	skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
>-	if (likely(skb)) {
>-		unsigned long p	= (unsigned long) skb->data;
>-		skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
>+	if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
>+		unsigned char *start;
>+		/*
>+		 * Workaround for a bug in FIFO that cause hang
>+		 * if the FIFO if the receive buffer is not 64 byte aligned.
>+		 * The buffer returned from netdev_alloc_skb is
>+		 * aligned except if slab debugging is enabled.
>+		 */
>+		skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
>+		if (!skb)
>+			goto nomem;
>+		start = PTR_ALIGN(skb->data, 8);
>+		skb_reserve(skb, start - skb->data);
>+	} else {
>+		skb = netdev_alloc_skb(sky2->netdev,
>+				       sky2->rx_data_size + NET_IP_ALIGN);
>+		if (!skb)
>+			goto nomem;
>+		skb_reserve(skb, NET_IP_ALIGN);
>+	}
>+
>+	for (i = 0; i < sky2->rx_nfrags; i++) {
>+		struct page *page = alloc_page(GFP_ATOMIC);
>+
>+		if (!page)
>+			goto free_partial;
>+		skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
> 	}
> 
> 	return skb;
>+free_partial:
>+	kfree_skb(skb);
>+nomem:
>+	return NULL;
>+}
>+
>+static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
>+{
>+	sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
> }
> 
> /*
>  * Allocate and setup receiver buffer pool.
>- * In case of 64 bit dma, there are 2X as many list elements
>- * available as ring entries
>- * and need to reserve one list element so we don't wrap around.
>+ * Normal case this ends up creating one list element for skb
>+ * in the receive ring. Worst case if using large MTU and each
>+ * allocation falls on a different 64 bit region, that results
>+ * in 6 list elements per ring entry.
>+ * One element is used for checksum enable/disable, and one
>+ * extra to avoid wrap.
>  */
> static int sky2_rx_start(struct sky2_port *sky2)
> {
> 	struct sky2_hw *hw = sky2->hw;
>+	struct rx_ring_info *re;
> 	unsigned rxq = rxqaddr[sky2->port];
>-	int i;
>-	unsigned thresh;
>+	unsigned i, size, thresh;
> 
> 	sky2->rx_put = sky2->rx_next = 0;
> 	sky2_qset(hw, rxq);
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
>-		/* MAC Rx RAM Read is controlled by hardware */
>-		sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
>-	}
>+	/* On PCI express lowering the watermark gives better performance */
>+	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
>+		sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
>+
>+	/* These chips have no ram buffer?
>+	 * MAC Rx RAM Read is controlled by hardware */
>+	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
>+	    (hw->chip_rev == CHIP_REV_YU_EC_U_A1
>+	     || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
>+		sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
> 
> 	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
> 
>-	rx_set_checksum(sky2);
>+	if (!(hw->flags & SKY2_HW_NEW_LE))
>+		rx_set_checksum(sky2);
>+
>+	/* Space needed for frame data + headers rounded up */
>+	size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
>+
>+	/* Stopping point for hardware truncation */
>+	thresh = (size - 8) / sizeof(u32);
>+
>+	sky2->rx_nfrags = size >> PAGE_SHIFT;
>+	BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
>+
>+	/* Compute residue after pages */
>+	size -= sky2->rx_nfrags << PAGE_SHIFT;
>+
>+	/* Optimize to handle small packets and headers */
>+	if (size < copybreak)
>+		size = copybreak;
>+	if (size < ETH_HLEN)
>+		size = ETH_HLEN;
>+
>+	sky2->rx_data_size = size;
>+
>+	/* Fill Rx ring */
> 	for (i = 0; i < sky2->rx_pending; i++) {
>-		struct ring_info *re = sky2->rx_ring + i;
>+		re = sky2->rx_ring + i;
> 
>-		re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
>+		re->skb = sky2_rx_alloc(sky2);
> 		if (!re->skb)
> 			goto nomem;
> 
>-		re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
>-					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
>-		sky2_rx_add(sky2, re->mapaddr);
>+		sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
>+		sky2_rx_submit(sky2, re);
> 	}
> 
>-
> 	/*
> 	 * The receiver hangs if it receives frames larger than the
> 	 * packet buffer. As a workaround, truncate oversize frames, but
> 	 * the register is limited to 9 bits, so if you do frames > 2052
> 	 * you better get the MTU right!
> 	 */
>-	thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
> 	if (thresh > 0x1ff)
> 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
> 	else {
>@@ -1022,9 +1322,8 @@
> 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
> 	}
> 
>-
> 	/* Tell chip about available buffers */
>-	sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
>+	sky2_rx_update(sky2, rxq);
> 	return 0;
> nomem:
> 	sky2_rx_clean(sky2);
>@@ -1037,7 +1336,7 @@
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 	struct sky2_hw *hw = sky2->hw;
> 	unsigned port = sky2->port;
>-	u32 ramsize, rxspace, imask;
>+	u32 imask, ramsize;
> 	int cap, err = -ENOMEM;
> 	struct net_device *otherdev = hw->dev[sky2->port^1];
> 
>@@ -1047,20 +1346,19 @@
> 	 */
> 	if (otherdev && netif_running(otherdev) &&
>  	    (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
>- 		struct sky2_port *osky2 = netdev_priv(otherdev);
>  		u16 cmd;
> 
>- 		cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
>+		cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
>  		cmd &= ~PCI_X_CMD_MAX_SPLIT;
>  		sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
> 
>- 		sky2->rx_csum = 0;
>- 		osky2->rx_csum = 0;
>  	}
> 
> 	if (netif_msg_ifup(sky2))
> 		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
> 
>+	netif_carrier_off(dev);
>+
> 	/* must be power of 2 */
> 	sky2->tx_le = pci_alloc_consistent(hw->pdev,
> 					   TX_RING_SIZE *
>@@ -1073,7 +1371,8 @@
> 				GFP_KERNEL);
> 	if (!sky2->tx_ring)
> 		goto err_out;
>-	sky2->tx_prod = sky2->tx_cons = 0;
>+
>+	tx_init(sky2);
> 
> 	sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
> 					   &sky2->rx_le_map);
>@@ -1081,36 +1380,45 @@
> 		goto err_out;
> 	memset(sky2->rx_le, 0, RX_LE_BYTES);
> 
>-	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
>+	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
> 				GFP_KERNEL);
> 	if (!sky2->rx_ring)
> 		goto err_out;
> 
>-	sky2_mac_init(hw, port);
>+	sky2_phy_power(hw, port, 1);
> 
>-	/* Determine available ram buffer space (in 4K blocks).
>-	 * Note: not sure about the FE setting below yet
>-	 */
>-	if (hw->chip_id == CHIP_ID_YUKON_FE)
>-		ramsize = 4;
>-	else
>-		ramsize = sky2_read8(hw, B2_E_0);
>+	sky2_mac_init(hw, port);
> 
>-	/* Give transmitter one third (rounded up) */
>-	rxspace = ramsize - (ramsize + 2) / 3;
>+	/* Register is number of 4K blocks on internal RAM buffer. */
>+	ramsize = sky2_read8(hw, B2_E_0) * 4;
>+	if (ramsize > 0) {
>+		u32 rxspace;
>+
>+		hw->flags |= SKY2_HW_RAM_BUFFER;
>+		pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
>+		if (ramsize < 16)
>+			rxspace = ramsize / 2;
>+		else
>+			rxspace = 8 + (2*(ramsize - 16))/3;
> 
>-	sky2_ramset(hw, rxqaddr[port], 0, rxspace);
>-	sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
>+		sky2_ramset(hw, rxqaddr[port], 0, rxspace);
>+		sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
> 
>-	/* Make sure SyncQ is disabled */
>-	sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
>-		    RB_RST_SET);
>+		/* Make sure SyncQ is disabled */
>+		sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
>+			    RB_RST_SET);
>+	}
> 
> 	sky2_qset(hw, txqaddr[port]);
> 
>+	/* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
>+	if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
>+		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
>+
> 	/* Set almost empty threshold */
>-	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
>-		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
>+	if (hw->chip_id == CHIP_ID_YUKON_EC_U
>+	    && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
>+		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
> 
> 	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
> 			   TX_RING_SIZE - 1);
>@@ -1124,6 +1432,7 @@
> 	imask |= portirq_msk[port];
> 	sky2_write32(hw, B0_IMSK, imask);
> 
>+	sky2_set_multicast(dev);
> 	return 0;
> 
> err_out:
>@@ -1166,10 +1475,10 @@
> 	count = sizeof(dma_addr_t) / sizeof(u32);
> 	count += skb_shinfo(skb)->nr_frags * count;
> 
>-	if (skb_is_tso(skb))
>+	if (skb_is_gso(skb))
> 		++count;
> 
>-	if (skb->ip_summed == CHECKSUM_HW)
>+	if (skb->ip_summed == CHECKSUM_PARTIAL)
> 		++count;
> 
> 	return count;
>@@ -1180,8 +1489,6 @@
>  * A single packet can generate multiple list elements, and
>  * the number of ring elements will probably be less than the number
>  * of list elements used.
>- *
>- * No BH disabling for tx_lock here (like tg3)
>  */
> static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
> {
>@@ -1190,33 +1497,13 @@
> 	struct sky2_tx_le *le = NULL;
> 	struct tx_ring_info *re;
> 	unsigned i, len;
>-	int avail;
> 	dma_addr_t mapping;
>-	u32 addr64;
> 	u16 mss;
> 	u8 ctrl;
>+	u32 addr64;
> 
>-	/* No BH disabling for tx_lock here.  We are running in BH disabled
>-	 * context and TX reclaim runs via poll inside of a software
>-	 * interrupt, and no related locks in IRQ processing.
>-	 */
>-	if (!spin_trylock(&sky2->tx_lock))
>-		return NETDEV_TX_LOCKED;
>-
>-	if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
>-		/* There is a known but harmless race with lockless tx
>-		 * and netif_stop_queue.
>-		 */
>-		if (!netif_queue_stopped(dev)) {
>-			netif_stop_queue(dev);
>-			if (net_ratelimit())
>-				printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
>-				       dev->name);
>-		}
>-		spin_unlock(&sky2->tx_lock);
>-
>-		return NETDEV_TX_BUSY;
>-	}
>+ 	if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
>+  		return NETDEV_TX_BUSY;
> 
> 	if (unlikely(netif_msg_tx_queued(sky2)))
> 		printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
>@@ -1224,41 +1511,34 @@
> 
> 	len = skb_headlen(skb);
> 	mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
>-	addr64 = high32(mapping);
> 
>-	re = sky2->tx_ring + sky2->tx_prod;
>+	addr64 = high32(mapping);
> 
>-	/* Send high bits if changed or crosses boundary */
>-	if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
>+	/* Send high bits if needed */
>+	if (sizeof(dma_addr_t) > sizeof(u32)) {
> 		le = get_tx_le(sky2);
>-		le->tx.addr = cpu_to_le32(addr64);
>+		le->addr = cpu_to_le32(addr64);
> 		le->ctrl = 0;
> 		le->opcode = OP_ADDR64 | HW_OWNER;
>-		sky2->tx_addr64 = high32(mapping + len);
> 	}
> 
> 	/* Check for TCP Segmentation Offload */
> 	mss = skb_shinfo(skb)->tso_size;
> 	if (mss != 0) {
>-		/* just drop the packet if non-linear expansion fails */
>-		if (skb_header_cloned(skb) &&
>-		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
>-			dev_kfree_skb(skb);
>-			goto out_unlock;
>-		}
> 
>-		mss += ((skb->h.th->doff - 5) * 4);	/* TCP options */
>-		mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
>-		mss += ETH_HLEN;
>-	}
>+		if (!(hw->flags & SKY2_HW_NEW_LE))
>+			mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
> 
>-	if (mss != sky2->tx_last_mss) {
>-		le = get_tx_le(sky2);
>-		le->tx.tso.size = cpu_to_le16(mss);
>-		le->tx.tso.rsvd = 0;
>-		le->opcode = OP_LRGLEN | HW_OWNER;
>-		le->ctrl = 0;
>-		sky2->tx_last_mss = mss;
>+  		if (mss != sky2->tx_last_mss) {
>+  			le = get_tx_le(sky2);
>+  			le->addr = cpu_to_le32(mss);
>+
>+			if (hw->flags & SKY2_HW_NEW_LE)
>+				le->opcode = OP_MSS | HW_OWNER;
>+			else
>+				le->opcode = OP_LRGLEN | HW_OWNER;
>+			sky2->tx_last_mss = mss;
>+		}
> 	}
> 
> 	ctrl = 0;
>@@ -1267,9 +1547,8 @@
> 	if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
> 		if (!le) {
> 			le = get_tx_le(sky2);
>-			le->tx.addr = 0;
>+			le->addr = 0;
> 			le->opcode = OP_VLAN|HW_OWNER;
>-			le->ctrl = 0;
> 		} else
> 			le->opcode |= OP_VLAN;
> 		le->length = cpu_to_be16(vlan_tx_tag_get(skb));
>@@ -1278,73 +1557,76 @@
> #endif
> 
> 	/* Handle TCP checksum offload */
>-	if (skb->ip_summed == CHECKSUM_HW) {
>-		u16 hdr = skb->h.raw - skb->data;
>-		u16 offset = hdr + skb->csum;
>+	if (skb->ip_summed == CHECKSUM_PARTIAL) {
>+		/* On Yukon EX (some versions) encoding change. */
>+ 		if (hw->flags & SKY2_HW_AUTO_TX_SUM)
>+ 			ctrl |= CALSUM;	/* auto checksum */
>+		else {
>+			const unsigned offset = skb_transport_offset(skb);
>+			u32 tcpsum;
>+
>+			tcpsum = offset << 16;                  /* sum start */
>+			tcpsum |= offset + skb->csum;    	/* sum write */
> 
>-		ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
>-		if (skb->nh.iph->protocol == IPPROTO_UDP)
>+			ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
>+			if (ip_hdr(skb)->protocol == IPPROTO_UDP)
> 			ctrl |= UDPTCP;
> 
>-		le = get_tx_le(sky2);
>-		le->tx.csum.start = cpu_to_le16(hdr);
>-		le->tx.csum.offset = cpu_to_le16(offset);
>-		le->length = 0;	/* initial checksum value */
>-		le->ctrl = 1;	/* one packet */
>-		le->opcode = OP_TCPLISW | HW_OWNER;
>+			if (tcpsum != sky2->tx_tcpsum) {
>+				sky2->tx_tcpsum = tcpsum;
>+
>+				le = get_tx_le(sky2);
>+				le->addr = cpu_to_le32(tcpsum);
>+				le->length = 0; /* initial checksum value */
>+				le->ctrl = 1;   /* one packet */
>+				le->opcode = OP_TCPLISW | HW_OWNER;
>+			}
>+		}
> 	}
> 
> 	le = get_tx_le(sky2);
>-	le->tx.addr = cpu_to_le32((u32) mapping);
>+	le->addr = cpu_to_le32((u32) mapping);
> 	le->length = cpu_to_le16(len);
> 	le->ctrl = ctrl;
> 	le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
> 
>-	/* Record the transmit mapping info */
>+	re = tx_le_re(sky2, le);
> 	re->skb = skb;
> 	pci_unmap_addr_set(re, mapaddr, mapping);
>+	pci_unmap_len_set(re, maplen, len);
> 
> 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
>-		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
>-		struct tx_ring_info *fre;
>+		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
> 
> 		mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
> 				       frag->size, PCI_DMA_TODEVICE);
>-		addr64 = high32(mapping);
>-		if (addr64 != sky2->tx_addr64) {
>+
>+		if (sizeof(dma_addr_t) > sizeof(u32)) {
> 			le = get_tx_le(sky2);
>-			le->tx.addr = cpu_to_le32(addr64);
>+			le->addr = cpu_to_le32(addr64);
> 			le->ctrl = 0;
> 			le->opcode = OP_ADDR64 | HW_OWNER;
>-			sky2->tx_addr64 = addr64;
> 		}
> 
> 		le = get_tx_le(sky2);
>-		le->tx.addr = cpu_to_le32((u32) mapping);
>+		le->addr = cpu_to_le32((u32) mapping);
> 		le->length = cpu_to_le16(frag->size);
> 		le->ctrl = ctrl;
> 		le->opcode = OP_BUFFER | HW_OWNER;
> 
>-		fre = sky2->tx_ring
>-		    + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
>-		pci_unmap_addr_set(fre, mapaddr, mapping);
>+		re = tx_le_re(sky2, le);
>+		re->skb = skb;
>+		pci_unmap_addr_set(re, mapaddr, mapping);
>+		pci_unmap_len_set(re, maplen, frag->size);
> 	}
> 
>-	re->idx = sky2->tx_prod;
> 	le->ctrl |= EOP;
> 
>-	avail = tx_avail(sky2);
>-	if (mss != 0 || avail < TX_MIN_PENDING) {
>- 		le->ctrl |= FRC_STAT;
>-		if (avail <= MAX_SKB_TX_LE)
>-			netif_stop_queue(dev);
>-	}
>+	if (tx_avail(sky2) <= MAX_SKB_TX_LE)
>+		netif_stop_queue(dev);
> 
> 	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
> 
>-out_unlock:
>-	spin_unlock(&sky2->tx_lock);
>-
> 	dev->trans_start = jiffies;
> 	return NETDEV_TX_OK;
> }
>@@ -1353,59 +1635,64 @@
>  * Free ring elements from starting at tx_cons until "done"
>  *
>  * NB: the hardware will tell us about partial completion of multi-part
>- *     buffers; these are deferred until completion.
>+ *     buffers so make sure not to free skb to early.
>  */
> static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
> {
> 	struct net_device *dev = sky2->netdev;
> 	struct pci_dev *pdev = sky2->hw->pdev;
>-	u16 nxt, put;
>-	unsigned i;
>+	unsigned idx;
> 
> 	BUG_ON(done >= TX_RING_SIZE);
> 
>-	if (unlikely(netif_msg_tx_done(sky2)))
>-		printk(KERN_DEBUG "%s: tx done, up to %u\n",
>-		       dev->name, done);
>-
>-	for (put = sky2->tx_cons; put != done; put = nxt) {
>-		struct tx_ring_info *re = sky2->tx_ring + put;
>-		struct sk_buff *skb = re->skb;
>-
>-		nxt = re->idx;
>-		BUG_ON(nxt >= TX_RING_SIZE);
>-		prefetch(sky2->tx_ring + nxt);
>-
>-		/* Check for partial status */
>-		if (tx_dist(put, done) < tx_dist(put, nxt))
>-			break;
>-
>-		skb = re->skb;
>-		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
>-				 skb_headlen(skb), PCI_DMA_TODEVICE);
>-
>-		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
>-			struct tx_ring_info *fre;
>-			fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
>-			pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
>-				       skb_shinfo(skb)->frags[i].size,
>+	for (idx = sky2->tx_cons; idx != done;
>+	     idx = RING_NEXT(idx, TX_RING_SIZE)) {
>+		struct sky2_tx_le *le = sky2->tx_le + idx;
>+		struct tx_ring_info *re = sky2->tx_ring + idx;
>+
>+		switch(le->opcode & ~HW_OWNER) {
>+		case OP_LARGESEND:
>+		case OP_PACKET:
>+			pci_unmap_single(pdev,
>+					 pci_unmap_addr(re, mapaddr),
>+					 pci_unmap_len(re, maplen),
>+					 PCI_DMA_TODEVICE);
>+			break;
>+		case OP_BUFFER:
>+			pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
>+				       pci_unmap_len(re, maplen),
> 				       PCI_DMA_TODEVICE);
>+			break;
> 		}
> 
>-		dev_kfree_skb(skb);
>+		if (le->ctrl & EOP) {
>+			if (unlikely(netif_msg_tx_done(sky2)))
>+				printk(KERN_DEBUG "%s: tx done %u\n",
>+				       dev->name, idx);
>+
>+			sky2->net_stats.tx_packets++;
>+			sky2->net_stats.tx_bytes += re->skb->len;
>+
>+			dev_kfree_skb_any(re->skb);
>+			sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
>+		}
> 	}
> 
>-	sky2->tx_cons = put;
>+	sky2->tx_cons = idx;
>+	smp_mb();
>+
> 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
> 		netif_wake_queue(dev);
> }
> 
> /* Cleanup all untransmitted buffers, assume transmitter not running */
>-static void sky2_tx_clean(struct sky2_port *sky2)
>+static void sky2_tx_clean(struct net_device *dev)
> {
>-	spin_lock_bh(&sky2->tx_lock);
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+
>+	netif_tx_lock_bh(dev);
> 	sky2_tx_complete(sky2, sky2->tx_prod);
>-	spin_unlock_bh(&sky2->tx_lock);
>+	netif_tx_unlock_bh(dev);
> }
> 
> /* Network shutdown */
>@@ -1427,7 +1714,21 @@
> 	/* Stop more packets from being queued */
> 	netif_stop_queue(dev);
> 
>-	sky2_phy_reset(hw, port);
>+	/* Disable port IRQ */
>+	imask = sky2_read32(hw, B0_IMSK);
>+	imask &= ~portirq_msk[port];
>+	sky2_write32(hw, B0_IMSK, imask);
>+
>+	synchronize_irq(hw->pdev->irq);
>+
>+	/*
>+	 * Both ports share the NAPI poll on port 0, so if necessary undo the
>+	 * the disable that is done in dev_close.
>+	 */
>+	if (sky2->port == 0 && hw->ports > 1)
>+		netif_poll_enable(dev);
>+
>+	sky2_gmac_reset(hw, port);
> 
> 	/* Stop transmitter */
> 	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
>@@ -1470,17 +1771,14 @@
> 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
> 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
> 
>-	/* Disable port IRQ */
>-	imask = sky2_read32(hw, B0_IMSK);
>-	imask &= ~portirq_msk[port];
>-	sky2_write32(hw, B0_IMSK, imask);
>+	sky2_phy_power(hw, port, 0);
>+
>+	netif_carrier_off(dev);
> 
> 	/* turn off LED's */
> 	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
> 
>-	synchronize_irq(hw->pdev->irq);
>-
>-	sky2_tx_clean(sky2);
>+	sky2_tx_clean(dev);
> 	sky2_rx_clean(sky2);
> 
> 	pci_free_consistent(hw->pdev, RX_LE_BYTES,
>@@ -1503,11 +1801,15 @@
> 
> static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
> {
>-	if (!hw->copper)
>+	if (hw->flags & SKY2_HW_FIBRE_PHY)
> 		return SPEED_1000;
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_FE)
>-		return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
>+	if (!(hw->flags & SKY2_HW_GIGABIT)) {
>+		if (aux & PHY_M_PS_SPEED_100)
>+			return SPEED_100;
>+		else
>+			return SPEED_10;
>+	}
> 
> 	switch (aux & PHY_M_PS_SPEED_MSK) {
> 	case PHY_M_PS_SPEED_1000:
>@@ -1524,81 +1826,34 @@
> 	struct sky2_hw *hw = sky2->hw;
> 	unsigned port = sky2->port;
> 	u16 reg;
>-
>-	/* Enable Transmit FIFO Underrun */
>-	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
>-
>-	reg = gma_read16(hw, port, GM_GP_CTRL);
>-	if (sky2->autoneg == AUTONEG_DISABLE) {
>-		reg |= GM_GPCR_AU_ALL_DIS;
>-
>-		/* Is write/read necessary?  Copied from sky2_mac_init */
>-		gma_write16(hw, port, GM_GP_CTRL, reg);
>-		gma_read16(hw, port, GM_GP_CTRL);
>-
>-		switch (sky2->speed) {
>-		case SPEED_1000:
>-			reg &= ~GM_GPCR_SPEED_100;
>-			reg |= GM_GPCR_SPEED_1000;
>-			break;
>-		case SPEED_100:
>-			reg &= ~GM_GPCR_SPEED_1000;
>-			reg |= GM_GPCR_SPEED_100;
>-			break;
>-		case SPEED_10:
>-			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
>-			break;
>-		}
>-	} else
>-		reg &= ~GM_GPCR_AU_ALL_DIS;
>-
>-	if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
>-		reg |= GM_GPCR_DUP_FULL;
>+	static const char *fc_name[] = {
>+		[FC_NONE]	= "none",
>+		[FC_TX]		= "tx",
>+		[FC_RX]		= "rx",
>+		[FC_BOTH]	= "both",
>+	};
> 
> 	/* enable Rx/Tx */
>+	reg = gma_read16(hw, port, GM_GP_CTRL);
> 	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
> 	gma_write16(hw, port, GM_GP_CTRL, reg);
>-	gma_read16(hw, port, GM_GP_CTRL);
> 
> 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
> 
> 	netif_carrier_on(sky2->netdev);
>-	netif_wake_queue(sky2->netdev);
>+
>+	mod_timer(&hw->watchdog_timer, jiffies + 1);
> 
> 	/* Turn on link LED */
> 	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
> 		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
>-		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
>-		u16 led = PHY_M_LEDC_LOS_CTRL(1);	/* link active */
>-
>-		switch(sky2->speed) {
>-		case SPEED_10:
>-			led |= PHY_M_LEDC_INIT_CTRL(7);
>-			break;
>-
>-		case SPEED_100:
>-			led |= PHY_M_LEDC_STA1_CTRL(7);
>-			break;
>-
>-		case SPEED_1000:
>-			led |= PHY_M_LEDC_STA0_CTRL(7);
>-			break;
>-		}
>-
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
>-		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>-	}
>-
> 	if (netif_msg_link(sky2))
> 		printk(KERN_INFO PFX
> 		       "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
> 		       sky2->netdev->name, sky2->speed,
> 		       sky2->duplex == DUPLEX_FULL ? "full" : "half",
>-		       (sky2->tx_pause && sky2->rx_pause) ? "both" :
>-		       sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
>+		       fc_name[sky2->flow_status]);
> }
> 
> static void sky2_link_down(struct sky2_port *sky2)
>@@ -1612,65 +1867,82 @@
> 	reg = gma_read16(hw, port, GM_GP_CTRL);
> 	reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
> 	gma_write16(hw, port, GM_GP_CTRL, reg);
>-	gma_read16(hw, port, GM_GP_CTRL);	/* PCI post */
>-
>-	if (sky2->rx_pause && !sky2->tx_pause) {
>-		/* restore Asymmetric Pause bit */
>-		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
>-			     gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
>-			     | PHY_M_AN_ASP);
>-	}
> 
> 	netif_carrier_off(sky2->netdev);
>-	netif_stop_queue(sky2->netdev);
> 
> 	/* Turn on link LED */
> 	sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
> 
> 	if (netif_msg_link(sky2))
> 		printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
>+
> 	sky2_phy_init(hw, port);
> }
> 
>+static enum flow_control sky2_flow(int rx, int tx)
>+{
>+	if (rx)
>+		return tx ? FC_BOTH : FC_RX;
>+	else
>+		return tx ? FC_TX : FC_NONE;
>+}
>+
> static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
> {
> 	struct sky2_hw *hw = sky2->hw;
> 	unsigned port = sky2->port;
>-	u16 lpa;
>+	u16 advert, lpa;
> 
>+	advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
> 	lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
>-
> 	if (lpa & PHY_M_AN_RF) {
> 		printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
> 		return -1;
> 	}
> 
>-	if (hw->chip_id != CHIP_ID_YUKON_FE &&
>-	    gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
>-		printk(KERN_ERR PFX "%s: master/slave fault",
>-		       sky2->netdev->name);
>-		return -1;
>-	}
>-
> 	if (!(aux & PHY_M_PS_SPDUP_RES)) {
> 		printk(KERN_ERR PFX "%s: speed/duplex mismatch",
> 		       sky2->netdev->name);
> 		return -1;
> 	}
> 
>-	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
>-
> 	sky2->speed = sky2_phy_speed(hw, aux);
>+	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
> 
>-	/* Pause bits are offset (9..8) */
>-	if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
>-		aux >>= 6;
>-
>-	sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
>-	sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
>+	/* Since the pause result bits seem to in different positions on
>+	 * different chips. look at registers.
>+	 */
>+	if (hw->flags & SKY2_HW_FIBRE_PHY) {
>+		/* Shift for bits in fiber PHY */
>+		advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
>+		lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
>+
>+		if (advert & ADVERTISE_1000XPAUSE)
>+			advert |= ADVERTISE_PAUSE_CAP;
>+		if (advert & ADVERTISE_1000XPSE_ASYM)
>+			advert |= ADVERTISE_PAUSE_ASYM;
>+		if (lpa & LPA_1000XPAUSE)
>+			lpa |= LPA_PAUSE_CAP;
>+		if (lpa & LPA_1000XPAUSE_ASYM)
>+			lpa |= LPA_PAUSE_ASYM;
>+	}
>+
>+	sky2->flow_status = FC_NONE;
>+	if (advert & ADVERTISE_PAUSE_CAP) {
>+		if (lpa & LPA_PAUSE_CAP)
>+			sky2->flow_status = FC_BOTH;
>+		else if (advert & ADVERTISE_PAUSE_ASYM)
>+			sky2->flow_status = FC_RX;
>+	} else if (advert & ADVERTISE_PAUSE_ASYM) {
>+		if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
>+			sky2->flow_status = FC_TX;
>+	}
>+
>+	if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
>+	    && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
>+		sky2->flow_status = FC_NONE;
> 
>-	if ((sky2->tx_pause || sky2->rx_pause)
>-	    && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
>+	if (sky2->flow_status & FC_TX)
> 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
> 	else
> 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
>@@ -1685,18 +1957,18 @@
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 	u16 istatus, phystat;
> 
>+	if (!netif_running(dev))
>+		return;
>+
> 	spin_lock(&sky2->phy_lock);
> 	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
> 	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
> 
>-	if (!netif_running(dev))
>-		goto out;
>-
> 	if (netif_msg_intr(sky2))
> 		printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
> 		       sky2->netdev->name, istatus, phystat);
> 
>-	if (istatus & PHY_M_IS_AN_COMPL) {
>+	if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
> 		if (sky2_autoneg_done(sky2, phystat) == 0)
> 			sky2_link_up(sky2);
> 		goto out;
>@@ -1719,64 +1991,31 @@
> 	spin_unlock(&sky2->phy_lock);
> }
> 
>-
>-/* Transmit timeout is only called if we are running, carries is up
>+/* Transmit timeout is only called if we are running, carrier is up
>  * and tx queue is full (stopped).
>  */
> static void sky2_tx_timeout(struct net_device *dev)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 	struct sky2_hw *hw = sky2->hw;
>-	unsigned txq = txqaddr[sky2->port];
>-	u16 report, done;
> 
> 	if (netif_msg_timer(sky2))
> 		printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
> 
>-	report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
>-	done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
>-
> 	printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
>-	       dev->name,
>-	       sky2->tx_cons, sky2->tx_prod, report, done);
>-
>-	if (report != done) {
>-		printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
>-
>-		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
>-		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
>-	} else if (report != sky2->tx_cons) {
>-		printk(KERN_INFO PFX "status report lost?\n");
>-
>-		spin_lock_bh(&sky2->tx_lock);
>-		sky2_tx_complete(sky2, report);
>-		spin_unlock_bh(&sky2->tx_lock);
>-	} else {
>-		printk(KERN_INFO PFX "hardware hung? flushing\n");
>-
>-		sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
>-		sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
>+	       dev->name, sky2->tx_cons, sky2->tx_prod,
>+	       sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
>+	       sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
> 
>-		sky2_tx_clean(sky2);
>-
>-		sky2_qset(hw, txq);
>-		sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
>-	}
>-}
>-
>-
>-/* Want receive buffer size to be multiple of 64 bits
>- * and incl room for vlan and truncation
>- */
>-static inline unsigned sky2_buf_size(int mtu)
>-{
>-	return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
>+	/* can't restart safely under softirq */
>+	schedule_work(&hw->restart_work);
> }
> 
> static int sky2_change_mtu(struct net_device *dev, int new_mtu)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 	struct sky2_hw *hw = sky2->hw;
>+	unsigned port = sky2->port;
> 	int err;
> 	u16 ctl, mode;
> 	u32 imask;
>@@ -1784,7 +2023,9 @@
> 	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
> 		return -EINVAL;
> 
>-	if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
>+	if (new_mtu > ETH_DATA_LEN &&
>+	    (hw->chip_id == CHIP_ID_YUKON_FE ||
>+	     hw->chip_id == CHIP_ID_YUKON_FE_P))
> 		return -EINVAL;
> 
> 	if (!netif_running(dev)) {
>@@ -1801,31 +2042,36 @@
> 
> 	synchronize_irq(hw->pdev->irq);
> 
>-	ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
>-	gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
>+	if (!(hw->flags & SKY2_HW_RAM_BUFFER))
>+		sky2_set_tx_stfwd(hw, port);
>+
>+	ctl = gma_read16(hw, port, GM_GP_CTRL);
>+	gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
> 	sky2_rx_stop(sky2);
> 	sky2_rx_clean(sky2);
> 
> 	dev->mtu = new_mtu;
>-	sky2->rx_bufsize = sky2_buf_size(new_mtu);
>+
> 	mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
> 		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
> 
> 	if (dev->mtu > ETH_DATA_LEN)
> 		mode |= GM_SMOD_JUMBO_ENA;
> 
>-	gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
>+	gma_write16(hw, port, GM_SERIAL_MODE, mode);
> 
>-	sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
>+	sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
> 
> 	err = sky2_rx_start(sky2);
> 	sky2_write32(hw, B0_IMSK, imask);
> 
>+	sky2_read32(hw, B0_Y2_SP_LISR);
>+	netif_poll_enable(hw->dev[0]);
>+
> 	if (err)
> 		dev_close(dev);
> 	else {
>-		gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
>-
>+		gma_write16(hw, port, GM_GP_CTRL, ctl);
> 		netif_poll_enable(hw->dev[0]);
> 		netif_wake_queue(dev);
> 	}
>@@ -1833,80 +2079,162 @@
> 	return err;
> }
> 
>+/* For small just reuse existing skb for next receive */
>+static struct sk_buff *receive_copy(struct sky2_port *sky2,
>+				    const struct rx_ring_info *re,
>+				    unsigned length)
>+{
>+	struct sk_buff *skb;
>+
>+	skb = netdev_alloc_skb(sky2->netdev, length + 2);
>+	if (likely(skb)) {
>+		skb_reserve(skb, 2);
>+		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
>+					    length, PCI_DMA_FROMDEVICE);
>+		skb_copy_from_linear_data(re->skb, skb->data, length);
>+		skb->ip_summed = re->skb->ip_summed;
>+		skb->csum = re->skb->csum;
>+		pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
>+					       length, PCI_DMA_FROMDEVICE);
>+		re->skb->ip_summed = CHECKSUM_NONE;
>+		skb_put(skb, length);
>+	}
>+	return skb;
>+}
>+
>+/* Adjust length of skb with fragments to match received data */
>+static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
>+			  unsigned int length)
>+{
>+	int i, num_frags;
>+	unsigned int size;
>+
>+	/* put header into skb */
>+	size = min(length, hdr_space);
>+	skb->tail += size;
>+	skb->len += size;
>+	length -= size;
>+
>+	num_frags = skb_shinfo(skb)->nr_frags;
>+	for (i = 0; i < num_frags; i++) {
>+		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
>+
>+		if (length == 0) {
>+			/* don't need this page */
>+			__free_page(frag->page);
>+			--skb_shinfo(skb)->nr_frags;
>+		} else {
>+			size = min(length, (unsigned) PAGE_SIZE);
>+
>+			frag->size = size;
>+			skb->data_len += size;
>+			skb->truesize += size;
>+			skb->len += size;
>+			length -= size;
>+		}
>+	}
>+}
>+
>+/* Normal packet - take skb from ring element and put in a new one  */
>+static struct sk_buff *receive_new(struct sky2_port *sky2,
>+				   struct rx_ring_info *re,
>+				   unsigned int length)
>+{
>+	struct sk_buff *skb, *nskb;
>+	unsigned hdr_space = sky2->rx_data_size;
>+
>+	/* Don't be tricky about reusing pages (yet) */
>+	nskb = sky2_rx_alloc(sky2);
>+	if (unlikely(!nskb))
>+		return NULL;
>+
>+	skb = re->skb;
>+	sky2_rx_unmap_skb(sky2->hw->pdev, re);
>+
>+	prefetch(skb->data);
>+	re->skb = nskb;
>+	sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
>+
>+	if (skb_shinfo(skb)->nr_frags)
>+		skb_put_frags(skb, hdr_space, length);
>+	else
>+		skb_put(skb, length);
>+	return skb;
>+}
>+
> /*
>  * Receive one packet.
>- * For small packets or errors, just reuse existing skb.
>  * For larger packets, get new buffer.
>  */
>-static struct sk_buff *sky2_receive(struct sky2_port *sky2,
>+static struct sk_buff *sky2_receive(struct net_device *dev,
> 				    u16 length, u32 status)
> {
>-	struct ring_info *re = sky2->rx_ring + sky2->rx_next;
>+ 	struct sky2_port *sky2 = netdev_priv(dev);
>+	struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
> 	struct sk_buff *skb = NULL;
>+	u16 count = (status & GMR_FS_LEN) >> 16;
>+
>+#ifdef SKY2_VLAN_TAG_USED
>+	/* Account for vlan tag */
>+	if (sky2->vlgrp && (status & GMR_FS_VLAN))
>+		count -= VLAN_HLEN;
>+#endif
> 
> 	if (unlikely(netif_msg_rx_status(sky2)))
> 		printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
>-		       sky2->netdev->name, sky2->rx_next, status, length);
>+		       dev->name, sky2->rx_next, status, length);
> 
> 	sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
> 	prefetch(sky2->rx_ring + sky2->rx_next);
> 
>+	/* This chip has hardware problems that generates bogus status.
>+	 * So do only marginal checking and expect higher level protocols
>+	 * to handle crap frames.
>+	 */
>+	if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+	    sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
>+	    length != count)
>+		goto okay;
>+
> 	if (status & GMR_FS_ANY_ERR)
> 		goto error;
> 
> 	if (!(status & GMR_FS_RX_OK))
> 		goto resubmit;
> 
>-	if (length > sky2->netdev->mtu + ETH_HLEN)
>-		goto oversize;
>-
>-	if (length < copybreak) {
>-		skb = alloc_skb(length + 2, GFP_ATOMIC);
>-		if (!skb)
>-			goto resubmit;
>-
>-		skb_reserve(skb, 2);
>-		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
>-					    length, PCI_DMA_FROMDEVICE);
>-		memcpy(skb->data, re->skb->data, length);
>-		skb->ip_summed = re->skb->ip_summed;
>-		skb->csum = re->skb->csum;
>-		pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
>-					       length, PCI_DMA_FROMDEVICE);
>-	} else {
>-		struct sk_buff *nskb;
>-
>-		nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
>-		if (!nskb)
>-			goto resubmit;
>-
>-		skb = re->skb;
>-		re->skb = nskb;
>-		pci_unmap_single(sky2->hw->pdev, re->mapaddr,
>-				 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
>-		prefetch(skb->data);
>-
>-		re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
>-					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
>-	}
>-
>-	skb_put(skb, length);
>+	/* if length reported by DMA does not match PHY, packet was truncated */
>+	if (length != count)
>+		goto len_error;
>+
>+okay:
>+	if (length < copybreak)
>+		skb = receive_copy(sky2, re, length);
>+	else
>+		skb = receive_new(sky2, re, length);
> resubmit:
>-	re->skb->ip_summed = CHECKSUM_NONE;
>-	sky2_rx_add(sky2, re->mapaddr);
>+	sky2_rx_submit(sky2, re);
> 
> 	return skb;
> 
>-oversize:
>-	++sky2->net_stats.rx_over_errors;
>+len_error:
>+	/* Truncation of overlength packets
>+	   causes PHY length to not match MAC length */
>+	++sky2->net_stats.rx_length_errors;
>+	if (netif_msg_rx_err(sky2) && net_ratelimit())
>+		pr_info(PFX "%s: rx length error: status %#x length %d\n",
>+			dev->name, status, length);
> 	goto resubmit;
> 
> error:
> 	++sky2->net_stats.rx_errors;
>+	if (status & GMR_FS_RX_FF_OV) {
>+		sky2->net_stats.rx_over_errors++;
>+		goto resubmit;
>+	}
> 
> 	if (netif_msg_rx_err(sky2) && net_ratelimit())
> 		printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
>-		       sky2->netdev->name, status, length);
>+		       dev->name, status, length);
> 
> 	if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
> 		sky2->net_stats.rx_length_errors++;
>@@ -1914,8 +2242,6 @@
> 		sky2->net_stats.rx_frame_errors++;
> 	if (status & GMR_FS_CRC_ERR)
> 		sky2->net_stats.rx_crc_errors++;
>-	if (status & GMR_FS_RX_FF_OV)
>-		sky2->net_stats.rx_fifo_errors++;
> 
> 	goto resubmit;
> }
>@@ -1926,46 +2252,63 @@
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 
> 	if (netif_running(dev)) {
>-		spin_lock(&sky2->tx_lock);
>+		netif_tx_lock(dev);
> 		sky2_tx_complete(sky2, last);
>-		spin_unlock(&sky2->tx_lock);
>+		netif_tx_unlock(dev);
> 	}
> }
> 
> /* Process status response ring */
>-static int sky2_status_intr(struct sky2_hw *hw, int to_do)
>+static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
> {
>-	struct sky2_port *sky2;
> 	int work_done = 0;
>-	unsigned buf_write[2] = { 0, 0 };
>-	u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
>+	unsigned rx[2] = { 0, 0 };
> 
> 	rmb();
>-
>-	while (hw->st_idx != hwidx) {
>+	do {
>+		struct sky2_port *sky2;
> 		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
>+		unsigned port;
> 		struct net_device *dev;
> 		struct sk_buff *skb;
> 		u32 status;
> 		u16 length;
>+		u8 opcode = le->opcode;
> 
>-		hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
>+		if (!(opcode & HW_OWNER))
>+			break;
> 
>-		BUG_ON(le->link >= 2);
>-		dev = hw->dev[le->link];
>+		hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
> 
>+		port = le->css & CSS_LINK_BIT;
>+		dev = hw->dev[port];
> 		sky2 = netdev_priv(dev);
>-		length = le->length;
>-		status = le->status;
>+		length = le16_to_cpu(le->length);
>+		status = le32_to_cpu(le->status);
> 
>-		switch (le->opcode & ~HW_OWNER) {
>+		le->opcode = 0;
>+		switch (opcode & ~HW_OWNER) {
> 		case OP_RXSTAT:
>-			skb = sky2_receive(sky2, length, status);
>-			if (!skb)
>+			++rx[port];
>+			skb = sky2_receive(dev, length, status);
>+			if (unlikely(!skb)) {
>+				sky2->net_stats.rx_dropped++;
> 				break;
>+			}
>+
>+			/* This chip reports checksum status differently */
>+			if (hw->flags & SKY2_HW_NEW_LE) {
>+				if (sky2->rx_csum &&
>+				    (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
>+				    (le->css & CSS_TCPUDPCSOK))
>+					skb->ip_summed = CHECKSUM_UNNECESSARY;
>+				else
>+					skb->ip_summed = CHECKSUM_NONE;
>+			}
> 
>-			skb->dev = dev;
> 			skb->protocol = eth_type_trans(skb, dev);
>+			sky2->net_stats.rx_packets++;
>+			sky2->net_stats.rx_bytes += skb->len;
> 			dev->last_rx = jiffies;
> 
> #ifdef SKY2_VLAN_TAG_USED
>@@ -1977,13 +2320,6 @@
> #endif
> 				netif_receive_skb(skb);
> 
>-			/* Update receiver after 16 frames */
>-			if (++buf_write[le->link] == RX_BUF_WRITE) {
>-				sky2_put_idx(hw, rxqaddr[le->link],
>-					     sky2->rx_put);
>-				buf_write[le->link] = 0;
>-			}
>-
> 			/* Stop after net poll weight */
> 			if (++work_done >= to_do)
> 				goto exit_loop;
>@@ -1999,9 +2335,36 @@
> 			/* fall through */
> #endif
> 		case OP_RXCHKS:
>-			skb = sky2->rx_ring[sky2->rx_next].skb;
>-			skb->ip_summed = CHECKSUM_HW;
>-			skb->csum = le16_to_cpu(status);
>+			if (!sky2->rx_csum)
>+				break;
>+
>+			/* If this happens then driver assuming wrong format */
>+			if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
>+				if (net_ratelimit())
>+					printk(KERN_NOTICE "%s: unexpected"
>+					       " checksum status\n",
>+					       dev->name);
>+				break;
>+			}
>+
>+			/* Both checksum counters are programmed to start at
>+			 * the same offset, so unless there is a problem they
>+			 * should match. This failure is an early indication that
>+			 * hardware receive checksumming won't work.
>+			 */
>+			if (likely(status >> 16 == (status & 0xffff))) {
>+				skb = sky2->rx_ring[sky2->rx_next].skb;
>+				skb->ip_summed = CHECKSUM_COMPLETE;
>+				skb->csum = status & 0xffff;
>+			} else {
>+				printk(KERN_NOTICE PFX "%s: hardware receive "
>+				       "checksum problem (status = %#x)\n",
>+				       dev->name, status);
>+				sky2->rx_csum = 0;
>+				sky2_write32(sky2->hw,
>+					     Q_ADDR(rxqaddr[port], Q_CSR),
>+					     BMU_DIS_RX_CHKSUM);
>+			}
> 			break;
> 
> 		case OP_TXINDEXLE:
>@@ -2017,24 +2380,19 @@
> 		default:
> 			if (net_ratelimit())
> 				printk(KERN_WARNING PFX
>-				       "unknown status opcode 0x%x\n", le->opcode);
>-			goto exit_loop;
>+				       "unknown status opcode 0x%x\n", opcode);
> 		}
>-	}
>+	} while (hw->st_idx != idx);
> 
> 	/* Fully processed status ring so clear irq */
> 	sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
> 
> exit_loop:
>-	if (buf_write[0]) {
>-		sky2 = netdev_priv(hw->dev[0]);
>-		sky2_put_idx(hw, Q_R1, sky2->rx_put);
>-	}
>+	if (rx[0])
>+		sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
> 
>-	if (buf_write[1]) {
>-		sky2 = netdev_priv(hw->dev[1]);
>-		sky2_put_idx(hw, Q_R2, sky2->rx_put);
>-	}
>+	if (rx[1])
>+		sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
> 
> 	return work_done;
> }
>@@ -2085,7 +2443,11 @@
> 
> static void sky2_hw_intr(struct sky2_hw *hw)
> {
>+	struct pci_dev *pdev = hw->pdev;
> 	u32 status = sky2_read32(hw, B0_HWE_ISRC);
>+	u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
>+
>+	status &= hwmsk;
> 
> 	if (status & Y2_IS_TIST_OV)
> 		sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
>@@ -2093,12 +2455,12 @@
> 	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
> 		u16 pci_err;
> 
>+		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
> 		pci_err = sky2_pci_read16(hw, PCI_STATUS);
> 		if (net_ratelimit())
>-			printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
>-			       pci_name(hw->pdev), pci_err);
>+			dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
>+			        pci_err);
> 
>-		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
> 		sky2_pci_write16(hw, PCI_STATUS,
> 				      pci_err | PCI_STATUS_ERROR_BITS);
> 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
>@@ -2106,25 +2468,17 @@
> 
> 	if (status & Y2_IS_PCI_EXP) {
> 		/* PCI-Express uncorrectable Error occurred */
>-		u32 pex_err;
>-
>-		pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
>+		u32 err;
> 
>+		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
>+		err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
>+		sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
>+			     0xfffffffful);
> 		if (net_ratelimit())
>-			printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
>-			       pci_name(hw->pdev), pex_err);
>+			dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
> 
>-		/* clear the interrupt */
>-		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
>-		sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
>-				       0xffffffffUL);
>-		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
>-
>-		if (pex_err & PEX_FATAL_ERRORS) {
>-			u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
>-			hwmsk &= ~Y2_IS_PCI_EXP;
>-			sky2_write32(hw, B0_HWE_IMSK, hwmsk);
>-		}
>+		sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
>+		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
> 	}
> 
> 	if (status & Y2_HWE_L1_MASK)
>@@ -2144,6 +2498,12 @@
> 		printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
> 		       dev->name, status);
> 
>+	if (status & GM_IS_RX_CO_OV)
>+		gma_read16(hw, port, GM_RX_IRQ_SRC);
>+
>+	if (status & GM_IS_TX_CO_OV)
>+		gma_read16(hw, port, GM_TX_IRQ_SRC);
>+
> 	if (status & GM_IS_RX_FF_OR) {
> 		++sky2->net_stats.rx_fifo_errors;
> 		sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
>@@ -2155,66 +2515,101 @@
> 	}
> }
> 
>-/* This should never happen it is a fatal situation */
>-static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
>-				  const char *rxtx, u32 mask)
>+/* This should never happen it is a bug. */
>+static void sky2_le_error(struct sky2_hw *hw, unsigned port,
>+			  u16 q, unsigned ring_size)
> {
> 	struct net_device *dev = hw->dev[port];
> 	struct sky2_port *sky2 = netdev_priv(dev);
>-	u32 imask;
>+	unsigned idx;
>+	const u64 *le = (q == Q_R1 || q == Q_R2)
>+		? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
> 
>-	printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
>-	       dev ? dev->name : "<not registered>", rxtx);
>+	idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
>+	printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
>+	       dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
>+	       (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
> 
>-	imask = sky2_read32(hw, B0_IMSK);
>-	imask &= ~mask;
>-	sky2_write32(hw, B0_IMSK, imask);
>-
>-	if (dev) {
>-		spin_lock(&sky2->phy_lock);
>-		sky2_link_down(sky2);
>-		spin_unlock(&sky2->phy_lock);
>-	}
>+	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
> }
> 
>-/* If idle then force a fake soft NAPI poll once a second
>- * to work around cases where sharing an edge triggered interrupt.
>- */
>-static inline void sky2_idle_start(struct sky2_hw *hw)
>+static int sky2_rx_hung(struct net_device *dev)
> {
>-	if (idle_timeout > 0)
>-		mod_timer(&hw->idle_timer,
>-			  jiffies + msecs_to_jiffies(idle_timeout));
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+	struct sky2_hw *hw = sky2->hw;
>+	unsigned port = sky2->port;
>+	unsigned rxq = rxqaddr[port];
>+	u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
>+	u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
>+	u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
>+	u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
>+
>+	/* If idle and MAC or PCI is stuck */
>+	if (sky2->check.last == dev->last_rx &&
>+	    ((mac_rp == sky2->check.mac_rp &&
>+	      mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
>+	     /* Check if the PCI RX hang */
>+	     (fifo_rp == sky2->check.fifo_rp &&
>+	      fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
>+		printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
>+		       dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
>+		       sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
>+		return 1;
>+	} else {
>+		sky2->check.last = dev->last_rx;
>+		sky2->check.mac_rp = mac_rp;
>+		sky2->check.mac_lev = mac_lev;
>+		sky2->check.fifo_rp = fifo_rp;
>+		sky2->check.fifo_lev = fifo_lev;
>+		return 0;
>+	}
> }
> 
>-static void sky2_idle(unsigned long arg)
>+static void sky2_watchdog(unsigned long arg)
> {
> 	struct sky2_hw *hw = (struct sky2_hw *) arg;
>-	struct net_device *dev = hw->dev[0];
>+	struct net_device *dev;
> 
>-	if (__netif_rx_schedule_prep(dev))
>-		__netif_rx_schedule(dev);
>+	/* Check for lost IRQ once a second */
>+	if (sky2_read32(hw, B0_ISRC)) {
>+		dev = hw->dev[0];
>+		if (__netif_rx_schedule_prep(dev))
>+			__netif_rx_schedule(dev);
>+	} else {
>+		int i, active = 0;
> 
>-	mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
>-}
>+		for (i = 0; i < hw->ports; i++) {
>+			dev = hw->dev[i];
>+			if (!netif_running(dev))
>+				continue;
>+			++active;
>+
>+			/* For chips with Rx FIFO, check if stuck */
>+			if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
>+			     sky2_rx_hung(dev)) {
>+				pr_info(PFX "%s: receiver hang detected\n",
>+					dev->name);
>+				schedule_work(&hw->restart_work);
>+				return;
>+			}
>+		}
> 
>+		if (active == 0)
>+			return;
>+	}
> 
>-static int sky2_poll(struct net_device *dev0, int *budget)
>+	mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
>+}
>+
>+/* Hardware/software error handling */
>+static void sky2_err_intr(struct sky2_hw *hw, u32 status)
> {
>-	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
>-	int work_limit = min(dev0->quota, *budget);
>-	int work_done = 0;
>-	u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
>+	if (net_ratelimit())
>+		dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
> 
> 	if (status & Y2_IS_HW_ERR)
> 		sky2_hw_intr(hw);
> 
>-	if (status & Y2_IS_IRQ_PHY1)
>-		sky2_phy_intr(hw, 0);
>-
>-	if (status & Y2_IS_IRQ_PHY2)
>-		sky2_phy_intr(hw, 1);
>-
> 	if (status & Y2_IS_IRQ_MAC1)
> 		sky2_mac_intr(hw, 0);
> 
>@@ -2222,31 +2617,56 @@
> 		sky2_mac_intr(hw, 1);
> 
> 	if (status & Y2_IS_CHK_RX1)
>-		sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
>+		sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
> 
> 	if (status & Y2_IS_CHK_RX2)
>-		sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
>+		sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
> 
> 	if (status & Y2_IS_CHK_TXA1)
>-		sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
>+		sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
> 
> 	if (status & Y2_IS_CHK_TXA2)
>-		sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
>+		sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
>+}
> 
>-	work_done = sky2_status_intr(hw, work_limit);
>-	if (work_done < work_limit) {
>-		netif_rx_complete(dev0);
>+static int sky2_poll(struct net_device *dev0, int *budget)
>+{
>+	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
>+	u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
>+	int work_done = 0;
> 
>-		sky2_read32(hw, B0_Y2_SP_LISR);
>-		return 0;
>-	} else {
>-		*budget -= work_done;
>-		dev0->quota -= work_done;
>+	if (unlikely(status & Y2_IS_ERROR))
>+		sky2_err_intr(hw, status);
>+
>+	if (status & Y2_IS_IRQ_PHY1)
>+		sky2_phy_intr(hw, 0);
>+
>+	if (status & Y2_IS_IRQ_PHY2)
>+		sky2_phy_intr(hw, 1);
>+
>+	work_done = sky2_status_intr(hw, min(dev0->quota, *budget), 
>+				     sky2_read16(hw, STAT_PUT_IDX));
>+	*budget -= work_done;
>+	dev0->quota -= work_done;
>+
>+	/* More work? */
>+	if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
> 		return 1;
>+
>+	/* Bug/Errata workaround?
>+	 * Need to kick the TX irq moderation timer.
>+	 */
>+	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
>+		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
>+		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
> 	}
>+	netif_rx_complete(dev0);
>+
>+	sky2_read32(hw, B0_Y2_SP_LISR);
>+	return 0;
> }
> 
>-static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
>+static irqreturn_t sky2_intr(int irq, void *dev_id)
> {
> 	struct sky2_hw *hw = dev_id;
> 	struct net_device *dev0 = hw->dev[0];
>@@ -2276,16 +2696,26 @@
> #endif
> 
> /* Chip internal frequency for clock calculations */
>-static inline u32 sky2_mhz(const struct sky2_hw *hw)
>+static u32 sky2_mhz(const struct sky2_hw *hw)
> {
> 	switch (hw->chip_id) {
> 	case CHIP_ID_YUKON_EC:
> 	case CHIP_ID_YUKON_EC_U:
>-		return 125;	/* 125 Mhz */
>+	case CHIP_ID_YUKON_EX:
>+	case CHIP_ID_YUKON_SUPR:
>+		return 125;
>+
> 	case CHIP_ID_YUKON_FE:
>-		return 100;	/* 100 Mhz */
>-	default:		/* YUKON_XL */
>-		return 156;	/* 156 Mhz */
>+		return 100;
>+
>+	case CHIP_ID_YUKON_FE_P:
>+		return 50;
>+
>+	case CHIP_ID_YUKON_XL:
>+		return 156;
>+
>+	default:
>+		BUG();
> 	}
> }
> 
>@@ -2300,73 +2730,144 @@
> }
> 
> 
>-static int sky2_reset(struct sky2_hw *hw)
>+static int __devinit sky2_init(struct sky2_hw *hw)
> {
>-	u16 status;
>-	u8 t8, pmd_type;
>-	int i;
>+	u8 t8;
>+
>+	/* Enable all clocks and check for bad PCI access */
>+	sky2_pci_write32(hw, PCI_DEV_REG3, 0);
> 
> 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
> 
> 	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
>-	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
>-		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
>-		       pci_name(hw->pdev), hw->chip_id);
>+	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
>+
>+	switch(hw->chip_id) {
>+	case CHIP_ID_YUKON_XL:
>+		hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
>+		break;
>+
>+	case CHIP_ID_YUKON_EC_U:
>+		hw->flags = SKY2_HW_GIGABIT
>+			| SKY2_HW_NEWER_PHY
>+			| SKY2_HW_ADV_POWER_CTL;
>+		break;
>+
>+	case CHIP_ID_YUKON_EX:
>+		hw->flags = SKY2_HW_GIGABIT
>+			| SKY2_HW_NEWER_PHY
>+			| SKY2_HW_NEW_LE
>+			| SKY2_HW_ADV_POWER_CTL;
>+
>+		/* New transmit checksum */
>+		if (hw->chip_rev != CHIP_REV_YU_EX_B0)
>+			hw->flags |= SKY2_HW_AUTO_TX_SUM;
>+		break;
>+
>+	case CHIP_ID_YUKON_EC:
>+		/* This rev is really old, and requires untested workarounds */
>+		if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
>+			dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
>+			return -EOPNOTSUPP;
>+		}
>+		hw->flags = SKY2_HW_GIGABIT;
>+		break;
>+
>+	case CHIP_ID_YUKON_FE:
>+		break;
>+
>+	case CHIP_ID_YUKON_FE_P:
>+		hw->flags = SKY2_HW_NEWER_PHY
>+			| SKY2_HW_NEW_LE
>+			| SKY2_HW_AUTO_TX_SUM
>+			| SKY2_HW_ADV_POWER_CTL;
>+		break;
>+
>+	case CHIP_ID_YUKON_SUPR:
>+		hw->flags = SKY2_HW_GIGABIT
>+			| SKY2_HW_NEWER_PHY
>+			| SKY2_HW_NEW_LE
>+			| SKY2_HW_AUTO_TX_SUM
>+			| SKY2_HW_ADV_POWER_CTL;
>+		break;
>+
>+	default:
>+		dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
>+			hw->chip_id);
> 		return -EOPNOTSUPP;
> 	}
> 
>-	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
>+	hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
>+	if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
>+		hw->flags |= SKY2_HW_FIBRE_PHY;
> 
>-	/* This rev is really old, and requires untested workarounds */
>-	if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
>-		printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
>-		       pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
>-		       hw->chip_id, hw->chip_rev);
>-		return -EOPNOTSUPP;
>+
>+	hw->ports = 1;
>+	t8 = sky2_read8(hw, B2_Y2_HW_RES);
>+	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
>+		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
>+			++hw->ports;
> 	}
> 
>+	return 0;
>+}
>+
>+static void sky2_reset(struct sky2_hw *hw)
>+{
>+	struct pci_dev *pdev = hw->pdev;
>+	u16 status;
>+	int i, cap;
>+	u32 hwe_mask = Y2_HWE_ALL_MASK;
>+
> 	/* disable ASF */
>-	if (hw->chip_id <= CHIP_ID_YUKON_EC) {
>+	if (hw->chip_id == CHIP_ID_YUKON_EX) {
>+		status = sky2_read16(hw, HCU_CCSR);
>+		status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
>+			    HCU_CCSR_UC_STATE_MSK);
>+		sky2_write16(hw, HCU_CCSR, status);
>+	} else
> 		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
>-		sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
>-	}
>+	sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
> 
> 	/* do a SW reset */
> 	sky2_write8(hw, B0_CTST, CS_RST_SET);
> 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
> 
>-	/* clear PCI errors, if any */
>-	status = sky2_pci_read16(hw, PCI_STATUS);
>-
>+	/* allow writes to PCI config */
> 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
>-	sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
> 
>+	/* clear PCI errors, if any */
>+	status = sky2_pci_read16(hw, PCI_STATUS);
>+	status |= PCI_STATUS_ERROR_BITS;
>+	sky2_pci_write16(hw, PCI_STATUS, status);
> 
> 	sky2_write8(hw, B0_CTST, CS_MRST_CLR);
> 
>-	/* clear any PEX errors */
>-	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
>-		sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
>-
>-
>-	pmd_type = sky2_read8(hw, B2_PMD_TYP);
>-	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
>-
>-	hw->ports = 1;
>-	t8 = sky2_read8(hw, B2_Y2_HW_RES);
>-	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
>-		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
>-			++hw->ports;
>+	cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
>+	if (cap) {
>+		sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
>+			     0xfffffffful);
>+
>+		/* If error bit is stuck on ignore it */
>+		if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
>+			dev_info(&pdev->dev, "ignoring stuck error report bit\n");
>+		else
>+			hwe_mask |= Y2_IS_PCI_EXP;
> 	}
> 
>-	sky2_set_power_state(hw, PCI_D0);
>+	sky2_power_on(hw);
>+	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
> 
> 	for (i = 0; i < hw->ports; i++) {
> 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
> 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
>-	}
> 
>-	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
>+		if (hw->chip_id == CHIP_ID_YUKON_EX ||
>+		    hw->chip_id == CHIP_ID_YUKON_SUPR)
>+			sky2_write16(hw, SK_REG(i, GMAC_CTRL),
>+				     GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
>+				     | GMC_BYP_RETR_ON);
>+	}
> 
> 	/* Clear I2C IRQ noise */
> 	sky2_write32(hw, B2_I2C_IRQ, 1);
>@@ -2406,10 +2907,10 @@
> 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
> 	}
> 
>-	sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
>+	sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
> 
> 	for (i = 0; i < hw->ports; i++)
>-		sky2_phy_reset(hw, i);
>+		sky2_gmac_reset(hw, i);
> 
> 	memset(hw->st_le, 0, STATUS_LE_BYTES);
> 	hw->st_idx = 0;
>@@ -2442,27 +2943,95 @@
> 	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
> 	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
> 	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
>+}
>+
>+static void sky2_restart(struct work_struct *work)
>+{
>+	struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
>+	struct net_device *dev;
>+	int i, err;
>+
>+	rtnl_lock();
>+	for (i = 0; i < hw->ports; i++) {
>+		dev = hw->dev[i];
>+		if (netif_running(dev))
>+			sky2_down(dev);
>+	}
>+
>+	sky2_write32(hw, B0_IMSK, 0);
>+	sky2_reset(hw);
>+	sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
>+	netif_poll_disable(hw->dev[0]);
>+
>+
>+	for (i = 0; i < hw->ports; i++) {
>+		dev = hw->dev[i];
>+		if (netif_running(dev)) {
>+			err = sky2_up(dev);
>+			if (err) {
>+				printk(KERN_INFO PFX "%s: could not restart %d\n",
>+				       dev->name, err);
>+				dev_close(dev);
>+			}
>+		}
>+	}
>+	netif_poll_enable(hw->dev[0]);
>+
>+	rtnl_unlock();
>+}
>+
>+static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
>+{
>+	return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
>+}
> 
>+static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
>+{
>+	const struct sky2_port *sky2 = netdev_priv(dev);
>+
>+	wol->supported = sky2_wol_supported(sky2->hw);
>+	wol->wolopts = sky2->wol;
>+}
>+
>+static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
>+{
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+	struct sky2_hw *hw = sky2->hw;
>+
>+	if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
>+		return -EOPNOTSUPP;
>+
>+	sky2->wol = wol->wolopts;
>+
>+	if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
>+	    hw->chip_id == CHIP_ID_YUKON_EX ||
>+	    hw->chip_id == CHIP_ID_YUKON_FE_P)
>+		sky2_write32(hw, B0_CTST, sky2->wol
>+			     ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
>+
>+	if (!netif_running(dev))
>+		sky2_wol_init(sky2);
> 	return 0;
> }
> 
> static u32 sky2_supported_modes(const struct sky2_hw *hw)
> {
>-	u32 modes;
>-	if (hw->copper) {
>-		modes = SUPPORTED_10baseT_Half
>-		    | SUPPORTED_10baseT_Full
>-		    | SUPPORTED_100baseT_Half
>-		    | SUPPORTED_100baseT_Full
>-		    | SUPPORTED_Autoneg | SUPPORTED_TP;
>+	if (sky2_is_copper(hw)) {
>+		u32 modes = SUPPORTED_10baseT_Half
>+			| SUPPORTED_10baseT_Full
>+			| SUPPORTED_100baseT_Half
>+			| SUPPORTED_100baseT_Full
>+			| SUPPORTED_Autoneg | SUPPORTED_TP;
> 
>-		if (hw->chip_id != CHIP_ID_YUKON_FE)
>+		if (hw->flags & SKY2_HW_GIGABIT)
> 			modes |= SUPPORTED_1000baseT_Half
>-			    | SUPPORTED_1000baseT_Full;
>+				| SUPPORTED_1000baseT_Full;
>+		return modes;
> 	} else
>-		modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
>-		    | SUPPORTED_Autoneg;
>-	return modes;
>+		return  SUPPORTED_1000baseT_Half
>+			| SUPPORTED_1000baseT_Full
>+			| SUPPORTED_Autoneg
>+			| SUPPORTED_FIBRE;
> }
> 
> static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
>@@ -2473,21 +3042,16 @@
> 	ecmd->transceiver = XCVR_INTERNAL;
> 	ecmd->supported = sky2_supported_modes(hw);
> 	ecmd->phy_address = PHY_ADDR_MARV;
>-	if (hw->copper) {
>-		ecmd->supported = SUPPORTED_10baseT_Half
>-		    | SUPPORTED_10baseT_Full
>-		    | SUPPORTED_100baseT_Half
>-		    | SUPPORTED_100baseT_Full
>-		    | SUPPORTED_1000baseT_Half
>-		    | SUPPORTED_1000baseT_Full
>-		    | SUPPORTED_Autoneg | SUPPORTED_TP;
>+	if (sky2_is_copper(hw)) {
> 		ecmd->port = PORT_TP;
>-	} else
>+		ecmd->speed = sky2->speed;
>+	} else {
>+		ecmd->speed = SPEED_1000;
> 		ecmd->port = PORT_FIBRE;
>+	}
> 
> 	ecmd->advertising = sky2->advertising;
> 	ecmd->autoneg = sky2->autoneg;
>-	ecmd->speed = sky2->speed;
> 	ecmd->duplex = sky2->duplex;
> 	return 0;
> }
>@@ -2545,8 +3109,10 @@
> 	sky2->autoneg = ecmd->autoneg;
> 	sky2->advertising = ecmd->advertising;
> 
>-	if (netif_running(dev))
>+	if (netif_running(dev)) {
> 		sky2_phy_reinit(sky2);
>+		sky2_set_multicast(dev);
>+	}
> 
> 	return 0;
> }
>@@ -2635,10 +3201,11 @@
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 
>-	if (sky2->autoneg != AUTONEG_ENABLE)
>+	if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
> 		return -EINVAL;
> 
> 	sky2_phy_reinit(sky2);
>+	sky2_set_multicast(dev);
> 
> 	return 0;
> }
>@@ -2664,9 +3231,14 @@
> 	sky2->msg_enable = value;
> }
> 
>-static int sky2_get_stats_count(struct net_device *dev)
>+static int sky2_get_sset_count(struct net_device *dev, int sset)
> {
>-	return ARRAY_SIZE(sky2_stats);
>+	switch (sset) {
>+	case ETH_SS_STATS:
>+		return ARRAY_SIZE(sky2_stats);
>+	default:
>+		return -EOPNOTSUPP;
>+	}
> }
> 
> static void sky2_get_ethtool_stats(struct net_device *dev,
>@@ -2690,28 +3262,6 @@
> 	}
> }
> 
>-/* Use hardware MIB variables for critical path statistics and
>- * transmit feedback not reported at interrupt.
>- * Other errors are accounted for in interrupt handler.
>- */
>-static struct net_device_stats *sky2_get_stats(struct net_device *dev)
>-{
>-	struct sky2_port *sky2 = netdev_priv(dev);
>-	u64 data[13];
>-
>-	sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
>-
>-	sky2->net_stats.tx_bytes = data[0];
>-	sky2->net_stats.rx_bytes = data[1];
>-	sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
>-	sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
>-	sky2->net_stats.multicast = data[3] + data[5];
>-	sky2->net_stats.collisions = data[10];
>-	sky2->net_stats.tx_aborted_errors = data[12];
>-
>-	return &sky2->net_stats;
>-}
>-
> static int sky2_set_mac_address(struct net_device *dev, void *p)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
>@@ -2737,6 +3287,14 @@
> 	return 0;
> }
> 
>+static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
>+{
>+	u32 bit;
>+
>+	bit = ether_crc(ETH_ALEN, addr) & 63;
>+	filter[bit >> 3] |= 1 << (bit & 7);
>+}
>+
> static void sky2_set_multicast(struct net_device *dev)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
>@@ -2745,7 +3303,10 @@
> 	struct dev_mc_list *list = dev->mc_list;
> 	u16 reg;
> 	u8 filter[8];
>+	int rx_pause;
>+	static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
> 
>+	rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
> 	memset(filter, 0, sizeof(filter));
> 
> 	reg = gma_read16(hw, port, GM_RX_CTRL);
>@@ -2753,18 +3314,19 @@
> 
> 	if (dev->flags & IFF_PROMISC)	/* promiscuous */
> 		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
>-	else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16)	/* all multicast */
>+	else if (dev->flags & IFF_ALLMULTI)
> 		memset(filter, 0xff, sizeof(filter));
>-	else if (dev->mc_count == 0)	/* no multicast */
>+	else if (dev->mc_count == 0 && !rx_pause)
> 		reg &= ~GM_RXCR_MCF_ENA;
> 	else {
> 		int i;
> 		reg |= GM_RXCR_MCF_ENA;
> 
>-		for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
>-			u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
>-			filter[bit / 8] |= 1 << (bit % 8);
>-		}
>+		if (rx_pause)
>+			sky2_add_filter(filter, pause_mc_addr);
>+
>+		for (i = 0; list && i < dev->mc_count; i++, list = list->next)
>+			sky2_add_filter(filter, list->dmi_addr);
> 	}
> 
> 	gma_write16(hw, port, GM_MC_ADDR_H1,
>@@ -2782,92 +3344,80 @@
> /* Can have one global because blinking is controlled by
>  * ethtool and that is always under RTNL mutex
>  */
>-static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
>+static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
> {
>-	u16 pg;
>+	struct sky2_hw *hw = sky2->hw;
>+	unsigned port = sky2->port;
> 
>-	switch (hw->chip_id) {
>-	case CHIP_ID_YUKON_XL:
>+	spin_lock_bh(&sky2->phy_lock);
>+	if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
>+	    hw->chip_id == CHIP_ID_YUKON_EX ||
>+	    hw->chip_id == CHIP_ID_YUKON_SUPR) {
>+		u16 pg;
> 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
> 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
>-		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
>-			     on ? (PHY_M_LEDC_LOS_CTRL(1) |
>-				   PHY_M_LEDC_INIT_CTRL(7) |
>-				   PHY_M_LEDC_STA1_CTRL(7) |
>-				   PHY_M_LEDC_STA0_CTRL(7))
>-			     : 0);
> 
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>-		break;
>+		switch (mode) {
>+		case MO_LED_OFF:
>+			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
>+				     PHY_M_LEDC_LOS_CTRL(8) |
>+				     PHY_M_LEDC_INIT_CTRL(8) |
>+				     PHY_M_LEDC_STA1_CTRL(8) |
>+				     PHY_M_LEDC_STA0_CTRL(8));
>+			break;
>+		case MO_LED_ON:
>+			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
>+				     PHY_M_LEDC_LOS_CTRL(9) |
>+				     PHY_M_LEDC_INIT_CTRL(9) |
>+				     PHY_M_LEDC_STA1_CTRL(9) |
>+				     PHY_M_LEDC_STA0_CTRL(9));
>+			break;
>+		case MO_LED_BLINK:
>+			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
>+				     PHY_M_LEDC_LOS_CTRL(0xa) |
>+				     PHY_M_LEDC_INIT_CTRL(0xa) |
>+				     PHY_M_LEDC_STA1_CTRL(0xa) |
>+				     PHY_M_LEDC_STA0_CTRL(0xa));
>+			break;
>+		case MO_LED_NORM:
>+			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
>+				     PHY_M_LEDC_LOS_CTRL(1) |
>+				     PHY_M_LEDC_INIT_CTRL(8) |
>+				     PHY_M_LEDC_STA1_CTRL(7) |
>+				     PHY_M_LEDC_STA0_CTRL(7));
>+		}
> 
>-	default:
>-		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
>-		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
>-			     on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
>-			     PHY_M_LED_MO_10(MO_LED_ON) |
>-			     PHY_M_LED_MO_100(MO_LED_ON) |
>-			     PHY_M_LED_MO_1000(MO_LED_ON) |
>-			     PHY_M_LED_MO_RX(MO_LED_ON)
>-			     : PHY_M_LED_MO_DUP(MO_LED_OFF) |
>-			     PHY_M_LED_MO_10(MO_LED_OFF) |
>-			     PHY_M_LED_MO_100(MO_LED_OFF) |
>-			     PHY_M_LED_MO_1000(MO_LED_OFF) |
>-			     PHY_M_LED_MO_RX(MO_LED_OFF));
>+		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>+	} else
>+		gm_phy_write(hw, port, PHY_MARV_LED_OVER, 
>+				     PHY_M_LED_MO_DUP(mode) |
>+				     PHY_M_LED_MO_10(mode) |
>+				     PHY_M_LED_MO_100(mode) |
>+				     PHY_M_LED_MO_1000(mode) |
>+				     PHY_M_LED_MO_RX(mode) |
>+				     PHY_M_LED_MO_TX(mode));
> 
>-	}
>+	spin_unlock_bh(&sky2->phy_lock);
> }
> 
> /* blink LED's for finding board */
> static int sky2_phys_id(struct net_device *dev, u32 data)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
>-	struct sky2_hw *hw = sky2->hw;
>-	unsigned port = sky2->port;
>-	u16 ledctrl, ledover = 0;
>-	long ms;
>-	int interrupted;
>-	int onoff = 1;
>+	unsigned int i;
> 
>-	if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
>-		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
>-	else
>-		ms = data * 1000;
>-
>-	/* save initial values */
>-	spin_lock_bh(&sky2->phy_lock);
>-	if (hw->chip_id == CHIP_ID_YUKON_XL) {
>-		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
>-		ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>-	} else {
>-		ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
>-		ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
>-	}
>+	if (data == 0)
>+		data = UINT_MAX;
> 
>-	interrupted = 0;
>-	while (!interrupted && ms > 0) {
>-		sky2_led(hw, port, onoff);
>-		onoff = !onoff;
>-
>-		spin_unlock_bh(&sky2->phy_lock);
>-		interrupted = msleep_interruptible(250);
>-		spin_lock_bh(&sky2->phy_lock);
>-
>-		ms -= 250;
>-	}
>-
>-	/* resume regularly scheduled programming */
>-	if (hw->chip_id == CHIP_ID_YUKON_XL) {
>-		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
>-		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
>-		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
>-	} else {
>-		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
>-		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
>+	for (i = 0; i < data; i++) {
>+		sky2_led(sky2, MO_LED_ON);
>+		if (msleep_interruptible(500))
>+			break;
>+		sky2_led(sky2, MO_LED_OFF);
>+		if (msleep_interruptible(500))
>+			break;
> 	}
>-	spin_unlock_bh(&sky2->phy_lock);
>+	sky2_led(sky2, MO_LED_NORM);
> 
> 	return 0;
> }
>@@ -2877,8 +3427,20 @@
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
> 
>-	ecmd->tx_pause = sky2->tx_pause;
>-	ecmd->rx_pause = sky2->rx_pause;
>+	switch (sky2->flow_mode) {
>+	case FC_NONE:
>+		ecmd->tx_pause = ecmd->rx_pause = 0;
>+		break;
>+	case FC_TX:
>+		ecmd->tx_pause = 1, ecmd->rx_pause = 0;
>+		break;
>+	case FC_RX:
>+		ecmd->tx_pause = 0, ecmd->rx_pause = 1;
>+		break;
>+	case FC_BOTH:
>+		ecmd->tx_pause = ecmd->rx_pause = 1;
>+	}
>+
> 	ecmd->autoneg = sky2->autoneg;
> }
> 
>@@ -2886,15 +3448,14 @@
> 			       struct ethtool_pauseparam *ecmd)
> {
> 	struct sky2_port *sky2 = netdev_priv(dev);
>-	int err = 0;
> 
> 	sky2->autoneg = ecmd->autoneg;
>-	sky2->tx_pause = ecmd->tx_pause != 0;
>-	sky2->rx_pause = ecmd->rx_pause != 0;
>+	sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
> 
>-	sky2_phy_reinit(sky2);
>+	if (netif_running(dev))
>+		sky2_phy_reinit(sky2);
> 
>-	return err;
>+	return 0;
> }
> 
> static int sky2_get_coalesce(struct net_device *dev,
>@@ -3018,8 +3579,6 @@
> 		err = sky2_up(dev);
> 		if (err)
> 			dev_close(dev);
>-		else
>-			sky2_set_multicast(dev);
> 	}
> 
> 	return err;
>@@ -3032,82 +3591,423 @@
> 
> /*
>  * Returns copy of control register region
>- * Note: access to the RAM address register set will cause timeouts.
>+ * Note: ethtool_get_regs always provides full size (16k) buffer
>  */
> static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
> 			  void *p)
> {
> 	const struct sky2_port *sky2 = netdev_priv(dev);
>-#if 0 /* Not in RHEL4... */
> 	const void __iomem *io = sky2->hw->regs;
>-#else /* RHEL4 */
>-	void __iomem *io = sky2->hw->regs;
>-#endif
>+	unsigned int b;
> 
>-	BUG_ON(regs->len < B3_RI_WTO_R1);
> 	regs->version = 1;
>-	memset(p, 0, regs->len);
> 
>-	memcpy_fromio(p, io, B3_RAM_ADDR);
>+	for (b = 0; b < 128; b++) {
>+		/* This complicated switch statement is to make sure and
>+		 * only access regions that are unreserved.
>+		 * Some blocks are only valid on dual port cards.
>+		 * and block 3 has some special diagnostic registers that
>+		 * are poison.
>+		 */
>+		switch (b) {
>+		case 3:
>+			/* skip diagnostic ram region */
>+			memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
>+			break;
>+
>+		/* dual port cards only */
>+		case 5:		/* Tx Arbiter 2 */
>+		case 9: 	/* RX2 */
>+		case 14 ... 15:	/* TX2 */
>+		case 17: case 19: /* Ram Buffer 2 */
>+		case 22 ... 23: /* Tx Ram Buffer 2 */
>+		case 25: 	/* Rx MAC Fifo 1 */
>+		case 27: 	/* Tx MAC Fifo 2 */
>+		case 31:	/* GPHY 2 */
>+		case 40 ... 47: /* Pattern Ram 2 */
>+		case 52: case 54: /* TCP Segmentation 2 */
>+		case 112 ... 116: /* GMAC 2 */
>+			if (sky2->hw->ports == 1)
>+				goto reserved;
>+			/* fall through */
>+		case 0:		/* Control */
>+		case 2:		/* Mac address */
>+		case 4:		/* Tx Arbiter 1 */
>+		case 7:		/* PCI express reg */
>+		case 8:		/* RX1 */
>+		case 12 ... 13: /* TX1 */
>+		case 16: case 18:/* Rx Ram Buffer 1 */
>+		case 20 ... 21: /* Tx Ram Buffer 1 */
>+		case 24: 	/* Rx MAC Fifo 1 */
>+		case 26: 	/* Tx MAC Fifo 1 */
>+		case 28 ... 29: /* Descriptor and status unit */
>+		case 30:	/* GPHY 1*/
>+		case 32 ... 39: /* Pattern Ram 1 */
>+		case 48: case 50: /* TCP Segmentation 1 */
>+		case 56 ... 60:	/* PCI space */
>+		case 80 ... 84:	/* GMAC 1 */
>+			memcpy_fromio(p, io, 128);
>+			break;
>+		default:
>+reserved:
>+			memset(p, 0, 128);
>+		}
>+
>+		p += 128;
>+		io += 128;
>+	}
>+}
>+
>+/* In order to do Jumbo packets on these chips, need to turn off the
>+ * transmit store/forward. Therefore checksum offload won't work.
>+ */
>+static int no_tx_offload(struct net_device *dev)
>+{
>+	const struct sky2_port *sky2 = netdev_priv(dev);
>+	const struct sky2_hw *hw = sky2->hw;
> 
>-	memcpy_fromio(p + B3_RI_WTO_R1,
>-		      io + B3_RI_WTO_R1,
>-		      regs->len - B3_RI_WTO_R1);
>-}
>-
>-static struct ethtool_ops sky2_ethtool_ops = {
>-	.get_settings = sky2_get_settings,
>-	.set_settings = sky2_set_settings,
>-	.get_drvinfo = sky2_get_drvinfo,
>-	.get_msglevel = sky2_get_msglevel,
>-	.set_msglevel = sky2_set_msglevel,
>-	.nway_reset   = sky2_nway_reset,
>-	.get_regs_len = sky2_get_regs_len,
>-	.get_regs = sky2_get_regs,
>-	.get_link = ethtool_op_get_link,
>-	.get_sg = ethtool_op_get_sg,
>-	.set_sg = ethtool_op_set_sg,
>-	.get_tx_csum = ethtool_op_get_tx_csum,
>-	.set_tx_csum = ethtool_op_set_tx_csum,
>-	.get_tso = ethtool_op_get_tso,
>-	.set_tso = ethtool_op_set_tso,
>-	.get_rx_csum = sky2_get_rx_csum,
>-	.set_rx_csum = sky2_set_rx_csum,
>-	.get_strings = sky2_get_strings,
>-	.get_coalesce = sky2_get_coalesce,
>-	.set_coalesce = sky2_set_coalesce,
>-	.get_ringparam = sky2_get_ringparam,
>-	.set_ringparam = sky2_set_ringparam,
>+	return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
>+}
>+
>+static int sky2_set_tx_csum(struct net_device *dev, u32 data)
>+{
>+	if (data && no_tx_offload(dev))
>+		return -EINVAL;
>+
>+	return ethtool_op_set_tx_csum(dev, data);
>+}
>+
>+
>+static int sky2_set_tso(struct net_device *dev, u32 data)
>+{
>+	if (data && no_tx_offload(dev))
>+		return -EINVAL;
>+
>+	return ethtool_op_set_tso(dev, data);
>+}
>+
>+static int sky2_get_eeprom_len(struct net_device *dev)
>+{
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+	struct sky2_hw *hw = sky2->hw;
>+	u16 reg2;
>+
>+	reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
>+	return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
>+}
>+
>+static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
>+{
>+	u32 val;
>+
>+	sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
>+
>+	do {
>+		offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
>+	} while (!(offset & PCI_VPD_ADDR_F));
>+
>+	val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
>+	return val;
>+}
>+
>+static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
>+{
>+	sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
>+	sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
>+	do {
>+		offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
>+	} while (offset & PCI_VPD_ADDR_F);
>+}
>+
>+static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
>+			   u8 *data)
>+{
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+	int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
>+	int length = eeprom->len;
>+	u16 offset = eeprom->offset;
>+
>+	if (!cap)
>+		return -EINVAL;
>+
>+	eeprom->magic = SKY2_EEPROM_MAGIC;
>+
>+	while (length > 0) {
>+		u32 val = sky2_vpd_read(sky2->hw, cap, offset);
>+		int n = min_t(int, length, sizeof(val));
>+
>+		memcpy(data, &val, n);
>+		length -= n;
>+		data += n;
>+		offset += n;
>+	}
>+	return 0;
>+}
>+
>+static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
>+			   u8 *data)
>+{
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+	int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
>+	int length = eeprom->len;
>+	u16 offset = eeprom->offset;
>+
>+	if (!cap)
>+		return -EINVAL;
>+
>+	if (eeprom->magic != SKY2_EEPROM_MAGIC)
>+		return -EINVAL;
>+
>+	while (length > 0) {
>+		u32 val;
>+		int n = min_t(int, length, sizeof(val));
>+
>+		if (n < sizeof(val))
>+			val = sky2_vpd_read(sky2->hw, cap, offset);
>+		memcpy(&val, data, n);
>+
>+		sky2_vpd_write(sky2->hw, cap, offset, val);
>+
>+		length -= n;
>+		data += n;
>+		offset += n;
>+	}
>+	return 0;
>+}
>+
>+
>+static const struct ethtool_ops sky2_ethtool_ops = {
>+	.get_settings	= sky2_get_settings,
>+	.set_settings	= sky2_set_settings,
>+	.get_drvinfo	= sky2_get_drvinfo,
>+	.get_wol	= sky2_get_wol,
>+	.set_wol	= sky2_set_wol,
>+	.get_msglevel	= sky2_get_msglevel,
>+	.set_msglevel	= sky2_set_msglevel,
>+	.nway_reset	= sky2_nway_reset,
>+	.get_regs_len	= sky2_get_regs_len,
>+	.get_regs	= sky2_get_regs,
>+	.get_link	= ethtool_op_get_link,
>+	.get_eeprom_len	= sky2_get_eeprom_len,
>+	.get_eeprom	= sky2_get_eeprom,
>+	.set_eeprom	= sky2_set_eeprom,
>+	.set_sg 	= ethtool_op_set_sg,
>+	.set_tx_csum	= sky2_set_tx_csum,
>+	.set_tso	= sky2_set_tso,
>+	.get_rx_csum	= sky2_get_rx_csum,
>+	.set_rx_csum	= sky2_set_rx_csum,
>+	.get_strings	= sky2_get_strings,
>+	.get_coalesce	= sky2_get_coalesce,
>+	.set_coalesce	= sky2_set_coalesce,
>+	.get_ringparam	= sky2_get_ringparam,
>+	.set_ringparam	= sky2_set_ringparam,
> 	.get_pauseparam = sky2_get_pauseparam,
> 	.set_pauseparam = sky2_set_pauseparam,
>-	.phys_id = sky2_phys_id,
>-	.get_stats_count = sky2_get_stats_count,
>+	.phys_id	= sky2_phys_id,
> 	.get_ethtool_stats = sky2_get_ethtool_stats,
>-#if 0 /* Not in RHEL4... */
>-	.get_perm_addr	= ethtool_op_get_perm_addr,
>-#endif
> };
> 
>+#ifdef CONFIG_SKY2_DEBUG
>+
>+static struct dentry *sky2_debug;
>+
>+static int sky2_debug_show(struct seq_file *seq, void *v)
>+{
>+	struct net_device *dev = seq->private;
>+	const struct sky2_port *sky2 = netdev_priv(dev);
>+	const struct sky2_hw *hw = sky2->hw;
>+	unsigned port = sky2->port;
>+	unsigned idx, last;
>+	int sop;
>+
>+	if (!netif_running(dev))
>+		return -ENETDOWN;
>+
>+	seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
>+		   sky2_read32(hw, B0_ISRC),
>+		   sky2_read32(hw, B0_IMSK),
>+		   sky2_read32(hw, B0_Y2_SP_ICR));
>+
>+	netif_poll_disable(hw->dev[0]);
>+	last = sky2_read16(hw, STAT_PUT_IDX);
>+
>+	if (hw->st_idx == last)
>+		seq_puts(seq, "Status ring (empty)\n");
>+	else {
>+		seq_puts(seq, "Status ring\n");
>+		for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
>+		     idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
>+			const struct sky2_status_le *le = hw->st_le + idx;
>+			seq_printf(seq, "[%d] %#x %d %#x\n",
>+				   idx, le->opcode, le->length, le->status);
>+		}
>+		seq_puts(seq, "\n");
>+	}
>+
>+	seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
>+		   sky2->tx_cons, sky2->tx_prod,
>+		   sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
>+		   sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
>+
>+	/* Dump contents of tx ring */
>+	sop = 1;
>+	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
>+	     idx = RING_NEXT(idx, TX_RING_SIZE)) {
>+		const struct sky2_tx_le *le = sky2->tx_le + idx;
>+		u32 a = le32_to_cpu(le->addr);
>+
>+		if (sop)
>+			seq_printf(seq, "%u:", idx);
>+		sop = 0;
>+
>+		switch(le->opcode & ~HW_OWNER) {
>+		case OP_ADDR64:
>+			seq_printf(seq, " %#x:", a);
>+			break;
>+		case OP_LRGLEN:
>+			seq_printf(seq, " mtu=%d", a);
>+			break;
>+		case OP_VLAN:
>+			seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
>+			break;
>+		case OP_TCPLISW:
>+			seq_printf(seq, " csum=%#x", a);
>+			break;
>+		case OP_LARGESEND:
>+			seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
>+			break;
>+		case OP_PACKET:
>+			seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
>+			break;
>+		case OP_BUFFER:
>+			seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
>+			break;
>+		default:
>+			seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
>+				   a, le16_to_cpu(le->length));
>+		}
>+
>+		if (le->ctrl & EOP) {
>+			seq_putc(seq, '\n');
>+			sop = 1;
>+		}
>+	}
>+
>+	seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
>+		   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
>+		   last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
>+		   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
>+
>+	sky2_read32(hw, B0_Y2_SP_LISR);
>+	netif_poll_enable(hw->dev[0]);
>+	return 0;
>+}
>+
>+static int sky2_debug_open(struct inode *inode, struct file *file)
>+{
>+	return single_open(file, sky2_debug_show, inode->i_private);
>+}
>+
>+static const struct file_operations sky2_debug_fops = {
>+	.owner		= THIS_MODULE,
>+	.open		= sky2_debug_open,
>+	.read		= seq_read,
>+	.llseek		= seq_lseek,
>+	.release	= single_release,
>+};
>+
>+/*
>+ * Use network device events to create/remove/rename
>+ * debugfs file entries
>+ */
>+static int sky2_device_event(struct notifier_block *unused,
>+			     unsigned long event, void *ptr)
>+{
>+	struct net_device *dev = ptr;
>+	struct sky2_port *sky2 = netdev_priv(dev);
>+
>+	if (dev->open != sky2_up || !sky2_debug)
>+		return NOTIFY_DONE;
>+
>+	switch(event) {
>+	case NETDEV_CHANGENAME:
>+		if (sky2->debugfs) {
>+			sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
>+						       sky2_debug, dev->name);
>+		}
>+		break;
>+
>+	case NETDEV_GOING_DOWN:
>+		if (sky2->debugfs) {
>+			printk(KERN_DEBUG PFX "%s: remove debugfs\n",
>+			       dev->name);
>+			debugfs_remove(sky2->debugfs);
>+			sky2->debugfs = NULL;
>+		}
>+		break;
>+
>+	case NETDEV_UP:
>+		sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
>+						    sky2_debug, dev,
>+						    &sky2_debug_fops);
>+		if (IS_ERR(sky2->debugfs))
>+			sky2->debugfs = NULL;
>+	}
>+
>+	return NOTIFY_DONE;
>+}
>+
>+static struct notifier_block sky2_notifier = {
>+	.notifier_call = sky2_device_event,
>+};
>+
>+
>+static __init void sky2_debug_init(void)
>+{
>+	struct dentry *ent;
>+
>+	ent = debugfs_create_dir("sky2", NULL);
>+	if (!ent || IS_ERR(ent))
>+		return;
>+
>+	sky2_debug = ent;
>+	register_netdevice_notifier(&sky2_notifier);
>+}
>+
>+static __exit void sky2_debug_cleanup(void)
>+{
>+	if (sky2_debug) {
>+		unregister_netdevice_notifier(&sky2_notifier);
>+		debugfs_remove(sky2_debug);
>+		sky2_debug = NULL;
>+	}
>+}
>+
>+#else
>+#define sky2_debug_init()
>+#define sky2_debug_cleanup()
>+#endif
>+
>+
> /* Initialize network device */
> static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
>-						     unsigned port, int highmem)
>+						     unsigned port,
>+						     int highmem, int wol)
> {
> 	struct sky2_port *sky2;
> 	struct net_device *dev = alloc_etherdev(sizeof(*sky2));
> 
> 	if (!dev) {
>-		printk(KERN_ERR "sky2 etherdev alloc failed");
>+		dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
> 		return NULL;
> 	}
> 
>-	SET_MODULE_OWNER(dev);
> 	SET_NETDEV_DEV(dev, &hw->pdev->dev);
> 	dev->irq = hw->pdev->irq;
> 	dev->open = sky2_up;
> 	dev->stop = sky2_down;
> 	dev->do_ioctl = sky2_ioctl;
> 	dev->hard_start_xmit = sky2_xmit_frame;
>-	dev->get_stats = sky2_get_stats;
> 	dev->set_multicast_list = sky2_set_multicast;
> 	dev->set_mac_address = sky2_set_mac_address;
> 	dev->change_mtu = sky2_change_mtu;
>@@ -3118,7 +4018,8 @@
> 		dev->poll = sky2_poll;
> 	dev->weight = NAPI_WEIGHT;
> #ifdef CONFIG_NET_POLL_CONTROLLER
>-	dev->poll_controller = sky2_netpoll;
>+	if (port == 0)
>+		dev->poll_controller = sky2_netpoll;
> #endif
> 
> 	sky2 = netdev_priv(dev);
>@@ -3126,36 +4027,35 @@
> 	sky2->hw = hw;
> 	sky2->msg_enable = netif_msg_init(debug, default_msg);
> 
>-	spin_lock_init(&sky2->tx_lock);
> 	/* Auto speed and flow control */
> 	sky2->autoneg = AUTONEG_ENABLE;
>-	sky2->tx_pause = 1;
>-	sky2->rx_pause = 1;
>+	sky2->flow_mode = FC_BOTH;
>+
> 	sky2->duplex = -1;
> 	sky2->speed = -1;
> 	sky2->advertising = sky2_supported_modes(hw);
>-	sky2->rx_csum = 1;
>+	sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
>+	sky2->wol = wol;
> 
> 	spin_lock_init(&sky2->phy_lock);
> 	sky2->tx_pending = TX_DEF_PENDING;
> 	sky2->rx_pending = RX_DEF_PENDING;
>-	sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
> 
> 	hw->dev[port] = dev;
> 
> 	sky2->port = port;
> 
>-	dev->features |= NETIF_F_LLTX;
>-	if (hw->chip_id != CHIP_ID_YUKON_EC_U)
>-		dev->features |= NETIF_F_TSO;
>+	dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
> 	if (highmem)
> 		dev->features |= NETIF_F_HIGHDMA;
>-	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
> 
> #ifdef SKY2_VLAN_TAG_USED
>-	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
>-	dev->vlan_rx_register = sky2_vlan_rx_register;
>-	dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
>+	/* The workaround for FE+ status conflicts with VLAN tag detection. */
>+	if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
>+	      sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
>+		dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
>+		dev->vlan_rx_register = sky2_vlan_rx_register;
>+	}
> #endif
> 
> 	/* read the mac address */
>@@ -3164,27 +4064,21 @@
> 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
> #endif
> 
>-	/* device is off until link detection */
>-	netif_carrier_off(dev);
>-	netif_stop_queue(dev);
>-
> 	return dev;
> }
> 
> static void __devinit sky2_show_addr(struct net_device *dev)
> {
> 	const struct sky2_port *sky2 = netdev_priv(dev);
>+	DECLARE_MAC_BUF(mac);
> 
> 	if (netif_msg_probe(sky2))
>-		printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
>-		       dev->name,
>-		       dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
>-		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
>+		printk(KERN_INFO PFX "%s: addr %s\n",
>+		       dev->name, print_mac(mac, dev->dev_addr));
> }
> 
> /* Handle software interrupt used during MSI test */
>-static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
>-					    struct pt_regs *regs)
>+static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
> {
> 	struct sky2_hw *hw = dev_id;
> 	u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
>@@ -3193,7 +4087,7 @@
> 		return IRQ_NONE;
> 
> 	if (status & Y2_IS_IRQ_SW) {
>-		hw->msi_detected = 1;
>+		hw->flags |= SKY2_HW_USE_MSI;
> 		wake_up(&hw->msi_wait);
> 		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
> 	}
>@@ -3208,96 +4102,94 @@
> 	struct pci_dev *pdev = hw->pdev;
> 	int err;
> 
>+	init_waitqueue_head (&hw->msi_wait);
>+
> 	sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
> 
>-	err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
>+	err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
> 	if (err) {
>-		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
>-		       pci_name(pdev), pdev->irq);
>+		dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
> 		return err;
> 	}
> 
>-	init_waitqueue_head (&hw->msi_wait);
>-
> 	sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
>-	wmb();
>+	sky2_read8(hw, B0_CTST);
> 
>-	wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
>+	wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
> 
>-	if (!hw->msi_detected) {
>+	if (!(hw->flags & SKY2_HW_USE_MSI)) {
> 		/* MSI test failed, go back to INTx mode */
>-		printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
>-		       "switching to INTx mode. Please report this failure to "
>-		       "the PCI maintainer and include system chipset information.\n",
>-		       pci_name(pdev));
>+		dev_info(&pdev->dev, "No interrupt generated using MSI, "
>+			 "switching to INTx mode.\n");
> 
> 		err = -EOPNOTSUPP;
> 		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
> 	}
> 
> 	sky2_write32(hw, B0_IMSK, 0);
>+	sky2_read32(hw, B0_IMSK);
> 
> 	free_irq(pdev->irq, hw);
> 
> 	return err;
> }
> 
>+static int __devinit pci_wake_enabled(struct pci_dev *dev)
>+{
>+	int pm  = pci_find_capability(dev, PCI_CAP_ID_PM);
>+	u16 value;
>+
>+	if (!pm)
>+		return 0;
>+	if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
>+		return 0;
>+	return value & PCI_PM_CTRL_PME_ENABLE;
>+}
>+
> static int __devinit sky2_probe(struct pci_dev *pdev,
> 				const struct pci_device_id *ent)
> {
>-	struct net_device *dev, *dev1 = NULL;
>+	struct net_device *dev;
> 	struct sky2_hw *hw;
>-	int err, pm_cap, using_dac = 0;
>+	int err, using_dac = 0, wol_default;
> 
> 	err = pci_enable_device(pdev);
> 	if (err) {
>-		printk(KERN_ERR PFX "%s cannot enable PCI device\n",
>-		       pci_name(pdev));
>+		dev_err(&pdev->dev, "cannot enable PCI device\n");
> 		goto err_out;
> 	}
> 
> 	err = pci_request_regions(pdev, DRV_NAME);
> 	if (err) {
>-		printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
>-		       pci_name(pdev));
>-		goto err_out;
>+		dev_err(&pdev->dev, "cannot obtain PCI resources\n");
>+		goto err_out_disable;
> 	}
> 
> 	pci_set_master(pdev);
> 
>-	/* Find power-management capability. */
>-	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
>-	if (pm_cap == 0) {
>-		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
>-		       "aborting.\n");
>-		err = -EIO;
>-		goto err_out_free_regions;
>-	}
>-
> 	if (sizeof(dma_addr_t) > sizeof(u32) &&
> 	    !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
> 		using_dac = 1;
> 		err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
> 		if (err < 0) {
>-			printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
>-			       "for consistent allocations\n", pci_name(pdev));
>+			dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
>+				"for consistent allocations\n");
> 			goto err_out_free_regions;
> 		}
>-
> 	} else {
> 		err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
> 		if (err) {
>-			printk(KERN_ERR PFX "%s no usable DMA configuration\n",
>-			       pci_name(pdev));
>+			dev_err(&pdev->dev, "no usable DMA configuration\n");
> 			goto err_out_free_regions;
> 		}
> 	}
> 
>+	wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
>+
> 	err = -ENOMEM;
> 	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
> 	if (!hw) {
>-		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
>-		       pci_name(pdev));
>+		dev_err(&pdev->dev, "cannot allocate hardware struct\n");
> 		goto err_out_free_regions;
> 	}
> 
>@@ -3305,61 +4197,42 @@
> 
> 	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
> 	if (!hw->regs) {
>-		printk(KERN_ERR PFX "%s: cannot map device registers\n",
>-		       pci_name(pdev));
>+		dev_err(&pdev->dev, "cannot map device registers\n");
> 		goto err_out_free_hw;
> 	}
>-	hw->pm_cap = pm_cap;
> 
> #ifdef __BIG_ENDIAN
>-	/* byte swap descriptors in hardware */
>+	/* The sk98lin vendor driver uses hardware byte swapping but
>+	 * this driver uses software swapping.
>+	 */
> 	{
> 		u32 reg;
>-
> 		reg = sky2_pci_read32(hw, PCI_DEV_REG2);
>-		reg |= PCI_REV_DESC;
>+		reg &= ~PCI_REV_DESC;
> 		sky2_pci_write32(hw, PCI_DEV_REG2, reg);
> 	}
> #endif
> 
> 	/* ring for status responses */
>-	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
>-					 &hw->st_dma);
>+	hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
> 	if (!hw->st_le)
> 		goto err_out_iounmap;
> 
>-	err = sky2_reset(hw);
>+	err = sky2_init(hw);
> 	if (err)
> 		goto err_out_iounmap;
> 
>-	printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
>+	dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
> 	       DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
> 	       pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
> 	       hw->chip_id, hw->chip_rev);
> 
>-	dev = sky2_init_netdev(hw, 0, using_dac);
>-	if (!dev)
>-		goto err_out_free_pci;
>+	sky2_reset(hw);
> 
>-	err = register_netdev(dev);
>-	if (err) {
>-		printk(KERN_ERR PFX "%s: cannot register net device\n",
>-		       pci_name(pdev));
>-		goto err_out_free_netdev;
>-	}
>-
>-	sky2_show_addr(dev);
>-
>-	if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
>-		if (register_netdev(dev1) == 0)
>-			sky2_show_addr(dev1);
>-		else {
>-			/* Failure to register second port need not be fatal */
>-			printk(KERN_WARNING PFX
>-			       "register of second port failed\n");
>-			hw->dev[1] = NULL;
>-			free_netdev(dev1);
>-		}
>+	dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
>+	if (!dev) {
>+		err = -ENOMEM;
>+		goto err_out_free_pci;
> 	}
> 
> 	if (!disable_msi && pci_enable_msi(pdev) == 0) {
>@@ -3367,81 +4240,103 @@
> 		if (err == -EOPNOTSUPP)
>  			pci_disable_msi(pdev);
> 		else if (err)
>-			goto err_out_unregister;
>+			goto err_out_free_netdev;
>  	}
> 
>-	err = request_irq(pdev->irq,  sky2_intr, SA_SHIRQ, DRV_NAME, hw);
>+	err = register_netdev(dev);
> 	if (err) {
>-		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
>-		       pci_name(pdev), pdev->irq);
>-		goto err_out_unregister;
>+		dev_err(&pdev->dev, "cannot register net device\n");
>+		goto err_out_free_netdev;
> 	}
> 
>+	err = request_irq(pdev->irq, sky2_intr,
>+			  (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
>+			  dev->name, hw);
>+	if (err) {
>+		dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
>+		goto err_out_unregister;
>+	}
> 	sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
>+	netif_poll_enable(hw->dev[0]);
>+
>+	sky2_show_addr(dev);
> 
>-	setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
>-	sky2_idle_start(hw);
>+	if (hw->ports > 1) {
>+		struct net_device *dev1;
>+
>+		dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
>+		if (!dev1)
>+			dev_warn(&pdev->dev, "allocation for second device failed\n");
>+		else if ((err = register_netdev(dev1))) {
>+			dev_warn(&pdev->dev,
>+				 "register of second port failed (%d)\n", err);
>+			hw->dev[1] = NULL;
>+			free_netdev(dev1);
>+		} else
>+			sky2_show_addr(dev1);
>+	}
>+
>+	setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
>+	INIT_WORK(&hw->restart_work, sky2_restart);
> 
> 	pci_set_drvdata(pdev, hw);
> 
> 	return 0;
> 
> err_out_unregister:
>-	pci_disable_msi(pdev);
>-	if (dev1) {
>-		unregister_netdev(dev1);
>-		free_netdev(dev1);
>-	}
>+	if (hw->flags & SKY2_HW_USE_MSI)
>+		pci_disable_msi(pdev);
> 	unregister_netdev(dev);
> err_out_free_netdev:
> 	free_netdev(dev);
> err_out_free_pci:
> 	sky2_write8(hw, B0_CTST, CS_RST_SET);
>-	pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
>+	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
> err_out_iounmap:
> 	iounmap(hw->regs);
> err_out_free_hw:
> 	kfree(hw);
> err_out_free_regions:
> 	pci_release_regions(pdev);
>+err_out_disable:
> 	pci_disable_device(pdev);
> err_out:
>+	pci_set_drvdata(pdev, NULL);
> 	return err;
> }
> 
> static void __devexit sky2_remove(struct pci_dev *pdev)
> {
> 	struct sky2_hw *hw = pci_get_drvdata(pdev);
>-	struct net_device *dev0, *dev1;
>+	int i;
> 
> 	if (!hw)
> 		return;
> 
>-	del_timer_sync(&hw->idle_timer);
>+	del_timer_sync(&hw->watchdog_timer);
>+	flush_scheduled_work();
>+
>+	for (i = hw->ports-1; i >= 0; --i)
>+		unregister_netdev(hw->dev[i]);
> 
> 	sky2_write32(hw, B0_IMSK, 0);
>-	synchronize_irq(hw->pdev->irq);
> 
>-	dev0 = hw->dev[0];
>-	dev1 = hw->dev[1];
>-	if (dev1)
>-		unregister_netdev(dev1);
>-	unregister_netdev(dev0);
>+	sky2_power_aux(hw);
> 
>-	sky2_set_power_state(hw, PCI_D3hot);
> 	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
> 	sky2_write8(hw, B0_CTST, CS_RST_SET);
> 	sky2_read8(hw, B0_CTST);
> 
> 	free_irq(pdev->irq, hw);
>-	pci_disable_msi(pdev);
>+	if (hw->flags & SKY2_HW_USE_MSI)
>+		pci_disable_msi(pdev);
> 	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
> 	pci_release_regions(pdev);
> 	pci_disable_device(pdev);
> 
>-	if (dev1)
>-		free_netdev(dev1);
>-	free_netdev(dev0);
>+	for (i = hw->ports-1; i >= 0; --i)
>+		free_netdev(hw->dev[i]);
>+
> 	iounmap(hw->regs);
> 	kfree(hw);
> 
>@@ -3452,27 +4347,34 @@
> static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
> {
> 	struct sky2_hw *hw = pci_get_drvdata(pdev);
>-	int i;
>-	pci_power_t pstate = pci_choose_state(pdev, state);
>+	int i, wol = 0;
> 
>-	if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
>-		return -EINVAL;
>+	if (!hw)
>+		return 0;
> 
>-	del_timer_sync(&hw->idle_timer);
> 	netif_poll_disable(hw->dev[0]);
> 
> 	for (i = 0; i < hw->ports; i++) {
> 		struct net_device *dev = hw->dev[i];
>+		struct sky2_port *sky2 = netdev_priv(dev);
> 
>-		if (netif_running(dev)) {
>+		if (netif_running(dev))
> 			sky2_down(dev);
>-			netif_device_detach(dev);
>-		}
>+
>+		if (sky2->wol)
>+			sky2_wol_init(sky2);
>+
>+		wol |= sky2->wol;
> 	}
> 
> 	sky2_write32(hw, B0_IMSK, 0);
>+	netif_poll_disable(hw->dev[0]);
>+	sky2_power_aux(hw);
>+
> 	pci_save_state(pdev, hw->pci_cfg_state);
>-	sky2_set_power_state(hw, pstate);
>+	pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
>+	pci_set_power_state(pdev, pci_choose_state(pdev, state));
>+
> 	return 0;
> }
> 
>@@ -3481,21 +4383,31 @@
> 	struct sky2_hw *hw = pci_get_drvdata(pdev);
> 	int i, err;
> 
>-	pci_restore_state(pdev, hw->pci_cfg_state);
>-	pci_enable_wake(pdev, PCI_D0, 0);
>-	sky2_set_power_state(hw, PCI_D0);
>+	if (!hw)
>+		return 0;
> 
>-	err = sky2_reset(hw);
>+	err = pci_set_power_state(pdev, PCI_D0);
> 	if (err)
> 		goto out;
> 
>+	err = pci_restore_state(pdev, hw->pci_cfg_state);
>+	if (err)
>+		goto out;
>+
>+	pci_enable_wake(pdev, PCI_D0, 0);
>+
>+	/* Re-enable all clocks */
>+	if (hw->chip_id == CHIP_ID_YUKON_EX ||
>+	    hw->chip_id == CHIP_ID_YUKON_EC_U ||
>+	    hw->chip_id == CHIP_ID_YUKON_FE_P)
>+		sky2_pci_write32(hw, PCI_DEV_REG3, 0);
>+
>+	sky2_reset(hw);
> 	sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
> 
> 	for (i = 0; i < hw->ports; i++) {
> 		struct net_device *dev = hw->dev[i];
> 		if (netif_running(dev)) {
>-			netif_device_attach(dev);
>-
> 			err = sky2_up(dev);
> 			if (err) {
> 				printk(KERN_ERR PFX "%s: could not up: %d\n",
>@@ -3507,12 +4419,46 @@
> 	}
> 
> 	netif_poll_enable(hw->dev[0]);
>-	sky2_idle_start(hw);
>+
>+	return 0;
> out:
>+	dev_err(&pdev->dev, "resume failed (%d)\n", err);
>+	pci_disable_device(pdev);
> 	return err;
> }
> #endif
> 
>+static void sky2_shutdown(struct pci_dev *pdev)
>+{
>+	struct sky2_hw *hw = pci_get_drvdata(pdev);
>+	int i, wol = 0;
>+
>+	if (!hw)
>+		return;
>+
>+	del_timer_sync(&hw->watchdog_timer);
>+
>+	for (i = 0; i < hw->ports; i++) {
>+		struct net_device *dev = hw->dev[i];
>+		struct sky2_port *sky2 = netdev_priv(dev);
>+
>+		if (sky2->wol) {
>+			wol = 1;
>+			sky2_wol_init(sky2);
>+		}
>+	}
>+
>+	if (wol)
>+		sky2_power_aux(hw);
>+
>+	pci_enable_wake(pdev, PCI_D3hot, wol);
>+	pci_enable_wake(pdev, PCI_D3cold, wol);
>+
>+	pci_disable_device(pdev);
>+	pci_set_power_state(pdev, PCI_D3hot);
>+
>+}
>+
> static struct pci_driver sky2_driver = {
> 	.name = DRV_NAME,
> 	.id_table = sky2_id_table,
>@@ -3526,18 +4472,20 @@
> 
> static int __init sky2_init_module(void)
> {
>+	sky2_debug_init();
> 	return pci_register_driver(&sky2_driver);
> }
> 
> static void __exit sky2_cleanup_module(void)
> {
> 	pci_unregister_driver(&sky2_driver);
>+	sky2_debug_cleanup();
> }
> 
> module_init(sky2_init_module);
> module_exit(sky2_cleanup_module);
> 
> MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
>-MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
>+MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
> MODULE_LICENSE("GPL");
> MODULE_VERSION(DRV_VERSION);

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Attachments on bug 216799: 143079 | 143081 | 302651