Attachment 302760 Details for Bug 230717 – use PCI power management to reset the controller

[patch] use PCI power management to reset the controller

cciss.patch (text/plain), 6.74 KB, created by Chip Coldwell on 2008-04-17 15:15:19 UTC

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Creator: Chip Coldwell

Created: 2008-04-17 15:15:19 UTC

Size: 6.74 KB

patch

obsolete

>diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
>index 6dc22bf..132a2ce 100644
>--- a/drivers/block/cciss.c
>+++ b/drivers/block/cciss.c
>@@ -3286,6 +3286,199 @@ static void free_hba(int i)
> 	kfree(p);
> }
> 
>+/* Reset the controller by sending a "Reset Controller" message CDB
>+   to the firmware.  This is effectively a soft reset. */
>+
>+static int __devinit cciss_reset_controller(struct pci_dev *pdev)
>+{
>+	typedef struct {
>+		CommandListHeader_struct CommandHeader;
>+		RequestBlock_struct Request;
>+		ErrDescriptor_struct ErrorDescriptor;
>+	} Command;
>+	static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
>+	Command *cmd;
>+	ErrorInfo_struct *errinfo;
>+	dma_addr_t paddr64;
>+	unsigned long paddr32, tag;
>+	void __iomem *vaddr;
>+	int i, err;
>+
>+	printk(KERN_INFO "cciss: sending Reset Controller message to firmware\n");
>+
>+	vaddr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
>+	if (vaddr == NULL)
>+		return -ENOMEM;
>+
>+	/* The Inbound Post Queue only accepts 32-bit physical addresses for the
>+	   CCISS commands, so they must be allocated from the lower 4GiB of
>+	   memory. */
>+	err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
>+	if (err) {
>+		iounmap(vaddr);
>+		return -ENOMEM;
>+	}
>+
>+	cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
>+	if (cmd == NULL) {
>+		iounmap(vaddr);
>+		return -ENOMEM;
>+	}
>+	errinfo = (ErrorInfo_struct *)(cmd + 1);
>+	memset(errinfo, -1, sizeof(err));
>+
>+	/* This must fit, because of the 32-bit consistent DMA mask.  Also,
>+	   although there's no guarantee, we assume that the address is at
>+	   least 4-byte aligned (most likely, it's page-aligned). */
>+	paddr32 = paddr64;
>+
>+	cmd->CommandHeader.ReplyQueue = 0;
>+	cmd->CommandHeader.SGList = 0;
>+	cmd->CommandHeader.SGTotal = 0;
>+	cmd->CommandHeader.Tag.lower = paddr32;
>+	cmd->CommandHeader.Tag.upper = 0;
>+	memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
>+
>+	cmd->Request.CDBLen = 16;
>+	cmd->Request.Type.Type = 1; /* Message */
>+	cmd->Request.Type.Attribute = 5; /* Head of Queue */
>+	cmd->Request.Type.Direction = 0; /* Direction: none */
>+	cmd->Request.Timeout = 0; /* Don't time out */
>+	cmd->Request.CDB[0] = 0x01; /* Reset message */
>+	cmd->Request.CDB[1] = 0x00; /* Reset controller */
>+	memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
>+
>+	cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
>+	cmd->ErrorDescriptor.Addr.upper = 0;
>+	cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
>+
>+	writel(paddr32, vaddr + 0x40);
>+
>+	for (i = 0; i < 10; i++) {
>+		tag = readl(vaddr + 0x44);
>+		if ((tag & ~3) == paddr32)
>+			break;
>+		set_current_state(TASK_UNINTERRUPTIBLE);
>+		schedule_timeout(HZ >> 1);
>+	}
>+
>+	pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
>+	iounmap(vaddr);
>+
>+	if (i == 10 || (tag & 2)) {
>+		printk(KERN_ERR "cciss: controller soft reset failed\n");
>+		return -ENODEV;
>+	} else 
>+		printk(KERN_INFO "cciss: controller soft reset succeeded\n");
>+		
>+	return 0;
>+}
>+
>+static int cciss_reset_msi(struct pci_dev *pdev)
>+{
>+/* the #defines are stolen from drivers/pci/msi.h. */
>+#define msi_control_reg(base)		(base + PCI_MSI_FLAGS)
>+#define PCI_MSIX_FLAGS_ENABLE		(1 << 15)
>+
>+	int pos;
>+	u16 control = 0;
>+
>+	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
>+	if (pos) {
>+		pci_read_config_word(pdev, msi_control_reg(pos), &control);
>+		if (control & PCI_MSI_FLAGS_ENABLE) {
>+			printk(KERN_INFO "cciss: resetting MSI\n");
>+			pci_write_config_word(pdev, msi_control_reg(pos), control & ~PCI_MSI_FLAGS_ENABLE);
>+		}
>+	}
>+
>+	pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
>+	if (pos) {
>+		pci_read_config_word(pdev, msi_control_reg(pos), &control);
>+		if (control & PCI_MSIX_FLAGS_ENABLE) {
>+			printk(KERN_INFO "cciss: resetting MSI-X\n");
>+			pci_write_config_word(pdev, msi_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE);
>+		}
>+	}
>+
>+	return 0;
>+}
>+
>+/* This does a hard reset of the controller using PCI power management
>+ * states. */
>+static int cciss_hard_reset_controller(struct pci_dev *pdev)
>+{
>+	u16 pmcsr, saved_config_space[32];
>+	int i, pos;
>+
>+	printk(KERN_INFO "cciss: using PCI PM to reset controller\n");
>+
>+	/* This is very nearly the same thing as
>+
>+	   pci_save_state(pci_dev);
>+	   pci_set_power_state(pci_dev, PCI_D3hot);
>+	   pci_set_power_state(pci_dev, PCI_D0);
>+	   pci_restore_state(pci_dev);
>+
>+	   but we can't use these nice canned kernel routines on
>+	   kexec, because they also check the MSI/MSI-X state in PCI
>+	   configuration space and do the wrong thing when it is
>+	   set/cleared.  Also, the pci_save/restore_state functions
>+	   violate the ordering requirements for restoring the
>+	   configuration space from the CCISS document (see the
>+	   comment below).  So we roll our own .... */
>+
>+	for (i = 0; i < 32; i++)
>+		pci_read_config_word(pdev, 2*i, &saved_config_space[i]);
>+
>+	pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
>+	if (pos == 0) {
>+		printk(KERN_ERR "cciss_reset_controller: PCI PM not supported\n");
>+		return -ENODEV;
>+	}
>+
>+	/* Quoting from the Open CISS Specification: "The Power
>+	 * Management Control/Status Register (CSR) controls the power
>+	 * state of the device.  The normal operating state is D0,
>+	 * CSR=00h.  The software off state is D3, CSR=03h.  To reset
>+	 * the controller, place the interface device in D3 then to
>+	 * D0, this causes a secondary PCI reset which will reset the
>+	 * controller." */
>+
>+	/* enter the D3hot power management state */
>+	pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
>+	pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
>+	pmcsr |= PCI_D3hot;
>+	pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
>+
>+	set_current_state(TASK_UNINTERRUPTIBLE);
>+	schedule_timeout(HZ >> 1);
>+
>+	/* enter the D0 power management state */
>+	pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
>+	pmcsr |= PCI_D0;
>+	pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
>+
>+	set_current_state(TASK_UNINTERRUPTIBLE);
>+	schedule_timeout(HZ >> 1);
>+
>+	/* Restore the PCI configuration space.  The Open CISS
>+	 * Specification says, "Restore the PCI Configuration
>+	 * Registers, offsets 00h through 60h. It is important to
>+	 * restore the command register, 16-bits at offset 04h,
>+	 * last. Do not restore the configuration status register,
>+	 * 16-bits at offset 06h."  Note that the offset is 2*i. */
>+	for (i = 0; i < 32; i++) {
>+		if (i == 2 || i == 3)
>+			continue;
>+		pci_write_config_word(pdev, 2*i, saved_config_space[i]);
>+	}
>+	wmb();
>+	pci_write_config_word(pdev, 4, saved_config_space[2]);
>+
>+	return 0;
>+}
>+
> /*
>  *  This is it.  Find all the controllers and register them.  I really hate
>  *  stealing all these major device numbers.
>@@ -3299,6 +3492,12 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
> 	int rc;
> 	int dac;
> 
>+	if (reset_devices) {
>+		if (cciss_hard_reset_controller(pdev) ||
>+		    cciss_reset_msi(pdev))
>+			return -ENODEV;
>+	}
>+
> 	i = alloc_cciss_hba();
> 	if (i < 0)
> 		return -1;

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Attachments on bug 230717: 149128 | 149208 | 292178 | 293393 | 293602 | 293604 | 294226 | 298090 | 298451 | 298533 | 298806 | 299186 | 299200 | 302760 | 302938 | 303074