Attachment 309737 Details for Bug 451593 – a back port

[patch] a back port

451593.patch (text/plain), 8.92 KB, created by Luming Yu on 2008-06-18 14:24:58 UTC

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Creator: Luming Yu

Created: 2008-06-18 14:24:58 UTC

Size: 8.92 KB

patch

obsolete

>diff -Bru 0/arch/ia64/kernel/efi.c 1/arch/ia64/kernel/efi.c
>--- 0/arch/ia64/kernel/efi.c	2008-06-18 00:33:09.000000000 -0400
>+++ 1/arch/ia64/kernel/efi.c	2008-06-18 01:26:36.000000000 -0400
>@@ -34,6 +34,7 @@
> #include <asm/pgtable.h>
> #include <asm/processor.h>
> #include <asm/mca.h>
>+#include <asm/tlbflush.h>
> 
> #define EFI_DEBUG	0
> 
>@@ -385,6 +386,41 @@
> 	return NULL;
> }
> 
>+
>+static u8 __init palo_checksum(u8 *buffer, u32 length)
>+{
>+	u8 sum = 0;
>+	u8 *end = buffer + length;
>+
>+	while (buffer < end)
>+		sum = (u8) (sum + *(buffer++));
>+
>+	return sum;
>+}
>+
>+/*
>+ * Parse and handle PALO table which is published at:
>+ * http://www.dig64.org/home/DIG64_PALO_R1_0.pdf
>+ */
>+static void __init handle_palo(unsigned long palo_phys)
>+{
>+	struct palo_table *palo = __va(palo_phys);
>+	u8  checksum;
>+
>+	if (strncmp(palo->signature, PALO_SIG, sizeof(PALO_SIG) - 1)) {
>+		printk(KERN_INFO "PALO signature incorrect.\n");
>+		return;
>+	}
>+
>+	checksum = palo_checksum((u8 *)palo, palo->length);
>+	if (checksum) {
>+		printk(KERN_INFO "PALO checksum incorrect.\n");
>+		return;
>+	}
>+
>+	setup_ptcg_sem(palo->max_tlb_purges, 1);
>+}
>+
> void
> efi_map_pal_code (void)
> {
>@@ -415,6 +451,7 @@
> 	char *cp, vendor[100] = "unknown";
> 	extern char saved_command_line[];
> 	int i;
>+	unsigned long palo_phys;
> 
> 	/* it's too early to be able to use the standard kernel command line support... */
> 	for (cp = saved_command_line; *cp; ) {
>@@ -473,6 +510,8 @@
> 	efi.hcdp       = EFI_INVALID_TABLE_ADDR;
> 	efi.uga        = EFI_INVALID_TABLE_ADDR;
> 
>+	palo_phys      = EFI_INVALID_TABLE_ADDR;
>+
> 	for (i = 0; i < (int) efi.systab->nr_tables; i++) {
> 		if (efi_guidcmp(config_tables[i].guid, MPS_TABLE_GUID) == 0) {
> 			efi.mps = config_tables[i].table;
>@@ -492,10 +531,17 @@
> 		} else if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) {
> 			efi.hcdp = config_tables[i].table;
> 			printk(" HCDP=0x%lx", config_tables[i].table);
>+		} else if (efi_guidcmp(config_tables[i].guid,
>+			 PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID) == 0) {
>+			palo_phys = config_tables[i].table;
>+			printk(" PALO=0x%lx", config_tables[i].table);
> 		}
> 	}
> 	printk("\n");
> 
>+	if (palo_phys != EFI_INVALID_TABLE_ADDR)
>+		handle_palo(palo_phys);
>+
> 	runtime = __va(efi.systab->runtime);
> 	efi.get_time = phys_get_time;
> 	efi.set_time = phys_set_time;
>diff -Bru 0/arch/ia64/kernel/setup.c 1/arch/ia64/kernel/setup.c
>--- 0/arch/ia64/kernel/setup.c	2008-06-18 00:33:09.000000000 -0400
>+++ 1/arch/ia64/kernel/setup.c	2008-06-18 01:26:36.000000000 -0400
>@@ -60,6 +60,7 @@
> #include <asm/setup.h>
> #include <asm/smp.h>
> #include <asm/system.h>
>+#include <asm/tlbflush.h>
> #include <asm/unistd.h>
> #include <asm/system.h>
> #include <asm/kexec.h>
>@@ -1035,9 +1036,10 @@
> #endif
> 
> 	/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
>-	if (ia64_pal_vm_summary(NULL, &vmi) == 0)
>+	if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
> 		max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
>-	else {
>+		setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, 0);
>+	} else {
> 		printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
> 		max_ctx = (1U << 15) - 1;	/* use architected minimum */
> 	}
>diff -Bru 0/arch/ia64/mm/tlb.c 1/arch/ia64/mm/tlb.c
>--- 0/arch/ia64/mm/tlb.c	2008-06-18 00:33:09.000000000 -0400
>+++ 1/arch/ia64/mm/tlb.c	2008-06-18 01:40:19.000000000 -0400
>@@ -10,6 +10,9 @@
>  *              IPI based ptc implementation and A-step IPI implementation.
>  * Rohit Seth <rohit.seth@intel.com>
>  * Ken Chen <kenneth.w.chen@intel.com>
>+ * Copyright (C) 2007 Intel Corp
>+ *	Fenghua Yu <fenghua.yu@intel.com>
>+ *	Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
>  */
> #include <linux/module.h>
> #include <linux/init.h>
>@@ -25,6 +28,7 @@
> #include <asm/pal.h>
> #include <asm/tlbflush.h>
> #include <asm/dma.h>
>+#include <asm/sal.h>
> 
> static struct {
> 	unsigned long mask;	/* mask of supported purge page-sizes */
>@@ -83,30 +87,123 @@
> 	local_flush_tlb_all();
> }
> 
>+/*
>+ * Implement "spinaphores" ... like counting semaphores, but they
>+ * spin instead of sleeping.  If there are ever any other users for
>+ * this primitive it can be moved up to a spinaphore.h header.
>+ */
>+struct spinaphore {
>+ 	atomic_t	cur;
>+};
>+ 
>+static inline void spinaphore_init(struct spinaphore *ss, int val)
>+{
>+	atomic_set(&ss->cur, val);
>+}
>+ 
>+static inline void down_spin(struct spinaphore *ss)
>+{
>+	while (unlikely(!atomic_add_unless(&ss->cur, -1, 0)))
>+		while (atomic_read(&ss->cur) == 0)
>+			cpu_relax();
>+}
>+
>+static inline void up_spin(struct spinaphore *ss)
>+{
>+	atomic_add(1, &ss->cur);
>+}
>+
>+static struct spinaphore ptcg_sem;
>+static u16 nptcg = 1;
>+static int need_ptcg_sem = 1;
>+static int toolatetochangeptcgsem = 0;
>+
>+/*
>+ * Maximum number of simultaneous ptc.g purges in the system can
>+ * be defined by PAL_VM_SUMMARY (in which case we should take
>+ * the smallest value for any cpu in the system) or by the PAL
>+ * override table (in which case we should ignore the value from
>+ * PAL_VM_SUMMARY).
>+ *
>+ * Complicating the logic here is the fact that num_possible_cpus()
>+ * isn't fully setup until we start bringing cpus online.
>+ */
>+void
>+setup_ptcg_sem(int max_purges, int from_palo)
>+{
>+	static int have_palo;
>+	static int firstcpu = 1;
>+ 
>+	if (toolatetochangeptcgsem) {
>+		BUG_ON(max_purges < nptcg);
>+		return;
>+	}
>+
>+	if (from_palo) {
>+		have_palo = 1;
>+
>+		/* In PALO max_purges == 0 really means it! */
>+		if (max_purges == 0)
>+			panic("Whoa! Platform does not support global TLB purges.\n");
>+		nptcg = max_purges;
>+		if (nptcg == PALO_MAX_TLB_PURGES) {
>+			need_ptcg_sem = 0;
>+			return;
>+		}
>+		goto resetsema;
>+	}
>+	if (have_palo) {
>+		if (nptcg != PALO_MAX_TLB_PURGES)
>+			need_ptcg_sem = (num_possible_cpus() > nptcg);
>+		return;
>+	}
>+
>+	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
>+	if (max_purges == 0) max_purges = 1;
>+
>+	if (firstcpu) {
>+		nptcg = max_purges;
>+		firstcpu = 0;
>+	}
>+	if (max_purges < nptcg)
>+		nptcg = max_purges;
>+	if (nptcg == PAL_MAX_PURGES) {
>+		need_ptcg_sem = 0;
>+		return;
>+	} else
>+		need_ptcg_sem = (num_possible_cpus() > nptcg);
>+
>+resetsema:
>+	spinaphore_init(&ptcg_sem, max_purges);
>+}
>+
> void
> ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
> 		       unsigned long end, unsigned long nbits)
> {
>-	static DEFINE_SPINLOCK(ptcg_lock);
>+ 
>+	toolatetochangeptcgsem = 1;
> 
> 	if (mm != current->active_mm || !current->mm) {
> 		flush_tlb_all();
> 		return;
> 	}
> 
>-	/* HW requires global serialization of ptc.ga.  */
>-	spin_lock(&ptcg_lock);
>-	{
>-		do {
>-			/*
>-			 * Flush ALAT entries also.
>-			 */
>-			ia64_ptcga(start, (nbits<<2));
>-			ia64_srlz_i();
>-			start += (1UL << nbits);
>-		} while (start < end);
>-	}
>-	spin_unlock(&ptcg_lock);
>+	if (need_ptcg_sem)
>+		down_spin(&ptcg_sem);
>+
>+	do {
>+		/*
>+		 * Flush ALAT entries also.
>+		 */
>+		ia64_ptcga(start, (nbits << 2));
>+		ia64_srlz_i();
>+		start += (1UL << nbits);
>+	} while (start < end);
>+
>+	if (need_ptcg_sem)
>+		up_spin(&ptcg_sem);
>+  
> }
> 
> void
>diff -Bru 0/include/asm-ia64/pal.h 1/include/asm-ia64/pal.h
>--- 0/include/asm-ia64/pal.h	2008-06-18 00:33:24.000000000 -0400
>+++ 1/include/asm-ia64/pal.h	2008-06-18 01:56:56.000000000 -0400
>@@ -1525,12 +1525,15 @@
> 	} pal_vm_info_1_s;
> } pal_vm_info_1_u_t;
> 
>+#define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
>+
> typedef union pal_vm_info_2_u {
> 	u64			pvi2_val;
> 	struct {
> 		u64		impl_va_msb	: 8,
> 				rid_size	: 8,
>-				reserved	: 48;
>+                                max_purges      : 16,
>+				reserved	: 32;
> 	} pal_vm_info_2_s;
> } pal_vm_info_2_u_t;
> 
>diff -Bru 0/include/asm-ia64/sal.h 1/include/asm-ia64/sal.h
>--- 0/include/asm-ia64/sal.h	2008-06-18 00:33:24.000000000 -0400
>+++ 1/include/asm-ia64/sal.h	2008-06-18 01:26:36.000000000 -0400
>@@ -299,6 +299,9 @@
>     EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
> #define SAL_PLAT_BUS_ERR_SECT_GUID  \
>     EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
>+#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
>+    EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
>+		0xca, 0x4d)
> 
> #define MAX_CACHE_ERRORS	6
> #define MAX_TLB_ERRORS		6
>@@ -902,6 +905,20 @@
> 
> extern void ia64_sal_handler_init(void *entry_point, void *gpval);
> 
>+#define PALO_MAX_TLB_PURGES	0xFFFF
>+#define PALO_SIG	"PALO"
>+
>+struct palo_table {
>+	u8  signature[4];	/* Should be "PALO" */
>+	u32 length;
>+	u8  minor_revision;
>+	u8  major_revision;
>+	u8  checksum;
>+	u8  reserved1[5];
>+	u16 max_tlb_purges;
>+	u8  reserved2[6];
>+};
>+
> #endif /* __ASSEMBLY__ */
> 
> #endif /* _ASM_IA64_SAL_H */
>diff -Bru 0/include/asm-ia64/tlbflush.h 1/include/asm-ia64/tlbflush.h
>--- 0/include/asm-ia64/tlbflush.h	2008-06-18 00:33:24.000000000 -0400
>+++ 1/include/asm-ia64/tlbflush.h	2008-06-18 01:26:36.000000000 -0400
>@@ -17,6 +17,7 @@
>  * Now for some TLB flushing routines.  This is the kind of stuff that
>  * can be very expensive, so try to avoid them whenever possible.
>  */
>+extern void setup_ptcg_sem(int max_purges, int from_palo);
> 
> /*
>  * Flush everything (kernel mapping may also have changed due to

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Attachments on bug 451593: 309737