Attachment 314654 Details for Bug 459644 – RHEL-5 version of the patch

[patch] RHEL-5 version of the patch

perfctr-fix_ht_p4.patch (text/plain), 1.33 KB, created by Aristeu Rozanski on 2008-08-20 19:54:56 UTC

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Creator: Aristeu Rozanski

Created: 2008-08-20 19:54:56 UTC

Size: 1.33 KB

patch

obsolete

>perfctr-watchdog: don't use CCCR_OVF_PMI1 on Pentium 4 D's
>
>https://bugzilla.redhat.com/show_bug.cgi?id=447618
>
>Currently, setup_p4_watchdog() use CCCR_OVF_PMI1 to enable the counter
>overflow interrupts to the second logical core. But this bit doesn't work
>on Pentium 4 Ds (model 4, stepping 4) and this patch avoids its use on
>these processors. Tested on 4 different machines that have this
>specific model with success.
>
>Tested on Dave's box (where the problem was found) and other similar
>Pentium 4 Ds in RHTS.
>
>Upstream: Ingo merged it on his tip/x86/urgent tree
>
>---
> arch/x86_64/kernel/perfctr-watchdog.c |    8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>--- tree.orig/arch/x86_64/kernel/perfctr-watchdog.c	2008-08-20 10:29:21.000000000 -0400
>+++ tree/arch/x86_64/kernel/perfctr-watchdog.c	2008-08-20 11:02:33.000000000 -0400
>@@ -473,7 +473,13 @@ static int setup_p4_watchdog(unsigned nm
> 		perfctr_msr = MSR_P4_IQ_PERFCTR1;
> 		evntsel_msr = MSR_P4_CRU_ESCR0;
> 		cccr_msr = MSR_P4_IQ_CCCR1;
>-		cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
>+
>+		/* Pentium 4 D processors don't support P4_CCCR_OVF_PMI1 */
>+		if (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask == 4)
>+			cccr_val = P4_CCCR_OVF_PMI0;
>+		else
>+			cccr_val = P4_CCCR_OVF_PMI1;
>+		cccr_val |= P4_CCCR_ESCR_SELECT(4);
> 	}
> 
> 	evntsel = P4_ESCR_EVENT_SELECT(0x3F)

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