Attachment 317617 Details for Bug 463276 – RHEL5 version of the patch

[patch] RHEL5 version of the patch

perfct-zero_p4_perfctr_regs_on_kdump_kernel.patch (text/plain), 1.73 KB, created by Aristeu Rozanski on 2008-09-24 19:53:57 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Aristeu Rozanski

Created: 2008-09-24 19:53:57 UTC

Size: 1.73 KB

patch

obsolete

>---
> arch/x86_64/kernel/perfctr-watchdog.c |   41 ++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
>--- tree.orig/arch/x86_64/kernel/perfctr-watchdog.c	2008-09-22 16:32:47.000000000 -0400
>+++ tree/arch/x86_64/kernel/perfctr-watchdog.c	2008-09-22 16:33:48.000000000 -0400
>@@ -219,6 +219,27 @@ void enable_lapic_nmi_watchdog(void)
> 	touch_nmi_watchdog();
> }
> 
>+#define P4_CONTROLS 18
>+static unsigned int p4_controls[18] = {
>+	MSR_P4_BPU_CCCR0,
>+	MSR_P4_BPU_CCCR1,
>+	MSR_P4_BPU_CCCR2,
>+	MSR_P4_BPU_CCCR3,
>+	MSR_P4_MS_CCCR0,
>+	MSR_P4_MS_CCCR1,
>+	MSR_P4_MS_CCCR2,
>+	MSR_P4_MS_CCCR3,
>+	MSR_P4_FLAME_CCCR0,
>+	MSR_P4_FLAME_CCCR1,
>+	MSR_P4_FLAME_CCCR2,
>+	MSR_P4_FLAME_CCCR3,
>+	MSR_P4_IQ_CCCR0,
>+	MSR_P4_IQ_CCCR1,
>+	MSR_P4_IQ_CCCR2,
>+	MSR_P4_IQ_CCCR3,
>+	MSR_P4_IQ_CCCR4,
>+	MSR_P4_IQ_CCCR5,
>+};
> /*
>  * Activate the NMI watchdog via the local APIC.
>  */
>@@ -468,6 +489,26 @@ static int setup_p4_watchdog(unsigned nm
> 		evntsel_msr = MSR_P4_CRU_ESCR0;
> 		cccr_msr = MSR_P4_IQ_CCCR0;
> 		cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
>+
>+		/*
>+		 * If we're on the kdump kernel or other situation, we may
>+		 * still have other performance counter registers set to
>+		 * interrupt and they'll keep interrupting forever because
>+		 * of the P4_CCCR_OVF quirk. So we need to ACK all the
>+		 * pending interrupts and disable all the registers here,
>+		 * before reenabling the NMI delivery. Refer to p4_rearm()
>+		 * about the P4_CCCR_OVF quirk.
>+		 */
>+		if (reset_devices) {
>+			unsigned int low, high;
>+			int i;
>+
>+			for (i = 0; i < P4_CONTROLS; i++) {
>+				rdmsr(p4_controls[i], low, high);
>+				low &= ~(P4_CCCR_ENABLE | P4_CCCR_OVF);
>+				wrmsr(p4_controls[i], low, high);
>+			}
>+		}
> 	} else {
> 		/* logical cpu 1 */
> 		perfctr_msr = MSR_P4_IQ_PERFCTR1;

Actions: View | Diff

Attachments on bug 463276: 317617