Attachment 575128 Details for Bug 747034 – dmesg out on kernel -259

dmesg out on kernel -259

dmesg.out (text/plain), 872.71 KB, created by Tomas Pelka on 2012-04-04 13:33:21 UTC

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Creator: Tomas Pelka

Created: 2012-04-04 13:33:21 UTC

Size: 872.71 KB

patch

obsolete

>Initializing cgroup subsys cpuset
>Initializing cgroup subsys cpu
>Linux version 2.6.32-259.el6.x86_64 (mockbuild@x86-003.build.bos.redhat.com) (gcc version 4.4.6 20110731 (Red Hat 4.4.6-3) (GCC) ) #1 SMP Thu Mar 29 12:14:22 EDT 2012
>Command line: initrd=initrd0.img root=live:UUID=2f213bb8-f15f-40ed-a9c0-9292f8db6d9d rootfstype=ext3 ro liveimg  LANG=en_US.utf8 quiet  rhgb rd_NO_LUKS rd_NO_MD rd_NO_DM log_buf_len=1M drm.debug=14 nouveau.reg_debug=0x600 BOOT_IMAGE=vmlinuz0 
>KERNEL supported cpus:
>  Intel GenuineIntel
>  AMD AuthenticAMD
>  Centaur CentaurHauls
>BIOS-provided physical RAM map:
> BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
> BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
> BIOS-e820: 00000000000e8000 - 0000000000100000 (reserved)
> BIOS-e820: 0000000000100000 - 00000000eafc1da0 (usable)
> BIOS-e820: 00000000eafc1da0 - 00000000eafc1e00 (ACPI NVS)
> BIOS-e820: 00000000eafc1e00 - 00000000ec000000 (reserved)
> BIOS-e820: 00000000f4000000 - 00000000f8000000 (reserved)
> BIOS-e820: 00000000fec00000 - 00000000fed40000 (reserved)
> BIOS-e820: 00000000fed45000 - 0000000100000000 (reserved)
> BIOS-e820: 0000000100000000 - 0000000114000000 (usable)
>DMI 2.6 present.
>SMBIOS version 2.6 @ 0xF9C00
>DMI: Hewlett-Packard HP xw4600 Workstation/0AA0h, BIOS 786F3 v01.15 08/28/2008
>e820 update range: 0000000000000000 - 0000000000001000 (usable) ==> (reserved)
>e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
>last_pfn = 0x114000 max_arch_pfn = 0x400000000
>MTRR default type: uncachable
>MTRR fixed ranges enabled:
>  00000-9FFFF write-back
>  A0000-BFFFF uncachable
>  C0000-E3FFF write-protect
>  E4000-EFFFF write-back
>  F0000-FFFFF write-protect
>MTRR variable ranges enabled:
>  0 base 000000000 mask F00000000 write-back
>  1 base 0EC000000 mask FFC000000 uncachable
>  2 base 0F0000000 mask FF0000000 uncachable
>  3 base 100000000 mask FF0000000 write-back
>  4 base 110000000 mask FFC000000 write-back
>  5 disabled
>  6 disabled
>  7 disabled
>x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
>original variable MTRRs
>reg 0, base: 0GB, range: 4GB, type WB
>reg 1, base: 3776MB, range: 64MB, type UC
>reg 2, base: 3840MB, range: 256MB, type UC
>reg 3, base: 4GB, range: 256MB, type WB
>reg 4, base: 4352MB, range: 64MB, type WB
>total RAM covered: 4096M
>Found optimal setting for mtrr clean up
> gran_size: 64K 	chunk_size: 1G 	num_reg: 5  	lose cover RAM: 0G
>New variable MTRRs
>reg 0, base: 0GB, range: 4GB, type WB
>reg 1, base: 3776MB, range: 64MB, type UC
>reg 2, base: 3840MB, range: 256MB, type UC
>reg 3, base: 4GB, range: 256MB, type WB
>reg 4, base: 4352MB, range: 64MB, type WB
>e820 update range: 00000000ec000000 - 0000000100000000 (usable) ==> (reserved)
>last_pfn = 0xeafc1 max_arch_pfn = 0x400000000
>initial memory mapped : 0 - 20000000
>init_memory_mapping: 0000000000000000-00000000eafc1000
> 0000000000 - 00eae00000 page 2M
> 00eae00000 - 00eafc1000 page 4k
>kernel direct mapping tables up to eafc1000 @ 8000-e000
>init_memory_mapping: 0000000100000000-0000000114000000
> 0100000000 - 0114000000 page 2M
>kernel direct mapping tables up to 114000000 @ c000-12000
>log_buf_len: 1048576
>early log buf free: 520980(99%)
>RAMDISK: 7f651000 - 7fffe0a6
>ACPI: RSDP 00000000000e6410 00024 (v02 COMPAQ)
>ACPI: XSDT 00000000eafc1ee8 0005C (v01 HPQOEM SLIC-WKS 20080828      00000000)
>ACPI: FACP 00000000eafc2088 000F4 (v03 COMPAQ          EAFC2647      00000000)
>ACPI Error: 32/64X address mismatch in Gpe0Block: 0000F820/000000000001F028, using 32 (20090903/tbfadt-427)
>ACPI: DSDT 00000000eafc2647 098EC (v01 COMPAQ DSDT_PRJ 00000001 MSFT 0100000E)
>ACPI: FACS 00000000eafc1e00 00040
>ACPI: APIC 00000000eafc217c 00084 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: ASF! 00000000eafc2200 00063 (v32 COMPAQ BEARLX38 00000001      00000000)
>ACPI: MCFG 00000000eafc2263 0003C (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: TCPA 00000000eafc229f 00032 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: HPET 00000000eafc2447 00038 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: DMAR 00000000eafc247f 00158 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: Local APIC address 0xfee00000
>No NUMA configuration found
>Faking a node at 0000000000000000-0000000114000000
>Bootmem setup node 0 0000000000000000-0000000114000000
>  NODE_DATA [000000000000d000 - 0000000000040fff]
>  bootmap [0000000000041000 -  00000000000637ff] pages 23
>(9 early reservations) ==> bootmem [0000000000 - 0114000000]
>  #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
>  #1 [0000006000 - 0000008000]       TRAMPOLINE ==> [0000006000 - 0000008000]
>  #2 [0001000000 - 0002011ce4]    TEXT DATA BSS ==> [0001000000 - 0002011ce4]
>  #3 [007f651000 - 007fffe0a6]          RAMDISK ==> [007f651000 - 007fffe0a6]
>  #4 [000009f800 - 0000100000]    BIOS reserved ==> [000009f800 - 0000100000]
>  #5 [0002012000 - 0002012140]              BRK ==> [0002012000 - 0002012140]
>  #6 [0000008000 - 000000c000]          PGTABLE ==> [0000008000 - 000000c000]
>  #7 [000000c000 - 000000d000]          PGTABLE ==> [000000c000 - 000000d000]
>  #8 [00eaec1000 - 00eafc1000]          LOG BUF ==> [00eaec1000 - 00eafc1000]
>found SMP MP-table at [ffff8800000f9bf0] f9bf0
> [ffffea0000000000-ffffea0003dfffff] PMD -> [ffff880028600000-ffff88002c1fffff] on node 0
>Zone PFN ranges:
>  DMA      0x00000001 -> 0x00001000
>  DMA32    0x00001000 -> 0x00100000
>  Normal   0x00100000 -> 0x00114000
>Movable zone start PFN for each node
>early_node_map[3] active PFN ranges
>    0: 0x00000001 -> 0x0000009f
>    0: 0x00000100 -> 0x000eafc1
>    0: 0x00100000 -> 0x00114000
>On node 0 totalpages: 1044319
>  DMA zone: 56 pages used for memmap
>  DMA zone: 104 pages reserved
>  DMA zone: 3838 pages, LIFO batch:0
>  DMA32 zone: 14280 pages used for memmap
>  DMA32 zone: 944121 pages, LIFO batch:31
>  Normal zone: 1120 pages used for memmap
>  Normal zone: 80800 pages, LIFO batch:15
>ACPI: PM-Timer IO Port: 0xf808
>ACPI: Local APIC address 0xfee00000
>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled)
>ACPI: LAPIC (acpi_id[0x03] lapic_id[0x02] enabled)
>ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled)
>ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>ACPI: IRQ0 used by override.
>ACPI: IRQ2 used by override.
>ACPI: IRQ9 used by override.
>Using ACPI (MADT) for SMP configuration information
>ACPI: HPET id: 0x8086a201 base: 0xfed00000
>SMP: Allowing 4 CPUs, 0 hotplug CPUs
>nr_irqs_gsi: 24
>PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
>PM: Registered nosave memory: 00000000000a0000 - 00000000000e8000
>PM: Registered nosave memory: 00000000000e8000 - 0000000000100000
>PM: Registered nosave memory: 00000000eafc1000 - 00000000eafc2000
>PM: Registered nosave memory: 00000000eafc1000 - 00000000eafc2000
>PM: Registered nosave memory: 00000000eafc2000 - 00000000ec000000
>PM: Registered nosave memory: 00000000ec000000 - 00000000f4000000
>PM: Registered nosave memory: 00000000f4000000 - 00000000f8000000
>PM: Registered nosave memory: 00000000f8000000 - 00000000fec00000
>PM: Registered nosave memory: 00000000fec00000 - 00000000fed40000
>PM: Registered nosave memory: 00000000fed40000 - 00000000fed45000
>PM: Registered nosave memory: 00000000fed45000 - 0000000100000000
>Allocating PCI resources starting at ec000000 (gap: ec000000:8000000)
>Booting paravirtualized kernel on bare hardware
>NR_CPUS:4096 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1
>PERCPU: Embedded 31 pages/cpu @ffff880028200000 s94424 r8192 d24360 u524288
>pcpu-alloc: s94424 r8192 d24360 u524288 alloc=1*2097152
>pcpu-alloc: [0] 0 1 2 3 
>Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1028759
>Policy zone: Normal
>Kernel command line: initrd=initrd0.img root=live:UUID=2f213bb8-f15f-40ed-a9c0-9292f8db6d9d rootfstype=ext3 ro liveimg  LANG=en_US.utf8 quiet  rhgb rd_NO_LUKS rd_NO_MD rd_NO_DM log_buf_len=1M drm.debug=14 nouveau.reg_debug=0x600 BOOT_IMAGE=vmlinuz0 
>PID hash table entries: 4096 (order: 3, 32768 bytes)
>xsave/xrstor: enabled xstate_bv 0x3, cntxt size 0x240
>Checking aperture...
>No AGP bridge found
>------------[ cut here ]------------
>WARNING: at drivers/pci/dmar.c:594 warn_invalid_dmar+0x7a/0x90() (Not tainted)
>Hardware name: HP xw4600 Workstation
>[Firmware Warn]: Your BIOS is broken; DMAR reported at address fed90000 returns all ones!
>BIOS vendor: Hewlett-Packard; Ver: 786F3 v01.15; Product Version:  
>Modules linked in:
>Pid: 0, comm: swapper Not tainted 2.6.32-259.el6.x86_64 #1
>Call Trace:
> [<ffffffff8106b607>] ? warn_slowpath_common+0x87/0xc0
> [<ffffffff8106b69f>] ? warn_slowpath_fmt_taint+0x3f/0x50
> [<ffffffff8103933d>] ? native_set_pte_at+0xd/0x40
> [<ffffffff81038d29>] ? native_flush_tlb_single+0x9/0x10
> [<ffffffff812a6d0a>] ? warn_invalid_dmar+0x7a/0x90
> [<ffffffff81c51191>] ? check_zero_address+0xd6/0x118
> [<ffffffff812edd6f>] ? acpi_get_table_with_size+0x5a/0xb4
> [<ffffffff81504fd5>] ? _etext+0x0/0x3
> [<ffffffff81c511e5>] ? detect_intel_iommu+0x12/0x91
> [<ffffffff81c2a149>] ? pci_iommu_alloc+0x5e/0x6c
> [<ffffffff81c3ce52>] ? mem_init+0x19/0xec
> [<ffffffff81c21d78>] ? start_kernel+0x221/0x430
> [<ffffffff81c2133a>] ? x86_64_start_reservations+0x125/0x129
> [<ffffffff81c21438>] ? x86_64_start_kernel+0xfa/0x109
>---[ end trace a7919e7f17c0a725 ]---
>Disabling lock debugging due to kernel taint
>PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>Placing 64MB software IO TLB between ffff880020000000 - ffff880024000000
>software IO TLB at phys 0x20000000 - 0x24000000
>Memory: 4021380k/4521984k available (5139k kernel code, 344708k absent, 155896k reserved, 7177k data, 1260k init)
>Hierarchical RCU implementation.
>NR_IRQS:33024 nr_irqs:440
>Extended CMOS year: 2000
>Console: colour VGA+ 80x25
>console [tty0] enabled
>allocated 34603008 bytes of page_cgroup
>please try 'cgroup_disable=memory' option if you don't want memory cgroups
>hpet clockevent registered
>Fast TSC calibration using PIT
>Detected 2833.026 MHz processor.
>Calibrating delay loop (skipped), value calculated using timer frequency.. 5666.05 BogoMIPS (lpj=2833026)
>pid_max: default: 32768 minimum: 301
>Security Framework initialized
>SELinux:  Initializing.
>SELinux:  Starting in permissive mode
>Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
>Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
>Mount-cache hash table entries: 256
>Initializing cgroup subsys ns
>Initializing cgroup subsys cpuacct
>Initializing cgroup subsys memory
>Initializing cgroup subsys devices
>Initializing cgroup subsys freezer
>Initializing cgroup subsys net_cls
>Initializing cgroup subsys blkio
>Initializing cgroup subsys perf_event
>Initializing cgroup subsys net_prio
>CPU: Physical Processor ID: 0
>CPU: Processor Core ID: 0
>mce: CPU supports 6 MCE banks
>CPU0: Thermal monitoring enabled (TM2)
>using mwait in idle threads.
>ACPI: Core revision 20090903
>ftrace: converting mcount calls to 0f 1f 44 00 00
>ftrace: allocating 20961 entries in 83 pages
>DMAR: Host address width 36
>DMAR: DRHD base: 0x000000fed90000 flags: 0x0
>------------[ cut here ]------------
>WARNING: at drivers/pci/dmar.c:594 warn_invalid_dmar+0x7a/0x90() (Tainted: G          I---------------   )
>Hardware name: HP xw4600 Workstation
>[Firmware Warn]: Your BIOS is broken; DMAR reported at address fed90000 returns all ones!
>BIOS vendor: Hewlett-Packard; Ver: 786F3 v01.15; Product Version:  
>Modules linked in:
>Pid: 1, comm: swapper Tainted: G          I---------------    2.6.32-259.el6.x86_64 #1
>Call Trace:
> [<ffffffff8106b607>] ? warn_slowpath_common+0x87/0xc0
> [<ffffffff8106b69f>] ? warn_slowpath_fmt_taint+0x3f/0x50
> [<ffffffff810449d8>] ? __ioremap_caller+0x2a8/0x390
> [<ffffffff812a6d0a>] ? warn_invalid_dmar+0x7a/0x90
> [<ffffffff812a6f23>] ? alloc_iommu+0x203/0x2b0
> [<ffffffff81c517d0>] ? dmar_table_init+0x1bd/0x3be
> [<ffffffff81c32384>] ? enable_IR_x2apic+0x23/0x221
> [<ffffffff81c30288>] ? native_smp_prepare_cpus+0x143/0x389
> [<ffffffff81c21740>] ? kernel_init+0x112/0x2fe
> [<ffffffff8100c14a>] ? child_rip+0xa/0x20
> [<ffffffff81c2162e>] ? kernel_init+0x0/0x2fe
> [<ffffffff8100c140>] ? child_rip+0x0/0x20
>---[ end trace a7919e7f17c0a726 ]---
>DMAR: parse DMAR table failure.
>Setting APIC routing to flat
>..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>CPU0: Intel(R) Core(TM)2 Quad CPU    Q9550  @ 2.83GHz stepping 0a
>Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver.
>... version:                2
>... bit width:              40
>... generic registers:      2
>... value mask:             000000ffffffffff
>... max period:             000000007fffffff
>... fixed-purpose events:   3
>... event mask:             0000000700000003
>NMI watchdog enabled, takes one hw-pmu counter.
>Booting Node   0, Processors  #1 #2 #3 Ok.
>Brought up 4 CPUs
>Total of 4 processors activated (22664.20 BogoMIPS).
>sizeof(vma)=200 bytes
>sizeof(page)=56 bytes
>sizeof(inode)=592 bytes
>sizeof(dentry)=192 bytes
>sizeof(ext3inode)=800 bytes
>sizeof(buffer_head)=104 bytes
>sizeof(skbuff)=232 bytes
>sizeof(task_struct)=2648 bytes
>devtmpfs: initialized
>PM: Registering ACPI NVS region at eafc1da0 (96 bytes)
>regulator: core version 0.5
>NET: Registered protocol family 16
>ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>ACPI: bus type pci registered
>PCI: MCFG configuration 0: base f4000000 segment 0 buses 0 - 63
>PCI: MCFG area at f4000000 reserved in E820
>PCI: Using MMCONFIG at f4000000 - f7ffffff
>PCI: Using configuration type 1 for base access
>bio: create slab <bio-0> at 0
>ACPI: EC: Look up EC in DSDT
>ACPI: Interpreter enabled
>ACPI: (supports S0 S3 S4 S5)
>ACPI: Using IOAPIC for interrupt routing
>ACPI: No dock devices found.
>HEST: Table not found.
>PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880110c27808), AE_ALREADY_EXISTS
>ACPI: Marking method _OSC as Serialized because of AE_ALREADY_EXISTS error
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
>ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>pci_root PNP0A08:00: host bridge window [mem 0xf8000000-0xfebfffff]
>pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
>pci_root PNP0A08:00: host bridge window [io  0x1000-0x2fff]
>pci_root PNP0A08:00: host bridge window [io  0x3000-0x6fff]
>pci_root PNP0A08:00: host bridge window [io  0x7000-0xafff]
>pci_root PNP0A08:00: host bridge window [io  0xb000-0xffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
>pci_root PNP0A08:00: host bridge window [mem 0xec000000-0xf3ffffff]
>pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:01.0: PME# disabled
>pci 0000:00:1a.0: reg 20: [io  0x3100-0x311f]
>pci 0000:00:1a.1: reg 20: [io  0x3120-0x313f]
>pci 0000:00:1a.2: reg 20: [io  0x3140-0x315f]
>pci 0000:00:1a.7: reg 10: [mem 0xfe204800-0xfe204bff]
>pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
>pci 0000:00:1a.7: PME# disabled
>pci 0000:00:1b.0: reg 10: [mem 0xfe200000-0xfe203fff 64bit]
>pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:1b.0: PME# disabled
>pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.0: PME# disabled
>pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.4: PME# disabled
>pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.5: PME# disabled
>pci 0000:00:1d.0: reg 20: [io  0x3160-0x317f]
>pci 0000:00:1d.1: reg 20: [io  0x3180-0x319f]
>pci 0000:00:1d.2: reg 20: [io  0x31a0-0x31bf]
>pci 0000:00:1d.7: reg 10: [mem 0xfe204c00-0xfe204fff]
>pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
>pci 0000:00:1d.7: PME# disabled
>pci 0000:00:1f.0: quirk: [io  0xf800-0xf87f] claimed by ICH6 ACPI/GPIO/TCO
>pci 0000:00:1f.0: quirk: [io  0xfa00-0xfa3f] claimed by ICH6 GPIO
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 0400 (mask 007f)
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 0480 (mask 000f)
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 0cb0 (mask 000f)
>pci 0000:00:1f.2: reg 10: [io  0x3200-0x3207]
>pci 0000:00:1f.2: reg 14: [io  0x3210-0x3213]
>pci 0000:00:1f.2: reg 18: [io  0x3208-0x320f]
>pci 0000:00:1f.2: reg 1c: [io  0x3214-0x3217]
>pci 0000:00:1f.2: reg 20: [io  0x31c0-0x31df]
>pci 0000:00:1f.2: reg 24: [mem 0xfe204000-0xfe2047ff]
>pci 0000:00:1f.2: PME# supported from D3hot
>pci 0000:00:1f.2: PME# disabled
>pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
>pci 0000:01:00.0: PME# disabled
>pci 0000:00:01.0: PCI bridge to [bus 01-04]
>pci 0000:00:01.0:   bridge window [io  0x1000-0x2fff]
>pci 0000:00:01.0:   bridge window [mem 0xf8000000-0xfdffffff]
>pci 0000:00:01.0:   bridge window [mem 0xec000000-0xf3ffffff 64bit pref]
>pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
>pci 0000:02:00.0: PME# disabled
>pci 0000:02:02.0: PME# supported from D0 D3hot D3cold
>pci 0000:02:02.0: PME# disabled
>pci 0000:01:00.0: PCI bridge to [bus 02-04]
>pci 0000:01:00.0:   bridge window [io  0x1000-0x2fff]
>pci 0000:01:00.0:   bridge window [mem 0xf8000000-0xfdffffff]
>pci 0000:01:00.0:   bridge window [mem 0xec000000-0xf3ffffff 64bit pref]
>pci 0000:03:00.0: reg 10: [mem 0xfb000000-0xfbffffff]
>pci 0000:03:00.0: reg 14: [mem 0xf0000000-0xf3ffffff 64bit pref]
>pci 0000:03:00.0: reg 1c: [mem 0xfc000000-0xfdffffff 64bit]
>pci 0000:03:00.0: reg 24: [io  0x2100-0x217f]
>pci 0000:03:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>pci 0000:02:00.0: PCI bridge to [bus 03-03]
>pci 0000:02:00.0:   bridge window [io  0x2000-0x2fff]
>pci 0000:02:00.0:   bridge window [mem 0xfb000000-0xfdffffff]
>pci 0000:02:00.0:   bridge window [mem 0xf0000000-0xf3ffffff 64bit pref]
>pci 0000:04:00.0: reg 10: [mem 0xfa000000-0xfaffffff]
>pci 0000:04:00.0: reg 14: [mem 0xec000000-0xefffffff 64bit pref]
>pci 0000:04:00.0: reg 1c: [mem 0xf8000000-0xf9ffffff 64bit]
>pci 0000:04:00.0: reg 24: [io  0x1100-0x117f]
>pci 0000:04:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>pci 0000:02:02.0: PCI bridge to [bus 04-04]
>pci 0000:02:02.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:02:02.0:   bridge window [mem 0xf8000000-0xfaffffff]
>pci 0000:02:02.0:   bridge window [mem 0xec000000-0xefffffff 64bit pref]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
>pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:34:00.0: reg 10: [mem 0xfe100000-0xfe10ffff 64bit]
>pci 0000:34:00.0: reg 30: [mem 0x00000000-0x0000ffff pref]
>pci 0000:34:00.0: PME# supported from D3hot D3cold
>pci 0000:34:00.0: PME# disabled
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.4:   bridge window [mem 0xfe100000-0xfe1fffff]
>pci 0000:00:1c.4:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:3f:00.0: reg 10: [mem 0xfe000000-0xfe00ffff 64bit]
>pci 0000:3f:00.0: PME# supported from D3hot D3cold
>pci 0000:3f:00.0: PME# disabled
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.5:   bridge window [mem 0xfe000000-0xfe0fffff]
>pci 0000:00:1c.5:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:10:0b.0: reg 10: [mem 0xfe300000-0xfe300fff]
>pci 0000:10:0b.0: supports D1 D2
>pci 0000:10:0b.0: PME# supported from D0 D1 D2 D3hot
>pci 0000:10:0b.0: PME# disabled
>pci 0000:00:1e.0: PCI bridge to [bus 10-10] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1e.0:   bridge window [mem 0xfe300000-0xfe3fffff]
>pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:00:1e.0:   bridge window [mem 0xf8000000-0xfebfffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x1000-0x2fff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x3000-0x6fff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x7000-0xafff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0xb000-0xffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [mem 0xec000000-0xf3ffffff] (subtractive decode)
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEG1._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX1._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX5._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX6._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.HUB_._PRT]
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880110c27808), AE_ALREADY_EXISTS
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
> pci0000:00: Requesting ACPI _OSC control (0x1d)
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880110c27808), AE_ALREADY_EXISTS
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
>Unable to assume _OSC PCIe control. Disabling ASPM
>ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 *10 11 14 15)
>ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 *5 6 7 10 11 14 15)
>ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7 10 11 14 15)
>ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 *5 6 7 10 11 14 15)
>ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *10 11 14 15)
>ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 *11 14 15)
>ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>vgaarb: device added: PCI:0000:04:00.0,decodes=io+mem,owns=io+mem,locks=none
>vgaarb: loaded
>vgaarb: bridge control possible 0000:04:00.0
>SCSI subsystem initialized
>libata version 3.00 loaded.
>usbcore: registered new interface driver usbfs
>usbcore: registered new interface driver hub
>usbcore: registered new device driver usb
>PCI: Using ACPI for IRQ routing
>PCI: old code would have set cacheline size to 32 bytes, but clflush_size = 64
>PCI: pci_cache_line_size set to 64 bytes
>NetLabel: Initializing
>NetLabel:  domain hash size = 128
>NetLabel:  protocols = UNLABELED CIPSOv4
>NetLabel:  unlabeled traffic allowed by default
>HPET: 4 timers in total, 0 timers will be used for per-cpu timer
>hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
>hpet0: 4 comparators, 64-bit 14.318180 MHz counter
>Switching to clocksource hpet
>pnp: PnP ACPI init
>ACPI: bus type pnp registered
>pnp 00:00: [io  0x0cf8-0x0cff]
>pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
>pnp 00:01: [io  0x00f0-0x00ff]
>pnp 00:01: [irq 13]
>pnp 00:01: Plug and Play ACPI device, IDs PNP0c04 (active)
>pnp 00:02: [io  0x0000-0x000f]
>pnp 00:02: [io  0x0080-0x008f]
>pnp 00:02: [io  0x00c0-0x00df]
>pnp 00:02: [dma 4]
>pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active)
>pnp 00:03: [io  0x0070-0x0071]
>pnp 00:03: [irq 8]
>pnp 00:03: Plug and Play ACPI device, IDs PNP0b00 (active)
>pnp 00:04: [io  0x0061]
>pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active)
>pnp 00:05: [irq 12]
>pnp 00:05: Plug and Play ACPI device, IDs PNP0f13 PNP0f0e (active)
>pnp 00:06: [io  0x0060]
>pnp 00:06: [io  0x0064]
>pnp 00:06: [irq 1]
>pnp 00:06: Plug and Play ACPI device, IDs PNP0303 (active)
>pnp 00:07: [irq 7]
>pnp 00:07: [dma 3]
>pnp 00:07: [io  0x0378-0x037f]
>pnp 00:07: [io  0x0778-0x077d]
>pnp 00:07: Plug and Play ACPI device, IDs PNP0401 (active)
>pnp 00:08: [irq 4]
>pnp 00:08: [io  0x03f8-0x03ff]
>pnp 00:08: Plug and Play ACPI device, IDs PNP0501 PNP0500 (active)
>pnp 00:09: [irq 6]
>pnp 00:09: [dma 2]
>pnp 00:09: [io  0x03f0-0x03f5]
>pnp 00:09: [io  0x03f7]
>pnp 00:09: Plug and Play ACPI device, IDs PNP0700 (active)
>pnp 00:0a: [mem 0xfec00000-0xfec00fff]
>pnp 00:0a: Plug and Play ACPI device, IDs PNP0003 (active)
>pnp 00:0b: [mem 0xfed00000-0xfed003ff]
>pnp 00:0b: Plug and Play ACPI device, IDs PNP0103 (active)
>pnp 00:0c: [io  0x0010-0x001f]
>pnp 00:0c: [io  0x0050-0x0053]
>pnp 00:0c: [io  0x0072-0x0077]
>pnp 00:0c: [io  0x0090-0x009f]
>pnp 00:0c: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0d: [io  0x0400-0x041f]
>pnp 00:0d: [io  0x0420-0x043f]
>pnp 00:0d: [io  0x0440-0x045f]
>pnp 00:0d: [io  0x0460-0x047f]
>pnp 00:0d: [io  0x0480-0x048f]
>pnp 00:0d: [io  0xf800-0xf81f]
>pnp 00:0d: [io  0xf820-0xf83f]
>pnp 00:0d: [io  0xf840-0xf85f]
>pnp 00:0d: [io  0xf860-0xf87f]
>pnp 00:0d: [io  0xfa00-0xfa3f]
>pnp 00:0d: [io  0xfc00-0xfc7f]
>pnp 00:0d: [io  0xfc80-0xfcff]
>pnp 00:0d: [io  0xfe00-0xfe7f]
>pnp 00:0d: [io  0xfe80-0xfeff]
>pnp 00:0d: disabling [io  0xf800-0xf81f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf820-0xf83f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf840-0xf85f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf860-0xf87f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0e: [io  0x004e-0x004f]
>pnp 00:0e: [io  0x04d0-0x04d1]
>pnp 00:0e: [io  0x0cb0-0x0cbf]
>pnp 00:0e: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0f: [mem 0x00000000-0x0009ffff]
>pnp 00:0f: [mem 0x00100000-0xebffffff]
>pnp 00:0f: [mem 0x000e4000-0x000fffff]
>pnp 00:0f: [mem 0xfec01000-0xfecfffff]
>pnp 00:0f: [mem 0xfed00400-0xfed3ffff]
>pnp 00:0f: [mem 0xfed40000-0xffffffff]
>pnp 00:0f: [mem 0xf4000000-0xf7ffffff]
>pnp 00:0f: [mem 0x000d2c00-0x000e3fff]
>pnp 00:0f: Plug and Play ACPI device, IDs PNP0c01 (active)
>pnp: PnP ACPI: found 16 devices
>ACPI: ACPI bus type pnp unregistered
>system 00:0d: [io  0x0400-0x041f] has been reserved
>system 00:0d: [io  0x0420-0x043f] has been reserved
>system 00:0d: [io  0x0440-0x045f] has been reserved
>system 00:0d: [io  0x0460-0x047f] has been reserved
>system 00:0d: [io  0x0480-0x048f] has been reserved
>system 00:0d: [io  0xfa00-0xfa3f] has been reserved
>system 00:0d: [io  0xfc00-0xfc7f] has been reserved
>system 00:0d: [io  0xfc80-0xfcff] has been reserved
>system 00:0d: [io  0xfe00-0xfe7f] has been reserved
>system 00:0d: [io  0xfe80-0xfeff] has been reserved
>system 00:0e: [io  0x04d0-0x04d1] has been reserved
>system 00:0e: [io  0x0cb0-0x0cbf] has been reserved
>system 00:0f: [mem 0x00000000-0x0009ffff] could not be reserved
>system 00:0f: [mem 0x00100000-0xebffffff] could not be reserved
>system 00:0f: [mem 0x000e4000-0x000fffff] could not be reserved
>system 00:0f: [mem 0xfec01000-0xfecfffff] has been reserved
>system 00:0f: [mem 0xfed00400-0xfed3ffff] has been reserved
>system 00:0f: [mem 0xfed40000-0xffffffff] could not be reserved
>system 00:0f: [mem 0xf4000000-0xf7ffffff] has been reserved
>system 00:0f: [mem 0x000d2c00-0x000e3fff] has been reserved
>PCI: max bus depth: 3 pci_try_num: 4
>pci 0000:00:1c.4: BAR 15: assigned [mem 0xfe400000-0xfe4fffff pref]
>pci 0000:00:1c.5: BAR 15: assigned [mem 0xfe500000-0xfe6fffff 64bit pref]
>pci 0000:00:1c.5: BAR 13: assigned [io  0x4000-0x4fff]
>pci 0000:00:1c.4: BAR 13: assigned [io  0x5000-0x5fff]
>pci 0000:00:1c.0: BAR 14: assigned [mem 0xfe700000-0xfe8fffff]
>pci 0000:00:1c.0: BAR 15: assigned [mem 0xfe900000-0xfeafffff 64bit pref]
>pci 0000:00:1c.0: BAR 13: assigned [io  0x6000-0x6fff]
>pci 0000:03:00.0: BAR 6: can't assign mem pref (size 0x20000)
>pci 0000:02:00.0: PCI bridge to [bus 03-03]
>pci 0000:02:00.0: PCI bridge to [bus 03-03]
>pci 0000:02:00.0:   bridge window [io  0x2000-0x2fff]
>pci 0000:02:00.0:   bridge window [mem 0xfb000000-0xfdffffff]
>pci 0000:02:00.0:   bridge window [mem 0xf0000000-0xf3ffffff 64bit pref]
>pci 0000:04:00.0: BAR 6: can't assign mem pref (size 0x20000)
>pci 0000:02:02.0: PCI bridge to [bus 04-04]
>pci 0000:02:02.0: PCI bridge to [bus 04-04]
>pci 0000:02:02.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:02:02.0:   bridge window [mem 0xf8000000-0xfaffffff]
>pci 0000:02:02.0:   bridge window [mem 0xec000000-0xefffffff 64bit pref]
>pci 0000:01:00.0: PCI bridge to [bus 02-04]
>pci 0000:01:00.0: PCI bridge to [bus 02-04]
>pci 0000:01:00.0:   bridge window [io  0x1000-0x2fff]
>pci 0000:01:00.0:   bridge window [mem 0xf8000000-0xfdffffff]
>pci 0000:01:00.0:   bridge window [mem 0xec000000-0xf3ffffff 64bit pref]
>pci 0000:00:01.0: PCI bridge to [bus 01-04]
>pci 0000:00:01.0: PCI bridge to [bus 01-04]
>pci 0000:00:01.0:   bridge window [io  0x1000-0x2fff]
>pci 0000:00:01.0:   bridge window [mem 0xf8000000-0xfdffffff]
>pci 0000:00:01.0:   bridge window [mem 0xec000000-0xf3ffffff 64bit pref]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0:   bridge window [io  0x6000-0x6fff]
>pci 0000:00:1c.0:   bridge window [mem 0xfe700000-0xfe8fffff]
>pci 0000:00:1c.0:   bridge window [mem 0xfe900000-0xfeafffff 64bit pref]
>pci 0000:34:00.0: BAR 6: assigned [mem 0xfe400000-0xfe40ffff pref]
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4:   bridge window [io  0x5000-0x5fff]
>pci 0000:00:1c.4:   bridge window [mem 0xfe100000-0xfe1fffff]
>pci 0000:00:1c.4:   bridge window [mem 0xfe400000-0xfe4fffff pref]
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5:   bridge window [io  0x4000-0x4fff]
>pci 0000:00:1c.5:   bridge window [mem 0xfe000000-0xfe0fffff]
>pci 0000:00:1c.5:   bridge window [mem 0xfe500000-0xfe6fffff 64bit pref]
>pci 0000:00:1e.0: PCI bridge to [bus 10-10]
>pci 0000:00:1e.0: PCI bridge to [bus 10-10]
>pci 0000:00:1e.0:   bridge window [io  disabled]
>pci 0000:00:1e.0:   bridge window [mem 0xfe300000-0xfe3fffff]
>pci 0000:00:1e.0:   bridge window [mem pref disabled]
>  alloc irq_desc for 16 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:01.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>pci 0000:00:01.0: setting latency timer to 64
>pci 0000:01:00.0: setting latency timer to 64
>pci 0000:02:00.0: setting latency timer to 64
>pci 0000:02:02.0: setting latency timer to 64
>pci 0000:00:1c.0: setting latency timer to 64
>  alloc irq_desc for 20 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:1c.4: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>pci 0000:00:1c.4: setting latency timer to 64
>  alloc irq_desc for 21 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:1c.5: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>pci 0000:00:1c.5: setting latency timer to 64
>pci 0000:00:1e.0: setting latency timer to 64
>pci_bus 0000:00: resource 4 [mem 0xf8000000-0xfebfffff]
>pci_bus 0000:00: resource 5 [io  0x0000-0x0cf7]
>pci_bus 0000:00: resource 6 [io  0x1000-0x2fff]
>pci_bus 0000:00: resource 7 [io  0x3000-0x6fff]
>pci_bus 0000:00: resource 8 [io  0x7000-0xafff]
>pci_bus 0000:00: resource 9 [io  0xb000-0xffff]
>pci_bus 0000:00: resource 10 [mem 0x000a0000-0x000bffff]
>pci_bus 0000:00: resource 11 [mem 0xec000000-0xf3ffffff]
>pci_bus 0000:01: resource 0 [io  0x1000-0x2fff]
>pci_bus 0000:01: resource 1 [mem 0xf8000000-0xfdffffff]
>pci_bus 0000:01: resource 2 [mem 0xec000000-0xf3ffffff 64bit pref]
>pci_bus 0000:02: resource 0 [io  0x1000-0x2fff]
>pci_bus 0000:02: resource 1 [mem 0xf8000000-0xfdffffff]
>pci_bus 0000:02: resource 2 [mem 0xec000000-0xf3ffffff 64bit pref]
>pci_bus 0000:03: resource 0 [io  0x2000-0x2fff]
>pci_bus 0000:03: resource 1 [mem 0xfb000000-0xfdffffff]
>pci_bus 0000:03: resource 2 [mem 0xf0000000-0xf3ffffff 64bit pref]
>pci_bus 0000:04: resource 0 [io  0x1000-0x1fff]
>pci_bus 0000:04: resource 1 [mem 0xf8000000-0xfaffffff]
>pci_bus 0000:04: resource 2 [mem 0xec000000-0xefffffff 64bit pref]
>pci_bus 0000:28: resource 0 [io  0x6000-0x6fff]
>pci_bus 0000:28: resource 1 [mem 0xfe700000-0xfe8fffff]
>pci_bus 0000:28: resource 2 [mem 0xfe900000-0xfeafffff 64bit pref]
>pci_bus 0000:34: resource 0 [io  0x5000-0x5fff]
>pci_bus 0000:34: resource 1 [mem 0xfe100000-0xfe1fffff]
>pci_bus 0000:34: resource 2 [mem 0xfe400000-0xfe4fffff pref]
>pci_bus 0000:3f: resource 0 [io  0x4000-0x4fff]
>pci_bus 0000:3f: resource 1 [mem 0xfe000000-0xfe0fffff]
>pci_bus 0000:3f: resource 2 [mem 0xfe500000-0xfe6fffff 64bit pref]
>pci_bus 0000:10: resource 1 [mem 0xfe300000-0xfe3fffff]
>pci_bus 0000:10: resource 4 [mem 0xf8000000-0xfebfffff]
>pci_bus 0000:10: resource 5 [io  0x0000-0x0cf7]
>pci_bus 0000:10: resource 6 [io  0x1000-0x2fff]
>pci_bus 0000:10: resource 7 [io  0x3000-0x6fff]
>pci_bus 0000:10: resource 8 [io  0x7000-0xafff]
>pci_bus 0000:10: resource 9 [io  0xb000-0xffff]
>pci_bus 0000:10: resource 10 [mem 0x000a0000-0x000bffff]
>pci_bus 0000:10: resource 11 [mem 0xec000000-0xf3ffffff]
>NET: Registered protocol family 2
>IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
>TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
>TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>TCP: Hash tables configured (established 524288 bind 65536)
>TCP reno registered
>NET: Registered protocol family 1
>pci 0000:04:00.0: Boot video device
>Trying to unpack rootfs image as initramfs...
>Freeing initrd memory: 9908k freed
>audit: initializing netlink socket (disabled)
>type=2000 audit(1333545620.262:1): initialized
>HugeTLB registered 2 MB page size, pre-allocated 0 pages
>VFS: Disk quotas dquot_6.5.2
>Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>msgmni has been set to 7873
>SELinux:  Registering netfilter hooks
>alg: No test for stdrng (krng)
>ksign: Installing public key data
>Loading keyring
>- Added public key 74AF74C721E99240
>- User ID: Red Hat, Inc. (Kernel Module GPG key)
>- Added public key D4A26C9CCD09BEDA
>- User ID: Red Hat Enterprise Linux Driver Update Program <secalert@redhat.com>
>Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
>io scheduler noop registered
>io scheduler anticipatory registered
>io scheduler deadline registered
>io scheduler cfq registered (default)
>pcieport 0000:00:01.0: setting latency timer to 64
>  alloc irq_desc for 24 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:01.0: irq 24 for MSI/MSI-X
>pcieport 0000:00:1c.0: setting latency timer to 64
>  alloc irq_desc for 25 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.0: irq 25 for MSI/MSI-X
>pcieport 0000:00:1c.4: setting latency timer to 64
>  alloc irq_desc for 26 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.4: irq 26 for MSI/MSI-X
>pcieport 0000:00:1c.5: setting latency timer to 64
>  alloc irq_desc for 27 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.5: irq 27 for MSI/MSI-X
>pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>pciehp: PCI Express Hot Plug Controller Driver version: 0.4
>acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>intel_idle: MWAIT substates: 0x22220
>intel_idle: does not run on family 6 model 23
>input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
>ACPI: Power Button [PBTN]
>input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
>ACPI: Power Button [PWRF]
>ACPI: acpi_idle registered with cpuidle
>ACPI: SSDT 00000000eafcd361 003AC (v01 COMPAQ  CPU_TM2 00000001 MSFT 0100000E)
>ACPI: SSDT 00000000eafcd1e5 0017C (v01 COMPAQ      CST 00000001 MSFT 0100000E)
>Marking TSC unstable due to TSC halts in idle
>ERST: Table is not found!
>GHES: HEST is not enabled!
>Non-volatile memory driver v1.3
>Linux agpgart interface v0.103
>crash memory driver: version 1.1
>Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
>00:08: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
>brd: module loaded
>loop: module loaded
>input: Macintosh mouse button emulation as /devices/virtual/input/input2
>Fixed MDIO Bus: probed
>ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>  alloc irq_desc for 22 on node -1
>  alloc kstat_irqs on node -1
>ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>ehci_hcd 0000:00:1a.7: setting latency timer to 64
>ehci_hcd 0000:00:1a.7: EHCI Host Controller
>ehci_hcd 0000:00:1a.7: new USB bus registered, assigned bus number 1
>ehci_hcd 0000:00:1a.7: debug port 1
>ehci_hcd 0000:00:1a.7: cache line size of 64 is not supported
>ehci_hcd 0000:00:1a.7: irq 22, io mem 0xfe204800
>ehci_hcd 0000:00:1a.7: USB 2.0 started, EHCI 1.00
>usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb1: Product: EHCI Host Controller
>usb usb1: Manufacturer: Linux 2.6.32-259.el6.x86_64 ehci_hcd
>usb usb1: SerialNumber: 0000:00:1a.7
>usb usb1: configuration #1 chosen from 1 choice
>hub 1-0:1.0: USB hub found
>hub 1-0:1.0: 6 ports detected
>ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>ehci_hcd 0000:00:1d.7: setting latency timer to 64
>ehci_hcd 0000:00:1d.7: EHCI Host Controller
>ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 2
>ehci_hcd 0000:00:1d.7: debug port 1
>ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
>ehci_hcd 0000:00:1d.7: irq 20, io mem 0xfe204c00
>ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
>usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
>usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb2: Product: EHCI Host Controller
>usb usb2: Manufacturer: Linux 2.6.32-259.el6.x86_64 ehci_hcd
>usb usb2: SerialNumber: 0000:00:1d.7
>usb usb2: configuration #1 chosen from 1 choice
>hub 2-0:1.0: USB hub found
>hub 2-0:1.0: 6 ports detected
>ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>uhci_hcd: USB Universal Host Controller Interface driver
>uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1a.0: setting latency timer to 64
>uhci_hcd 0000:00:1a.0: UHCI Host Controller
>uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3
>uhci_hcd 0000:00:1a.0: irq 20, io base 0x00003100
>usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb3: Product: UHCI Host Controller
>usb usb3: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb3: SerialNumber: 0000:00:1a.0
>usb usb3: configuration #1 chosen from 1 choice
>hub 3-0:1.0: USB hub found
>hub 3-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1a.1: setting latency timer to 64
>uhci_hcd 0000:00:1a.1: UHCI Host Controller
>uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
>uhci_hcd 0000:00:1a.1: irq 21, io base 0x00003120
>usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb4: Product: UHCI Host Controller
>usb usb4: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb4: SerialNumber: 0000:00:1a.1
>usb usb4: configuration #1 chosen from 1 choice
>hub 4-0:1.0: USB hub found
>hub 4-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1a.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1a.2: setting latency timer to 64
>uhci_hcd 0000:00:1a.2: UHCI Host Controller
>uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5
>uhci_hcd 0000:00:1a.2: irq 22, io base 0x00003140
>usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb5: Product: UHCI Host Controller
>usb usb5: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb5: SerialNumber: 0000:00:1a.2
>usb usb5: configuration #1 chosen from 1 choice
>hub 5-0:1.0: USB hub found
>hub 5-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1d.0: setting latency timer to 64
>uhci_hcd 0000:00:1d.0: UHCI Host Controller
>uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6
>uhci_hcd 0000:00:1d.0: irq 20, io base 0x00003160
>usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb6: Product: UHCI Host Controller
>usb usb6: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb6: SerialNumber: 0000:00:1d.0
>usb usb6: configuration #1 chosen from 1 choice
>hub 6-0:1.0: USB hub found
>hub 6-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1d.1: setting latency timer to 64
>uhci_hcd 0000:00:1d.1: UHCI Host Controller
>uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7
>uhci_hcd 0000:00:1d.1: irq 21, io base 0x00003180
>usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb7: Product: UHCI Host Controller
>usb usb7: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb7: SerialNumber: 0000:00:1d.1
>usb usb7: configuration #1 chosen from 1 choice
>hub 7-0:1.0: USB hub found
>hub 7-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1d.2: setting latency timer to 64
>uhci_hcd 0000:00:1d.2: UHCI Host Controller
>uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8
>uhci_hcd 0000:00:1d.2: irq 22, io base 0x000031a0
>usb usb8: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb8: Product: UHCI Host Controller
>usb usb8: Manufacturer: Linux 2.6.32-259.el6.x86_64 uhci_hcd
>usb usb8: SerialNumber: 0000:00:1d.2
>usb usb8: configuration #1 chosen from 1 choice
>hub 8-0:1.0: USB hub found
>hub 8-0:1.0: 2 ports detected
>PNP: PS/2 Controller [PNP0303:KBD,PNP0f0e:PS2M] at 0x60,0x64 irq 1,12
>serio: i8042 KBD port at 0x60,0x64 irq 1
>serio: i8042 AUX port at 0x60,0x64 irq 12
>mice: PS/2 mouse device common for all mice
>rtc_cmos 00:03: RTC can wake from S4
>rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
>rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
>cpuidle: using governor ladder
>cpuidle: using governor menu
>EFI Variables Facility v0.08 2004-May-17
>usbcore: registered new interface driver hiddev
>usbcore: registered new interface driver usbhid
>usbhid: v2.6:USB HID core driver
>TCP cubic registered
>Initializing XFRM netlink socket
>NET: Registered protocol family 17
>registered taskstats version 1
>rtc_cmos 00:03: setting system clock to 2012-04-04 13:20:21 UTC (1333545621)
>Initalizing network drop monitor service
>Freeing unused kernel memory: 1260k freed
>Write protecting the kernel read-only data: 10240k
>Freeing unused kernel memory: 984k freed
>Freeing unused kernel memory: 1736k freed
>dracut: dracut-004-281.el6
>input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
>dracut: rd_NO_LUKS: removing cryptoluks activation
>dracut: root was live:/dev/disk/by-uuid/2f213bb8-f15f-40ed-a9c0-9292f8db6d9d, liveroot is now live:UUID=2f213bb8-f15f-40ed-a9c0-9292f8db6d9d
>device-mapper: uevent: version 1.0.3
>device-mapper: ioctl: 4.22.6-ioctl (2011-10-19) initialised: dm-devel@redhat.com
>udev: starting version 147
>ACPI: WMI: Mapper loaded
>[drm] Initialized drm 1.1.0 20060810
>VGA switcheroo: detected Optimus DSM method \ handle
>nouveau 0000:03:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>nouveau 0000:03:00.0: setting latency timer to 64
>[drm] nouveau 0000:03:00.0: nouveau_load:1008 - vendor: 0x10DE device: 0x6FA class: 0x30200
>[drm] nouveau 0000:03:00.0: nouveau_load:1025 - regs mapped ok at 0xfb000000
>[drm] nouveau 0000:03:00.0: Detected an NV50 generation card (0x298d00a2)
>[drm] nouveau 0000:03:00.0: nouveau_load:1098 - crystal freq: 27000KHz
>[drm] nouveau 0000:03:00.0: Attempting to load BIOS image from PRAMIN
>[drm] nouveau 0000:03:00.0: ... BIOS signature not found
>[drm] nouveau 0000:03:00.0: Attempting to load BIOS image from PROM
>usb 1-6: new high speed USB device number 2 using ehci_hcd
>[drm] nouveau 0000:03:00.0: ... appears to be valid
>[drm] nouveau 0000:03:00.0: BIT BIOS found
>[drm] nouveau 0000:03:00.0: Bios version 62.98.77.00
>[drm] nouveau 0000:03:00.0: TMDS table version 2.0
>[drm] nouveau 0000:03:00.0: MXM: no VBIOS data, nothing to do
>[drm] nouveau 0000:03:00.0: DCB version 4.0
>[drm] nouveau 0000:03:00.0: DCB outp 00: 02000386 0f200010
>[drm] nouveau 0000:03:00.0: DCB outp 01: 02000332 00020010
>[drm] nouveau 0000:03:00.0: DCB outp 02: 040113a6 0f200010
>[drm] nouveau 0000:03:00.0: DCB outp 03: 04011342 00020010
>[drm] nouveau 0000:03:00.0: DCB conn 00: 00005046
>[drm] nouveau 0000:03:00.0: DCB conn 01: 0000a146
>[drm] nouveau 0000:03:00.0: Adaptor not initialised, running VBIOS init tables.
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table 0 at offset 0xDBFC
>[drm] nouveau 0000:03:00.0: 0xDBFC: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xDBFC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000200, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xDC05: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC05: Repeating following segment 20 times
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xDC15: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDC15: Condition: 0x07
>[drm] nouveau 0000:03:00.0: 0xDC15: Cond: 0x07, Reg: 0x0000C040, Mask: 0x00000300
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000C040, Data: 0x3E801008
>[drm] nouveau 0000:03:00.0: 0xDC15: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDC15: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:03:00.0: 0xDC17: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001540, Data: 0xF1010001
>[drm] nouveau 0000:03:00.0: 0xDC20: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDC21: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:03:00.0: 0xDC2A: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xDC2A: Executing subroutine at 0xE742
>[drm] nouveau 0000:03:00.0: 0xE742: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xE742: BaseReg: 0x001009C0, Count: 0x07
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C0, Data: 0x04040004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C4, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C8, Data: 0x04040004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009CC, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D0, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D4, Data: 0x04000004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D8, Data: 0x04000004
>[drm] nouveau 0000:03:00.0: 0xE764: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x10402812
>[drm] nouveau 0000:03:00.0: 0xE764: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x05, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009EC, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE80B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xDC2A: End of 0xE742 subroutine
>[drm] nouveau 0000:03:00.0: 0xDC2D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC2D: Reg: 0x001008C0, Mask: 0xFF000000, Data: 0x08000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x001008C0, Data: 0x83303A98
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001008C0, Data: 0x8B000000
>[drm] nouveau 0000:03:00.0: 0xDC3A: [ (0x69) - INIT_IO ]
>[drm] nouveau 0000:03:00.0: 0xDC3A: Port: 0x03C3, Mask: 0x00, Data: 0x01
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614100, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614100, Data: 0x00800000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614900, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614900, Data: 0x00800000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000200, Data: 0x80110111
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000200, Data: 0x80110111
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614100, Data: 0x00800018
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614900, Data: 0x00800018
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614100, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614900, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614280, Data: 0x04840484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614A80, Data: 0x04840484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00615280, Data: 0x04840484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800084
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614200, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800084
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614108, Data: 0x40050012
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614108, Data: 0x00050012
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614908, Data: 0x40050012
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614908, Data: 0x00050012
>[drm] nouveau 0000:03:00.0: 0xDC3F: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x3F, Head: 0x00, Data: 0x57
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061943C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061943C, Data: 0x57000000
>[drm] nouveau 0000:03:00.0: 0xDC42: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC42: Reg: 0x0000E104, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E104, Data: 0x44444404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E104, Data: 0x44444404
>[drm] nouveau 0000:03:00.0: 0xDC4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC4F: Reg: 0x0000E108, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444C
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444C
>[drm] nouveau 0000:03:00.0: 0xDC5C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC5C: Reg: 0x0000E300, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:03:00.0: 0xDC69: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020108, Data: 0x08000000
>[drm] nouveau 0000:03:00.0: 0xDC72: [ (0x8E) - INIT_GPIO ]
>[drm] nouveau 0000:03:00.0: 0xDC73: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDC73: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001084, Data: 0x00001C69
>[drm] nouveau 0000:03:00.0: 0xDC80: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E054, Data: 0x7FFF7FFF
>[drm] nouveau 0000:03:00.0: 0xDC89: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00009220, Data: 0x00000009
>[drm] nouveau 0000:03:00.0: 0xDC92: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00009200, Data: 0x00000144
>[drm] nouveau 0000:03:00.0: 0xDC9B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00009210, Data: 0x0000007D
>[drm] nouveau 0000:03:00.0: 0xDCA4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCA4: Reg: 0x00101000, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x10402812
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xDCB1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCB1: Reg: 0x0010100C, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0010100C, Data: 0x00013020
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010100C, Data: 0x80013020
>[drm] nouveau 0000:03:00.0: 0xDCBE: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDCBE: Condition: 0x07
>[drm] nouveau 0000:03:00.0: 0xDCBE: Cond: 0x07, Reg: 0x0000C040, Mask: 0x00000300
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000C040, Data: 0x3E801008
>[drm] nouveau 0000:03:00.0: 0xDCBE: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDCBE: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:03:00.0: 0xDCC0: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCC0: SrcReg: 0x00614004, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x00610184, DstMask: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00614004, Data: 0x77704557
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00610184, Data: 0x7F700000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00610184, Data: 0x77704557
>[drm] nouveau 0000:03:00.0: 0xDCD6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDCD7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619F00, Data: 0x00000009
>[drm] nouveau 0000:03:00.0: 0xDCE0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDCE0: Condition: 0x06
>[drm] nouveau 0000:03:00.0: 0xDCE0: Cond: 0x06, Reg: 0x00021218, Mask: 0x000000FF
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00021218, Data: 0x00000022
>[drm] nouveau 0000:03:00.0: 0xDCE0: Checking if 0x00000022 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDCE0: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xDCE2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCEB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCF4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCFD: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xDCFD: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xDCFE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDCFE: Reg: 0x0061A068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A068, Data: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A068, Data: 0x44000000
>[drm] nouveau 0000:03:00.0: 0xDD0B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD0B: Reg: 0x0061A868, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A868, Data: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:03:00.0: 0xDD18: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD18: Reg: 0x0061B068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061B068, Data: 0x40800000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061B068, Data: 0x44800000
>[drm] nouveau 0000:03:00.0: 0xDD25: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDD26: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00617348, Data: 0x80000001
>[drm] nouveau 0000:03:00.0: 0xDD2F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004700, Data: 0x80000001
>[drm] nouveau 0000:03:00.0: 0xDD38: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:03:00.0: 0xDD38: Reg: 0x00101000, Shift: 0x02, SrcMask: 0x0F, Port: 0x03D4, Index: 0x88, Mask: 0xF0
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 0xDD43: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:03:00.0: 0xDD43: Reg: 0x00101000, Shift: 0x18, SrcMask: 0x0F, Port: 0x03D4, Index: 0x8B, Mask: 0xF0
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 0xDD4E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD4E: Reg: 0x00001580, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001580, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001580, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDD5B: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDD5B: Condition: 0x09
>[drm] nouveau 0000:03:00.0: 0xDD5B: Cond: 0x09, Reg: 0x00000000, Mask: 0xE0000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xDD5B: Checking if 0x20000000 equals 0x20000000
>[drm] nouveau 0000:03:00.0: 0xDD5B: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:03:00.0: 0xDD5D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001538, Data: 0x00011111
>[drm] nouveau 0000:03:00.0: 0xDD66: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xDD66: ------ Skipping following commands  ------
>[drm] nouveau 0000:03:00.0: 0xDD67: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD70: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDD70: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xDD71: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD71: Reg: 0x0010002C, Mask: 0xFFFFFF00, Data: 0x00000012
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0010002C, Data: 0x00000032
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010002C, Data: 0x00000012
>[drm] nouveau 0000:03:00.0: 0xDD7E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD7E: Reg: 0x00003310, Mask: 0xFFFFF8FF, Data: 0x00000500
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00003310, Data: 0x00000300
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00003310, Data: 0x00000500
>[drm] nouveau 0000:03:00.0: 0xDD8B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDD8B: Reg: 0x00001530, Mask: 0xFFFFFFF0, Data: 0x0000000A
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001530, Data: 0x800412FA
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001530, Data: 0x800412FA
>[drm] nouveau 0000:03:00.0: 0xDD98: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0002004C, Data: 0x40072A0B
>[drm] nouveau 0000:03:00.0: 0xDDA1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000204CC, Data: 0x0000005D
>[drm] nouveau 0000:03:00.0: 0xDDAA: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020060, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDDB3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088138, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 0xDDBC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDDBC: Reg: 0x0008813C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0008813C, Data: 0x33FF0000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008813C, Data: 0x33FF0000
>[drm] nouveau 0000:03:00.0: 0xDDC9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088140, Data: 0x08010000
>[drm] nouveau 0000:03:00.0: 0xDDD2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDDD2: Reg: 0x0008818C, Mask: 0x0FFFFFF8, Data: 0xD0000007
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0008818C, Data: 0x50000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008818C, Data: 0xD0000007
>[drm] nouveau 0000:03:00.0: 0xDDDF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDDDF: Reg: 0x00088458, Mask: 0xFC00FFFF, Data: 0x0028001F
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00088458, Data: 0x0057001F
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088458, Data: 0x0028001F
>[drm] nouveau 0000:03:00.0: 0xDDEC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDDEC: Reg: 0x00001604, Mask: 0xFFF577FF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001604, Data: 0x002AAA04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001604, Data: 0x00202204
>[drm] nouveau 0000:03:00.0: 0xDDF9: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8F, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061948C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061948C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDDFC: [ (0x76) - INIT_IO_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDDFC: IO condition: 0x04
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061948C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8F, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 0xDDFC: Checking if 0x00 equals 0x01
>[drm] nouveau 0000:03:00.0: 0xDDFC: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xDDFE: [ (0x4D) - INIT_ZM_I2C_BYTE ]
>[drm] nouveau 0000:03:00.0: 0xDE04: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDE04: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xDE05: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E81C, Data: 0x00044001
>[drm] nouveau 0000:03:00.0: 0xDE0E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E824, Data: 0x00200000
>[drm] nouveau 0000:03:00.0: 0xDE17: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:03:00.0: 0xDE20: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E844, Data: 0x00022801
>[drm] nouveau 0000:03:00.0: 0xDE29: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDE29: Reg: 0x0000E84C, Mask: 0xFFF8FFFF, Data: 0x00120000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E84C, Data: 0x00030000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E84C, Data: 0x00120000
>[drm] nouveau 0000:03:00.0: 0xDE36: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E848, Data: 0x80191501
>[drm] nouveau 0000:03:00.0: 0xDE3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDE3F: Reg: 0x00004040, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004040, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004040, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 0xDE4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDE4C: Reg: 0x00004050, Mask: 0xFFEFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004050, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004050, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 0xDE59: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000C050, Data: 0x0000500E
>[drm] nouveau 0000:03:00.0: 0xDE62: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDE62: Sleeping for 0x07D0 microseconds
>[drm] nouveau 0000:03:00.0: 0xDE65: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:03:00.0: 0xDE65: Calling script 7
>[drm] nouveau 0000:03:00.0: 0xE871: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE871: Type 04 Reg 0x00004008 Freq 700000KHz
>[drm] nouveau 0000:03:00.0: Loading PLL limits for register 0x00004008
>[drm] nouveau 0000:03:00.0: pll.vco1.minfreq: 590000
>[drm] nouveau 0000:03:00.0: pll.vco1.maxfreq: 1180000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_inputfreq: 14000
>[drm] nouveau 0000:03:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_n: 14
>[drm] nouveau 0000:03:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:03:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:03:00.0: pll.vco2.minfreq: 590000
>[drm] nouveau 0000:03:00.0: pll.vco2.maxfreq: 1180000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:03:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:03:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:03:00.0: pll.log2p_bias: 1
>[drm] nouveau 0000:03:00.0: pll.refclk: 108000
>[drm] nouveau 0000:03:00.0: 0xE893: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xDE65: End of script 7
>[drm] nouveau 0000:03:00.0: 0xDE67: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:03:00.0: 0xDE67: Calling script 8
>[drm] nouveau 0000:03:00.0: 0xE894: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE894: Type 02 Reg 0x00004020 Freq 1200000KHz
>[drm] nouveau 0000:03:00.0: Loading PLL limits for register 0x00004020
>[drm] nouveau 0000:03:00.0: pll.vco1.minfreq: 1000000
>[drm] nouveau 0000:03:00.0: pll.vco1.maxfreq: 2000000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_inputfreq: 50000
>[drm] nouveau 0000:03:00.0: pll.vco1.max_inputfreq: 100000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_n: 10
>[drm] nouveau 0000:03:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:03:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:03:00.0: pll.vco2.minfreq: 1000000
>[drm] nouveau 0000:03:00.0: pll.vco2.maxfreq: 2000000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:03:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:03:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:03:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:03:00.0: pll.refclk: 100000
>[drm] nouveau 0000:03:00.0: 0xE8B6: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xDE67: End of script 8
>[drm] nouveau 0000:03:00.0: 0xDE69: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:03:00.0: 0xDE69: Calling script 6
>[drm] nouveau 0000:03:00.0: 0xE84E: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE84E: Type 01 Reg 0x00004028 Freq 480000KHz
>[drm] nouveau 0000:03:00.0: Loading PLL limits for register 0x00004028
>[drm] nouveau 0000:03:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:03:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_inputfreq: 14000
>[drm] nouveau 0000:03:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_n: 14
>[drm] nouveau 0000:03:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:03:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:03:00.0: pll.vco2.minfreq: 500000
>[drm] nouveau 0000:03:00.0: pll.vco2.maxfreq: 1000000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:03:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:03:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:03:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:03:00.0: pll.refclk: 100000
>[drm] nouveau 0000:03:00.0: 0xE870: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xDE69: End of script 6
>[drm] nouveau 0000:03:00.0: 0xDE6B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDE6B: Reg: 0x0000E18C, Mask: 0xFFFFFFFF, Data: 0x00100000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:03:00.0: 0xDE78: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDE78: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xDE7B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E818, Data: 0x88080000
>[drm] nouveau 0000:03:00.0: 0xDE84: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDE84: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:03:00.0: 0xDE87: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E818, Data: 0x80080000
>[drm] nouveau 0000:03:00.0: 0xDE90: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xDE90: Condition: 0x10
>[drm] nouveau 0000:03:00.0: 0xDE90: Cond: 0x10, Reg: 0x00004080, Mask: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004080, Data: 0x00030000
>[drm] nouveau 0000:03:00.0: 0xDE90: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:03:00.0: 0xDE90: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:03:00.0: 0xDE92: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xDE92: ------ Skipping following commands  ------
>[drm] nouveau 0000:03:00.0: 0xDE93: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEA0: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDEA3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEAC: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDEAF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEB8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xDEB8: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xDEB9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E824, Data: 0x00200000
>[drm] nouveau 0000:03:00.0: 0xDEC2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEC2: Reg: 0x0000E820, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:03:00.0: 0xDECF: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDECF: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xDED2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDED2: Reg: 0x00004020, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004020, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 0xDEDF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEDF: Reg: 0x00004028, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004028, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004028, Data: 0x80010000
>[drm] nouveau 0000:03:00.0: 0xDEEC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEEC: Reg: 0x00004008, Mask: 0xFFFFFFFF, Data: 0x90001200
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004008, Data: 0x00081200
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004008, Data: 0x90081200
>[drm] nouveau 0000:03:00.0: 0xDEF9: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDEF9: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xDEFC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDEFC: Reg: 0x00004028, Mask: 0xFFFFFFFF, Data: 0xA0000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004028, Data: 0x80010000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004028, Data: 0xA0010000
>[drm] nouveau 0000:03:00.0: 0xDF09: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF09: Reg: 0x00004008, Mask: 0xFFFFEFFF, Data: 0x90004600
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004008, Data: 0x90081200
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004008, Data: 0x90084600
>[drm] nouveau 0000:03:00.0: 0xDF16: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xDF16: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:03:00.0: 0xDF19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF19: Reg: 0x0000C040, Mask: 0x03FF3340, Data: 0x2C001033
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000C040, Data: 0x3E801008
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000C040, Data: 0x2E801033
>[drm] nouveau 0000:03:00.0: 0xDF26: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF26: Reg: 0x00004008, Mask: 0xFFFFFDFF, Data: 0x90004400
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004008, Data: 0x90084600
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004008, Data: 0x90084400
>[drm] nouveau 0000:03:00.0: 0xDF33: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF33: Reg: 0x00004020, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 0xDF40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF40: Reg: 0x00020018, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:03:00.0: 0xDF4D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xDF4D: Executing subroutine at 0xEC8E
>[drm] nouveau 0000:03:00.0: 0xEC8E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xDF4D: End of 0xEC8E subroutine
>[drm] nouveau 0000:03:00.0: 0xDF50: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000C044, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xDF59: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100F34, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xDF62: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:03:00.0: 0xDF6B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E610, Data: 0x0000000F
>[drm] nouveau 0000:03:00.0: 0xDF74: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E61C, Data: 0x0000000F
>[drm] nouveau 0000:03:00.0: 0xDF7D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E690, Data: 0xF4770204
>[drm] nouveau 0000:03:00.0: 0xDF86: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF86: Reg: 0x00089008, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00089008, Data: 0x03000010
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00089008, Data: 0x03000010
>[drm] nouveau 0000:03:00.0: 0xDF93: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDF93: Reg: 0x0008900C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0008900C, Data: 0x00FCACAC
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008900C, Data: 0x00FCACAC
>[drm] nouveau 0000:03:00.0: 0xDFA0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFA0: Reg: 0x0000154C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000154C, Data: 0x0000007C
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000154C, Data: 0x0000007C
>[drm] nouveau 0000:03:00.0: 0xDFAD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFAD: Reg: 0x00088460, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00088460, Data: 0xB0602220
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088460, Data: 0xB0602220
>[drm] nouveau 0000:03:00.0: 0xDFBA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFBA: Reg: 0x00089028, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00089028, Data: 0x00FAF100
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00089028, Data: 0x00FAF100
>[drm] nouveau 0000:03:00.0: 0xDFC7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFC7: Reg: 0x0008902C, Mask: 0xFF8FFF60, Data: 0x0040008E
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0008902C, Data: 0x00408E8E
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008902C, Data: 0x00408E8E
>[drm] nouveau 0000:03:00.0: 0xDFD4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008848C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xDFDD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFDD: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001C69
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:03:00.0: 0xDFEA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xDFEA: Reg: 0x00088610, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00088610, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088610, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xDFF7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020080, Data: 0x100C0736
>[drm] nouveau 0000:03:00.0: 0xE000: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table 1 at offset 0xE001
>[drm] nouveau 0000:03:00.0: 0xE001: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xE001: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE001: Reg: 0x00100718, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100718, Data: 0x00022077
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010071C, Data: 0x00044077
>[drm] nouveau 0000:03:00.0: 0xE048: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE048: Reg: 0x001008A0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001008A0, Data: 0x87703FB9
>[drm] nouveau 0000:03:00.0: 0xE06F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100920, Data: 0x0F0F0F0F
>[drm] nouveau 0000:03:00.0: 0xE078: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE078: Reg: 0x00100A20, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100A20, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE09F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE09F: Reg: 0x00100A40, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100A40, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE0C6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE0C6: Reg: 0x00100A60, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100A60, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE0ED: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE0ED: Reg: 0x00100A80, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100A80, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE114: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE114: Reg: 0x00100AA0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100AA0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE13B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE13B: Reg: 0x00100AC0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100AC0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE162: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE162: Reg: 0x001005A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001005A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001005A4, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE1A9: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xE1A9: Executing subroutine at 0xE5AD
>[drm] nouveau 0000:03:00.0: 0xE5AD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE5AD: Reg: 0x00004008, Mask: 0xFFFF9FFF, Data: 0x00006000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004008, Data: 0x90084400
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:03:00.0: 0xE5BA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE5BA: Reg: 0x00100760, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100760, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE5E1: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE5E1: Reg: 0x00100780, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100780, Data: 0xDDDDDDDD
>[drm] nouveau 0000:03:00.0: 0xE608: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE608: Reg: 0x001007A0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001007A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE62F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE62F: Reg: 0x001007C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001007C0, Data: 0xDDDDDDDD
>[drm] nouveau 0000:03:00.0: 0xE656: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE656: Reg: 0x001007E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001007E0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE67D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE67D: Reg: 0x00100800, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100800, Data: 0xAAAAAAAA
>[drm] nouveau 0000:03:00.0: 0xE6A4: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xE1A9: End of 0xE5AD subroutine
>[drm] nouveau 0000:03:00.0: 0xE1AC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xE1AC: Executing subroutine at 0xE6A5
>[drm] nouveau 0000:03:00.0: 0xE6A5: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE6A5: Reg: 0x00100820, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100820, Data: 0x11111111
>[drm] nouveau 0000:03:00.0: 0xE6CC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE6CC: Reg: 0x00100840, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100840, Data: 0x22222222
>[drm] nouveau 0000:03:00.0: 0xE6F3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xE1AC: End of 0xE6A5 subroutine
>[drm] nouveau 0000:03:00.0: 0xE1AF: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xE1AF: Executing subroutine at 0xE6F4
>[drm] nouveau 0000:03:00.0: 0xE6F4: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE6F4: Reg: 0x00100860, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100860, Data: 0x11111111
>[drm] nouveau 0000:03:00.0: 0xE71B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE71B: Reg: 0x00100880, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100880, Data: 0x22222222
>[drm] nouveau 0000:03:00.0: 0xE742: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xE742: BaseReg: 0x001009C0, Count: 0x07
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C0, Data: 0x04040004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C4, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009C8, Data: 0x04040004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009CC, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D0, Data: 0x00000404
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D4, Data: 0x04000004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009D8, Data: 0x04000004
>[drm] nouveau 0000:03:00.0: 0xE764: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE764: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x05, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009E8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001009EC, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE80B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xE1AF: End of 0xE6F4 subroutine
>[drm] nouveau 0000:03:00.0: 0xE1B2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE1B2: Reg: 0x00100714, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100714, Data: 0x00033122
>[drm] nouveau 0000:03:00.0: 0xE1D9: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xE1D9: BaseReg: 0x00100740, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100740, Data: 0x0E000000
>[drm] nouveau 0000:03:00.0: 0xE1E3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100DA0, Data: 0x00000010
>[drm] nouveau 0000:03:00.0: 0xE1EC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100710, Data: 0x00000070
>[drm] nouveau 0000:03:00.0: 0xE1F5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010024C, Data: 0x0A010080
>[drm] nouveau 0000:03:00.0: 0xE1FE: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE1FE: Reg: 0x00100254, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100254, Data: 0x00000002
>[drm] nouveau 0000:03:00.0: 0xE225: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010053C, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xE22E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE22E: Reg: 0x00100080, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100080, Data: 0x00000020
>[drm] nouveau 0000:03:00.0: 0xE255: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE255: Reg: 0x00100220, RegIncrement: 0x04, Count: 0x0B, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100220, Data: 0x0C162A22
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100224, Data: 0x0E010A0B
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100228, Data: 0x0208070B
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010022C, Data: 0x1F160A0A
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100230, Data: 0x23000808
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100234, Data: 0x2A0B0D0C
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100238, Data: 0x00330136
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010023C, Data: 0x040A0202
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100240, Data: 0x110F0300
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100244, Data: 0x00000186
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100248, Data: 0x03EBE80F
>[drm] nouveau 0000:03:00.0: 0xE3BC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE3BC: Reg: 0x00100200, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xE3E3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE3E3: Reg: 0x00100204, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100204, Data: 0x01559000
>[drm] nouveau 0000:03:00.0: 0xE40A: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xE40A: Condition: 0x0B
>[drm] nouveau 0000:03:00.0: 0xE40A: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE40A: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:03:00.0: 0xE40A: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xE40C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE419: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xE419: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xE41A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE41A: Reg: 0x00100214, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100214, Data: 0x00000022
>[drm] nouveau 0000:03:00.0: 0xE441: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE441: Reg: 0x00100250, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100250, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE468: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE468: Reg: 0x0000122C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000122C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000122C, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE475: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE475: Sleeping for 0x0FA0 microseconds
>[drm] nouveau 0000:03:00.0: 0xE478: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE478: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE47A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE47A: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE47D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100218, Data: 0x01000000
>[drm] nouveau 0000:03:00.0: 0xE486: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0010021C, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE48F: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE48F: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE492: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xE492: Condition: 0x0B
>[drm] nouveau 0000:03:00.0: 0xE492: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE492: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:03:00.0: 0xE492: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xE494: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xE49D: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xE49D: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xE49E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100218, Data: 0x01000100
>[drm] nouveau 0000:03:00.0: 0xE4A7: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xE4A8: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE4A8: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE4AB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100218, Data: 0x01000101
>[drm] nouveau 0000:03:00.0: 0xE4B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE4B4: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE4B7: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE4B7: Macro: 0x02, MacroTableIndex: 0x02, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE4B9: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE4B9: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE4BB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE4BB: Reg: 0x001002E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002E0, Data: 0x00600000
>[drm] nouveau 0000:03:00.0: 0xE4E2: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xE4E2: Condition: 0x0B
>[drm] nouveau 0000:03:00.0: 0xE4E2: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE4E2: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:03:00.0: 0xE4E2: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xE4E4: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 0xE50B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xE50B: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xE50C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE50C: Reg: 0x001002C4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002C4, Data: 0x001002B8
>[drm] nouveau 0000:03:00.0: 0xE533: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xE534: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:03:00.0: 0xE534: Reg: 0x001002C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:03:00.0: 0xE55B: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xE55B: Condition: 0x0C
>[drm] nouveau 0000:03:00.0: 0xE55B: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xE55B: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:03:00.0: 0xE55B: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xE55D: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xE566: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xE56F: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xE578: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xE578: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xE579: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE579: Reg: 0x0000E108, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:03:00.0: 0xE586: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE586: Macro: 0x02, MacroTableIndex: 0x02, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE588: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE588: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE58A: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE58A: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE58C: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE58C: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE58E: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE58E: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE590: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE590: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE593: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100210, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE59C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE59C: Reg: 0x00004008, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:03:00.0: 0xE5A9: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE5A9: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE5AC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table 2 at offset 0xE80C
>[drm] nouveau 0000:03:00.0: 0xE80C: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xE80C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE80C: Reg: 0x001008C0, Mask: 0x00000000, Data: 0x8B303A98
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x001008C0, Data: 0x8B000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001008C0, Data: 0x8B303A98
>[drm] nouveau 0000:03:00.0: 0xE819: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000108C, Data: 0x000000D1
>[drm] nouveau 0000:03:00.0: 0xE822: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xF0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194F0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194F0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE825: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:03:00.0: 0xE825: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x08, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x08
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x09
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 0xE82C: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:03:00.0: 0xE82C: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x18, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x18
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 0xE833: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:03:00.0: 0xE833: Index: 0x88, Mask: 0xBF, Data: 0x40
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x44
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 0xE837: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:03:00.0: 0xE837: Index: 0x8A, Mask: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 0xE83B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E200, Data: 0x0003103C
>[drm] nouveau 0000:03:00.0: 0xE844: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x30, Head: 0x00, Data: 0x10
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619430, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:03:00.0: 0xE847: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x31, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:03:00.0: 0xE84A: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xAA, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006194A8, Data: 0x00020000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006194A8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xE84D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table 3 at offset 0xE8DA
>[drm] nouveau 0000:03:00.0: 0xE8DA: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xE8DA: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xE8DA: Executing subroutine at 0xCDD0
>[drm] nouveau 0000:03:00.0: 0xCDD0: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xE8DA: End of 0xCDD0 subroutine
>[drm] nouveau 0000:03:00.0: 0xE8DD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE8DD: Reg: 0x00100E04, Mask: 0xFFE0007F, Data: 0x00048900
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100E04, Data: 0x80040801
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100E04, Data: 0x80048901
>[drm] nouveau 0000:03:00.0: 0xE8EA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE8EA: Reg: 0x00100E08, Mask: 0xF01FFFFF, Data: 0x05E00000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100E08, Data: 0x06610808
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100E08, Data: 0x05E10808
>[drm] nouveau 0000:03:00.0: 0xE8F7: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xE8F7: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: 0xE8FA: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:03:00.0: 0xE8FA: Calling script 10
>[drm] nouveau 0000:03:00.0: 0xBD68: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBD68: Condition: 0x0C
>[drm] nouveau 0000:03:00.0: 0xBD68: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xBD68: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:03:00.0: 0xBD68: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBD6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBD77: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBD77: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBD78: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBD78: Reg: 0x001002C0, Mask: 0xFFFFFEFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:03:00.0: 0xBD85: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBD85: Condition: 0x0C
>[drm] nouveau 0000:03:00.0: 0xBD85: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xBD85: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:03:00.0: 0xBD85: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBD87: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBD94: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBD94: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBD95: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBD95: Reg: 0x001002C0, Mask: 0xFFFFFFFF, Data: 0x00000100
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:03:00.0: 0xBDA2: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:03:00.0: 0xBDA2: Sleeping for 0x0028 microseconds
>[drm] nouveau 0000:03:00.0: 0xBDA5: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBDA5: Condition: 0x0C
>[drm] nouveau 0000:03:00.0: 0xBDA5: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xBDA5: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:03:00.0: 0xBDA5: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBDA7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDB4: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBDB4: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBDB5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDB5: Reg: 0x001002C0, Mask: 0xFFFFFEFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:03:00.0: 0xBDC2: [ (0x39) - INIT_IO_FLAG_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBDC2: Port: 0x03D4, Index: 0x88, Mask: 0x07, Shift: 0x00, FlagArray: 0xBD5F, FAMask: 0x80, Cmpval: 0x80
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x44
>[drm] nouveau 0000:03:00.0: 0xBDC2: Checking if 0x00 equals 0x80
>[drm] nouveau 0000:03:00.0: 0xBDC2: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBDC4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDCD: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDD6: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDDF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDE8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDF1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 0xBDFA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBDFA: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBDFB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xE8FA: End of script 10
>[drm] nouveau 0000:03:00.0: 0xE8FC: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE8FC: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE8FE: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE8FE: Repeating following segment 10 times
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:03:00.0: 0xE903: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE903: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE905: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE905: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE907: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:03:00.0: 0xE907: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 0xE909: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100210, Data: 0x80000001
>[drm] nouveau 0000:03:00.0: 0xE912: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE912: Reg: 0x00100200, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:03:00.0: 0xE91F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100678, Data: 0x58805880
>[drm] nouveau 0000:03:00.0: 0xE928: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100B08, Data: 0x000003FF
>[drm] nouveau 0000:03:00.0: 0xE931: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE931: Reg: 0x00100600, Mask: 0xFFFFFFFF, Data: 0x00004000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00100600, Data: 0x97030610
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:03:00.0: 0xE93E: [ (0x63) - INIT_COMPUTE_MEM ]
>[drm] nouveau 0000:03:00.0: 0xE93F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00612000, Data: 0x00000210
>[drm] nouveau 0000:03:00.0: 0xE948: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614000, Data: 0x00000210
>[drm] nouveau 0000:03:00.0: 0xE951: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614100, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 0xE95A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614900, Data: 0x10000000
>[drm] nouveau 0000:03:00.0: 0xE963: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614110, Data: 0x0005003A
>[drm] nouveau 0000:03:00.0: 0xE96C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614114, Data: 0x50070012
>[drm] nouveau 0000:03:00.0: 0xE975: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614120, Data: 0x00450800
>[drm] nouveau 0000:03:00.0: 0xE97E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614920, Data: 0x00450800
>[drm] nouveau 0000:03:00.0: 0xE987: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614124, Data: 0x00040000
>[drm] nouveau 0000:03:00.0: 0xE990: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00614924, Data: 0x00040000
>[drm] nouveau 0000:03:00.0: 0xE999: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A008, Data: 0x03A502D1
>[drm] nouveau 0000:03:00.0: 0xE9A2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A178, Data: 0x0E08C28C
>[drm] nouveau 0000:03:00.0: 0xE9AB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A1B8, Data: 0x0E08C28C
>[drm] nouveau 0000:03:00.0: 0xE9B4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A1F8, Data: 0x8BC8927C
>[drm] nouveau 0000:03:00.0: 0xE9BD: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A238, Data: 0x0E08C28C
>[drm] nouveau 0000:03:00.0: 0xE9C6: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A2B8, Data: 0x8BC8927C
>[drm] nouveau 0000:03:00.0: 0xE9CF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A338, Data: 0x000BD234
>[drm] nouveau 0000:03:00.0: 0xE9D8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE9D8: Reg: 0x0061A148, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A148, Data: 0x4015020D
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A148, Data: 0x4015020D
>[drm] nouveau 0000:03:00.0: 0xE9E5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE9E5: Reg: 0x0061A188, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A188, Data: 0x4015020D
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A188, Data: 0x4015020D
>[drm] nouveau 0000:03:00.0: 0xE9F2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE9F2: Reg: 0x0061A1C8, Mask: 0xFF00FFFF, Data: 0x00170000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A1C8, Data: 0x0C170271
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A1C8, Data: 0x0C170271
>[drm] nouveau 0000:03:00.0: 0xE9FF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xE9FF: Reg: 0x0061A208, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A208, Data: 0x4415020D
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A208, Data: 0x4415020D
>[drm] nouveau 0000:03:00.0: 0xEA0C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA0C: Reg: 0x0061A288, Mask: 0xFF00FFFF, Data: 0x00170000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061A288, Data: 0x0C170271
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061A288, Data: 0x0C170271
>[drm] nouveau 0000:03:00.0: 0xEA19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA19: Reg: 0x006165A4, Mask: 0xFFFFFF80, Data: 0x00000038
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006165A4, Data: 0x00020038
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006165A4, Data: 0x00020038
>[drm] nouveau 0000:03:00.0: 0xEA26: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA26: Reg: 0x00616DA4, Mask: 0xFFFFFF80, Data: 0x00000038
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00616DA4, Data: 0x00020038
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00616DA4, Data: 0x00020038
>[drm] nouveau 0000:03:00.0: 0xEA33: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA33: Reg: 0x0061E818, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061E818, Data: 0x00000302
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:03:00.0: 0xEA40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA40: Reg: 0x0061F018, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061F018, Data: 0x00000302
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:03:00.0: 0xEA4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA4D: Reg: 0x00003310, Mask: 0xFFFFF8FF, Data: 0x00000300
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00003310, Data: 0x00000500
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00003310, Data: 0x00000300
>[drm] nouveau 0000:03:00.0: 0xEA5A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00617338, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 0xEA63: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C080, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEA6C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C084, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEA75: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x85, Head: 0x00, Data: 0xFF
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619484, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619484, Data: 0x0000FF00
>[drm] nouveau 0000:03:00.0: 0xEA78: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA78: Reg: 0x006105D4, Mask: 0xFFFFFFE0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006105D4, Data: 0x0000001F
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006105D4, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEA85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA85: Reg: 0x006105D8, Mask: 0xFFFFFFE0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006105D8, Data: 0x0000001F
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006105D8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEA92: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA92: Reg: 0x006105DC, Mask: 0xF8000000, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x006105DC, Data: 0x07F70003
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x006105DC, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEA9F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEA9F: Reg: 0x0008814C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:03:00.0: 0xEAAC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00100DC0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEAB5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000010A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEABE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEABE: Reg: 0x00001090, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEACB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEACB: Reg: 0x00001090, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEAD8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000010A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEAE1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEAE1: Reg: 0x00088150, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00088150, Data: 0x6000FE15
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00088150, Data: 0x6000FE15
>[drm] nouveau 0000:03:00.0: 0xEAEE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEAEE: Reg: 0x0000E120, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEAFB: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xEAFB: BaseReg: 0x00020480, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020480, Data: 0x0000007D
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020484, Data: 0x0000000A
>[drm] nouveau 0000:03:00.0: 0xEB09: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000204C0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000204D8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000204E0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x000204E8, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB2D: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xEB2D: BaseReg: 0x0002010C, Count: 0x06
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0002010C, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020110, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020114, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020118, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0002011C, Data: 0x00876530
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020120, Data: 0x00000241
>[drm] nouveau 0000:03:00.0: 0xEB4B: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xEB4B: BaseReg: 0x00020074, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020074, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020078, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB59: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xEB59: BaseReg: 0x00020094, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020094, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020098, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB67: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEB67: Reg: 0x0000E1F4, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:03:00.0: 0xEB74: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xEB74: BaseReg: 0x00020000, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020000, Data: 0xC0000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020004, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEB82: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00020108, Data: 0x08000000
>[drm] nouveau 0000:03:00.0: 0xEB8B: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:03:00.0: 0xEB8B: Index: 0x88, Mask: 0x7F, Data: 0x80
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x44
>[drm] nouveau 0000:03:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000044
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:03:00.0: 0xEB8F: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table 4 at offset 0xEB90
>[drm] nouveau 0000:03:00.0: 0xEB90: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xEB90: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Parsing VBIOS init table at offset 0xEBF5
>[drm] nouveau 0000:03:00.0: 0xEBF5: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:03:00.0: 0xEBF5: Condition: 0x01, Retries: 0x64
>[drm] nouveau 0000:03:00.0: 0xEBF5: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 0xEBF5: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:03:00.0: 0xEBF5: Condition met, continuing
>[drm] nouveau 0000:03:00.0: 0xEBF5: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 0xEBF5: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:03:00.0: 0xEBF8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xEBF9: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEBF9: SrcReg: 0x00610000, Shift: 0x00, SrcMask: 0x0000FFFF, Xor: 0x00000000, DstReg: 0x0061000C, DstMask: 0xFFFF0000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00610000, Data: 0x887D0140
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061000C, Data: 0x80000140
>[drm] nouveau 0000:03:00.0: 0xEC0F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xEC0F: Reg: 0x0061000C, Mask: 0xBFFFFFFF, Data: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000140
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061000C, Data: 0xC0000140
>[drm] nouveau 0000:03:00.0: 0xEC1C: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:03:00.0: 0xEC1C: Condition: 0x02, Retries: 0x64
>[drm] nouveau 0000:03:00.0: 0xEC1C: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0xC0000140
>[drm] nouveau 0000:03:00.0: 0xEC1C: Checking if 0x40000000 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEC1C: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:03:00.0: 0xEC1C: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000140
>[drm] nouveau 0000:03:00.0: 0xEC1C: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEC1C: Condition met, continuing
>[drm] nouveau 0000:03:00.0: 0xEC1C: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000140
>[drm] nouveau 0000:03:00.0: 0xEC1C: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:03:00.0: 0xEC1F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xEC20: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:03:00.0: 0xCD08: parsing output script 0
>[drm] nouveau 0000:03:00.0: 0xCD08: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:03:00.0: 0xCA3C: parsing output script 0
>[drm] nouveau 0000:03:00.0: 0xCA3C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xCA3C: Executing subroutine at 0xCA84
>[drm] nouveau 0000:03:00.0: 0xCA84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xCA84: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C84C, Data: 0x0000A000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C864, Data: 0x1E002000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 0xCACA: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xCA3C: End of 0xCA84 subroutine
>[drm] nouveau 0000:03:00.0: 0xCA3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xCA3F: Reg: 0x4061C014, Mask: 0xFFFEFFFF, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C814, Data: 0x00850000
>[drm] nouveau 0000:03:00.0: 0xCA4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xCA4C: Reg: 0x4061C00C, Mask: 0xFFFFFFDF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x020003F0
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061C80C, Data: 0x020003D0
>[drm] nouveau 0000:03:00.0: 0xCA59: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:03:00.0: 0xCD08: parsing output script 0
>[drm] nouveau 0000:03:00.0: 0xCD08: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: Searching for output entry for 2 0 4
>[drm] nouveau 0000:03:00.0: 0xCA3C: parsing output script 0
>[drm] nouveau 0000:03:00.0: 0xCA3C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xCA3C: Executing subroutine at 0xCA84
>[drm] nouveau 0000:03:00.0: 0xCA84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xCA84: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D040, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D044, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D048, Data: 0x1E000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D04C, Data: 0x0000A000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D050, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D054, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D058, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D05C, Data: 0x00008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D060, Data: 0x00002000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D064, Data: 0x1E002000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D068, Data: 0x1F000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D06C, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D070, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D074, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D078, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D07C, Data: 0x1F008000
>[drm] nouveau 0000:03:00.0: 0xCACA: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xCA3C: End of 0xCA84 subroutine
>[drm] nouveau 0000:03:00.0: 0xCA3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xCA3F: Reg: 0x4061C014, Mask: 0xFFFEFFFF, Data: 0x00010000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D014, Data: 0x00840000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D014, Data: 0x00850000
>[drm] nouveau 0000:03:00.0: 0xCA4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xCA4C: Reg: 0x4061C00C, Mask: 0xFFFFFFDF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D00C, Data: 0x020003F0
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D00C, Data: 0x020003D0
>[drm] nouveau 0000:03:00.0: 0xCA59: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:602 - Entry 0: 220: 02040605 08010805 02020102 19160404
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 06020702 00000000 04040202
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:602 - Entry 1: 220: 02040605 08010807 02020102 1b160606
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 06020902 00000000 04060202
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:602 - Entry 2: 220: 0c162a22 0d01090b 0208070b 1f160a0a
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 2a0b0d0c 00000000 040a0202
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:602 - Entry 3: 220: 0916271f 0d01080a 0208060a 1e160909
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 270a0c09 00000000 04090202
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:602 - Entry 4: 220: 02050807 08010607 02020202 1b160606
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:605 -          230: 1f160707 08020902 00000000 04060202
>[drm] nouveau 0000:03:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:03:00.0: nouveau_i2c_identify:540 - Probing monitoring devices on I2C bus: 2
>[drm] nouveau 0000:03:00.0: nouveau_i2c_identify:549 - No devices found.
>[drm] nouveau 0000:03:00.0: 2 available performance level(s)
>[drm] nouveau 0000:03:00.0: 0: core 169MHz shader 338MHz memory 100MHz timing 0 voltage 900mV fanspeed 100%
>[drm] nouveau 0000:03:00.0: 3: core 480MHz shader 1200MHz memory 700MHz timing 3 voltage 1000mV fanspeed 100%
>[drm] nouveau 0000:03:00.0: c: core 480MHz shader 1200MHz memory 702MHz voltage 1000mV
>[drm] nouveau 0000:03:00.0: nv50_vram_rblock:153 - memcfg 0x00001000 0x01559000 0x00000001 0xf1010001
>[drm] nouveau 0000:03:00.0: nv50_vram_rblock:181 - rblock 98304 bytes
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_init:242 - 
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000003
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010dac05c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=131072 align=4096 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010dac0cc0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00010200 vinst=0x0000058200 size=0x00004000 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d9961c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00014200 vinst=0x000005c200 size=0x00000100 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d9965c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d9966c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d996a40
>[TTM] Zone  kernel: Available graphics memory: 2017636 kiB.
>[TTM] Initializing pool allocator.
>[TTM] Initializing DMA pool allocator.
>[drm] nouveau 0000:03:00.0: Detected 256MiB VRAM
>mtrr: type mismatch for f0000000,4000000 old: write-back new: write-combining
>[drm] nouveau 0000:03:00.0: 512 MiB GART (aperture)
>[drm] nouveau 0000:03:00.0: nv50_fb_create:59 - 959 tags available
>[drm] nouveau 0000:03:00.0: nv50_graph_init:131 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_init:166 - 
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da2b9c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d8072c0
>[drm] nouveau 0000:03:00.0: nv50_fifo_init_reset:99 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_init_intr:108 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_init_context_table:121 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch1
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch2
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch3
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch4
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch5
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch6
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch7
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch8
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch9
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch10
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch11
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch12
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch13
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch14
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch15
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch16
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch17
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch18
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch19
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch20
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch21
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch22
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch23
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch24
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch25
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch26
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch27
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch28
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch29
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch30
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch31
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch32
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch33
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch34
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch35
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch36
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch37
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch38
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch39
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch40
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch41
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch42
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch43
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch44
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch45
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch46
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch47
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch48
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch49
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch50
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch51
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch52
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch53
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch54
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch55
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch56
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch57
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch58
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch59
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch60
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch61
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch62
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch63
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch64
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch65
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch66
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch67
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch68
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch69
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch70
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch71
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch72
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch73
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch74
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch75
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch76
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch77
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch78
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch79
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch80
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch81
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch82
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch83
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch84
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch85
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch86
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch87
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch88
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch89
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch90
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch91
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch92
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch93
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch94
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch95
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch96
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch97
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch98
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch99
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch100
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch101
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch102
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch103
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch104
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch105
>usb 1-6: New USB device found, idVendor=0951, idProduct=162d
>usb 1-6: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>usb 1-6: Product: DataTraveler 102
>usb 1-6: Manufacturer: Kingston
>usb 1-6: SerialNumber: 001372982B41BB31851C006E
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch106
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch107
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch108
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch109
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch110
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch111
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch112
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch113
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch114
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch115
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch116
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch117
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch118
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch119
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch120
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch121
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch122
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch123
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch124
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch125
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_disable:85 - ch126
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:03:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_init_regs__nv:136 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_init_regs:144 - 
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_enable:68 - ch127
>usb 1-6: configuration #1 chosen from 1 choice
>Slow work thread pool: Starting up
>Slow work thread pool: Ready
>[drm] nouveau 0000:03:00.0: nv50_display_create:330 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010dac02c0
>[drm] nouveau 0000:03:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:03:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:03:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:03:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:03:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:03:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:03:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:03:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:03:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=32768 align=65536 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5bd40
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=16 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5bc40
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=0 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5bbc0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5bb40
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000d30: h=0xcafe0000, c=0x00800000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5bac0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000200
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000200: h=0x01000000, c=0x00808000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5ba40
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000218: h=0x01000003, c=0x00810000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b9c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000210: h=0x01000002, c=0x00818000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b940
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000208: h=0x01000001, c=0x00820000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b740
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000d38: h=0xcafe0000, c=0x10828001
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b6c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000220: h=0x01000003, c=0x10830001
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b640
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000228: h=0x01000002, c=0x10838001
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b5c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000208: h=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000228: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000230: h=0x01000001, c=0x10840001
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b3c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d38: h=0xcafe0000
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000d40: h=0xcafe0000, c=0x20848002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b340
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000238: h=0x01000003, c=0x20850002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b2c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000240: h=0x01000002, c=0x20858002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b240
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000208: h=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000240: h=0x01000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000248: h=0x01000001, c=0x20860002
>[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[drm] No driver support for vblank timestamp query.
>[drm] nouveau 0000:03:00.0: nouveau_channel_alloc:157 - initialising channel 1
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_channel_init:752 - ch1 vram=0x80000002 tt=0x80000003
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_channel_init_pramin:660 - ch1
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=66560 align=4096 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010da5b140
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x0013a200 vinst=0x0000198200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d25df40
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25dec0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25de40
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000010
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25ddc0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000011
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25dd40
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000002
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000410
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000410: h=0x80000002, c=0x00000e04
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25dcc0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000003
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000418
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000418: h=0x80000003, c=0x00000e06
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25dbc0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d8c0
>[drm] nouveau 0000:03:00.0: nv50_fifo_create_context:237 - ch1
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d840
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d7c0
>[drm] nouveau 0000:03:00.0: nv50_fifo_channel_enable:68 - ch1
>[drm] nouveau 0000:03:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x5039
>[drm] nouveau 0000:03:00.0: nv50_graph_context_new:235 - ch1
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=376832 align=0 flags=0x00000006
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d6c0
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d5c0
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000001
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000408: h=0x80000001, c=0x00100f40
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d540
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000006
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000430: h=0x80000006, c=0x00000f41
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x506e
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x8000000e
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_channel_alloc:215 - channel 1 initialised
>[drm] nouveau 0000:03:00.0: nv50_display_init:147 - 
>[drm] nouveau 0000:03:00.0: Ch0/0x00000080: 0x00080084
>[drm] nouveau 0000:03:00.0: Ch0/0x00000084: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000088: 0xcafe0000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000008c: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch0/0x00000090: 0x80000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000094: 0x00040080
>[drm] nouveau 0000:03:00.0: Ch0/0x00000098: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000009c: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch0/0x000000a0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000a4: PUSH!
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1]
>[drm] nouveau 0000:03:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(0): sink not detected
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1] disconnected
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-2]
>[drm] nouveau 0000:03:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 00 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 01 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 02 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 03 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 04 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 05 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 06 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 07 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 08 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 09 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 10 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 11 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 12 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 13 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 14 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 15 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 16 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 17 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 18 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 19 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 20 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 21 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 22 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 23 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 24 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 25 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 26 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 27 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 28 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 29 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 30 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 31 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-2] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 13 enabled? no
>[drm:drm_enable_connectors], connector 16 enabled? yes
>[drm:drm_target_preferred], looking for cmdline mode on connector 16
>[drm:drm_target_preferred], looking for preferred mode on connector 16
>[drm:drm_target_preferred], found mode 1680x1050
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1680x1050 set on crtc 11
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d340
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x502d
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:03:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d25d240
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000007
>[drm] nouveau 0000:03:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000438
>[drm] nouveau 0000:03:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000438: h=0x80000007, c=0x00100f43
>[drm] nouveau 0000:03:00.0: allocated 1680x1050 fb: 0x310000, bo ffff88010d1f2800
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:41] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-2] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm] nouveau 0000:03:00.0: nv50_sor_mode_fixup:156 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:03:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:03:00.0: Ch1/0x00000080: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch1/0x00000084: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x00000088: 0x00040094
>[drm] nouveau 0000:03:00.0: Ch1/0x0000008c: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x00000090: 0x000400c0
>[drm] nouveau 0000:03:00.0: Ch1/0x00000094: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x00000098: 0x00040080
>[drm] nouveau 0000:03:00.0: Ch1/0x0000009c: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000a0: PUSH!
>[drm] nouveau 0000:03:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:03:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:03:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:03:00.0: Ch0/0x000000a4: 0x00080880
>[drm] nouveau 0000:03:00.0: Ch0/0x000000a8: 0x05000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000ac: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000b0: 0x0004089c
>[drm] nouveau 0000:03:00.0: Ch0/0x000000b4: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000b8: 0x00080840
>[drm] nouveau 0000:03:00.0: Ch0/0x000000bc: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000c0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000c4: 0x0004085c
>[drm] nouveau 0000:03:00.0: Ch0/0x000000c8: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000cc: 0x00040874
>[drm] nouveau 0000:03:00.0: Ch0/0x000000d0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000d4: 0x00080804
>[drm] nouveau 0000:03:00.0: Ch0/0x000000d8: 0x00823b4a
>[drm] nouveau 0000:03:00.0: Ch0/0x000000dc: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000e0: 0x00180810
>[drm] nouveau 0000:03:00.0: Ch0/0x000000e4: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000000e8: 0x044108c0
>[drm] nouveau 0000:03:00.0: Ch0/0x000000ec: 0x000500af
>[drm] nouveau 0000:03:00.0: Ch0/0x000000f0: 0x002301c7
>[drm] nouveau 0000:03:00.0: Ch0/0x000000f4: 0x043d0857
>[drm] nouveau 0000:03:00.0: Ch0/0x000000f8: 0x00000001
>[drm] nouveau 0000:03:00.0: Ch0/0x000000fc: 0x0004082c
>[drm] nouveau 0000:03:00.0: Ch0/0x00000100: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000104: 0x00040900
>[drm] nouveau 0000:03:00.0: Ch0/0x00000108: 0x00000311
>[drm] nouveau 0000:03:00.0: Ch0/0x0000010c: 0x000408c8
>[drm] nouveau 0000:03:00.0: Ch0/0x00000110: 0x041a0690
>[drm] nouveau 0000:03:00.0: Ch0/0x00000114: 0x000408d4
>[drm] nouveau 0000:03:00.0: Ch0/0x00000118: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000011c: 0x000408a0
>[drm] nouveau 0000:03:00.0: Ch0/0x00000120: 0x00000011
>[drm] nouveau 0000:03:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:03:00.0: Ch0/0x00000124: 0x000408a4
>[drm] nouveau 0000:03:00.0: Ch0/0x00000128: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000012c: 0x000808d8
>[drm] nouveau 0000:03:00.0: Ch0/0x00000130: 0x041a0690
>[drm] nouveau 0000:03:00.0: Ch0/0x00000134: 0x041a0690
>[drm] nouveau 0000:03:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:03:00.0: Ch0/0x00000138: 0x00140860
>[drm] nouveau 0000:03:00.0: Ch0/0x0000013c: 0x00003100
>[drm] nouveau 0000:03:00.0: Ch0/0x00000140: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000144: 0x041a0690
>[drm] nouveau 0000:03:00.0: Ch0/0x00000148: 0x00101b00
>[drm] nouveau 0000:03:00.0: Ch0/0x0000014c: 0x0000cf00
>[drm] nouveau 0000:03:00.0: Ch0/0x00000150: 0x00040840
>[drm] nouveau 0000:03:00.0: Ch0/0x00000154: 0xc0000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000158: 0x000408a8
>[drm] nouveau 0000:03:00.0: Ch0/0x0000015c: 0x00040000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000160: 0x000408c0
>[drm] nouveau 0000:03:00.0: Ch0/0x00000164: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:21:1680x1050]
>[drm] nouveau 0000:03:00.0: nv50_sor_mode_set:203 - or 2 type 2 -> crtc 0
>[drm] nouveau 0000:03:00.0: nv50_sor_dpms:78 - or 2 type 2 mode 0
>[drm] nouveau 0000:03:00.0: Ch0/0x00000168: 0x00040680
>[drm] nouveau 0000:03:00.0: Ch0/0x0000016c: 0x00003101
>[drm] nouveau 0000:03:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:03:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:03:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:03:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:03:00.0: Ch0/0x00000170: 0x00080880
>[drm] nouveau 0000:03:00.0: Ch0/0x00000174: 0x05000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000178: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000017c: 0x0004089c
>[drm] nouveau 0000:03:00.0: Ch0/0x00000180: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000184: 0x00080840
>[drm] nouveau 0000:03:00.0: Ch0/0x00000188: 0xc0000000
>[drm] nouveau 0000:03:00.0: Ch0/0x0000018c: 0x000007a0
>[drm] nouveau 0000:03:00.0: Ch0/0x00000190: 0x0004085c
>[drm] nouveau 0000:03:00.0: Ch0/0x00000194: 0x01000000
>[drm] nouveau 0000:03:00.0: Ch0/0x00000198: 0x00080860
>[drm] nouveau 0000:03:00.0: Ch0/0x0000019c: 0x00003100
>[drm] nouveau 0000:03:00.0: Ch0/0x000001a0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000001a4: 0x00040874
>[drm] nouveau 0000:03:00.0: Ch0/0x000001a8: 0x01000003
>[drm] nouveau 0000:03:00.0: Ch0/0x000001ac: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch0/0x000001b0: 0x80000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000001b4: 0x00040080
>[drm] nouveau 0000:03:00.0: Ch0/0x000001b8: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000001bc: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch0/0x000001c0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch0/0x000001c4: PUSH!
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:03:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000002a0
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000002b0
>[drm] nouveau 0000:03:00.0: Loading PLL limits for register 0x00614100
>[drm] nouveau 0000:03:00.0: pll.vco1.minfreq: 250000
>[drm] nouveau 0000:03:00.0: pll.vco1.maxfreq: 500000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_inputfreq: 4000
>[drm] nouveau 0000:03:00.0: pll.vco1.max_inputfreq: 27000
>[drm] nouveau 0000:03:00.0: pll.vco1.min_n: 20
>[drm] nouveau 0000:03:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:03:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco1.max_m: 2
>[drm] nouveau 0000:03:00.0: pll.vco2.minfreq: 500000
>[drm] nouveau 0000:03:00.0: pll.vco2.maxfreq: 1000000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_inputfreq: 14000
>[drm] nouveau 0000:03:00.0: pll.vco2.max_inputfreq: 75000
>[drm] nouveau 0000:03:00.0: pll.vco2.min_n: 14
>[drm] nouveau 0000:03:00.0: pll.vco2.max_n: 255
>[drm] nouveau 0000:03:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:03:00.0: pll.vco2.max_m: 255
>[drm] nouveau 0000:03:00.0: pll.max_log2p: 6
>[drm] nouveau 0000:03:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:03:00.0: pll.refclk: 27000
>[drm] nouveau 0000:03:00.0: nv50_crtc_set_clock:312 - pclk 146250 out 146250 NM1 20 2 NM2 26 12 P 2
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00003101
>[drm] nouveau 0000:03:00.0: Searching for output entry for 2 0 4
>[drm] nouveau 0000:03:00.0: 0xC9B0: parsing clock script 0
>[drm] nouveau 0000:03:00.0: 0xC9B0: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xC9B0: Executing subroutine at 0xC9CE
>[drm] nouveau 0000:03:00.0: 0xC9CE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xC9CE: Reg: 0x0061D120, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D120, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D120, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xC9DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xC9DB: Reg: 0x0061D1A0, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D1A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D1A0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xC9E8: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xC9E8: Executing subroutine at 0xC9EC
>[drm] nouveau 0000:03:00.0: 0xC9EC: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xC9EC: Condition: 0x09
>[drm] nouveau 0000:03:00.0: 0xC9EC: Cond: 0x09, Reg: 0x00000000, Mask: 0xE0000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:03:00.0: 0xC9EC: Checking if 0x20000000 equals 0x20000000
>[drm] nouveau 0000:03:00.0: 0xC9EC: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:03:00.0: 0xC9EE: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xC9EE: BaseReg: 0x0061D118, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D118, Data: 0x25252525
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D11C, Data: 0x00000025
>[drm] nouveau 0000:03:00.0: 0xC9FC: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xC9FC: BaseReg: 0x0061D198, Count: 0x02
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D198, Data: 0x25252525
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D19C, Data: 0x00000025
>[drm] nouveau 0000:03:00.0: 0xCA0A: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xCA0A: ------ Skipping following commands  ------
>[drm] nouveau 0000:03:00.0: 0xCA0B: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xCA19: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xCA27: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xCA27: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xCA28: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xCA28: Executing subroutine at 0xCDD0
>[drm] nouveau 0000:03:00.0: 0xCDD0: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xCA28: End of 0xCDD0 subroutine
>[drm] nouveau 0000:03:00.0: 0xCA2B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xC9E8: End of 0xC9EC subroutine
>[drm] nouveau 0000:03:00.0: 0xC9EB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xC9B0: End of 0xC9CE subroutine
>[drm] nouveau 0000:03:00.0: 0xC9B3: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xC9B3: Executing subroutine at 0xC009
>[drm] nouveau 0000:03:00.0: 0xC009: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xC009: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00615300, Data: 0x00800484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00615300, Data: 0x00830484
>[drm] nouveau 0000:03:00.0: 0xC016: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xC9B3: End of 0xC009 subroutine
>[drm] nouveau 0000:03:00.0: 0xC9B6: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xC9B6: Executing subroutine at 0xBF07
>[drm] nouveau 0000:03:00.0: 0xBF07: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:03:00.0: 0xBF07: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D00C, Data: 0x03010E00
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D010, Data: 0x0000152F
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D014, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D018, Data: 0x00245AF8
>[drm] nouveau 0000:03:00.0: 0xBF1D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xBF1D: Executing subroutine at 0xBF55
>[drm] nouveau 0000:03:00.0: 0xBF55: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF55: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:03:00.0: 0xBF62: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF62: Reg: 0x4061C130, Mask: 0xFFBF00FF, Data: 0x00400400
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D130, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D130, Data: 0x00400400
>[drm] nouveau 0000:03:00.0: 0xBF6F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF6F: Reg: 0x4061C1B0, Mask: 0xFFBF00FF, Data: 0x00400400
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D1B0, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D1B0, Data: 0x00400400
>[drm] nouveau 0000:03:00.0: 0xBF7C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF7C: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D00C, Data: 0x03010E00
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D00C, Data: 0x03010E00
>[drm] nouveau 0000:03:00.0: 0xBF89: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF89: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00615300, Data: 0x00830484
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x00615300, Data: 0x00870484
>[drm] nouveau 0000:03:00.0: 0xBF96: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBF96: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D014, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D014, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xBFA3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:03:00.0: 0xBFA3: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x00401100
>[drm] nouveau 0000:03:00.0: 	Write: Reg: 0x0061D10C, Data: 0x00401101
>[drm] nouveau 0000:03:00.0: 0xBFB0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBFB0: Condition: 0x0D
>[drm] nouveau 0000:03:00.0: 0xBFB0: Cond: 0x0D, Reg: 0x00000008, Mask: 0x000000F0
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000008, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xBFB0: Checking if 0x00000000 equals 0x00000010
>[drm] nouveau 0000:03:00.0: 0xBFB0: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBFB2: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xBFB2: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xBFB3: [ (0x76) - INIT_IO_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBFB3: IO condition: 0x05
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619494, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x94, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 0xBFB3: Checking if 0x00 equals 0x80
>[drm] nouveau 0000:03:00.0: 0xBFB3: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBFB5: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xBFB8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBFB8: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBFB9: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xBF1D: End of 0xBF55 subroutine
>[drm] nouveau 0000:03:00.0: 0xBF20: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: 0xC9B6: End of 0xBF07 subroutine
>[drm] nouveau 0000:03:00.0: 0xC9B9: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:03:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:03:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000002b0
>[drm] nouveau 0000:03:00.0: Searching for output entry for 2 0 4
>[drm] nouveau 0000:03:00.0: 0xBFBA: parsing clock script 1
>[drm] nouveau 0000:03:00.0: 0xBFBA: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBFBA: Condition: 0x0D
>[drm] nouveau 0000:03:00.0: 0xBFBA: Cond: 0x0D, Reg: 0x00000008, Mask: 0x000000F0
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00000008, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 0xBFBA: Checking if 0x00000000 equals 0x00000010
>[drm] nouveau 0000:03:00.0: 0xBFBA: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBFBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xBFBF: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xBFC2: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:03:00.0: 0xBFC2: ------ Executing following commands ------
>[drm] nouveau 0000:03:00.0: 0xBFC3: [ (0x76) - INIT_IO_CONDITION ]
>[drm] nouveau 0000:03:00.0: 0xBFC3: IO condition: 0x05
>[drm] nouveau 0000:03:00.0: 	Read:  Reg: 0x00619494, Data: 0x00000000
>[drm] nouveau 0000:03:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x94, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:03:00.0: 0xBFC3: Checking if 0x00 equals 0x80
>[drm] nouveau 0000:03:00.0: 0xBFC3: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:03:00.0: 0xBFC5: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:03:00.0: 0xBFC8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:03:00.0: 0xBFC8: ---- Executing following commands ----
>[drm] nouveau 0000:03:00.0: 0xBFC9: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:03:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000a0: 0x00040100
>[drm] nouveau 0000:03:00.0: Ch1/0x000000a4: 0xfffe0000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000a8: 0x00040084
>[drm] nouveau 0000:03:00.0: Ch1/0x000000ac: 0x00000010
>[drm] nouveau 0000:03:00.0: Ch1/0x000000b0: 0x000400e0
>[drm] nouveau 0000:03:00.0: Ch1/0x000000b4: 0x40000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000b8: 0x00100088
>[drm] nouveau 0000:03:00.0: Ch1/0x000000bc: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000c0: 0xf00d0000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000c4: 0x74b1e000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000c8: 0xcafe0000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000cc: 0x000800a0
>[drm] nouveau 0000:03:00.0: Ch1/0x000000d0: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000d4: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000d8: 0x000400c0
>[drm] nouveau 0000:03:00.0: Ch1/0x000000dc: 0x01000003
>[drm] nouveau 0000:03:00.0: Ch1/0x000000e0: 0x00080110
>[drm] nouveau 0000:03:00.0: Ch1/0x000000e4: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000e8: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000ec: 0x00140800
>[drm] nouveau 0000:03:00.0: Ch1/0x000000f0: 0x00003100
>[drm] nouveau 0000:03:00.0: Ch1/0x000000f4: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x000000f8: 0x041a0690
>[drm] nouveau 0000:03:00.0: Ch1/0x000000fc: 0x00101b00
>[drm] nouveau 0000:03:00.0: Ch1/0x00000100: 0x0000cf00
>[drm] nouveau 0000:03:00.0: Ch1/0x00000104: 0x00040080
>[drm] nouveau 0000:03:00.0: Ch1/0x00000108: 0x00000000
>[drm] nouveau 0000:03:00.0: Ch1/0x0000010c: PUSH!
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-2] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [NOFB]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:41] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-2] to [CRTC:11]
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>Console: switching to colour frame buffer device 210x65
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:41] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-2] to [CRTC:11]
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_crtc_lut_load:48 - 
>fb0: nouveaufb frame buffer device
>drm: registered panic notifier
>[drm] Initialized nouveau 0.0.16 20090420 for 0000:03:00.0 on minor 0
>  alloc irq_desc for 18 on node -1
>  alloc kstat_irqs on node -1
>nouveau 0000:04:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
>nouveau 0000:04:00.0: setting latency timer to 64
>[drm] nouveau 0000:04:00.0: nouveau_load:1008 - vendor: 0x10DE device: 0x6FA class: 0x30000
>[drm] nouveau 0000:04:00.0: nouveau_load:1025 - regs mapped ok at 0xfa000000
>[drm] nouveau 0000:04:00.0: Detected an NV50 generation card (0x298d00a2)
>[drm] nouveau 0000:04:00.0: nouveau_load:1098 - crystal freq: 27000KHz
>[drm] nouveau 0000:04:00.0: Attempting to load BIOS image from PRAMIN
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: ... appears to be valid
>[drm] nouveau 0000:04:00.0: BIT BIOS found
>[drm] nouveau 0000:04:00.0: Bios version 62.98.77.00
>[drm] nouveau 0000:04:00.0: TMDS table version 2.0
>[drm] nouveau 0000:04:00.0: MXM: no VBIOS data, nothing to do
>[drm] nouveau 0000:04:00.0: DCB version 4.0
>[drm] nouveau 0000:04:00.0: DCB outp 00: 02000386 0f200010
>[drm] nouveau 0000:04:00.0: DCB outp 01: 02000332 00020010
>[drm] nouveau 0000:04:00.0: DCB outp 02: 040113a6 0f200010
>[drm] nouveau 0000:04:00.0: DCB outp 03: 04011342 00020010
>[drm] nouveau 0000:04:00.0: DCB conn 00: 00005046
>[drm] nouveau 0000:04:00.0: DCB conn 01: 0000a146
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table 0 at offset 0xDBFC
>[drm] nouveau 0000:04:00.0: 0xDBFC: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xDBFC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000200, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xDC05: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC05: Repeating following segment 20 times
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC07: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDC14: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xDC15: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDC15: Condition: 0x07
>[drm] nouveau 0000:04:00.0: 0xDC15: Cond: 0x07, Reg: 0x0000C040, Mask: 0x00000300
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000C040, Data: 0x2E801033
>[drm] nouveau 0000:04:00.0: 0xDC15: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDC15: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xDC17: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001540, Data: 0xF1010001
>[drm] nouveau 0000:04:00.0: 0xDC20: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDC21: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:04:00.0: 0xDC2A: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xDC2A: Executing subroutine at 0xE742
>[drm] nouveau 0000:04:00.0: 0xE742: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xE742: BaseReg: 0x001009C0, Count: 0x07
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C0, Data: 0x04040004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C4, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C8, Data: 0x04040004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009CC, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D0, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D4, Data: 0x04000004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D8, Data: 0x04000004
>[drm] nouveau 0000:04:00.0: 0xE764: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE764: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x05, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009EC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE80B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xDC2A: End of 0xE742 subroutine
>[drm] nouveau 0000:04:00.0: 0xDC2D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC2D: Reg: 0x001008C0, Mask: 0xFF000000, Data: 0x08000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x001008C0, Data: 0x8B303A98
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001008C0, Data: 0x8B000000
>[drm] nouveau 0000:04:00.0: 0xDC3A: [ (0x69) - INIT_IO ]
>[drm] nouveau 0000:04:00.0: 0xDC3A: Port: 0x03C3, Mask: 0x00, Data: 0x01
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614100, Data: 0x10000600
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614100, Data: 0x00800600
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00130000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614900, Data: 0x10000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614900, Data: 0x00800000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000200, Data: 0x80110111
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614100, Data: 0x00800018
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614900, Data: 0x00800018
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614100, Data: 0x10000018
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614900, Data: 0x10000018
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614280, Data: 0x04040484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614280, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614A80, Data: 0x04040484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614A80, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615280, Data: 0x04040484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00615280, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614300, Data: 0x00000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614300, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x03814040
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B00, Data: 0x03814040
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614380, Data: 0x00000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614380, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B80, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615380, Data: 0x00000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00615380, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00000084
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614A00, Data: 0x00000080
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614108, Data: 0x2008000F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614108, Data: 0x0008000F
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614908, Data: 0x40050012
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614908, Data: 0x00050012
>[drm] nouveau 0000:04:00.0: 0xDC3F: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x3F, Head: 0x00, Data: 0x57
>[drm] nouveau 0000:04:00.0: 0xDC42: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC42: Reg: 0x0000E104, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E104, Data: 0x27744444
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E104, Data: 0x27744444
>[drm] nouveau 0000:04:00.0: 0xDC4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC4F: Reg: 0x0000E108, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:04:00.0: 0xDC5C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC5C: Reg: 0x0000E300, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:04:00.0: 0xDC69: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020108, Data: 0x08000000
>[drm] nouveau 0000:04:00.0: 0xDC72: [ (0x8E) - INIT_GPIO ]
>[drm] nouveau 0000:04:00.0: 0xDC73: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDC73: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001084, Data: 0x00001C69
>[drm] nouveau 0000:04:00.0: 0xDC80: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E054, Data: 0x7FFF7FFF
>[drm] nouveau 0000:04:00.0: 0xDC89: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00009220, Data: 0x00000009
>[drm] nouveau 0000:04:00.0: 0xDC92: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00009200, Data: 0x00000144
>[drm] nouveau 0000:04:00.0: 0xDC9B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00009210, Data: 0x0000007D
>[drm] nouveau 0000:04:00.0: 0xDCA4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCA4: Reg: 0x00101000, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xDCB1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCB1: Reg: 0x0010100C, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0010100C, Data: 0x80013030
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010100C, Data: 0x80013030
>[drm] nouveau 0000:04:00.0: 0xDCBE: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDCBE: Condition: 0x07
>[drm] nouveau 0000:04:00.0: 0xDCBE: Cond: 0x07, Reg: 0x0000C040, Mask: 0x00000300
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000C040, Data: 0x2E801033
>[drm] nouveau 0000:04:00.0: 0xDCBE: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDCBE: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xDCC0: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCC0: SrcReg: 0x00614004, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x00610184, DstMask: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614004, Data: 0x77704557
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00610184, Data: 0x77704557
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00610184, Data: 0x77704557
>[drm] nouveau 0000:04:00.0: 0xDCD6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDCD7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00619F00, Data: 0x00000009
>[drm] nouveau 0000:04:00.0: 0xDCE0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDCE0: Condition: 0x06
>[drm] nouveau 0000:04:00.0: 0xDCE0: Cond: 0x06, Reg: 0x00021218, Mask: 0x000000FF
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00021218, Data: 0x00000021
>[drm] nouveau 0000:04:00.0: 0xDCE0: Checking if 0x00000021 equals 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDCE0: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xDCE2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCEB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCF4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCFD: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xDCFD: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xDCFE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDCFE: Reg: 0x0061A068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A068, Data: 0x44800000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A068, Data: 0x44800000
>[drm] nouveau 0000:04:00.0: 0xDD0B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD0B: Reg: 0x0061A868, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:04:00.0: 0xDD18: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD18: Reg: 0x0061B068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061B068, Data: 0x44000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061B068, Data: 0x44000000
>[drm] nouveau 0000:04:00.0: 0xDD25: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDD26: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00617348, Data: 0x80000001
>[drm] nouveau 0000:04:00.0: 0xDD2F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004700, Data: 0x80000001
>[drm] nouveau 0000:04:00.0: 0xDD38: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:04:00.0: 0xDD38: Reg: 0x00101000, Shift: 0x02, SrcMask: 0x0F, Port: 0x03D4, Index: 0x88, Mask: 0xF0
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 0xDD43: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:04:00.0: 0xDD43: Reg: 0x00101000, Shift: 0x18, SrcMask: 0x0F, Port: 0x03D4, Index: 0x8B, Mask: 0xF0
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xDD4E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD4E: Reg: 0x00001580, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001580, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001580, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDD5B: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDD5B: Condition: 0x09
>[drm] nouveau 0000:04:00.0: 0xDD5B: Cond: 0x09, Reg: 0x00000000, Mask: 0xE0000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000000, Data: 0x298D00A2
>[drm] nouveau 0000:04:00.0: 0xDD5B: Checking if 0x20000000 equals 0x20000000
>[drm] nouveau 0000:04:00.0: 0xDD5B: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xDD5D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001538, Data: 0x00011111
>[drm] nouveau 0000:04:00.0: 0xDD66: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xDD66: ------ Skipping following commands  ------
>[drm] nouveau 0000:04:00.0: 0xDD67: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD70: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDD70: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xDD71: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD71: Reg: 0x0010002C, Mask: 0xFFFFFF00, Data: 0x00000012
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0010002C, Data: 0x00000012
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010002C, Data: 0x00000012
>[drm] nouveau 0000:04:00.0: 0xDD7E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD7E: Reg: 0x00003310, Mask: 0xFFFFF8FF, Data: 0x00000500
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00003310, Data: 0x00000300
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00003310, Data: 0x00000500
>[drm] nouveau 0000:04:00.0: 0xDD8B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDD8B: Reg: 0x00001530, Mask: 0xFFFFFFF0, Data: 0x0000000A
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001530, Data: 0x800412FA
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001530, Data: 0x800412FA
>[drm] nouveau 0000:04:00.0: 0xDD98: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0002004C, Data: 0x40072A0B
>[drm] nouveau 0000:04:00.0: 0xDDA1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000204CC, Data: 0x0000005D
>[drm] nouveau 0000:04:00.0: 0xDDAA: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020060, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDDB3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088138, Data: 0x10000000
>[drm] nouveau 0000:04:00.0: 0xDDBC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDDBC: Reg: 0x0008813C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0008813C, Data: 0x33FF0000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008813C, Data: 0x33FF0000
>[drm] nouveau 0000:04:00.0: 0xDDC9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088140, Data: 0x08010000
>[drm] nouveau 0000:04:00.0: 0xDDD2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDDD2: Reg: 0x0008818C, Mask: 0x0FFFFFF8, Data: 0xD0000007
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0008818C, Data: 0xD0000007
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008818C, Data: 0xD0000007
>[drm] nouveau 0000:04:00.0: 0xDDDF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDDDF: Reg: 0x00088458, Mask: 0xFC00FFFF, Data: 0x0028001F
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00088458, Data: 0x0028001F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088458, Data: 0x0028001F
>[drm] nouveau 0000:04:00.0: 0xDDEC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDDEC: Reg: 0x00001604, Mask: 0xFFF577FF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001604, Data: 0x00202204
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001604, Data: 0x00202204
>[drm] nouveau 0000:04:00.0: 0xDDF9: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8F, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xDDFC: [ (0x76) - INIT_IO_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDDFC: IO condition: 0x04
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061948C, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8F, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xDDFC: Checking if 0x00 equals 0x01
>[drm] nouveau 0000:04:00.0: 0xDDFC: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xDDFE: [ (0x4D) - INIT_ZM_I2C_BYTE ]
>[drm] nouveau 0000:04:00.0: 0xDE04: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDE04: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xDE05: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E81C, Data: 0x00044001
>[drm] nouveau 0000:04:00.0: 0xDE0E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E824, Data: 0x00200000
>[drm] nouveau 0000:04:00.0: 0xDE17: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:04:00.0: 0xDE20: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E844, Data: 0x00022801
>[drm] nouveau 0000:04:00.0: 0xDE29: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDE29: Reg: 0x0000E84C, Mask: 0xFFF8FFFF, Data: 0x00120000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E84C, Data: 0x00120000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E84C, Data: 0x00120000
>[drm] nouveau 0000:04:00.0: 0xDE36: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E848, Data: 0x80191501
>[drm] nouveau 0000:04:00.0: 0xDE3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDE3F: Reg: 0x00004040, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004040, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004040, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 0xDE4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDE4C: Reg: 0x00004050, Mask: 0xFFEFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004050, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004050, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 0xDE59: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000C050, Data: 0x0000500E
>[drm] nouveau 0000:04:00.0: 0xDE62: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDE62: Sleeping for 0x07D0 microseconds
>[drm] nouveau 0000:04:00.0: 0xDE65: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:04:00.0: 0xDE65: Calling script 7
>[drm] nouveau 0000:04:00.0: 0xE871: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE871: Type 04 Reg 0x00004008 Freq 700000KHz
>[drm] nouveau 0000:04:00.0: Loading PLL limits for register 0x00004008
>[drm] nouveau 0000:04:00.0: pll.vco1.minfreq: 590000
>[drm] nouveau 0000:04:00.0: pll.vco1.maxfreq: 1180000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_inputfreq: 14000
>[drm] nouveau 0000:04:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_n: 14
>[drm] nouveau 0000:04:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:04:00.0: pll.vco2.minfreq: 590000
>[drm] nouveau 0000:04:00.0: pll.vco2.maxfreq: 1180000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:04:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:04:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:04:00.0: pll.log2p_bias: 1
>[drm] nouveau 0000:04:00.0: pll.refclk: 108000
>[drm] nouveau 0000:04:00.0: 0xE893: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xDE65: End of script 7
>[drm] nouveau 0000:04:00.0: 0xDE67: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:04:00.0: 0xDE67: Calling script 8
>[drm] nouveau 0000:04:00.0: 0xE894: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE894: Type 02 Reg 0x00004020 Freq 1200000KHz
>[drm] nouveau 0000:04:00.0: Loading PLL limits for register 0x00004020
>[drm] nouveau 0000:04:00.0: pll.vco1.minfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco1.maxfreq: 2000000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_inputfreq: 50000
>[drm] nouveau 0000:04:00.0: pll.vco1.max_inputfreq: 100000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_n: 10
>[drm] nouveau 0000:04:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:04:00.0: pll.vco2.minfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco2.maxfreq: 2000000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:04:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:04:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:04:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:04:00.0: pll.refclk: 100000
>[drm] nouveau 0000:04:00.0: 0xE8B6: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xDE67: End of script 8
>[drm] nouveau 0000:04:00.0: 0xDE69: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:04:00.0: 0xDE69: Calling script 6
>[drm] nouveau 0000:04:00.0: 0xE84E: [ (0x87) - INIT_RAM_RESTRICT_PLL ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE84E: Type 01 Reg 0x00004028 Freq 480000KHz
>[drm] nouveau 0000:04:00.0: Loading PLL limits for register 0x00004028
>[drm] nouveau 0000:04:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_inputfreq: 14000
>[drm] nouveau 0000:04:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_n: 14
>[drm] nouveau 0000:04:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:04:00.0: pll.vco2.minfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco2.maxfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_inputfreq: 0
>[drm] nouveau 0000:04:00.0: pll.vco2.max_inputfreq: 65535000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_n: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_m: 1
>[drm] nouveau 0000:04:00.0: pll.max_log2p: 7
>[drm] nouveau 0000:04:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:04:00.0: pll.refclk: 100000
>[drm] nouveau 0000:04:00.0: 0xE870: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xDE69: End of script 6
>[drm] nouveau 0000:04:00.0: 0xDE6B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDE6B: Reg: 0x0000E18C, Mask: 0xFFFFFFFF, Data: 0x00100000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00110000
>[drm] nouveau 0000:04:00.0: 0xDE78: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDE78: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:04:00.0: 0xDE7B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E818, Data: 0x88080000
>[drm] nouveau 0000:04:00.0: 0xDE84: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDE84: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xDE87: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E818, Data: 0x80080000
>[drm] nouveau 0000:04:00.0: 0xDE90: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xDE90: Condition: 0x10
>[drm] nouveau 0000:04:00.0: 0xDE90: Cond: 0x10, Reg: 0x00004080, Mask: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004080, Data: 0x00FF3303
>[drm] nouveau 0000:04:00.0: 0xDE90: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:04:00.0: 0xDE90: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xDE92: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xDE92: ------ Skipping following commands  ------
>[drm] nouveau 0000:04:00.0: 0xDE93: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEA0: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDEA3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEAC: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDEAF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEB8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xDEB8: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xDEB9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E824, Data: 0x00200000
>[drm] nouveau 0000:04:00.0: 0xDEC2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEC2: Reg: 0x0000E820, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E820, Data: 0x80660801
>[drm] nouveau 0000:04:00.0: 0xDECF: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDECF: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:04:00.0: 0xDED2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDED2: Reg: 0x00004020, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 0xDEDF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEDF: Reg: 0x00004028, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004028, Data: 0xA0010000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004028, Data: 0xA0010000
>[drm] nouveau 0000:04:00.0: 0xDEEC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEEC: Reg: 0x00004008, Mask: 0xFFFFFFFF, Data: 0x90001200
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004008, Data: 0x90087600
>[drm] nouveau 0000:04:00.0: 0xDEF9: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDEF9: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:04:00.0: 0xDEFC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDEFC: Reg: 0x00004028, Mask: 0xFFFFFFFF, Data: 0xA0000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004028, Data: 0xA0010000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004028, Data: 0xA0010000
>[drm] nouveau 0000:04:00.0: 0xDF09: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF09: Reg: 0x00004008, Mask: 0xFFFFEFFF, Data: 0x90004600
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004008, Data: 0x90086600
>[drm] nouveau 0000:04:00.0: 0xDF16: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xDF16: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xDF19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF19: Reg: 0x0000C040, Mask: 0x03FF3340, Data: 0x2C001033
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000C040, Data: 0x2E801033
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000C040, Data: 0x2E801033
>[drm] nouveau 0000:04:00.0: 0xDF26: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF26: Reg: 0x00004008, Mask: 0xFFFFFDFF, Data: 0x90004400
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 0xDF33: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF33: Reg: 0x00004020, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004020, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 0xDF40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF40: Reg: 0x00020018, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:04:00.0: 0xDF4D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xDF4D: Executing subroutine at 0xEC8E
>[drm] nouveau 0000:04:00.0: 0xEC8E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xDF4D: End of 0xEC8E subroutine
>[drm] nouveau 0000:04:00.0: 0xDF50: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000C044, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xDF59: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100F34, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xDF62: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:04:00.0: 0xDF6B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E610, Data: 0x0000000F
>[drm] nouveau 0000:04:00.0: 0xDF74: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E61C, Data: 0x0000000F
>[drm] nouveau 0000:04:00.0: 0xDF7D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E690, Data: 0xF4770204
>[drm] nouveau 0000:04:00.0: 0xDF86: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF86: Reg: 0x00089008, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00089008, Data: 0x03000010
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00089008, Data: 0x03000010
>[drm] nouveau 0000:04:00.0: 0xDF93: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDF93: Reg: 0x0008900C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0008900C, Data: 0x00FCACAC
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008900C, Data: 0x00FCACAC
>[drm] nouveau 0000:04:00.0: 0xDFA0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFA0: Reg: 0x0000154C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000154C, Data: 0x0000007C
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000154C, Data: 0x0000007C
>[drm] nouveau 0000:04:00.0: 0xDFAD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFAD: Reg: 0x00088460, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00088460, Data: 0xB0602220
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088460, Data: 0xB0602220
>[drm] nouveau 0000:04:00.0: 0xDFBA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFBA: Reg: 0x00089028, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00089028, Data: 0x00FAF100
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00089028, Data: 0x00FAF100
>[drm] nouveau 0000:04:00.0: 0xDFC7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFC7: Reg: 0x0008902C, Mask: 0xFF8FFF60, Data: 0x0040008E
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0008902C, Data: 0x00408E8E
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008902C, Data: 0x00408E8E
>[drm] nouveau 0000:04:00.0: 0xDFD4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008848C, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xDFDD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFDD: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:04:00.0: 0xDFEA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xDFEA: Reg: 0x00088610, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00088610, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088610, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xDFF7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020080, Data: 0x100C0736
>[drm] nouveau 0000:04:00.0: 0xE000: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table 1 at offset 0xE001
>[drm] nouveau 0000:04:00.0: 0xE001: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xE001: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE001: Reg: 0x00100718, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100718, Data: 0x00022077
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010071C, Data: 0x00044077
>[drm] nouveau 0000:04:00.0: 0xE048: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE048: Reg: 0x001008A0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001008A0, Data: 0x87703FB9
>[drm] nouveau 0000:04:00.0: 0xE06F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100920, Data: 0x0F0F0F0F
>[drm] nouveau 0000:04:00.0: 0xE078: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE078: Reg: 0x00100A20, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100A20, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE09F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE09F: Reg: 0x00100A40, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100A40, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE0C6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE0C6: Reg: 0x00100A60, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100A60, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE0ED: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE0ED: Reg: 0x00100A80, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100A80, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE114: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE114: Reg: 0x00100AA0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100AA0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE13B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE13B: Reg: 0x00100AC0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100AC0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE162: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE162: Reg: 0x001005A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001005A0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001005A4, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE1A9: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xE1A9: Executing subroutine at 0xE5AD
>[drm] nouveau 0000:04:00.0: 0xE5AD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE5AD: Reg: 0x00004008, Mask: 0xFFFF9FFF, Data: 0x00006000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 0xE5BA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE5BA: Reg: 0x00100760, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100760, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE5E1: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE5E1: Reg: 0x00100780, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100780, Data: 0xDDDDDDDD
>[drm] nouveau 0000:04:00.0: 0xE608: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE608: Reg: 0x001007A0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001007A0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE62F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE62F: Reg: 0x001007C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001007C0, Data: 0xDDDDDDDD
>[drm] nouveau 0000:04:00.0: 0xE656: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE656: Reg: 0x001007E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001007E0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE67D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE67D: Reg: 0x00100800, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100800, Data: 0xAAAAAAAA
>[drm] nouveau 0000:04:00.0: 0xE6A4: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xE1A9: End of 0xE5AD subroutine
>[drm] nouveau 0000:04:00.0: 0xE1AC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xE1AC: Executing subroutine at 0xE6A5
>[drm] nouveau 0000:04:00.0: 0xE6A5: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE6A5: Reg: 0x00100820, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100820, Data: 0x11111111
>[drm] nouveau 0000:04:00.0: 0xE6CC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE6CC: Reg: 0x00100840, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100840, Data: 0x22222222
>[drm] nouveau 0000:04:00.0: 0xE6F3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xE1AC: End of 0xE6A5 subroutine
>[drm] nouveau 0000:04:00.0: 0xE1AF: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xE1AF: Executing subroutine at 0xE6F4
>[drm] nouveau 0000:04:00.0: 0xE6F4: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE6F4: Reg: 0x00100860, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100860, Data: 0x11111111
>[drm] nouveau 0000:04:00.0: 0xE71B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE71B: Reg: 0x00100880, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100880, Data: 0x22222222
>[drm] nouveau 0000:04:00.0: 0xE742: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xE742: BaseReg: 0x001009C0, Count: 0x07
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C0, Data: 0x04040004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C4, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009C8, Data: 0x04040004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009CC, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D0, Data: 0x00000404
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D4, Data: 0x04000004
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009D8, Data: 0x04000004
>[drm] nouveau 0000:04:00.0: 0xE764: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE764: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x05, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009E8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001009EC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE80B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xE1AF: End of 0xE6F4 subroutine
>[drm] nouveau 0000:04:00.0: 0xE1B2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE1B2: Reg: 0x00100714, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100714, Data: 0x00033122
>[drm] nouveau 0000:04:00.0: 0xE1D9: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xE1D9: BaseReg: 0x00100740, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100740, Data: 0x0E000000
>[drm] nouveau 0000:04:00.0: 0xE1E3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100DA0, Data: 0x00000010
>[drm] nouveau 0000:04:00.0: 0xE1EC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100710, Data: 0x00000070
>[drm] nouveau 0000:04:00.0: 0xE1F5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010024C, Data: 0x0A010080
>[drm] nouveau 0000:04:00.0: 0xE1FE: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE1FE: Reg: 0x00100254, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100254, Data: 0x00000002
>[drm] nouveau 0000:04:00.0: 0xE225: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010053C, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xE22E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE22E: Reg: 0x00100080, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100080, Data: 0x00000020
>[drm] nouveau 0000:04:00.0: 0xE255: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE255: Reg: 0x00100220, RegIncrement: 0x04, Count: 0x0B, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100220, Data: 0x0C162A22
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100224, Data: 0x0E010A0B
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100228, Data: 0x0208070B
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010022C, Data: 0x1F160A0A
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100230, Data: 0x23000808
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100234, Data: 0x2A0B0D0C
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100238, Data: 0x00330136
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010023C, Data: 0x040A0202
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100240, Data: 0x110F0300
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100244, Data: 0x00000186
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100248, Data: 0x03EBE80F
>[drm] nouveau 0000:04:00.0: 0xE3BC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE3BC: Reg: 0x00100200, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xE3E3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE3E3: Reg: 0x00100204, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100204, Data: 0x01559000
>[drm] nouveau 0000:04:00.0: 0xE40A: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xE40A: Condition: 0x0B
>[drm] nouveau 0000:04:00.0: 0xE40A: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE40A: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:04:00.0: 0xE40A: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xE40C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE419: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xE419: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xE41A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE41A: Reg: 0x00100214, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100214, Data: 0x00000022
>[drm] nouveau 0000:04:00.0: 0xE441: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE441: Reg: 0x00100250, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100250, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE468: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE468: Reg: 0x0000122C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000122C, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000122C, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE475: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE475: Sleeping for 0x0FA0 microseconds
>[drm] nouveau 0000:04:00.0: 0xE478: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE478: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE47A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE47A: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:04:00.0: 0xE47D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100218, Data: 0x01000000
>[drm] nouveau 0000:04:00.0: 0xE486: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0010021C, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE48F: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE48F: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:04:00.0: 0xE492: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xE492: Condition: 0x0B
>[drm] nouveau 0000:04:00.0: 0xE492: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE492: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:04:00.0: 0xE492: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xE494: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xE49D: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xE49D: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xE49E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100218, Data: 0x01000100
>[drm] nouveau 0000:04:00.0: 0xE4A7: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xE4A8: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE4A8: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:04:00.0: 0xE4AB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100218, Data: 0x01000101
>[drm] nouveau 0000:04:00.0: 0xE4B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE4B4: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:04:00.0: 0xE4B7: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE4B7: Macro: 0x02, MacroTableIndex: 0x02, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE4B9: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE4B9: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE4BB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE4BB: Reg: 0x001002E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002E0, Data: 0x00600000
>[drm] nouveau 0000:04:00.0: 0xE4E2: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xE4E2: Condition: 0x0B
>[drm] nouveau 0000:04:00.0: 0xE4E2: Cond: 0x0B, Reg: 0x00101000, Mask: 0x00000020
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE4E2: Checking if 0x00000000 equals 0x00000020
>[drm] nouveau 0000:04:00.0: 0xE4E2: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xE4E4: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 0xE50B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xE50B: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xE50C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE50C: Reg: 0x001002C4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002C4, Data: 0x001002B8
>[drm] nouveau 0000:04:00.0: 0xE533: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xE534: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00101000, Data: 0x90402812
>[drm] nouveau 0000:04:00.0: 0xE534: Reg: 0x001002C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x04, Index: 0x04
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:04:00.0: 0xE55B: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xE55B: Condition: 0x0C
>[drm] nouveau 0000:04:00.0: 0xE55B: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xE55B: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:04:00.0: 0xE55B: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xE55D: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xE566: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xE56F: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xE578: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xE578: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xE579: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE579: Reg: 0x0000E108, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:04:00.0: 0xE586: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE586: Macro: 0x02, MacroTableIndex: 0x02, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE588: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE588: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE58A: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE58A: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE58C: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE58C: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE58E: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE58E: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE590: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE590: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:04:00.0: 0xE593: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100210, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE59C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE59C: Reg: 0x00004008, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00004008, Data: 0x90086400
>[drm] nouveau 0000:04:00.0: 0xE5A9: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE5A9: Sleeping for 0x03E8 microseconds
>Switching to clocksource tsc
>[drm] nouveau 0000:04:00.0: 0xE5AC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table 2 at offset 0xE80C
>[drm] nouveau 0000:04:00.0: 0xE80C: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xE80C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE80C: Reg: 0x001008C0, Mask: 0x00000000, Data: 0x8B303A98
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x001008C0, Data: 0x8B303A98
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001008C0, Data: 0x8B303A98
>[drm] nouveau 0000:04:00.0: 0xE819: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000108C, Data: 0x000000D1
>[drm] nouveau 0000:04:00.0: 0xE822: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xF0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xE825: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:04:00.0: 0xE825: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x08, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x08
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x09
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:04:00.0: 0xE82C: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:04:00.0: 0xE82C: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x18, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x18
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:04:00.0: 0xE833: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:04:00.0: 0xE833: Index: 0x88, Mask: 0xBF, Data: 0x40
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 0xE837: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:04:00.0: 0xE837: Index: 0x8A, Mask: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xE83B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E200, Data: 0x0003103C
>[drm] nouveau 0000:04:00.0: 0xE844: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x30, Head: 0x00, Data: 0x10
>[drm] nouveau 0000:04:00.0: 0xE847: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x31, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xE84A: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xAA, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:04:00.0: 0xE84D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table 3 at offset 0xE8DA
>[drm] nouveau 0000:04:00.0: 0xE8DA: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xE8DA: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xE8DA: Executing subroutine at 0xCDD0
>[drm] nouveau 0000:04:00.0: 0xCDD0: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xE8DA: End of 0xCDD0 subroutine
>[drm] nouveau 0000:04:00.0: 0xE8DD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE8DD: Reg: 0x00100E04, Mask: 0xFFE0007F, Data: 0x00048900
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100E04, Data: 0x80048901
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100E04, Data: 0x80048901
>[drm] nouveau 0000:04:00.0: 0xE8EA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE8EA: Reg: 0x00100E08, Mask: 0xF01FFFFF, Data: 0x05E00000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100E08, Data: 0x05E10808
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100E08, Data: 0x05E10808
>[drm] nouveau 0000:04:00.0: 0xE8F7: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xE8F7: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: 0xE8FA: [ (0x6B) - INIT_SUB ]
>[drm] nouveau 0000:04:00.0: 0xE8FA: Calling script 10
>[drm] nouveau 0000:04:00.0: 0xBD68: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBD68: Condition: 0x0C
>[drm] nouveau 0000:04:00.0: 0xBD68: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xBD68: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:04:00.0: 0xBD68: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBD6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBD77: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xBD77: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xBD78: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBD78: Reg: 0x001002C0, Mask: 0xFFFFFEFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:04:00.0: 0xBD85: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBD85: Condition: 0x0C
>[drm] nouveau 0000:04:00.0: 0xBD85: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xBD85: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:04:00.0: 0xBD85: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBD87: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBD94: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xBD94: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xBD95: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBD95: Reg: 0x001002C0, Mask: 0xFFFFFFFF, Data: 0x00000100
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000732
>[drm] nouveau 0000:04:00.0: 0xBDA2: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xBDA2: Sleeping for 0x0028 microseconds
>[drm] nouveau 0000:04:00.0: 0xBDA5: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBDA5: Condition: 0x0C
>[drm] nouveau 0000:04:00.0: 0xBDA5: Cond: 0x0C, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xBDA5: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:04:00.0: 0xBDA5: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBDA7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDB4: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xBDB4: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xBDB5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDB5: Reg: 0x001002C0, Mask: 0xFFFFFEFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002C0, Data: 0x00000632
>[drm] nouveau 0000:04:00.0: 0xBDC2: [ (0x39) - INIT_IO_FLAG_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBDC2: Port: 0x03D4, Index: 0x88, Mask: 0x07, Shift: 0x00, FlagArray: 0xBD5F, FAMask: 0x80, Cmpval: 0x80
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 0xBDC2: Checking if 0x00 equals 0x80
>[drm] nouveau 0000:04:00.0: 0xBDC2: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBDC4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDCD: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDD6: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDDF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDE8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDF1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 0xBDFA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xBDFA: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xBDFB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xE8FA: End of script 10
>[drm] nouveau 0000:04:00.0: 0xE8FC: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE8FC: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE8FE: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE8FE: Repeating following segment 10 times
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE900: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE900: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE902: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:04:00.0: 0xE903: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE903: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE905: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE905: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE907: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:04:00.0: 0xE907: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:04:00.0: 0xE909: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100210, Data: 0x80000001
>[drm] nouveau 0000:04:00.0: 0xE912: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE912: Reg: 0x00100200, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100200, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 0xE91F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100678, Data: 0x58805880
>[drm] nouveau 0000:04:00.0: 0xE928: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100B08, Data: 0x000003FF
>[drm] nouveau 0000:04:00.0: 0xE931: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE931: Reg: 0x00100600, Mask: 0xFFFFFFFF, Data: 0x00004000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:04:00.0: 0xE93E: [ (0x63) - INIT_COMPUTE_MEM ]
>[drm] nouveau 0000:04:00.0: 0xE93F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00612000, Data: 0x00000210
>[drm] nouveau 0000:04:00.0: 0xE948: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614000, Data: 0x00000210
>[drm] nouveau 0000:04:00.0: 0xE951: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614100, Data: 0x10000000
>[drm] nouveau 0000:04:00.0: 0xE95A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614900, Data: 0x10000000
>[drm] nouveau 0000:04:00.0: 0xE963: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614110, Data: 0x0005003A
>[drm] nouveau 0000:04:00.0: 0xE96C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614114, Data: 0x50070012
>[drm] nouveau 0000:04:00.0: 0xE975: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614120, Data: 0x00450800
>[drm] nouveau 0000:04:00.0: 0xE97E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614920, Data: 0x00450800
>[drm] nouveau 0000:04:00.0: 0xE987: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614124, Data: 0x00040000
>[drm] nouveau 0000:04:00.0: 0xE990: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614924, Data: 0x00040000
>[drm] nouveau 0000:04:00.0: 0xE999: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A008, Data: 0x03A502D1
>[drm] nouveau 0000:04:00.0: 0xE9A2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A178, Data: 0x0E08C28C
>[drm] nouveau 0000:04:00.0: 0xE9AB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A1B8, Data: 0x0E08C28C
>[drm] nouveau 0000:04:00.0: 0xE9B4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A1F8, Data: 0x8BC8927C
>[drm] nouveau 0000:04:00.0: 0xE9BD: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A238, Data: 0x0E08C28C
>[drm] nouveau 0000:04:00.0: 0xE9C6: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A2B8, Data: 0x8BC8927C
>[drm] nouveau 0000:04:00.0: 0xE9CF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A338, Data: 0x000BD234
>[drm] nouveau 0000:04:00.0: 0xE9D8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE9D8: Reg: 0x0061A148, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A148, Data: 0x4015020D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A148, Data: 0x4015020D
>[drm] nouveau 0000:04:00.0: 0xE9E5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE9E5: Reg: 0x0061A188, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A188, Data: 0x4015020D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A188, Data: 0x4015020D
>[drm] nouveau 0000:04:00.0: 0xE9F2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE9F2: Reg: 0x0061A1C8, Mask: 0xFF00FFFF, Data: 0x00170000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A1C8, Data: 0x0C170271
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A1C8, Data: 0x0C170271
>[drm] nouveau 0000:04:00.0: 0xE9FF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xE9FF: Reg: 0x0061A208, Mask: 0xFF00FFFF, Data: 0x00150000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A208, Data: 0x4415020D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A208, Data: 0x4415020D
>[drm] nouveau 0000:04:00.0: 0xEA0C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA0C: Reg: 0x0061A288, Mask: 0xFF00FFFF, Data: 0x00170000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061A288, Data: 0x0C170271
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061A288, Data: 0x0C170271
>[drm] nouveau 0000:04:00.0: 0xEA19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA19: Reg: 0x006165A4, Mask: 0xFFFFFF80, Data: 0x00000038
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006165A4, Data: 0x00020038
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x006165A4, Data: 0x00020038
>[drm] nouveau 0000:04:00.0: 0xEA26: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA26: Reg: 0x00616DA4, Mask: 0xFFFFFF80, Data: 0x00000038
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00616DA4, Data: 0x00020038
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00616DA4, Data: 0x00020038
>[drm] nouveau 0000:04:00.0: 0xEA33: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA33: Reg: 0x0061E818, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:04:00.0: 0xEA40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA40: Reg: 0x0061F018, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:04:00.0: 0xEA4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA4D: Reg: 0x00003310, Mask: 0xFFFFF8FF, Data: 0x00000300
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00003310, Data: 0x00000300
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00003310, Data: 0x00000300
>[drm] nouveau 0000:04:00.0: 0xEA5A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00617338, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 0xEA63: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C080, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEA6C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C084, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEA75: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x85, Head: 0x00, Data: 0xFF
>[drm] nouveau 0000:04:00.0: 0xEA78: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA78: Reg: 0x006105D4, Mask: 0xFFFFFFE0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006105D4, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x006105D4, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEA85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA85: Reg: 0x006105D8, Mask: 0xFFFFFFE0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006105D8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x006105D8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEA92: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA92: Reg: 0x006105DC, Mask: 0xF8000000, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x006105DC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x006105DC, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEA9F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEA9F: Reg: 0x0008814C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:04:00.0: 0xEAAC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00100DC0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEAB5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000010A0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEABE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEABE: Reg: 0x00001090, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEACB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEACB: Reg: 0x00001090, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00001090, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEAD8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000010A0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEAE1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEAE1: Reg: 0x00088150, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00088150, Data: 0x6000FE15
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00088150, Data: 0x6000FE15
>[drm] nouveau 0000:04:00.0: 0xEAEE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEAEE: Reg: 0x0000E120, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEAFB: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xEAFB: BaseReg: 0x00020480, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020480, Data: 0x0000007D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020484, Data: 0x0000000A
>[drm] nouveau 0000:04:00.0: 0xEB09: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000204C0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000204D8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000204E0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x000204E8, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB2D: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xEB2D: BaseReg: 0x0002010C, Count: 0x06
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0002010C, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020110, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020114, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020118, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0002011C, Data: 0x00876530
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020120, Data: 0x00000241
>[drm] nouveau 0000:04:00.0: 0xEB4B: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xEB4B: BaseReg: 0x00020074, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020074, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020078, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB59: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xEB59: BaseReg: 0x00020094, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020094, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020098, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB67: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEB67: Reg: 0x0000E1F4, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:04:00.0: 0xEB74: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xEB74: BaseReg: 0x00020000, Count: 0x02
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020000, Data: 0xC0000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020004, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEB82: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00020108, Data: 0x08000000
>[drm] nouveau 0000:04:00.0: 0xEB8B: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:04:00.0: 0xEB8B: Index: 0x88, Mask: 0x7F, Data: 0x80
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00619488, Data: 0x000000C4
>[drm] nouveau 0000:04:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0xC4
>[drm] nouveau 0000:04:00.0: 0xEB8F: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table 4 at offset 0xEB90
>[drm] nouveau 0000:04:00.0: 0xEB90: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xEB90: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Parsing VBIOS init table at offset 0xEBF5
>[drm] nouveau 0000:04:00.0: 0xEBF5: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:04:00.0: 0xEBF5: Condition: 0x01, Retries: 0x64
>[drm] nouveau 0000:04:00.0: 0xEBF5: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 0xEBF5: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:04:00.0: 0xEBF5: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEBF5: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 0xEBF5: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:04:00.0: 0xEBF5: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:04:00.0: 0xEBF8: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xEBF8: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xEBF9: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEBF9: SrcReg: 0x00610000, Shift: 0x00, SrcMask: 0x0000FFFF, Xor: 0x00000000, DstReg: 0x0061000C, DstMask: 0xFFFF0000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00610000, Data: 0x887D0140
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 0xEC0F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xEC0F: Reg: 0x0061000C, Mask: 0xBFFFFFFF, Data: 0x40000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061000C, Data: 0x40000140
>[drm] nouveau 0000:04:00.0: 0xEC1C: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:04:00.0: 0xEC1C: Condition: 0x02, Retries: 0x64
>[drm] nouveau 0000:04:00.0: 0xEC1C: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 0xEC1C: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEC1C: Condition met, continuing
>[drm] nouveau 0000:04:00.0: 0xEC1C: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000140
>[drm] nouveau 0000:04:00.0: 0xEC1C: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:04:00.0: 0xEC1F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xEC20: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:04:00.0: 0xCD08: parsing output script 0
>[drm] nouveau 0000:04:00.0: 0xCD08: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:04:00.0: 0xCA3C: parsing output script 0
>[drm] nouveau 0000:04:00.0: 0xCA3C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCA3C: Executing subroutine at 0xCA84
>[drm] nouveau 0000:04:00.0: 0xCA84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xCA84: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C84C, Data: 0x0000A000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C864, Data: 0x1E002000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 0xCACA: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCA3C: End of 0xCA84 subroutine
>[drm] nouveau 0000:04:00.0: 0xCA3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCA3F: Reg: 0x4061C014, Mask: 0xFFFEFFFF, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C814, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 0xCA4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCA4C: Reg: 0x4061C00C, Mask: 0xFFFFFFDF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x010003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C80C, Data: 0x010003D0
>[drm] nouveau 0000:04:00.0: 0xCA59: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:04:00.0: 0xCD08: parsing output script 0
>[drm] nouveau 0000:04:00.0: 0xCD08: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Searching for output entry for 2 0 4
>[drm] nouveau 0000:04:00.0: 0xCA3C: parsing output script 0
>[drm] nouveau 0000:04:00.0: 0xCA3C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCA3C: Executing subroutine at 0xCA84
>[drm] nouveau 0000:04:00.0: 0xCA84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:04:00.0: 0xCA84: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D040, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D044, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D048, Data: 0x1E000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D04C, Data: 0x0000A000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D050, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D054, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D058, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D05C, Data: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D060, Data: 0x00002000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D064, Data: 0x1E002000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D068, Data: 0x1F000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D06C, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D070, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D074, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D078, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D07C, Data: 0x1F008000
>[drm] nouveau 0000:04:00.0: 0xCACA: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCA3C: End of 0xCA84 subroutine
>[drm] nouveau 0000:04:00.0: 0xCA3F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCA3F: Reg: 0x4061C014, Mask: 0xFFFEFFFF, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D014, Data: 0x00850000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D014, Data: 0x00850000
>[drm] nouveau 0000:04:00.0: 0xCA4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCA4C: Reg: 0x4061C00C, Mask: 0xFFFFFFDF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D00C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D00C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 0xCA59: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:602 - Entry 0: 220: 02040605 08010805 02020102 19160404
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 06020702 00000000 04040202
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:602 - Entry 1: 220: 02040605 08010807 02020102 1b160606
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 06020902 00000000 04060202
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:602 - Entry 2: 220: 0c162a22 0d01090b 0208070b 1f160a0a
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 2a0b0d0c 00000000 040a0202
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:602 - Entry 3: 220: 0916271f 0d01080a 0208060a 1e160909
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:605 -          230: 1f160808 270a0c09 00000000 04090202
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:602 - Entry 4: 220: 02050807 08010607 02020202 1b160606
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:605 -          230: 1f160707 08020902 00000000 04060202
>[drm] nouveau 0000:04:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:04:00.0: nouveau_i2c_identify:540 - Probing monitoring devices on I2C bus: 2
>[drm] nouveau 0000:04:00.0: nouveau_i2c_identify:549 - No devices found.
>[drm] nouveau 0000:04:00.0: 2 available performance level(s)
>[drm] nouveau 0000:04:00.0: 0: core 169MHz shader 338MHz memory 100MHz timing 0 voltage 900mV fanspeed 100%
>[drm] nouveau 0000:04:00.0: 3: core 480MHz shader 1200MHz memory 700MHz timing 3 voltage 1000mV fanspeed 100%
>[drm] nouveau 0000:04:00.0: c: core 480MHz shader 1200MHz memory 702MHz voltage 1000mV
>[drm] nouveau 0000:04:00.0: nv50_vram_rblock:153 - memcfg 0x00001000 0x01559000 0x00000001 0xf1010001
>[drm] nouveau 0000:04:00.0: nv50_vram_rblock:181 - rblock 98304 bytes
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_init:242 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000003
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9e40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=131072 align=4096 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9d40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00010200 vinst=0x0000058200 size=0x00004000 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d2d9c40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00014200 vinst=0x000005c200 size=0x00000100 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d2d9bc0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9b40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9ac0
>[drm] nouveau 0000:04:00.0: Detected 256MiB VRAM
>mtrr: type mismatch for ec000000,4000000 old: write-back new: write-combining
>[drm] nouveau 0000:04:00.0: 512 MiB GART (aperture)
>[drm] nouveau 0000:04:00.0: nv50_fb_create:59 - 959 tags available
>[drm] nouveau 0000:04:00.0: nv50_graph_init:131 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_init:166 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9a40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9940
>[drm] nouveau 0000:04:00.0: nv50_fifo_init_reset:99 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_init_intr:108 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_init_context_table:121 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch1
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch2
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch3
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch4
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch5
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch6
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch7
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch8
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch9
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch10
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch11
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch12
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch13
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch14
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch15
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch16
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch17
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch18
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch19
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch20
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch21
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch22
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch23
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch24
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch25
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch26
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch27
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch28
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch29
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch30
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch31
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch32
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch33
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch34
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch35
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch36
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch37
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch38
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch39
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch40
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch41
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch42
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch43
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch44
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch45
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch46
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch47
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch48
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch49
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch50
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch51
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch52
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch53
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch54
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch55
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch56
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch57
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch58
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch59
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch60
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch61
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch62
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch63
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch64
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch65
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch66
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch67
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch68
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch69
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch70
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch71
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch72
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch73
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch74
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch75
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch76
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch77
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch78
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch79
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch80
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch81
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch82
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch83
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch84
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch85
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch86
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch87
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch88
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch89
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch90
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch91
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch92
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch93
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch94
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch95
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch96
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch97
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch98
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch99
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch100
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch101
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch102
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch103
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch104
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch105
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch106
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch107
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch108
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch109
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch110
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch111
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch112
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch113
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch114
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch115
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch116
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch117
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch118
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch119
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch120
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch121
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch122
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch123
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch124
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch125
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_disable:85 - ch126
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:04:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_init_regs__nv:136 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_init_regs:144 - 
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:04:00.0: nv50_display_create:330 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d2d9240
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:04:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:04:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:04:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:04:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:04:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:04:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:04:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:04:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=32768 align=65536 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4c40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=16 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4b40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=0 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4ac0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4a40
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000d30: h=0xcafe0000, c=0x00800000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c49c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000200
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000200: h=0x01000000, c=0x00808000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4940
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000218: h=0x01000003, c=0x00810000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c48c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000210: h=0x01000002, c=0x00818000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4840
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000208: h=0x01000001, c=0x00820000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4640
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000d38: h=0xcafe0000, c=0x10828001
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c45c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000220: h=0x01000003, c=0x10830001
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4540
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000228: h=0x01000002, c=0x10838001
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c44c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000208: h=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000228: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000230: h=0x01000001, c=0x10840001
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c42c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d38: h=0xcafe0000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000d40: h=0xcafe0000, c=0x20848002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4240
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000238: h=0x01000003, c=0x20850002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c41c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000240: h=0x01000002, c=0x20858002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1c4140
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000208: h=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000240: h=0x01000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000248: h=0x01000001, c=0x20860002
>[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[drm] No driver support for vblank timestamp query.
>[drm] nouveau 0000:04:00.0: nouveau_channel_alloc:157 - initialising channel 1
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_channel_init:752 - ch1 vram=0x80000002 tt=0x80000003
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_channel_init_pramin:660 - ch1
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=66560 align=4096 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cff40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x0013a200 vinst=0x0000198200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010d1cfe40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfdc0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfd40
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000010
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfcc0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000011
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfc40
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000410
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000410: h=0x80000002, c=0x00000e04
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfbc0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000418
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000418: h=0x80000003, c=0x00000e06
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cfac0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf7c0
>[drm] nouveau 0000:04:00.0: nv50_fifo_create_context:237 - ch1
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf740
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf6c0
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch1
>[drm] nouveau 0000:04:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x5039
>[drm] nouveau 0000:04:00.0: nv50_graph_context_new:235 - ch1
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=376832 align=0 flags=0x00000006
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf5c0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf4c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000408: h=0x80000001, c=0x00100f40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf440
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000006
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000430: h=0x80000006, c=0x00000f41
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x506e
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x8000000e
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_channel_alloc:215 - channel 1 initialised
>[drm] nouveau 0000:04:00.0: nv50_display_init:147 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x00000080: 0x00080084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000084: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000088: 0xcafe0000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000008c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000090: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000094: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x00000098: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000009c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000000a0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000a4: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000002a0
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00053801
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:04:00.0: 0xCD09: parsing output script 1
>[drm] nouveau 0000:04:00.0: 0xCD09: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000002b0
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:04:00.0: 0xCD0A: parsing output script 2
>[drm] nouveau 0000:04:00.0: 0xCD0A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD0A: Reg: 0x40614300, Mask: 0xFCF0FFFF, Data: 0x00040000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x03014080
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B00, Data: 0x00044080
>[drm] nouveau 0000:04:00.0: 0xCD17: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD17: Reg: 0x6061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x004F5089
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C90C, Data: 0x004F5088
>[drm] nouveau 0000:04:00.0: 0xCD24: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD24: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C00000
>[drm] nouveau 0000:04:00.0: 0xCD31: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD31: Reg: 0x6061C130, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C930, Data: 0x0040020F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400200
>[drm] nouveau 0000:04:00.0: 0xCD3E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:04:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000002b0
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00007700
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000080
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00007700
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000080
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000080
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000080
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): 00 0x01109007 0x10000100
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 13 enabled? yes
>[drm:drm_enable_connectors], connector 16 enabled? yes
>[drm:drm_target_preferred], looking for cmdline mode on connector 13
>[drm:drm_target_preferred], looking for preferred mode on connector 13
>[drm:drm_target_preferred], found mode 1680x1050
>[drm:drm_target_preferred], looking for cmdline mode on connector 16
>[drm:drm_target_preferred], looking for preferred mode on connector 16
>[drm:drm_target_preferred], found mode 1680x1050
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1680x1050 set on crtc 11
>[drm:drm_setup_crtcs], desired mode 1680x1050 set on crtc 12
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010d1cf1c0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x502d
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010c830f40
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000007
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000438
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000438: h=0x80000007, c=0x00100f43
>[drm] nouveau 0000:04:00.0: allocated 1680x1050 fb: 0x310000, bo ffff88010c829c00
>fbcon: nouveaufb (fb1) is primary device
>fbcon: Remapping primary device, fb1, to tty 1-63
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm] nouveau 0000:04:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:04:00.0: Ch0/0x000000a4: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000000a8: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000ac: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000000b0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000b4: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000000b8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000bc: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:04:00.0: Ch1/0x00000080: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch1/0x00000084: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000088: 0x00040094
>[drm] nouveau 0000:04:00.0: Ch1/0x0000008c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000090: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch1/0x00000094: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000098: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch1/0x0000009c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000a0: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:04:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x000000bc: 0x00080880
>[drm] nouveau 0000:04:00.0: Ch0/0x000000c0: 0x05000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000c4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000c8: 0x0004089c
>[drm] nouveau 0000:04:00.0: Ch0/0x000000cc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000d0: 0x00080840
>[drm] nouveau 0000:04:00.0: Ch0/0x000000d4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000d8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000dc: 0x0004085c
>[drm] nouveau 0000:04:00.0: Ch0/0x000000e0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000e4: 0x00040874
>[drm] nouveau 0000:04:00.0: Ch0/0x000000e8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000ec: 0x00080804
>[drm] nouveau 0000:04:00.0: Ch0/0x000000f0: 0x00823b4a
>[drm] nouveau 0000:04:00.0: Ch0/0x000000f4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000000f8: 0x00180810
>[drm] nouveau 0000:04:00.0: Ch0/0x000000fc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000100: 0x044108c0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000104: 0x000500af
>[drm] nouveau 0000:04:00.0: Ch0/0x00000108: 0x002301c7
>[drm] nouveau 0000:04:00.0: Ch0/0x0000010c: 0x043d0857
>[drm] nouveau 0000:04:00.0: Ch0/0x00000110: 0x00000001
>[drm] nouveau 0000:04:00.0: Ch0/0x00000114: 0x0004082c
>[drm] nouveau 0000:04:00.0: Ch0/0x00000118: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000011c: 0x00040900
>[drm] nouveau 0000:04:00.0: Ch0/0x00000120: 0x00000311
>[drm] nouveau 0000:04:00.0: Ch0/0x00000124: 0x000408c8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000128: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x0000012c: 0x000408d4
>[drm] nouveau 0000:04:00.0: Ch0/0x00000130: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000134: 0x000408a0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000138: 0x00000002
>[drm] nouveau 0000:04:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x0000013c: 0x000408a4
>[drm] nouveau 0000:04:00.0: Ch0/0x00000140: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000144: 0x000808d8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000148: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x0000014c: 0x041a0690
>[drm] nouveau 0000:04:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000150: 0x00140860
>[drm] nouveau 0000:04:00.0: Ch0/0x00000154: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch0/0x00000158: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000015c: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x00000160: 0x00101b00
>[drm] nouveau 0000:04:00.0: Ch0/0x00000164: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch0/0x00000168: 0x00040840
>[drm] nouveau 0000:04:00.0: Ch0/0x0000016c: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000170: 0x000408a8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000174: 0x00040000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000178: 0x000408c0
>[drm] nouveau 0000:04:00.0: Ch0/0x0000017c: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:42:1680x1050]
>[drm] nouveau 0000:04:00.0: nv50_sor_mode_set:203 - or 1 type 6 -> crtc 0
>[drm] nouveau 0000:04:00.0: nv50_sor_dpms:78 - or 1 type 6 mode 0
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000001
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCAD4: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCAD4: Executing subroutine at 0xCD40
>[drm] nouveau 0000:04:00.0: 0xCD40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD40: Reg: 0x0000E848, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E848, Data: 0x00191501
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E848, Data: 0x80191501
>[drm] nouveau 0000:04:00.0: 0xCD4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD4D: Reg: 0x0000E840, Mask: 0x77FFFFFF, Data: 0x88000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E840, Data: 0x80080000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E840, Data: 0x88080000
>[drm] nouveau 0000:04:00.0: 0xCD5A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xCD5A: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xCD5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD5D: Reg: 0x0000E840, Mask: 0xF7FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E840, Data: 0x88080000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E840, Data: 0x80080000
>[drm] nouveau 0000:04:00.0: 0xCD6A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCAD4: End of 0xCD40 subroutine
>[drm] nouveau 0000:04:00.0: 0xCAD7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAD7: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x004F5088
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C90C, Data: 0x004F5089
>[drm] nouveau 0000:04:00.0: 0xCAE4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAE4: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C928, Data: 0x950B160D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C928, Data: 0x950B160D
>[drm] nouveau 0000:04:00.0: 0xCAF1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAF1: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00044080
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B00, Data: 0x03044080
>[drm] nouveau 0000:04:00.0: 0xCAFE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C80C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 0xCB07: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060152F
>[drm] nouveau 0000:04:00.0: 0xCB10: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C814, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB19: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xCB19: Condition: 0x0D
>[drm] nouveau 0000:04:00.0: 0xCB19: Cond: 0x0D, Reg: 0x00000008, Mask: 0x000000F0
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000008, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB19: Checking if 0x00000000 equals 0x00000010
>[drm] nouveau 0000:04:00.0: 0xCB19: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xCB1B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xCB1B: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xCB1C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCB1C: Executing subroutine at 0xBFCA
>[drm] nouveau 0000:04:00.0: 0xBFCA: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBFCA: Condition: 0x0E
>[drm] nouveau 0000:04:00.0: 0xBFCA: Cond: 0x0E, Reg: 0x40614300, Mask: 0x00030000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x03044080
>[drm] nouveau 0000:04:00.0: 0xBFCA: Checking if 0x00000000 equals 0x00010000
>[drm] nouveau 0000:04:00.0: 0xBFCA: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBFCC: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xBFCC: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xBFCD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFCD: Reg: 0x4061C00C, Mask: 0xF0FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C80C, Data: 0x000003D0
>[drm] nouveau 0000:04:00.0: 0xBFDA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFDA: Reg: 0x4061C008, Mask: 0x00FFFFFF, Data: 0x14000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C808, Data: 0x00800000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C808, Data: 0x14800000
>[drm] nouveau 0000:04:00.0: 0xBFE7: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xBFE7: Sleeping for 0x0190 microseconds
>[drm] nouveau 0000:04:00.0: 0xBFEA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFEA: Reg: 0x4061C008, Mask: 0x00FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C808, Data: 0x14800000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C808, Data: 0x00800000
>[drm] nouveau 0000:04:00.0: 0xBFF7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFF7: Reg: 0x4061C00C, Mask: 0xF0FFFFFF, Data: 0x01000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x000003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C80C, Data: 0x010003D0
>[drm] nouveau 0000:04:00.0: 0xC004: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xC004: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xC007: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xC008: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCB1C: End of 0xBFCA subroutine
>[drm] nouveau 0000:04:00.0: 0xCB1F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xCB20: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB20: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x03044080
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B00, Data: 0x03054080
>[drm] nouveau 0000:04:00.0: 0xCB2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCB2D: Executing subroutine at 0xABD0
>[drm] nouveau 0000:04:00.0: 0xABD0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABD0: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060952F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 0xABDD: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xABDD: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xABE0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xABE0: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xABE0: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 0xABE0: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xABE0: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xABE2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABE2: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060812F
>[drm] nouveau 0000:04:00.0: 0xABEF: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xABF0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABF0: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060012F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060092F
>[drm] nouveau 0000:04:00.0: 0xABFD: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xABFD: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC00: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC00: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC00: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060892F
>[drm] nouveau 0000:04:00.0: 0xAC00: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC00: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xAC02: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC02: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060892F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060812F
>[drm] nouveau 0000:04:00.0: 0xAC0F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC10: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC10: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060012F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 0xAC1D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xAC1D: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC20: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC20: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC20: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 0xAC20: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC20: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xAC22: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC2F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC2F: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xAC30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC30: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060072F
>[drm] nouveau 0000:04:00.0: 0xAC3D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xAC3D: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC40: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC40: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC40: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060872F
>[drm] nouveau 0000:04:00.0: 0xAC40: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC40: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xAC42: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC42: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C810, Data: 0x0060872F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C810, Data: 0x0060852F
>[drm] nouveau 0000:04:00.0: 0xAC4F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC50: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCB2D: End of 0xABD0 subroutine
>[drm] nouveau 0000:04:00.0: 0xCB30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB30: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400200
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C930, Data: 0x004002FF
>[drm] nouveau 0000:04:00.0: 0xCB3D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xCB3D: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:04:00.0: 0xCB40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB40: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C930, Data: 0x004002FF
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C930, Data: 0x0040020F
>[drm] nouveau 0000:04:00.0: 0xCB4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB4D: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x004F5089
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C90C, Data: 0x004F4089
>[drm] nouveau 0000:04:00.0: 0xCB5A: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840601
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000001
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB62: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000020
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB6A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: dp_set_link_config:343 - 4 lanes at 162000 KB/s
>[drm] nouveau 0000:04:00.0: 0xCB9E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000100 2
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00008406
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840620
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000021
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 0 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 1 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 2 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 3 00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000103 4
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000202 6
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00801111
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: dp_link_train_update:490 - status 11 11 80 00 00 00
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 2
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00801121
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000022
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000202 6
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01817777
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: dp_link_train_update:490 - status 77 77 81 01 00 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 0 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 1 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 2 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 3 00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000103 4
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 0
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000102 1
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01817722
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000020
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB6B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB6B: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x004F4089
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C90C, Data: 0x004F5089
>[drm] nouveau 0000:04:00.0: 0xCB78: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01817720
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB80: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Ch0/0x00000180: 0x00040640
>[drm] nouveau 0000:04:00.0: Ch0/0x00000184: 0x00053801
>[drm] nouveau 0000:04:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:04:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x00000188: 0x00080880
>[drm] nouveau 0000:04:00.0: Ch0/0x0000018c: 0x05000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000190: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000194: 0x0004089c
>[drm] nouveau 0000:04:00.0: Ch0/0x00000198: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000019c: 0x00080840
>[drm] nouveau 0000:04:00.0: Ch0/0x000001a0: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001a4: 0x000007a0
>[drm] nouveau 0000:04:00.0: Ch0/0x000001a8: 0x0004085c
>[drm] nouveau 0000:04:00.0: Ch0/0x000001ac: 0x01000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001b0: 0x00080860
>[drm] nouveau 0000:04:00.0: Ch0/0x000001b4: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch0/0x000001b8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001bc: 0x00040874
>[drm] nouveau 0000:04:00.0: Ch0/0x000001c0: 0x01000003
>[drm] nouveau 0000:04:00.0: Ch0/0x000001c4: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000001c8: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001cc: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000001d0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001d4: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000001d8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001dc: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000002a0
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000002b0
>[drm] nouveau 0000:04:00.0: Loading PLL limits for register 0x00614100
>[drm] nouveau 0000:04:00.0: pll.vco1.minfreq: 250000
>[drm] nouveau 0000:04:00.0: pll.vco1.maxfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_inputfreq: 4000
>[drm] nouveau 0000:04:00.0: pll.vco1.max_inputfreq: 27000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_n: 20
>[drm] nouveau 0000:04:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco1.max_m: 2
>[drm] nouveau 0000:04:00.0: pll.vco2.minfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco2.maxfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_inputfreq: 14000
>[drm] nouveau 0000:04:00.0: pll.vco2.max_inputfreq: 75000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_n: 14
>[drm] nouveau 0000:04:00.0: pll.vco2.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_m: 255
>[drm] nouveau 0000:04:00.0: pll.max_log2p: 6
>[drm] nouveau 0000:04:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:04:00.0: pll.refclk: 27000
>[drm] nouveau 0000:04:00.0: nv50_crtc_set_clock:312 - pclk 146250 out 146250 NM1 20 2 NM2 26 12 P 2
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00053801
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:04:00.0: 0xCB81: parsing clock script 0
>[drm] nouveau 0000:04:00.0: 0xCB81: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB81: Reg: 0x6061C128, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061C928, Data: 0x950B160D
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061C928, Data: 0x950B160D
>[drm] nouveau 0000:04:00.0: 0xCB8E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB8E: Reg: 0x40614300, Mask: 0xFCFCFFFF, Data: 0x03010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00614B00, Data: 0x03814080
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00614B00, Data: 0x03814080
>[drm] nouveau 0000:04:00.0: 0xCB9B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:04:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000002b0
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:04:00.0: 0xCB9C: parsing clock script 1
>[drm] nouveau 0000:04:00.0: 0xCB9C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000a0: 0x00040100
>[drm] nouveau 0000:04:00.0: Ch1/0x000000a4: 0xfffe0000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000a8: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch1/0x000000ac: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch1/0x000000b0: 0x000400e0
>[drm] nouveau 0000:04:00.0: Ch1/0x000000b4: 0x40000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000b8: 0x00100088
>[drm] nouveau 0000:04:00.0: Ch1/0x000000bc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000c0: 0xf00d0000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000c4: 0x74b1e000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000c8: 0xcafe0000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000cc: 0x000800a0
>[drm] nouveau 0000:04:00.0: Ch1/0x000000d0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000d4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000d8: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch1/0x000000dc: 0x01000003
>[drm] nouveau 0000:04:00.0: Ch1/0x000000e0: 0x00080110
>[drm] nouveau 0000:04:00.0: Ch1/0x000000e4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000e8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000ec: 0x00140800
>[drm] nouveau 0000:04:00.0: Ch1/0x000000f0: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch1/0x000000f4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x000000f8: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch1/0x000000fc: 0x00101b00
>[drm] nouveau 0000:04:00.0: Ch1/0x00000100: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch1/0x00000104: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch1/0x00000108: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x0000010c: PUSH!
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-3] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 62:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 62:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm] nouveau 0000:04:00.0: nv50_sor_mode_fixup:156 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:04:00.0: Ch0/0x000001dc: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000001e0: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001e4: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000001e8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001ec: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000001f0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001f4: PUSH!
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:04:00.0: Ch2/0x00000080: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch2/0x00000084: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000088: 0x00040094
>[drm] nouveau 0000:04:00.0: Ch2/0x0000008c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000090: 0x000400c0
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: Ch2/0x00000094: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000098: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch2/0x0000009c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000a0: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:04:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x000001f4: 0x00080c80
>[drm] nouveau 0000:04:00.0: Ch0/0x000001f8: 0x05000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000001fc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000200: 0x00040c9c
>[drm] nouveau 0000:04:00.0: Ch0/0x00000204: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000208: 0x00080c40
>[drm] nouveau 0000:04:00.0: Ch0/0x0000020c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000210: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000214: 0x00040c5c
>[drm] nouveau 0000:04:00.0: Ch0/0x00000218: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000021c: 0x00040c74
>[drm] nouveau 0000:04:00.0: Ch0/0x00000220: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000224: 0x00080c04
>[drm] nouveau 0000:04:00.0: Ch0/0x00000228: 0x00823b4a
>[drm] nouveau 0000:04:00.0: Ch0/0x0000022c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000230: 0x00180c10
>[drm] nouveau 0000:04:00.0: Ch0/0x00000234: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000238: 0x044108c0
>[drm] nouveau 0000:04:00.0: Ch0/0x0000023c: 0x000500af
>[drm] nouveau 0000:04:00.0: Ch0/0x00000240: 0x002301c7
>[drm] nouveau 0000:04:00.0: Ch0/0x00000244: 0x043d0857
>[drm] nouveau 0000:04:00.0: Ch0/0x00000248: 0x00000001
>[drm] nouveau 0000:04:00.0: Ch0/0x0000024c: 0x00040c2c
>[drm] nouveau 0000:04:00.0: Ch0/0x00000250: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000254: 0x00040d00
>[drm] nouveau 0000:04:00.0: Ch0/0x00000258: 0x00000311
>[drm] nouveau 0000:04:00.0: Ch0/0x0000025c: 0x00040cc8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000260: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x00000264: 0x00040cd4
>[drm] nouveau 0000:04:00.0: Ch0/0x00000268: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000026c: 0x00040ca0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000270: 0x00000002
>[drm] nouveau 0000:04:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x00000274: 0x00040ca4
>[drm] nouveau 0000:04:00.0: Ch0/0x00000278: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000027c: 0x00080cd8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000280: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x00000284: 0x041a0690
>[drm] nouveau 0000:04:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:04:00.0: Ch0/0x00000288: 0x00140c60
>[drm] nouveau 0000:04:00.0: Ch0/0x0000028c: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch0/0x00000290: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000294: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch0/0x00000298: 0x00101b00
>[drm] nouveau 0000:04:00.0: Ch0/0x0000029c: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch0/0x000002a0: 0x00040c40
>[drm] nouveau 0000:04:00.0: Ch0/0x000002a4: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002a8: 0x00040ca8
>[drm] nouveau 0000:04:00.0: Ch0/0x000002ac: 0x00040000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002b0: 0x00040cc0
>[drm] nouveau 0000:04:00.0: Ch0/0x000002b4: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:17:TMDS-17] set [MODE:62:1680x1050]
>[drm] nouveau 0000:04:00.0: nv50_sor_mode_set:203 - or 2 type 6 -> crtc 1
>[drm] nouveau 0000:04:00.0: nv50_sor_dpms:78 - or 2 type 6 mode 0
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000001
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCAD4: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCAD4: Executing subroutine at 0xCD40
>[drm] nouveau 0000:04:00.0: 0xCD40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD40: Reg: 0x0000E848, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E848, Data: 0x80191501
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E848, Data: 0x80191501
>[drm] nouveau 0000:04:00.0: 0xCD4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD4D: Reg: 0x0000E840, Mask: 0x77FFFFFF, Data: 0x88000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E840, Data: 0x80080000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E840, Data: 0x88080000
>[drm] nouveau 0000:04:00.0: 0xCD5A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xCD5A: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xCD5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCD5D: Reg: 0x0000E840, Mask: 0xF7FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0000E840, Data: 0x88080000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0000E840, Data: 0x80080000
>[drm] nouveau 0000:04:00.0: 0xCD6A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCAD4: End of 0xCD40 subroutine
>[drm] nouveau 0000:04:00.0: 0xCAD7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAD7: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x00401100
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D10C, Data: 0x00405101
>[drm] nouveau 0000:04:00.0: 0xCAE4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAE4: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D128, Data: 0x14000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D128, Data: 0x94000000
>[drm] nouveau 0000:04:00.0: 0xCAF1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCAF1: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615300, Data: 0x00000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00615300, Data: 0x03000484
>[drm] nouveau 0000:04:00.0: 0xCAFE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D00C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 0xCB07: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060152F
>[drm] nouveau 0000:04:00.0: 0xCB10: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D014, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB19: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xCB19: Condition: 0x0D
>[drm] nouveau 0000:04:00.0: 0xCB19: Cond: 0x0D, Reg: 0x00000008, Mask: 0x000000F0
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00000008, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB19: Checking if 0x00000000 equals 0x00000010
>[drm] nouveau 0000:04:00.0: 0xCB19: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xCB1B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xCB1B: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xCB1C: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCB1C: Executing subroutine at 0xBFCA
>[drm] nouveau 0000:04:00.0: 0xBFCA: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xBFCA: Condition: 0x0E
>[drm] nouveau 0000:04:00.0: 0xBFCA: Cond: 0x0E, Reg: 0x40614300, Mask: 0x00030000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615300, Data: 0x03000484
>[drm] nouveau 0000:04:00.0: 0xBFCA: Checking if 0x00000000 equals 0x00010000
>[drm] nouveau 0000:04:00.0: 0xBFCA: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xBFCC: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:04:00.0: 0xBFCC: ------ Executing following commands ------
>[drm] nouveau 0000:04:00.0: 0xBFCD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFCD: Reg: 0x4061C00C, Mask: 0xF0FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D00C, Data: 0x020003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D00C, Data: 0x000003D0
>[drm] nouveau 0000:04:00.0: 0xBFDA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFDA: Reg: 0x4061C008, Mask: 0x00FFFFFF, Data: 0x14000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D008, Data: 0x00800000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D008, Data: 0x14800000
>[drm] nouveau 0000:04:00.0: 0xBFE7: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xBFE7: Sleeping for 0x0190 microseconds
>[drm] nouveau 0000:04:00.0: 0xBFEA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFEA: Reg: 0x4061C008, Mask: 0x00FFFFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D008, Data: 0x14800000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D008, Data: 0x00800000
>[drm] nouveau 0000:04:00.0: 0xBFF7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xBFF7: Reg: 0x4061C00C, Mask: 0xF0FFFFFF, Data: 0x01000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D00C, Data: 0x000003D0
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D00C, Data: 0x010003D0
>[drm] nouveau 0000:04:00.0: 0xC004: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xC004: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xC007: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xC008: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCB1C: End of 0xBFCA subroutine
>[drm] nouveau 0000:04:00.0: 0xCB1F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xCB20: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB20: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615300, Data: 0x03000484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00615300, Data: 0x03010484
>[drm] nouveau 0000:04:00.0: 0xCB2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:04:00.0: 0xCB2D: Executing subroutine at 0xABD0
>[drm] nouveau 0000:04:00.0: 0xABD0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABD0: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060952F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 0xABDD: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xABDD: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xABE0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xABE0: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xABE0: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 0xABE0: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xABE0: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xABE2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABE2: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060912F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060812F
>[drm] nouveau 0000:04:00.0: 0xABEF: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xABF0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xABF0: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060012F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060092F
>[drm] nouveau 0000:04:00.0: 0xABFD: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xABFD: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC00: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC00: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC00: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060892F
>[drm] nouveau 0000:04:00.0: 0xAC00: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC00: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xAC02: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC02: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060892F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060812F
>[drm] nouveau 0000:04:00.0: 0xAC0F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC10: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC10: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060012F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 0xAC1D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xAC1D: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC20: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC20: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC20: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 0xAC20: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC20: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:04:00.0: 0xAC22: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC2F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC2F: ---- Executing following commands ----
>[drm] nouveau 0000:04:00.0: 0xAC30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC30: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060052F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060072F
>[drm] nouveau 0000:04:00.0: 0xAC3D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xAC3D: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:04:00.0: 0xAC40: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:04:00.0: 0xAC40: Condition: 0x11
>[drm] nouveau 0000:04:00.0: 0xAC40: Cond: 0x11, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060872F
>[drm] nouveau 0000:04:00.0: 0xAC40: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:04:00.0: 0xAC40: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:04:00.0: 0xAC42: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xAC42: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0060872F
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D010, Data: 0x0060852F
>[drm] nouveau 0000:04:00.0: 0xAC4F: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:04:00.0: 0xAC50: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: 0xCB2D: End of 0xABD0 subroutine
>[drm] nouveau 0000:04:00.0: 0xCB30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB30: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D130, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:04:00.0: 0xCB3D: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:04:00.0: 0xCB3D: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:04:00.0: 0xCB40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB40: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:04:00.0: 0xCB4D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB4D: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x00405101
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D10C, Data: 0x00404101
>[drm] nouveau 0000:04:00.0: 0xCB5A: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840601
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000600 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000001
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB62: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000020
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB6A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: dp_set_link_config:343 - 4 lanes at 162000 KB/s
>[drm] nouveau 0000:04:00.0: 0xCB9E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000100 2
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00008406
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840620
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000021
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 0 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 1 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 2 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 3 00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000103 4
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000202 6
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00801111
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: dp_link_train_update:490 - status 11 11 80 00 00 00
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 2
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00801121
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000022
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000202 6
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01817777
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: dp_link_train_update:490 - status 77 77 81 01 00 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 0 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 1 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 2 00
>[drm] nouveau 0000:04:00.0: dp_link_train_commit:438 - config lane 3 00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000103 4
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: dp_set_training_pattern:395 - training pattern 0
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01817722
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000020
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB6B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB6B: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00001000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004F4101
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004F5101
>[drm] nouveau 0000:04:00.0: 0xCB78: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01817720
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 8: 0x00000102 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: 0xCB80: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: Ch0/0x000002b8: 0x00040680
>[drm] nouveau 0000:04:00.0: Ch0/0x000002bc: 0x00053802
>[drm] nouveau 0000:04:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:04:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:04:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x000002c0: 0x00080c80
>[drm] nouveau 0000:04:00.0: Ch0/0x000002c4: 0x05000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002c8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002cc: 0x00040c9c
>[drm] nouveau 0000:04:00.0: Ch0/0x000002d0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002d4: 0x00080c40
>[drm] nouveau 0000:04:00.0: Ch0/0x000002d8: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002dc: 0x000017f0
>[drm] nouveau 0000:04:00.0: Ch0/0x000002e0: 0x00040c5c
>[drm] nouveau 0000:04:00.0: Ch0/0x000002e4: 0x01000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002e8: 0x00080c60
>[drm] nouveau 0000:04:00.0: Ch0/0x000002ec: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch0/0x000002f0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000002f4: 0x00040c74
>[drm] nouveau 0000:04:00.0: Ch0/0x000002f8: 0x01000003
>[drm] nouveau 0000:04:00.0: Ch0/0x000002fc: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000300: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000304: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x00000308: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000030c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000310: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000314: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000540
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00053801
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000550
>[drm] nouveau 0000:04:00.0: Loading PLL limits for register 0x00614900
>[drm] nouveau 0000:04:00.0: pll.vco1.minfreq: 250000
>[drm] nouveau 0000:04:00.0: pll.vco1.maxfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_inputfreq: 4000
>[drm] nouveau 0000:04:00.0: pll.vco1.max_inputfreq: 27000
>[drm] nouveau 0000:04:00.0: pll.vco1.min_n: 20
>[drm] nouveau 0000:04:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco1.max_m: 2
>[drm] nouveau 0000:04:00.0: pll.vco2.minfreq: 500000
>[drm] nouveau 0000:04:00.0: pll.vco2.maxfreq: 1000000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_inputfreq: 14000
>[drm] nouveau 0000:04:00.0: pll.vco2.max_inputfreq: 75000
>[drm] nouveau 0000:04:00.0: pll.vco2.min_n: 14
>[drm] nouveau 0000:04:00.0: pll.vco2.max_n: 255
>[drm] nouveau 0000:04:00.0: pll.vco2.min_m: 1
>[drm] nouveau 0000:04:00.0: pll.vco2.max_m: 255
>[drm] nouveau 0000:04:00.0: pll.max_log2p: 6
>[drm] nouveau 0000:04:00.0: pll.log2p_bias: 0
>[drm] nouveau 0000:04:00.0: pll.refclk: 27000
>[drm] nouveau 0000:04:00.0: nv50_crtc_set_clock:312 - pclk 146250 out 146250 NM1 20 2 NM2 26 12 P 2
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00053801
>[drm] nouveau 0000:04:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00053802
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:04:00.0: 0xCB81: parsing clock script 0
>[drm] nouveau 0000:04:00.0: 0xCB81: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB81: Reg: 0x6061C128, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x0061D128, Data: 0x94000000
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x0061D128, Data: 0x94000000
>[drm] nouveau 0000:04:00.0: 0xCB8E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:04:00.0: 0xCB8E: Reg: 0x40614300, Mask: 0xFCFCFFFF, Data: 0x03010000
>[drm] nouveau 0000:04:00.0: 	Read:  Reg: 0x00615300, Data: 0x03810484
>[drm] nouveau 0000:04:00.0: 	Write: Reg: 0x00615300, Data: 0x03810484
>[drm] nouveau 0000:04:00.0: 0xCB9B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:04:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000550
>[drm] nouveau 0000:04:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:04:00.0: 0xCB9C: parsing clock script 1
>[drm] nouveau 0000:04:00.0: 0xCB9C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:04:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>usb 6-1: new low speed USB device number 2 using uhci_hcd
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000a0: 0x00040100
>[drm] nouveau 0000:04:00.0: Ch2/0x000000a4: 0xfffe0000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000a8: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch2/0x000000ac: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch2/0x000000b0: 0x000400e0
>[drm] nouveau 0000:04:00.0: Ch2/0x000000b4: 0x40000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000b8: 0x00100088
>[drm] nouveau 0000:04:00.0: Ch2/0x000000bc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000c0: 0xf00d0000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000c4: 0x74b1e000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000c8: 0xcafe0000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000cc: 0x000800a0
>[drm] nouveau 0000:04:00.0: Ch2/0x000000d0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000d4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000d8: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch2/0x000000dc: 0x01000003
>[drm] nouveau 0000:04:00.0: Ch2/0x000000e0: 0x00080110
>[drm] nouveau 0000:04:00.0: Ch2/0x000000e4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000e8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000ec: 0x00140800
>[drm] nouveau 0000:04:00.0: Ch2/0x000000f0: 0x00003100
>[drm] nouveau 0000:04:00.0: Ch2/0x000000f4: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x000000f8: 0x041a0690
>[drm] nouveau 0000:04:00.0: Ch2/0x000000fc: 0x00101b00
>[drm] nouveau 0000:04:00.0: Ch2/0x00000100: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch2/0x00000104: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch2/0x00000108: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x0000010c: PUSH!
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-4] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>fb1: nouveaufb frame buffer device
>[drm] Initialized nouveau 0.0.16 20090420 for 0000:04:00.0 on minor 1
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>Initializing USB Mass Storage driver...
>scsi0 : SCSI emulation for USB Mass Storage devices
>usb-storage: device found at 2
>usb-storage: waiting for device to settle before scanning
>usbcore: registered new interface driver usb-storage
>USB Mass Storage support registered.
>usb 6-1: New USB device found, idVendor=413c, idProduct=3012
>usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>usb 6-1: Product: Dell USB Optical Mouse
>usb 6-1: Manufacturer: Dell
>usb 6-1: configuration #1 chosen from 1 choice
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>input: Dell Dell USB Optical Mouse as /devices/pci0000:00/0000:00:1d.0/usb6/6-1/6-1:1.0/input/input4
>generic-usb 0003:413C:3012.0001: input,hidraw0: USB HID v1.11 Mouse [Dell Dell USB Optical Mouse] on usb-0000:00:1d.0-1/input0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Starting plymouth daemon
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:63] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1]
>[drm] nouveau 0000:03:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(0): sink not detected
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1]
>[drm] nouveau 0000:03:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(0): sink not detected
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-2]
>[drm] nouveau 0000:03:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 00 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 01 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 02 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 03 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 04 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 05 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 06 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 07 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 08 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 09 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 10 0x01104000 0x10000100
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 11 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 12 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 13 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 14 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 15 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 16 0x01104000 0x10000100
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 17 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 18 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 19 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 20 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 21 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 22 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 23 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 24 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 25 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 26 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 27 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 28 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 29 0x01104000 0x10000100
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 30 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 31 0x01104000 0x10000100
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-2] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>Switching to clocksource hpet
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: rd_NO_DM: removing DM RAID activation
>dracut: rd_NO_MD: removing MD RAID activation
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ahci 0000:00:1f.2: version 3.0
>ahci 0000:00:1f.2: PCI INT B -> GSI 18 (level, low) -> IRQ 18
>  alloc irq_desc for 28 on node -1
>  alloc kstat_irqs on node -1
>ahci 0000:00:1f.2: irq 28 for MSI/MSI-X
>ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 6 ports 3 Gbps 0x3f impl SATA mode
>ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ccc sxs 
>ahci 0000:00:1f.2: setting latency timer to 64
>scsi1 : ahci
>scsi2 : ahci
>scsi3 : ahci
>scsi4 : ahci
>scsi5 : ahci
>scsi6 : ahci
>ata1: SATA max UDMA/133 abar m2048@0xfe204000 port 0xfe204100 irq 28
>ata2: SATA max UDMA/133 irq_stat 0x00000040, connection status changed irq 28
>ata3: SATA max UDMA/133 abar m2048@0xfe204000 port 0xfe204200 irq 28
>ata4: SATA max UDMA/133 abar m2048@0xfe204000 port 0xfe204280 irq 28
>ata5: SATA max UDMA/133 abar m2048@0xfe204000 port 0xfe204300 irq 28
>ata6: SATA max UDMA/133 abar m2048@0xfe204000 port 0xfe204380 irq 28
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ata3: SATA link down (SStatus 0 SControl 300)
>ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>ata1.00: ATA-7: ST3250410AS, 3.AHC, max UDMA/100
>ata1.00: 488397168 sectors, multi 16: LBA48 NCQ (depth 31/32)
>ata1.00: configured for UDMA/100
>ata5: SATA link down (SStatus 0 SControl 300)
>ata4: SATA link down (SStatus 0 SControl 300)
>ata6: SATA link down (SStatus 0 SControl 300)
>scsi 1:0:0:0: Direct-Access     ATA      ST3250410AS      3.AH PQ: 0 ANSI: 5
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
>ata2.00: ATAPI: ATAPI   DVD D  DH16D3S, SH37, max UDMA/100
>ata2.00: configured for UDMA/100
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>scsi 2:0:0:0: CD-ROM            ATAPI    DVD D  DH16D3S   SH37 PQ: 0 ANSI: 5
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>usb-storage: device scan complete
>scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 102 PMAP PQ: 0 ANSI: 0 CCS
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_ohci 0000:10:0b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_ohci: Added fw-ohci device 0000:10:0b.0, OHCI version 1.0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sd 1:0:0:0: [sda] 488397168 512-byte logical blocks: (250 GB/232 GiB)
>sd 1:0:0:0: [sda] Write Protect is off
>sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
>sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
> sda:
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sd 0:0:0:0: [sdb] 30695424 512-byte logical blocks: (15.7 GB/14.6 GiB)
>sd 0:0:0:0: [sdb] Write Protect is off
>sd 0:0:0:0: [sdb] Mode Sense: 23 00 00 00
>sd 0:0:0:0: [sdb] Assuming drive cache: write through
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sd 0:0:0:0: [sdb] Assuming drive cache: write through
> sdb:
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
> sdb1
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sd 0:0:0:0: [sdb] Assuming drive cache: write through
>sd 0:0:0:0: [sdb] Attached SCSI removable disk
> unknown partition table
>sd 1:0:0:0: [sda] Attached SCSI disk
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sr0: scsi3-mmc drive: 48x/48x cd/rw xa/form2 cdda tray
>Uniform CD-ROM driver Revision: 3.20
>sr 2:0:0:0: Attached scsi CD-ROM sr0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>kjournald starting.  Commit interval 5 seconds
>EXT3-fs (sdb1): mounted filesystem with ordered data mode
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>squashfs: version 4.0 (2009/01/31) Phillip Lougher
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_core: created device fw0: GUID 0030bd051505e113, S400
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EXT4-fs (dm-0): mounted filesystem with ordered data mode. Opts: 
>dracut: Mounted root filesystem /dev/mapper/live-rw
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Loading SELinux policy
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>type=1404 audit(1333545624.295:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux: 2048 avtab hash slots, 230610 rules.
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux: 2048 avtab hash slots, 230610 rules.
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux:  9 users, 12 roles, 3641 types, 183 bools, 1 sens, 1024 cats
>SELinux:  81 classes, 230610 rules
>SELinux:  Completing initialization.
>SELinux:  Setting up existing superblocks.
>SELinux: initialized (dev dm-0, type ext4), uses xattr
>SELinux: (dev loop2, type squashfs) has no xattr support
>SELinux: (dev loop0, type squashfs) has no xattr support
>SELinux: initialized (dev sdb1, type ext3), uses xattr
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev usbfs, type usbfs), uses genfs_contexts
>SELinux: initialized (dev selinuxfs, type selinuxfs), uses genfs_contexts
>SELinux: initialized (dev mqueue, type mqueue), uses transition SIDs
>SELinux: initialized (dev hugetlbfs, type hugetlbfs), uses transition SIDs
>SELinux: initialized (dev devpts, type devpts), uses transition SIDs
>SELinux: initialized (dev inotifyfs, type inotifyfs), uses genfs_contexts
>SELinux: initialized (dev anon_inodefs, type anon_inodefs), uses genfs_contexts
>SELinux: initialized (dev pipefs, type pipefs), uses task SIDs
>SELinux: initialized (dev debugfs, type debugfs), uses genfs_contexts
>SELinux: initialized (dev sockfs, type sockfs), uses task SIDs
>SELinux: initialized (dev devtmpfs, type devtmpfs), uses transition SIDs
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev proc, type proc), uses genfs_contexts
>SELinux: initialized (dev bdev, type bdev), uses genfs_contexts
>SELinux: initialized (dev rootfs, type rootfs), uses genfs_contexts
>SELinux: initialized (dev sysfs, type sysfs), uses genfs_contexts
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>type=1403 audit(1333545624.639:3): policy loaded auid=4294967295 ses=4294967295
>dracut: 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Switching root
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>readahead-collector: starting
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>udev: starting version 147
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EDAC MC: Ver: 2.1.0 Mar 29 2012
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EDAC MC0: Giving out device to 'x38_edac' 'x38': DEV 0000:00:00.0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>snd_hda_intel 0000:00:1b.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21
>  alloc irq_desc for 29 on node -1
>  alloc kstat_irqs on node -1
>snd_hda_intel 0000:00:1b.0: irq 29 for MSI/MSI-X
>snd_hda_intel 0000:00:1b.0: setting latency timer to 64
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>hda_codec: ALC262: SKU not ready 0x411111f0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>input: HDA Intel Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input5
>input: HDA Intel Front Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input6
>input: HDA Intel Rear Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input7
>input: HDA Intel Front Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8
>input: HDA Intel Line-Out as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>tg3.c:v3.122 (December 7, 2011)
>tg3 0000:34:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>tg3 0000:34:00.0: setting latency timer to 64
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>tg3 0000:34:00.0: eth0: Tigon3 [partno(BCM95751A519FLP) rev 4201] (PCI Express) MAC address 00:10:18:48:2a:95
>tg3 0000:34:00.0: eth0: attached PHY is 5750 (10/100/1000Base-T Ethernet) (WireSpeed[1], EEE[0])
>tg3 0000:34:00.0: eth0: RXcsums[0] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>tg3 0000:34:00.0: eth0: dma_rwctrl[76180000] dma_mask[64-bit]
>  alloc irq_desc for 17 on node -1
>  alloc kstat_irqs on node -1
>tg3 0000:3f:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
>tg3 0000:3f:00.0: setting latency timer to 64
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>tg3 0000:3f:00.0: eth1: Tigon3 [partno(BCM95755) rev a002] (PCI Express) MAC address 00:23:7d:4a:74:3e
>tg3 0000:3f:00.0: eth1: attached PHY is 5755 (10/100/1000Base-T Ethernet) (WireSpeed[1], EEE[0])
>tg3 0000:3f:00.0: eth1: RXcsums[0] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>tg3 0000:3f:00.0: eth1: dma_rwctrl[76180000] dma_mask[64-bit]
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>iTCO_vendor_support: vendor-support=0
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>iTCO_wdt: Intel TCO WatchDog Timer Driver v1.05
>iTCO_wdt: Found a ICH9R TCO device (Version=2, TCOBASE=0xf860)
>iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sd 1:0:0:0: Attached scsi generic sg0 type 0
>sr 2:0:0:0: Attached scsi generic sg1 type 5
>sd 0:0:0:0: Attached scsi generic sg2 type 0
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU0 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU1 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU2 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU3 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU0 updated to revision 0xa0b, date = 2010-09-28 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU1 updated to revision 0xa0b, date = 2010-09-28 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU2 updated to revision 0xa0b, date = 2010-09-28 
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>microcode: CPU3 updated to revision 0xa0b, date = 2010-09-28 
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:03:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>parport_pc 00:07: reported by Plug and Play ACPI
>parport0: PC-style at 0x378 (0x778), irq 7 [PCSPP,TRISTATE]
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ppdev: user-space parallel port driver
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:04:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux: initialized (dev binfmt_misc, type binfmt_misc), uses genfs_contexts
>readahead-disable-service: delaying service auditd
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>NET: Registered protocol family 10
>lo: Disabled Privacy Extensions
>ip6_tables: (C) 2000-2006 Netfilter Core Team
>nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
>ip_tables: (C) 2000-2006 Netfilter Core Team
>[drm] nouveau 0000:03:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(0): sink not detected
>[drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2
>[drm] nouveau 0000:03:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:03:00.0: AUXCH(2): 00 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 01 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 02 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 03 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 04 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 05 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 06 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 07 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 08 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 09 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 10 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 11 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 12 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 13 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 14 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 15 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 16 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 17 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 18 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 19 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 20 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 21 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 22 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 23 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 24 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 25 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 26 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 27 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 28 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 29 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 30 0x01104000 0x10000100
>[drm] nouveau 0000:03:00.0: AUXCH(2): 31 0x01104000 0x10000100
>[drm:output_poll_execute], [CONNECTOR:16:DP-2] status updated from 1 to 1
>802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
>All bugs added by David S. Miller <davem@redhat.com>
>cnic: Broadcom NetXtreme II CNIC Driver cnic v2.5.9 (Feb 8, 2012)
>bnx2fc: Broadcom NetXtreme II FCoE Driver bnx2fc v1.0.10 (Jan 22, 2011)
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01817700
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01817700
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:13:DP-3] status updated from 1 to 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01817700
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01817700
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:16:DP-4] status updated from 1 to 1
>  alloc irq_desc for 30 on node -1
>  alloc kstat_irqs on node -1
>tg3 0000:34:00.0: irq 30 for MSI/MSI-X
>ADDRCONF(NETDEV_UP): eth0: link is not ready
>  alloc irq_desc for 31 on node -1
>  alloc kstat_irqs on node -1
>tg3 0000:3f:00.0: irq 31 for MSI/MSI-X
>ADDRCONF(NETDEV_UP): eth1: link is not ready
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:04:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:03:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d442c0
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nouveau_channel_alloc:157 - initialising channel 2
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_channel_init:752 - ch2 vram=0xd8000001 tt=0xd8000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_channel_init_pramin:660 - ch2
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=66560 align=4096 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02f40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x003b7200 vinst=0x0000b10200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff8800e2a02dc0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02cc0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d44ac0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000010
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d440c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000011
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02c40
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006c8
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006c8: h=0xd8000001, c=0x00000e04
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02ec0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000002
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006d0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006d0: h=0xd8000002, c=0x00000e06
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d44bc0
>[drm] nouveau 0000:04:00.0: nv50_fifo_create_context:237 - ch2
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d44140
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d44440
>[drm] nouveau 0000:04:00.0: nv50_fifo_channel_enable:68 - ch2
>[drm] nouveau 0000:04:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x5039
>[drm] nouveau 0000:04:00.0: nv50_graph_context_new:235 - ch2
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=376832 align=0 flags=0x00000006
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02ac0
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d448c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000001
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000408: h=0x80000001, c=0x00100f40
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e4d449c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000006
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000430: h=0x80000006, c=0x00000f41
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x506e
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x8000000e
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_channel_alloc:215 - channel 2 initialised
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x0030
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a029c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000000
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000000: h=0x00000000, c=0x00100f43
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a027c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000003
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006d8
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006d8: h=0xd8000003, c=0x00000f44
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x502d
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02740
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000020
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000500
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000500: h=0x80000020, c=0x00100f46
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x5039
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a026c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000018
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000004c0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000004c0: h=0x80000018, c=0x00100f47
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x8297
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02640
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000019
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000004c8
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000004c8: h=0x80000019, c=0x00100f48
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x506e
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000021
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000508
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000508: h=0x80000021, c=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a02540
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000004
>[drm] nouveau 0000:04:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006e0
>[drm] nouveau 0000:04:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006e0: h=0xd8000004, c=0x00000f49
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:04:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8800e2a024c0
>[drm:drm_mode_addfb], [FB:40]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DP-3]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:40] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: Ch1/0x0000010c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch1/0x00000110: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000114: 0x00040094
>[drm] nouveau 0000:04:00.0: Ch1/0x00000118: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x0000011c: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch1/0x00000120: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000124: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch1/0x00000128: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x0000012c: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000314: 0x00040874
>[drm] nouveau 0000:04:00.0: Ch0/0x00000318: 0x01000002
>[drm] nouveau 0000:04:00.0: Ch0/0x0000031c: 0x00140860
>[drm] nouveau 0000:04:00.0: Ch0/0x00000320: 0x0000b900
>[drm] nouveau 0000:04:00.0: Ch0/0x00000324: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000328: 0x041a0d20
>[drm] nouveau 0000:04:00.0: Ch0/0x0000032c: 0x0000d204
>[drm] nouveau 0000:04:00.0: Ch0/0x00000330: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch0/0x00000334: 0x00040840
>[drm] nouveau 0000:04:00.0: Ch0/0x00000338: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000033c: 0x000408a8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000340: 0x00040000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000344: 0x000408c0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000348: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000034c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000350: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000354: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x00000358: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000035c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x00000360: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000364: PUSH!
>[drm] nouveau 0000:04:00.0: Ch1/0x0000012c: 0x00040100
>[drm] nouveau 0000:04:00.0: Ch1/0x00000130: 0xfffe0000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000134: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch1/0x00000138: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch1/0x0000013c: 0x000400e0
>[drm] nouveau 0000:04:00.0: Ch1/0x00000140: 0x40000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000144: 0x00100088
>[drm] nouveau 0000:04:00.0: Ch1/0x00000148: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch1/0x0000014c: 0xf00d0001
>[drm] nouveau 0000:04:00.0: Ch1/0x00000150: 0x74b1e000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000154: 0xcafe0000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000158: 0x000800a0
>[drm] nouveau 0000:04:00.0: Ch1/0x0000015c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000160: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000164: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch1/0x00000168: 0x01000002
>[drm] nouveau 0000:04:00.0: Ch1/0x0000016c: 0x00080110
>[drm] nouveau 0000:04:00.0: Ch1/0x00000170: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000174: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000178: 0x00140800
>[drm] nouveau 0000:04:00.0: Ch1/0x0000017c: 0x0000b900
>[drm] nouveau 0000:04:00.0: Ch1/0x00000180: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000184: 0x041a0d20
>[drm] nouveau 0000:04:00.0: Ch1/0x00000188: 0x0000d204
>[drm] nouveau 0000:04:00.0: Ch1/0x0000018c: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch1/0x00000190: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch1/0x00000194: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch1/0x00000198: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-4]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:40] #connectors=1 (x y) (1680 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-3] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-4] to [CRTC:12]
>[drm] nouveau 0000:04:00.0: Ch2/0x0000010c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch2/0x00000110: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000114: 0x00040094
>[drm] nouveau 0000:04:00.0: Ch2/0x00000118: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x0000011c: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch2/0x00000120: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000124: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch2/0x00000128: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x0000012c: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:04:00.0: Ch0/0x00000364: 0x00040c74
>[drm] nouveau 0000:04:00.0: Ch0/0x00000368: 0x01000002
>[drm] nouveau 0000:04:00.0: Ch0/0x0000036c: 0x00140c60
>[drm] nouveau 0000:04:00.0: Ch0/0x00000370: 0x0000b900
>[drm] nouveau 0000:04:00.0: Ch0/0x00000374: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000378: 0x041a0d20
>[drm] nouveau 0000:04:00.0: Ch0/0x0000037c: 0x0000d204
>[drm] nouveau 0000:04:00.0: Ch0/0x00000380: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch0/0x00000384: 0x00040c40
>[drm] nouveau 0000:04:00.0: Ch0/0x00000388: 0xc0000000
>[drm] nouveau 0000:04:00.0: Ch0/0x0000038c: 0x00040ca8
>[drm] nouveau 0000:04:00.0: Ch0/0x00000390: 0x00040000
>[drm] nouveau 0000:04:00.0: Ch0/0x00000394: 0x00040cc0
>[drm] nouveau 0000:04:00.0: Ch0/0x00000398: 0x00000690
>[drm] nouveau 0000:04:00.0: Ch0/0x0000039c: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000003a0: 0x80000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003a4: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000003a8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003ac: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch0/0x000003b0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003b4: PUSH!
>[drm] nouveau 0000:04:00.0: Ch2/0x0000012c: 0x00040100
>[drm] nouveau 0000:04:00.0: Ch2/0x00000130: 0xfffe0000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000134: 0x00040084
>[drm] nouveau 0000:04:00.0: Ch2/0x00000138: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch2/0x0000013c: 0x000400e0
>[drm] nouveau 0000:04:00.0: Ch2/0x00000140: 0x40000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000144: 0x00100088
>[drm] nouveau 0000:04:00.0: Ch2/0x00000148: 0x00000010
>[drm] nouveau 0000:04:00.0: Ch2/0x0000014c: 0xf00d0001
>[drm] nouveau 0000:04:00.0: Ch2/0x00000150: 0x74b1e000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000154: 0xcafe0000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000158: 0x000800a0
>[drm] nouveau 0000:04:00.0: Ch2/0x0000015c: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000160: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000164: 0x000400c0
>[drm] nouveau 0000:04:00.0: Ch2/0x00000168: 0x01000002
>[drm] nouveau 0000:04:00.0: Ch2/0x0000016c: 0x00080110
>[drm] nouveau 0000:04:00.0: Ch2/0x00000170: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000174: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000178: 0x00140800
>[drm] nouveau 0000:04:00.0: Ch2/0x0000017c: 0x0000b900
>[drm] nouveau 0000:04:00.0: Ch2/0x00000180: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000184: 0x041a0d20
>[drm] nouveau 0000:04:00.0: Ch2/0x00000188: 0x0000d204
>[drm] nouveau 0000:04:00.0: Ch2/0x0000018c: 0x0000cf00
>[drm] nouveau 0000:04:00.0: Ch2/0x00000190: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch2/0x00000194: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch2/0x00000198: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x000003b4: 0x0004089c
>[drm] nouveau 0000:04:00.0: Ch0/0x000003b8: 0x01000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003bc: 0x00080880
>[drm] nouveau 0000:04:00.0: Ch0/0x000003c0: 0x85000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003c4: 0x000017b0
>[drm] nouveau 0000:04:00.0: Ch0/0x000003c8: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000003cc: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003d0: PUSH!
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>hda-intel: IRQ timing workaround is activated for card #0. Suggest a bigger bdl_pos_adj.
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>fuse init (API version 7.13)
>readahead-collector: starting delayed service auditd
>readahead-collector: sorting
>readahead-collector: finished
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:13:DP-3] status updated from 1 to 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:16:DP-4] status updated from 1 to 1
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3]
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DP-3] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 22:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 32:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4]
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm] nouveau 0000:04:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-4] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 41:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 45:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 60:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 57:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 59:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 47:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 50:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 49:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1091402c
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(0): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(0): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: AUXCH(0): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(0): rd 0xe4002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:13:DP-3] status updated from 1 to 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840600
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 4: 0x00000050 1
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): wr 0x00000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xffffff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00ffffff
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01af7204
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x10913fb9
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x04011509
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x781e2fa5
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xa395deea
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x26994c54
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xbf54500f
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x010190ee
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x40814f71
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0095c081
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00810101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x39210101
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1a623090
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xb0684027
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x28da0036
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x19000011
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfd000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x1f4d3800
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a001154
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x4c00ff00
>[drm] nouveau 0000:04:00.0: AUXCH(2): 5: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x43303850
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x34343030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a303030
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0xfc000000
>[drm] nouveau 0000:04:00.0: AUXCH(2): 1: 0x00000050 16
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x32324200
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x0a575033
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: AUXCH(2): 9: 0x00000000 8
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x01840611
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x00010000
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x20202020
>[drm] nouveau 0000:04:00.0: AUXCH(2): rd 0x58002020
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:663 - display: 4x162000 dpcd 0x11
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:666 - encoder: 4x270000
>[drm] nouveau 0000:04:00.0: nouveau_dp_detect:674 - maximum: 4x162000
>[drm:output_poll_execute], [CONNECTOR:16:DP-4] status updated from 1 to 1
>[drm] nouveau 0000:04:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:04:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:04:00.0: Ch0/0x000003d0: 0x00080880
>[drm] nouveau 0000:04:00.0: Ch0/0x000003d4: 0x05000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003d8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003dc: 0x0004089c
>[drm] nouveau 0000:04:00.0: Ch0/0x000003e0: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003e4: 0x00040080
>[drm] nouveau 0000:04:00.0: Ch0/0x000003e8: 0x00000000
>[drm] nouveau 0000:04:00.0: Ch0/0x000003ec: PUSH!
>EXT3-fs (sdb1): using internal journal

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Attachments on bug 747034: 528839 | 529017 | 529031 | 575128 | 575129