Attachment 578633 Details for Bug 814236 – dmesg after resume

dmesg after resume

dmesg.resume (text/plain), 1.45 MB, created by Tomas Pelka on 2012-04-19 12:39:47 UTC

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Creator: Tomas Pelka

Created: 2012-04-19 12:39:47 UTC

Size: 1.45 MB

patch

obsolete

>Initializing cgroup subsys cpuset
>Initializing cgroup subsys cpu
>Linux version 2.6.32-262.el6.x86_64 (mockbuild@x86-007.build.bos.redhat.com) (gcc version 4.4.6 20110731 (Red Hat 4.4.6-3) (GCC) ) #1 SMP Sun Apr 8 18:38:00 EDT 2012
>Command line: ro root=UUID=9b121955-0128-4149-a6a0-0cadb764525d rd_NO_LUKS rd_NO_LVM LANG=en_US.UTF-8 rd_NO_MD quiet SYSFONT=latarcyrheb-sun16 rhgb crashkernel=auto  KEYBOARDTYPE=pc KEYTABLE=us rd_NO_DM drm.debug=14 log_buf_len=16M
>KERNEL supported cpus:
>  Intel GenuineIntel
>  AMD AuthenticAMD
>  Centaur CentaurHauls
>BIOS-provided physical RAM map:
> BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
> BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
> BIOS-e820: 00000000000e8000 - 0000000000100000 (reserved)
> BIOS-e820: 0000000000100000 - 00000000e6fc1da0 (usable)
> BIOS-e820: 00000000e6fc1da0 - 00000000e6fc1e00 (ACPI NVS)
> BIOS-e820: 00000000e6fc1e00 - 00000000e8000000 (reserved)
> BIOS-e820: 00000000f4000000 - 00000000f8000000 (reserved)
> BIOS-e820: 00000000fec00000 - 00000000fed40000 (reserved)
> BIOS-e820: 00000000fed45000 - 0000000100000000 (reserved)
> BIOS-e820: 0000000100000000 - 0000000118000000 (usable)
>DMI 2.6 present.
>SMBIOS version 2.6 @ 0xF9C00
>DMI: Hewlett-Packard HP xw4600 Workstation/0AA0h, BIOS 786F3 v01.15 08/28/2008
>e820 update range: 0000000000000000 - 0000000000001000 (usable) ==> (reserved)
>e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
>last_pfn = 0x118000 max_arch_pfn = 0x400000000
>MTRR default type: uncachable
>MTRR fixed ranges enabled:
>  00000-9FFFF write-back
>  A0000-BFFFF uncachable
>  C0000-E3FFF write-protect
>  E4000-EFFFF write-back
>  F0000-FFFFF write-protect
>MTRR variable ranges enabled:
>  0 base 000000000 mask F00000000 write-back
>  1 base 0E8000000 mask FF8000000 uncachable
>  2 base 0F0000000 mask FF0000000 uncachable
>  3 base 118000000 mask FF8000000 uncachable
>  4 base 100000000 mask FE0000000 write-back
>  5 disabled
>  6 disabled
>  7 disabled
>x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
>original variable MTRRs
>reg 0, base: 0GB, range: 4GB, type WB
>reg 1, base: 3712MB, range: 128MB, type UC
>reg 2, base: 3840MB, range: 256MB, type UC
>reg 3, base: 4480MB, range: 128MB, type UC
>reg 4, base: 4GB, range: 512MB, type WB
>total RAM covered: 4096M
>Found optimal setting for mtrr clean up
> gran_size: 64K 	chunk_size: 512M 	num_reg: 5  	lose cover RAM: 0G
>New variable MTRRs
>reg 0, base: 0GB, range: 4GB, type WB
>reg 1, base: 3712MB, range: 128MB, type UC
>reg 2, base: 3840MB, range: 256MB, type UC
>reg 3, base: 4GB, range: 512MB, type WB
>reg 4, base: 4480MB, range: 128MB, type UC
>e820 update range: 00000000e8000000 - 0000000100000000 (usable) ==> (reserved)
>last_pfn = 0xe6fc1 max_arch_pfn = 0x400000000
>initial memory mapped : 0 - 20000000
>init_memory_mapping: 0000000000000000-00000000e6fc1000
> 0000000000 - 00e6e00000 page 2M
> 00e6e00000 - 00e6fc1000 page 4k
>kernel direct mapping tables up to e6fc1000 @ 8000-e000
>init_memory_mapping: 0000000100000000-0000000118000000
> 0100000000 - 0118000000 page 2M
>kernel direct mapping tables up to 118000000 @ c000-12000
>log_buf_len: 16777216
>early log buf free: 520986(99%)
>RAMDISK: 3707a000 - 37fefe96
>ACPI: RSDP 00000000000e6410 00024 (v02 COMPAQ)
>ACPI: XSDT 00000000e6fc1ee8 0005C (v01 HPQOEM SLIC-WKS 20080828      00000000)
>ACPI: FACP 00000000e6fc2088 000F4 (v03 COMPAQ          E6FC2647      00000000)
>ACPI Error: 32/64X address mismatch in Gpe0Block: 0000F820/000000000001F028, using 32 (20090903/tbfadt-427)
>ACPI: DSDT 00000000e6fc2647 098EC (v01 COMPAQ DSDT_PRJ 00000001 MSFT 0100000E)
>ACPI: FACS 00000000e6fc1e00 00040
>ACPI: APIC 00000000e6fc217c 00084 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: ASF! 00000000e6fc2200 00063 (v32 COMPAQ BEARLX38 00000001      00000000)
>ACPI: MCFG 00000000e6fc2263 0003C (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: TCPA 00000000e6fc229f 00032 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: HPET 00000000e6fc2447 00038 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: DMAR 00000000e6fc247f 00140 (v01 COMPAQ BEARLX38 00000001      00000000)
>ACPI: Local APIC address 0xfee00000
>No NUMA configuration found
>Faking a node at 0000000000000000-0000000118000000
>Bootmem setup node 0 0000000000000000-0000000118000000
>  NODE_DATA [000000000000d000 - 0000000000040fff]
>  bootmap [0000000000041000 -  0000000000063fff] pages 23
>(9 early reservations) ==> bootmem [0000000000 - 0118000000]
>  #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
>  #1 [0000006000 - 0000008000]       TRAMPOLINE ==> [0000006000 - 0000008000]
>  #2 [0001000000 - 0002011ce4]    TEXT DATA BSS ==> [0001000000 - 0002011ce4]
>  #3 [003707a000 - 0037fefe96]          RAMDISK ==> [003707a000 - 0037fefe96]
>  #4 [000009f800 - 0000100000]    BIOS reserved ==> [000009f800 - 0000100000]
>  #5 [0002012000 - 0002012140]              BRK ==> [0002012000 - 0002012140]
>  #6 [0000008000 - 000000c000]          PGTABLE ==> [0000008000 - 000000c000]
>  #7 [000000c000 - 000000d000]          PGTABLE ==> [000000c000 - 000000d000]
>  #8 [00e5fc1000 - 00e6fc1000]          LOG BUF ==> [00e5fc1000 - 00e6fc1000]
>found SMP MP-table at [ffff8800000f9bf0] f9bf0
>Reserving 129MB of memory at 48MB for crashkernel (System RAM: 4480MB)
> [ffffea0000000000-ffffea0003dfffff] PMD -> [ffff880028600000-ffff88002bffffff] on node 0
>Zone PFN ranges:
>  DMA      0x00000001 -> 0x00001000
>  DMA32    0x00001000 -> 0x00100000
>  Normal   0x00100000 -> 0x00118000
>Movable zone start PFN for each node
>early_node_map[3] active PFN ranges
>    0: 0x00000001 -> 0x0000009f
>    0: 0x00000100 -> 0x000e6fc1
>    0: 0x00100000 -> 0x00118000
>On node 0 totalpages: 1044319
>  DMA zone: 56 pages used for memmap
>  DMA zone: 104 pages reserved
>  DMA zone: 3838 pages, LIFO batch:0
>  DMA32 zone: 14280 pages used for memmap
>  DMA32 zone: 927737 pages, LIFO batch:31
>  Normal zone: 1344 pages used for memmap
>  Normal zone: 96960 pages, LIFO batch:31
>ACPI: PM-Timer IO Port: 0xf808
>ACPI: Local APIC address 0xfee00000
>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
>ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled)
>ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled)
>ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>ACPI: IRQ0 used by override.
>ACPI: IRQ2 used by override.
>ACPI: IRQ9 used by override.
>Using ACPI (MADT) for SMP configuration information
>ACPI: HPET id: 0x8086a201 base: 0xfed00000
>SMP: Allowing 4 CPUs, 0 hotplug CPUs
>nr_irqs_gsi: 24
>PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
>PM: Registered nosave memory: 00000000000a0000 - 00000000000e8000
>PM: Registered nosave memory: 00000000000e8000 - 0000000000100000
>PM: Registered nosave memory: 00000000e6fc1000 - 00000000e6fc2000
>PM: Registered nosave memory: 00000000e6fc1000 - 00000000e6fc2000
>PM: Registered nosave memory: 00000000e6fc2000 - 00000000e8000000
>PM: Registered nosave memory: 00000000e8000000 - 00000000f4000000
>PM: Registered nosave memory: 00000000f4000000 - 00000000f8000000
>PM: Registered nosave memory: 00000000f8000000 - 00000000fec00000
>PM: Registered nosave memory: 00000000fec00000 - 00000000fed40000
>PM: Registered nosave memory: 00000000fed40000 - 00000000fed45000
>PM: Registered nosave memory: 00000000fed45000 - 0000000100000000
>Allocating PCI resources starting at e8000000 (gap: e8000000:c000000)
>Booting paravirtualized kernel on bare hardware
>NR_CPUS:4096 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1
>PERCPU: Embedded 31 pages/cpu @ffff880028200000 s94424 r8192 d24360 u524288
>pcpu-alloc: s94424 r8192 d24360 u524288 alloc=1*2097152
>pcpu-alloc: [0] 0 1 2 3 
>Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1028535
>Policy zone: Normal
>Kernel command line: ro root=UUID=9b121955-0128-4149-a6a0-0cadb764525d rd_NO_LUKS rd_NO_LVM LANG=en_US.UTF-8 rd_NO_MD quiet SYSFONT=latarcyrheb-sun16 rhgb crashkernel=129M@0M  KEYBOARDTYPE=pc KEYTABLE=us rd_NO_DM drm.debug=14 log_buf_len=16M
>PID hash table entries: 4096 (order: 3, 32768 bytes)
>xsave/xrstor: enabled xstate_bv 0x3, cntxt size 0x240
>Checking aperture...
>No AGP bridge found
>------------[ cut here ]------------
>WARNING: at drivers/pci/dmar.c:594 warn_invalid_dmar+0x7a/0x90() (Not tainted)
>Hardware name: HP xw4600 Workstation
>[Firmware Warn]: Your BIOS is broken; DMAR reported at address fed93000 returns all ones!
>BIOS vendor: Hewlett-Packard; Ver: 786F3 v01.15; Product Version:  
>Modules linked in:
>Pid: 0, comm: swapper Not tainted 2.6.32-262.el6.x86_64 #1
>Call Trace:
> [<ffffffff8106b607>] ? warn_slowpath_common+0x87/0xc0
> [<ffffffff8106b69f>] ? warn_slowpath_fmt_taint+0x3f/0x50
> [<ffffffff8103933d>] ? native_set_pte_at+0xd/0x40
> [<ffffffff81038d29>] ? native_flush_tlb_single+0x9/0x10
> [<ffffffff812a6d5a>] ? warn_invalid_dmar+0x7a/0x90
> [<ffffffff81c51191>] ? check_zero_address+0xd6/0x118
> [<ffffffff812eddbf>] ? acpi_get_table_with_size+0x5a/0xb4
> [<ffffffff81505075>] ? _etext+0x0/0x3
> [<ffffffff81c511e5>] ? detect_intel_iommu+0x12/0x91
> [<ffffffff81c2a149>] ? pci_iommu_alloc+0x5e/0x6c
> [<ffffffff81c3ce52>] ? mem_init+0x19/0xec
> [<ffffffff81c21d78>] ? start_kernel+0x221/0x430
> [<ffffffff81c2133a>] ? x86_64_start_reservations+0x125/0x129
> [<ffffffff81c21438>] ? x86_64_start_kernel+0xfa/0x109
>---[ end trace a7919e7f17c0a725 ]---
>Disabling lock debugging due to kernel taint
>PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>Placing 64MB software IO TLB between ffff880020000000 - ffff880024000000
>software IO TLB at phys 0x20000000 - 0x24000000
>Memory: 3870052k/4587520k available (5140k kernel code, 410244k absent, 307224k reserved, 7176k data, 1260k init)
>Hierarchical RCU implementation.
>NR_IRQS:33024 nr_irqs:440
>Extended CMOS year: 2000
>Console: colour VGA+ 80x25
>console [tty0] enabled
>allocated 33554432 bytes of page_cgroup
>please try 'cgroup_disable=memory' option if you don't want memory cgroups
>hpet clockevent registered
>Fast TSC calibration using PIT
>Detected 2833.272 MHz processor.
>Calibrating delay loop (skipped), value calculated using timer frequency.. 5666.54 BogoMIPS (lpj=2833272)
>pid_max: default: 32768 minimum: 301
>Security Framework initialized
>SELinux:  Initializing.
>SELinux:  Starting in permissive mode
>Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
>Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
>Mount-cache hash table entries: 256
>Initializing cgroup subsys ns
>Initializing cgroup subsys cpuacct
>Initializing cgroup subsys memory
>Initializing cgroup subsys devices
>Initializing cgroup subsys freezer
>Initializing cgroup subsys net_cls
>Initializing cgroup subsys blkio
>Initializing cgroup subsys perf_event
>Initializing cgroup subsys net_prio
>CPU: Physical Processor ID: 0
>CPU: Processor Core ID: 0
>mce: CPU supports 6 MCE banks
>CPU0: Thermal monitoring enabled (TM2)
>using mwait in idle threads.
>ACPI: Core revision 20090903
>ftrace: converting mcount calls to 0f 1f 44 00 00
>ftrace: allocating 20962 entries in 83 pages
>DMAR: Host address width 36
>DMAR: DRHD base: 0x000000fed93000 flags: 0x1
>------------[ cut here ]------------
>WARNING: at drivers/pci/dmar.c:594 warn_invalid_dmar+0x7a/0x90() (Tainted: G          I---------------   )
>Hardware name: HP xw4600 Workstation
>[Firmware Warn]: Your BIOS is broken; DMAR reported at address fed93000 returns all ones!
>BIOS vendor: Hewlett-Packard; Ver: 786F3 v01.15; Product Version:  
>Modules linked in:
>Pid: 1, comm: swapper Tainted: G          I---------------    2.6.32-262.el6.x86_64 #1
>Call Trace:
> [<ffffffff8106b607>] ? warn_slowpath_common+0x87/0xc0
> [<ffffffff8106b69f>] ? warn_slowpath_fmt_taint+0x3f/0x50
> [<ffffffff810449d8>] ? __ioremap_caller+0x2a8/0x390
> [<ffffffff812a6d5a>] ? warn_invalid_dmar+0x7a/0x90
> [<ffffffff812a6f73>] ? alloc_iommu+0x203/0x2b0
> [<ffffffff81c517d0>] ? dmar_table_init+0x1bd/0x3be
> [<ffffffff81c32384>] ? enable_IR_x2apic+0x23/0x221
> [<ffffffff81c30288>] ? native_smp_prepare_cpus+0x143/0x389
> [<ffffffff81c21740>] ? kernel_init+0x112/0x2fe
> [<ffffffff8100c14a>] ? child_rip+0xa/0x20
> [<ffffffff81c2162e>] ? kernel_init+0x0/0x2fe
> [<ffffffff8100c140>] ? child_rip+0x0/0x20
>---[ end trace a7919e7f17c0a726 ]---
>DMAR: parse DMAR table failure.
>Setting APIC routing to flat
>..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>CPU0: Intel(R) Core(TM)2 Quad CPU    Q9550  @ 2.83GHz stepping 0a
>Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver.
>... version:                2
>... bit width:              40
>... generic registers:      2
>... value mask:             000000ffffffffff
>... max period:             000000007fffffff
>... fixed-purpose events:   3
>... event mask:             0000000700000003
>NMI watchdog enabled, takes one hw-pmu counter.
>Booting Node   0, Processors  #1 #2 #3 Ok.
>Brought up 4 CPUs
>Total of 4 processors activated (22666.17 BogoMIPS).
>sizeof(vma)=200 bytes
>sizeof(page)=56 bytes
>sizeof(inode)=592 bytes
>sizeof(dentry)=192 bytes
>sizeof(ext3inode)=800 bytes
>sizeof(buffer_head)=104 bytes
>sizeof(skbuff)=232 bytes
>sizeof(task_struct)=2648 bytes
>devtmpfs: initialized
>PM: Registering ACPI NVS region at e6fc1da0 (96 bytes)
>regulator: core version 0.5
>NET: Registered protocol family 16
>ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>ACPI: bus type pci registered
>PCI: MCFG configuration 0: base f4000000 segment 0 buses 0 - 63
>PCI: MCFG area at f4000000 reserved in E820
>PCI: Using MMCONFIG at f4000000 - f7ffffff
>PCI: Using configuration type 1 for base access
>bio: create slab <bio-0> at 0
>ACPI: EC: Look up EC in DSDT
>ACPI: Interpreter enabled
>ACPI: (supports S0 S3 S4 S5)
>ACPI: Using IOAPIC for interrupt routing
>ACPI: No dock devices found.
>HEST: Table not found.
>PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880115747808), AE_ALREADY_EXISTS
>ACPI: Marking method _OSC as Serialized because of AE_ALREADY_EXISTS error
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
>ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>pci_root PNP0A08:00: host bridge window [mem 0xf8000000-0xfebfffff]
>pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
>pci_root PNP0A08:00: host bridge window [io  0x1000-0x2fff]
>pci_root PNP0A08:00: host bridge window [io  0x3000-0x6fff]
>pci_root PNP0A08:00: host bridge window [io  0x7000-0xafff]
>pci_root PNP0A08:00: host bridge window [io  0xb000-0xffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
>pci_root PNP0A08:00: host bridge window [mem 0xe8000000-0xf3ffffff]
>pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:01.0: PME# disabled
>pci 0000:00:1a.0: reg 20: [io  0x2100-0x211f]
>pci 0000:00:1a.1: reg 20: [io  0x2120-0x213f]
>pci 0000:00:1a.2: reg 20: [io  0x2140-0x215f]
>pci 0000:00:1a.7: reg 10: [mem 0xf3204800-0xf3204bff]
>pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
>pci 0000:00:1a.7: PME# disabled
>pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.0: PME# disabled
>pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.4: PME# disabled
>pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
>pci 0000:00:1c.5: PME# disabled
>pci 0000:00:1d.0: reg 20: [io  0x2160-0x217f]
>pci 0000:00:1d.1: reg 20: [io  0x2180-0x219f]
>pci 0000:00:1d.2: reg 20: [io  0x21a0-0x21bf]
>pci 0000:00:1d.7: reg 10: [mem 0xf3204c00-0xf3204fff]
>pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
>pci 0000:00:1d.7: PME# disabled
>pci 0000:00:1f.0: quirk: [io  0xf800-0xf87f] claimed by ICH6 ACPI/GPIO/TCO
>pci 0000:00:1f.0: quirk: [io  0xfa00-0xfa3f] claimed by ICH6 GPIO
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 0400 (mask 007f)
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 0480 (mask 000f)
>pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 0cb0 (mask 000f)
>pci 0000:00:1f.2: reg 10: [io  0x2200-0x2207]
>pci 0000:00:1f.2: reg 14: [io  0x2210-0x2213]
>pci 0000:00:1f.2: reg 18: [io  0x2208-0x220f]
>pci 0000:00:1f.2: reg 1c: [io  0x2214-0x2217]
>pci 0000:00:1f.2: reg 20: [io  0x21c0-0x21df]
>pci 0000:00:1f.2: reg 24: [mem 0xf3204000-0xf32047ff]
>pci 0000:00:1f.2: PME# supported from D3hot
>pci 0000:00:1f.2: PME# disabled
>pci 0000:01:00.0: reg 10: [mem 0xf2000000-0xf2ffffff]
>pci 0000:01:00.0: reg 14: [mem 0xe8000000-0xefffffff 64bit pref]
>pci 0000:01:00.0: reg 1c: [mem 0xf0000000-0xf1ffffff 64bit pref]
>pci 0000:01:00.0: reg 24: [io  0x1100-0x117f]
>pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0007ffff pref]
>pci 0000:01:00.1: reg 10: [mem 0xf3000000-0xf3003fff]
>pci 0000:00:01.0: PCI bridge to [bus 01-01]
>pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:00:01.0:   bridge window [mem 0xf2000000-0xf30fffff]
>pci 0000:00:01.0:   bridge window [mem 0xe8000000-0xf1ffffff 64bit pref]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
>pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:34:00.0: reg 10: [mem 0xf3100000-0xf310ffff 64bit]
>pci 0000:34:00.0: reg 30: [mem 0x00000000-0x0000ffff pref]
>pci 0000:34:00.0: PME# supported from D3hot D3cold
>pci 0000:34:00.0: PME# disabled
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.4:   bridge window [mem 0xf3100000-0xf31fffff]
>pci 0000:00:1c.4:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1c.5:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
>pci 0000:00:1c.5:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:10:0b.0: reg 10: [mem 0xf3300000-0xf3300fff]
>pci 0000:10:0b.0: supports D1 D2
>pci 0000:10:0b.0: PME# supported from D0 D1 D2 D3hot
>pci 0000:10:0b.0: PME# disabled
>pci 0000:00:1e.0: PCI bridge to [bus 10-10] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0xf000-0x0000] (disabled)
>pci 0000:00:1e.0:   bridge window [mem 0xf3300000-0xf33fffff]
>pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:00:1e.0:   bridge window [mem 0xf8000000-0xfebfffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x1000-0x2fff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x3000-0x6fff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0x7000-0xafff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [io  0xb000-0xffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
>pci 0000:00:1e.0:   bridge window [mem 0xe8000000-0xf3ffffff] (subtractive decode)
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEG1._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX1._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX5._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCX6._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.HUB_._PRT]
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880115747808), AE_ALREADY_EXISTS
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
> pci0000:00: Requesting ACPI _OSC control (0x1d)
>ACPI Error (dsfield-0143): [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS
>ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff880115747808), AE_ALREADY_EXISTS
>ACPI Warning for \_SB_.PCI0._OSC: Parameter count mismatch - ASL declared 5, ACPI requires 4 (20090903/nspredef-336)
>Unable to assume _OSC PCIe control. Disabling ASPM
>ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 *10 11 14 15)
>ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7 10 11 14 15)
>ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 *5 6 7 10 11 14 15)
>ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *10 11 14 15)
>ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 *11 14 15)
>ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none
>vgaarb: loaded
>vgaarb: bridge control possible 0000:01:00.0
>SCSI subsystem initialized
>libata version 3.00 loaded.
>usbcore: registered new interface driver usbfs
>usbcore: registered new interface driver hub
>usbcore: registered new device driver usb
>PCI: Using ACPI for IRQ routing
>PCI: old code would have set cacheline size to 32 bytes, but clflush_size = 64
>PCI: pci_cache_line_size set to 64 bytes
>NetLabel: Initializing
>NetLabel:  domain hash size = 128
>NetLabel:  protocols = UNLABELED CIPSOv4
>NetLabel:  unlabeled traffic allowed by default
>HPET: 4 timers in total, 0 timers will be used for per-cpu timer
>hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
>hpet0: 4 comparators, 64-bit 14.318180 MHz counter
>Switching to clocksource hpet
>pnp: PnP ACPI init
>ACPI: bus type pnp registered
>pnp 00:00: [io  0x0cf8-0x0cff]
>pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
>pnp 00:01: [io  0x00f0-0x00ff]
>pnp 00:01: [irq 13]
>pnp 00:01: Plug and Play ACPI device, IDs PNP0c04 (active)
>pnp 00:02: [io  0x0000-0x000f]
>pnp 00:02: [io  0x0080-0x008f]
>pnp 00:02: [io  0x00c0-0x00df]
>pnp 00:02: [dma 4]
>pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active)
>pnp 00:03: [io  0x0070-0x0071]
>pnp 00:03: [irq 8]
>pnp 00:03: Plug and Play ACPI device, IDs PNP0b00 (active)
>pnp 00:04: [io  0x0061]
>pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active)
>pnp 00:05: [irq 12]
>pnp 00:05: Plug and Play ACPI device, IDs PNP0f13 PNP0f0e (active)
>pnp 00:06: [io  0x0060]
>pnp 00:06: [io  0x0064]
>pnp 00:06: [irq 1]
>pnp 00:06: Plug and Play ACPI device, IDs PNP0303 (active)
>pnp 00:07: [irq 7]
>pnp 00:07: [dma 3]
>pnp 00:07: [io  0x0378-0x037f]
>pnp 00:07: [io  0x0778-0x077d]
>pnp 00:07: Plug and Play ACPI device, IDs PNP0401 (active)
>pnp 00:08: [irq 4]
>pnp 00:08: [io  0x03f8-0x03ff]
>pnp 00:08: Plug and Play ACPI device, IDs PNP0501 PNP0500 (active)
>pnp 00:09: [irq 6]
>pnp 00:09: [dma 2]
>pnp 00:09: [io  0x03f0-0x03f5]
>pnp 00:09: [io  0x03f7]
>pnp 00:09: Plug and Play ACPI device, IDs PNP0700 (active)
>pnp 00:0a: [mem 0xfec00000-0xfec00fff]
>pnp 00:0a: Plug and Play ACPI device, IDs PNP0003 (active)
>pnp 00:0b: [mem 0xfed00000-0xfed003ff]
>pnp 00:0b: Plug and Play ACPI device, IDs PNP0103 (active)
>pnp 00:0c: [io  0x0010-0x001f]
>pnp 00:0c: [io  0x0050-0x0053]
>pnp 00:0c: [io  0x0072-0x0077]
>pnp 00:0c: [io  0x0090-0x009f]
>pnp 00:0c: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0d: [io  0x0400-0x041f]
>pnp 00:0d: [io  0x0420-0x043f]
>pnp 00:0d: [io  0x0440-0x045f]
>pnp 00:0d: [io  0x0460-0x047f]
>pnp 00:0d: [io  0x0480-0x048f]
>pnp 00:0d: [io  0xf800-0xf81f]
>pnp 00:0d: [io  0xf820-0xf83f]
>pnp 00:0d: [io  0xf840-0xf85f]
>pnp 00:0d: [io  0xf860-0xf87f]
>pnp 00:0d: [io  0xfa00-0xfa3f]
>pnp 00:0d: [io  0xfc00-0xfc7f]
>pnp 00:0d: [io  0xfc80-0xfcff]
>pnp 00:0d: [io  0xfe00-0xfe7f]
>pnp 00:0d: [io  0xfe80-0xfeff]
>pnp 00:0d: disabling [io  0xf800-0xf81f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf820-0xf83f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf840-0xf85f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: disabling [io  0xf860-0xf87f] because it overlaps 0000:00:1f.0 BAR 13 [io  0xf800-0xf87f]
>pnp 00:0d: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0e: [io  0x004e-0x004f]
>pnp 00:0e: [io  0x04d0-0x04d1]
>pnp 00:0e: [io  0x0cb0-0x0cbf]
>pnp 00:0e: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:0f: [mem 0x00000000-0x0009ffff]
>pnp 00:0f: [mem 0x00100000-0xe7ffffff]
>pnp 00:0f: [mem 0x000e4000-0x000fffff]
>pnp 00:0f: [mem 0xfec01000-0xfecfffff]
>pnp 00:0f: [mem 0xfed00400-0xfed3ffff]
>pnp 00:0f: [mem 0xfed40000-0xffffffff]
>pnp 00:0f: [mem 0xf4000000-0xf7ffffff]
>pnp 00:0f: [mem 0x000d0e00-0x000e3fff]
>pnp 00:0f: Plug and Play ACPI device, IDs PNP0c01 (active)
>pnp: PnP ACPI: found 16 devices
>ACPI: ACPI bus type pnp unregistered
>system 00:0d: [io  0x0400-0x041f] has been reserved
>system 00:0d: [io  0x0420-0x043f] has been reserved
>system 00:0d: [io  0x0440-0x045f] has been reserved
>system 00:0d: [io  0x0460-0x047f] has been reserved
>system 00:0d: [io  0x0480-0x048f] has been reserved
>system 00:0d: [io  0xfa00-0xfa3f] has been reserved
>system 00:0d: [io  0xfc00-0xfc7f] has been reserved
>system 00:0d: [io  0xfc80-0xfcff] has been reserved
>system 00:0d: [io  0xfe00-0xfe7f] has been reserved
>system 00:0d: [io  0xfe80-0xfeff] has been reserved
>system 00:0e: [io  0x04d0-0x04d1] has been reserved
>system 00:0e: [io  0x0cb0-0x0cbf] has been reserved
>system 00:0f: [mem 0x00000000-0x0009ffff] could not be reserved
>system 00:0f: [mem 0x00100000-0xe7ffffff] could not be reserved
>system 00:0f: [mem 0x000e4000-0x000fffff] could not be reserved
>system 00:0f: [mem 0xfec01000-0xfecfffff] has been reserved
>system 00:0f: [mem 0xfed00400-0xfed3ffff] has been reserved
>system 00:0f: [mem 0xfed40000-0xffffffff] could not be reserved
>system 00:0f: [mem 0xf4000000-0xf7ffffff] has been reserved
>system 00:0f: [mem 0x000d0e00-0x000e3fff] has been reserved
>PCI: max bus depth: 1 pci_try_num: 2
>pci 0000:00:1c.4: BAR 15: assigned [mem 0xf8000000-0xf80fffff pref]
>pci 0000:00:1c.5: BAR 14: assigned [mem 0xf8100000-0xf82fffff]
>pci 0000:00:1c.5: BAR 15: assigned [mem 0xf8300000-0xf84fffff 64bit pref]
>pci 0000:00:1c.5: BAR 13: assigned [io  0x3000-0x3fff]
>pci 0000:00:1c.4: BAR 13: assigned [io  0x4000-0x4fff]
>pci 0000:00:1c.0: BAR 14: assigned [mem 0xf8500000-0xf86fffff]
>pci 0000:00:1c.0: BAR 15: assigned [mem 0xf8700000-0xf88fffff 64bit pref]
>pci 0000:00:1c.0: BAR 13: assigned [io  0x5000-0x5fff]
>pci 0000:01:00.0: BAR 6: assigned [mem 0xf3080000-0xf30fffff pref]
>pci 0000:00:01.0: PCI bridge to [bus 01-01]
>pci 0000:00:01.0: PCI bridge to [bus 01-01]
>pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:00:01.0:   bridge window [mem 0xf2000000-0xf30fffff]
>pci 0000:00:01.0:   bridge window [mem 0xe8000000-0xf1ffffff 64bit pref]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0: PCI bridge to [bus 28-28]
>pci 0000:00:1c.0:   bridge window [io  0x5000-0x5fff]
>pci 0000:00:1c.0:   bridge window [mem 0xf8500000-0xf86fffff]
>pci 0000:00:1c.0:   bridge window [mem 0xf8700000-0xf88fffff 64bit pref]
>pci 0000:34:00.0: BAR 6: assigned [mem 0xf8000000-0xf800ffff pref]
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4: PCI bridge to [bus 34-34]
>pci 0000:00:1c.4:   bridge window [io  0x4000-0x4fff]
>pci 0000:00:1c.4:   bridge window [mem 0xf3100000-0xf31fffff]
>pci 0000:00:1c.4:   bridge window [mem 0xf8000000-0xf80fffff pref]
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5: PCI bridge to [bus 3f-3f]
>pci 0000:00:1c.5:   bridge window [io  0x3000-0x3fff]
>pci 0000:00:1c.5:   bridge window [mem 0xf8100000-0xf82fffff]
>pci 0000:00:1c.5:   bridge window [mem 0xf8300000-0xf84fffff 64bit pref]
>pci 0000:00:1e.0: PCI bridge to [bus 10-10]
>pci 0000:00:1e.0: PCI bridge to [bus 10-10]
>pci 0000:00:1e.0:   bridge window [io  disabled]
>pci 0000:00:1e.0:   bridge window [mem 0xf3300000-0xf33fffff]
>pci 0000:00:1e.0:   bridge window [mem pref disabled]
>  alloc irq_desc for 16 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:01.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>pci 0000:00:01.0: setting latency timer to 64
>pci 0000:00:1c.0: setting latency timer to 64
>  alloc irq_desc for 20 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:1c.4: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>pci 0000:00:1c.4: setting latency timer to 64
>  alloc irq_desc for 21 on node -1
>  alloc kstat_irqs on node -1
>pci 0000:00:1c.5: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>pci 0000:00:1c.5: setting latency timer to 64
>pci 0000:00:1e.0: setting latency timer to 64
>pci_bus 0000:00: resource 4 [mem 0xf8000000-0xfebfffff]
>pci_bus 0000:00: resource 5 [io  0x0000-0x0cf7]
>pci_bus 0000:00: resource 6 [io  0x1000-0x2fff]
>pci_bus 0000:00: resource 7 [io  0x3000-0x6fff]
>pci_bus 0000:00: resource 8 [io  0x7000-0xafff]
>pci_bus 0000:00: resource 9 [io  0xb000-0xffff]
>pci_bus 0000:00: resource 10 [mem 0x000a0000-0x000bffff]
>pci_bus 0000:00: resource 11 [mem 0xe8000000-0xf3ffffff]
>pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>pci_bus 0000:01: resource 1 [mem 0xf2000000-0xf30fffff]
>pci_bus 0000:01: resource 2 [mem 0xe8000000-0xf1ffffff 64bit pref]
>pci_bus 0000:28: resource 0 [io  0x5000-0x5fff]
>pci_bus 0000:28: resource 1 [mem 0xf8500000-0xf86fffff]
>pci_bus 0000:28: resource 2 [mem 0xf8700000-0xf88fffff 64bit pref]
>pci_bus 0000:34: resource 0 [io  0x4000-0x4fff]
>pci_bus 0000:34: resource 1 [mem 0xf3100000-0xf31fffff]
>pci_bus 0000:34: resource 2 [mem 0xf8000000-0xf80fffff pref]
>pci_bus 0000:3f: resource 0 [io  0x3000-0x3fff]
>pci_bus 0000:3f: resource 1 [mem 0xf8100000-0xf82fffff]
>pci_bus 0000:3f: resource 2 [mem 0xf8300000-0xf84fffff 64bit pref]
>pci_bus 0000:10: resource 1 [mem 0xf3300000-0xf33fffff]
>pci_bus 0000:10: resource 4 [mem 0xf8000000-0xfebfffff]
>pci_bus 0000:10: resource 5 [io  0x0000-0x0cf7]
>pci_bus 0000:10: resource 6 [io  0x1000-0x2fff]
>pci_bus 0000:10: resource 7 [io  0x3000-0x6fff]
>pci_bus 0000:10: resource 8 [io  0x7000-0xafff]
>pci_bus 0000:10: resource 9 [io  0xb000-0xffff]
>pci_bus 0000:10: resource 10 [mem 0x000a0000-0x000bffff]
>pci_bus 0000:10: resource 11 [mem 0xe8000000-0xf3ffffff]
>NET: Registered protocol family 2
>IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
>TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
>TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>TCP: Hash tables configured (established 524288 bind 65536)
>TCP reno registered
>NET: Registered protocol family 1
>pci 0000:01:00.0: Boot video device
>Trying to unpack rootfs image as initramfs...
>Freeing initrd memory: 15831k freed
>audit: initializing netlink socket (disabled)
>type=2000 audit(1334837938.358:1): initialized
>HugeTLB registered 2 MB page size, pre-allocated 0 pages
>VFS: Disk quotas dquot_6.5.2
>Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>msgmni has been set to 7589
>SELinux:  Registering netfilter hooks
>alg: No test for stdrng (krng)
>ksign: Installing public key data
>Loading keyring
>- Added public key 25D5FD8BBDE42C2F
>- User ID: Red Hat, Inc. (Kernel Module GPG key)
>- Added public key D4A26C9CCD09BEDA
>- User ID: Red Hat Enterprise Linux Driver Update Program <secalert@redhat.com>
>Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
>io scheduler noop registered
>io scheduler anticipatory registered
>io scheduler deadline registered
>io scheduler cfq registered (default)
>pcieport 0000:00:01.0: setting latency timer to 64
>  alloc irq_desc for 24 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:01.0: irq 24 for MSI/MSI-X
>pcieport 0000:00:1c.0: setting latency timer to 64
>  alloc irq_desc for 25 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.0: irq 25 for MSI/MSI-X
>pcieport 0000:00:1c.4: setting latency timer to 64
>  alloc irq_desc for 26 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.4: irq 26 for MSI/MSI-X
>pcieport 0000:00:1c.5: setting latency timer to 64
>  alloc irq_desc for 27 on node -1
>  alloc kstat_irqs on node -1
>pcieport 0000:00:1c.5: irq 27 for MSI/MSI-X
>pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>pciehp: PCI Express Hot Plug Controller Driver version: 0.4
>acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>intel_idle: MWAIT substates: 0x22220
>intel_idle: does not run on family 6 model 23
>input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
>ACPI: Power Button [PBTN]
>input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
>ACPI: Power Button [PWRF]
>ACPI: acpi_idle registered with cpuidle
>ACPI: SSDT 00000000e6fcd361 003AC (v01 COMPAQ  CPU_TM2 00000001 MSFT 0100000E)
>ACPI: SSDT 00000000e6fcd1e5 0017C (v01 COMPAQ      CST 00000001 MSFT 0100000E)
>Marking TSC unstable due to TSC halts in idle
>ERST: Table is not found!
>GHES: HEST is not enabled!
>Non-volatile memory driver v1.3
>Linux agpgart interface v0.103
>crash memory driver: version 1.1
>Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
>00:08: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
>brd: module loaded
>loop: module loaded
>input: Macintosh mouse button emulation as /devices/virtual/input/input2
>Fixed MDIO Bus: probed
>ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>  alloc irq_desc for 22 on node -1
>  alloc kstat_irqs on node -1
>ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>ehci_hcd 0000:00:1a.7: setting latency timer to 64
>ehci_hcd 0000:00:1a.7: EHCI Host Controller
>ehci_hcd 0000:00:1a.7: new USB bus registered, assigned bus number 1
>ehci_hcd 0000:00:1a.7: debug port 1
>ehci_hcd 0000:00:1a.7: cache line size of 64 is not supported
>ehci_hcd 0000:00:1a.7: irq 22, io mem 0xf3204800
>ehci_hcd 0000:00:1a.7: USB 2.0 started, EHCI 1.00
>usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb1: Product: EHCI Host Controller
>usb usb1: Manufacturer: Linux 2.6.32-262.el6.x86_64 ehci_hcd
>usb usb1: SerialNumber: 0000:00:1a.7
>usb usb1: configuration #1 chosen from 1 choice
>hub 1-0:1.0: USB hub found
>hub 1-0:1.0: 6 ports detected
>ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>ehci_hcd 0000:00:1d.7: setting latency timer to 64
>ehci_hcd 0000:00:1d.7: EHCI Host Controller
>ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 2
>ehci_hcd 0000:00:1d.7: debug port 1
>ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
>ehci_hcd 0000:00:1d.7: irq 20, io mem 0xf3204c00
>ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
>usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
>usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb2: Product: EHCI Host Controller
>usb usb2: Manufacturer: Linux 2.6.32-262.el6.x86_64 ehci_hcd
>usb usb2: SerialNumber: 0000:00:1d.7
>usb usb2: configuration #1 chosen from 1 choice
>hub 2-0:1.0: USB hub found
>hub 2-0:1.0: 6 ports detected
>ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>uhci_hcd: USB Universal Host Controller Interface driver
>uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1a.0: setting latency timer to 64
>uhci_hcd 0000:00:1a.0: UHCI Host Controller
>uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3
>uhci_hcd 0000:00:1a.0: irq 20, io base 0x00002100
>usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb3: Product: UHCI Host Controller
>usb usb3: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb3: SerialNumber: 0000:00:1a.0
>usb usb3: configuration #1 chosen from 1 choice
>hub 3-0:1.0: USB hub found
>hub 3-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1a.1: setting latency timer to 64
>uhci_hcd 0000:00:1a.1: UHCI Host Controller
>uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
>uhci_hcd 0000:00:1a.1: irq 21, io base 0x00002120
>usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb4: Product: UHCI Host Controller
>usb usb4: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb4: SerialNumber: 0000:00:1a.1
>usb usb4: configuration #1 chosen from 1 choice
>hub 4-0:1.0: USB hub found
>hub 4-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1a.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1a.2: setting latency timer to 64
>uhci_hcd 0000:00:1a.2: UHCI Host Controller
>uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5
>uhci_hcd 0000:00:1a.2: irq 22, io base 0x00002140
>usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb5: Product: UHCI Host Controller
>usb usb5: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb5: SerialNumber: 0000:00:1a.2
>usb usb5: configuration #1 chosen from 1 choice
>hub 5-0:1.0: USB hub found
>hub 5-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1d.0: setting latency timer to 64
>uhci_hcd 0000:00:1d.0: UHCI Host Controller
>uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6
>uhci_hcd 0000:00:1d.0: irq 20, io base 0x00002160
>usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb6: Product: UHCI Host Controller
>usb usb6: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb6: SerialNumber: 0000:00:1d.0
>usb usb6: configuration #1 chosen from 1 choice
>hub 6-0:1.0: USB hub found
>hub 6-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1d.1: setting latency timer to 64
>uhci_hcd 0000:00:1d.1: UHCI Host Controller
>uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7
>uhci_hcd 0000:00:1d.1: irq 21, io base 0x00002180
>usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb7: Product: UHCI Host Controller
>usb usb7: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb7: SerialNumber: 0000:00:1d.1
>usb usb7: configuration #1 chosen from 1 choice
>hub 7-0:1.0: USB hub found
>hub 7-0:1.0: 2 ports detected
>uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1d.2: setting latency timer to 64
>uhci_hcd 0000:00:1d.2: UHCI Host Controller
>uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8
>uhci_hcd 0000:00:1d.2: irq 22, io base 0x000021a0
>usb usb8: New USB device found, idVendor=1d6b, idProduct=0001
>usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>usb usb8: Product: UHCI Host Controller
>usb usb8: Manufacturer: Linux 2.6.32-262.el6.x86_64 uhci_hcd
>usb usb8: SerialNumber: 0000:00:1d.2
>usb usb8: configuration #1 chosen from 1 choice
>hub 8-0:1.0: USB hub found
>hub 8-0:1.0: 2 ports detected
>PNP: PS/2 Controller [PNP0303:KBD,PNP0f0e:PS2M] at 0x60,0x64 irq 1,12
>serio: i8042 KBD port at 0x60,0x64 irq 1
>serio: i8042 AUX port at 0x60,0x64 irq 12
>mice: PS/2 mouse device common for all mice
>rtc_cmos 00:03: RTC can wake from S4
>rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
>rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
>cpuidle: using governor ladder
>cpuidle: using governor menu
>EFI Variables Facility v0.08 2004-May-17
>usbcore: registered new interface driver hiddev
>usbcore: registered new interface driver usbhid
>usbhid: v2.6:USB HID core driver
>TCP cubic registered
>Initializing XFRM netlink socket
>NET: Registered protocol family 17
>registered taskstats version 1
>rtc_cmos 00:03: setting system clock to 2012-04-19 12:18:59 UTC (1334837939)
>Initalizing network drop monitor service
>Freeing unused kernel memory: 1260k freed
>Write protecting the kernel read-only data: 10240k
>Freeing unused kernel memory: 984k freed
>Freeing unused kernel memory: 1736k freed
>dracut: dracut-004-281.el6
>dracut: rd_NO_LUKS: removing cryptoluks activation
>input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
>dracut: rd_NO_LVM: removing LVM activation
>device-mapper: uevent: version 1.0.3
>device-mapper: ioctl: 4.22.6-ioctl (2011-10-19) initialised: dm-devel@redhat.com
>udev: starting version 147
>ACPI: WMI: Mapper loaded
>[drm] Initialized drm 1.1.0 20060810
>VGA switcheroo: detected Optimus DSM method \ handle
>nouveau 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>nouveau 0000:01:00.0: setting latency timer to 64
>[drm] nouveau 0000:01:00.0: nouveau_load:1008 - vendor: 0x10DE device: 0xA38 class: 0x30000
>[drm] nouveau 0000:01:00.0: nouveau_load:1025 - regs mapped ok at 0xf2000000
>[drm] nouveau 0000:01:00.0: Detected an NV50 generation card (0x0a5c00a2)
>[drm] nouveau 0000:01:00.0: nouveau_load:1098 - crystal freq: 27000KHz
>[drm] nouveau 0000:01:00.0: Attempting to load BIOS image from PRAMIN
>[drm] nouveau 0000:01:00.0: ... appears to be valid
>[drm] nouveau 0000:01:00.0: BIT BIOS found
>[drm] nouveau 0000:01:00.0: Bios version 70.16.71.00
>[drm] nouveau 0000:01:00.0: Pointer to BIT loadval table invalid
>[drm] nouveau 0000:01:00.0: TMDS table version 2.0
>[drm] nouveau 0000:01:00.0: MXM: no VBIOS data, nothing to do
>[drm] nouveau 0000:01:00.0: DCB version 4.0
>[drm] nouveau 0000:01:00.0: DCB outp 00: 02000380 00000000
>[drm] nouveau 0000:01:00.0: DCB outp 01: 08000382 00020030
>[drm] nouveau 0000:01:00.0: DCB outp 02: 028213a6 0f220010
>[drm] nouveau 0000:01:00.0: DCB outp 03: 02021362 00020010
>[drm] nouveau 0000:01:00.0: DCB conn 00: 00002030
>[drm] nouveau 0000:01:00.0: DCB conn 01: 00101146
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 0 at offset 0x6EA7
>[drm] nouveau 0000:01:00.0: 0x6EA7: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x6EA7: [ (0x8C) - INIT_8C ]
>[drm] nouveau 0000:01:00.0: 0x6EA8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EA8: Reg: 0x00022210, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6EB5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6EBE: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EBE: Repeating following segment 20 times
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6ECE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6ECE: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001084, Data: 0x00011469
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001084, Data: 0x00011C69
>[drm] nouveau 0000:01:00.0: 0x6EDB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7030003
>[drm] nouveau 0000:01:00.0: 0x6EE4: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6EE4: Condition: 0x10
>[drm] nouveau 0000:01:00.0: 0x6EE4: Cond: 0x10, Reg: 0x00021148, Mask: 0x000000FF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021148, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EE4: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EE4: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x6EE6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EE6: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x6EF3: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6EF4: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6EF4: Condition: 0x11
>[drm] nouveau 0000:01:00.0: 0x6EF4: Cond: 0x11, Reg: 0x00021144, Mask: 0x00000FFF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021144, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EF4: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EF4: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x6EF6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EF6: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x6F03: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6F04: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F04: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x6F11: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F11: Reg: 0x0000C040, Mask: 0xCFFFEFFF, Data: 0x20001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000C040, Data: 0x20001000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000C040, Data: 0x20001000
>[drm] nouveau 0000:01:00.0: 0x6F1E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 0x6F27: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F27: Reg: 0x00022210, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6F34: [ (0x8D) - INIT_8D ]
>[drm] nouveau 0000:01:00.0: 0x6F35: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x6F35: Executing subroutine at 0x6D6A
>[drm] nouveau 0000:01:00.0: 0x6D6A: [ (0x69) - INIT_IO ]
>[drm] nouveau 0000:01:00.0: 0x6D6A: Port: 0x03C3, Mask: 0x00, Data: 0x01
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614100, Data: 0x10000700
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x00800700
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x00800100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0x9FF3F113
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x00800018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x00800018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614108, Data: 0x0000F000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614108, Data: 0x0000F000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D6F: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x3F, Head: 0x00, Data: 0x57
>[drm] nouveau 0000:01:00.0: 0x6D72: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D72: Reg: 0x00614200, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:01:00.0: 0x6D7F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D7F: Reg: 0x00614A00, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6D8C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D8C: Reg: 0x00614280, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6D99: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D99: Reg: 0x00614A80, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DA6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DA6: Reg: 0x00615280, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DB3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DB3: Reg: 0x00614300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DC0: Reg: 0x00614B00, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DCD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DCD: Reg: 0x00615300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DDA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DDA: Reg: 0x00614380, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DE7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DE7: Reg: 0x00614B80, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DF4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DF4: Reg: 0x00615380, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6E01: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x6F35: End of 0x6D6A subroutine
>[drm] nouveau 0000:01:00.0: 0x6F38: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F38: Reg: 0x0000E108, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444F
>[drm] nouveau 0000:01:00.0: 0x6F45: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F45: Reg: 0x0000E300, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 0x6F52: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6F52: BaseReg: 0x00020480, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020480, Data: 0x0000006D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020484, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6F60: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204C0, Data: 0x00000068
>[drm] nouveau 0000:01:00.0: 0x6F69: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204D8, Data: 0x00000069
>[drm] nouveau 0000:01:00.0: 0x6F72: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204E0, Data: 0x00000066
>[drm] nouveau 0000:01:00.0: 0x6F7B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002041C, Data: 0x00000055
>[drm] nouveau 0000:01:00.0: 0x6F84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6F84: BaseReg: 0x0002010C, Count: 0x06
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002010C, Data: 0x00000049
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020110, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020114, Data: 0x00B46600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020118, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002011C, Data: 0x00765481
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020120, Data: 0x00000241
>[drm] nouveau 0000:01:00.0: 0x6FA2: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6FA2: BaseReg: 0x00020074, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020074, Data: 0x00000014
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020078, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FB0: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6FB0: BaseReg: 0x00020094, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020094, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020098, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FBE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6FBE: Reg: 0x0000E1F4, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:01:00.0: 0x6FCB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002004C, Data: 0x4407220B
>[drm] nouveau 0000:01:00.0: 0x6FD4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020424, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FDD: [ (0x8E) - INIT_GPIO ]
>[drm] nouveau 0000:01:00.0: 0x6FDE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E114, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6FE7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E118, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FF0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E11C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6FF9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7002: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7002: Reg: 0x0000E100, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E100, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 0x700F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020004, Data: 0x00100028
>[drm] nouveau 0000:01:00.0: 0x7018: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7018: Reg: 0x0008818C, Mask: 0x0FFFFFFE, Data: 0xE0000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008818C, Data: 0xE0000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008818C, Data: 0xE0000001
>[drm] nouveau 0000:01:00.0: 0x7025: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x7025: Condition: 0x13
>[drm] nouveau 0000:01:00.0: 0x7025: Cond: 0x13, Reg: 0x00101000, Mask: 0x001C0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7025: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7025: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x7027: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089014, Data: 0x0000E020
>[drm] nouveau 0000:01:00.0: 0x7030: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089018, Data: 0x2140ED20
>[drm] nouveau 0000:01:00.0: 0x7039: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:01:00.0: 0x7039: ------ Skipping following commands  ------
>[drm] nouveau 0000:01:00.0: 0x703A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x7043: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x704C: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x704C: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x704D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x704D: Reg: 0x00004B28, Mask: 0xFFF07FFF, Data: 0x00088000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004B28, Data: 0x0008A927
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004B28, Data: 0x0008A927
>[drm] nouveau 0000:01:00.0: 0x705A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x705A: Reg: 0x0008907C, Mask: 0xFFFF0000, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008907C, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008907C, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 0x7067: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008848C, Data: 0x0118008C
>[drm] nouveau 0000:01:00.0: 0x7070: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7070: Reg: 0x0008A088, Mask: 0xFFFFFFFC, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008A088, Data: 0x11010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008A088, Data: 0x1101000B
>[drm] nouveau 0000:01:00.0: 0x707D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089008, Data: 0x00004810
>[drm] nouveau 0000:01:00.0: 0x7086: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7086: Reg: 0x00088610, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088610, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088610, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 0x7093: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7093: Reg: 0x00001530, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001530, Data: 0x800492F0
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001530, Data: 0x800492F0
>[drm] nouveau 0000:01:00.0: 0x70A0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009220, Data: 0x00000412
>[drm] nouveau 0000:01:00.0: 0x70A9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009200, Data: 0x00000804
>[drm] nouveau 0000:01:00.0: 0x70B2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009210, Data: 0x00000271
>[drm] nouveau 0000:01:00.0: 0x70BB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70BB: Reg: 0x00101000, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x70C8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70C8: Reg: 0x0010100C, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0010100C, Data: 0x8001B010
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010100C, Data: 0x8001B010
>[drm] nouveau 0000:01:00.0: 0x70D5: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x70D5: Condition: 0x16
>[drm] nouveau 0000:01:00.0: 0x70D5: Cond: 0x16, Reg: 0x00101000, Mask: 0x0000003C
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x70D5: Checking if 0x00000028 equals 0x0000001C
>[drm] nouveau 0000:01:00.0: 0x70D5: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x70D7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70E4: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x70E4: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x70E5: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x70E5: Executing subroutine at 0x6E02
>[drm] nouveau 0000:01:00.0: 0x6E02: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:01:00.0: 0x6E02: Reg: 0x00101000, Shift: 0x18, SrcMask: 0x0F, Port: 0x03D4, Index: 0x8B, Mask: 0xF0
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000040
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x0F
>[drm] nouveau 0000:01:00.0: 0x6E0D: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E0D: SrcReg: 0x00614004, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x00610184, DstMask: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614004, Data: 0x7F304777
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00610184, Data: 0x7F304777
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00610184, Data: 0x7F304777
>[drm] nouveau 0000:01:00.0: 0x6E23: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619F00, Data: 0x00000009
>[drm] nouveau 0000:01:00.0: 0x6E2C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x70E5: End of 0x6E02 subroutine
>[drm] nouveau 0000:01:00.0: 0x70E8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 0x70F1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70F1: Reg: 0x0000E820, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x70FE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70FE: Reg: 0x0000E8A0, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x710B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x710B: Reg: 0x00004220, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 0x7118: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7118: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:01:00.0: 0x711B: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x711B: Condition: 0x06, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x711B: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x711B: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711B: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x711B: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x711B: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711E: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x711F: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x711F: Condition: 0x08, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x711F: Cond: 0x08, Reg: 0x0000E8A0, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x711F: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711F: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x711F: Cond: 0x08, Reg: 0x0000E8A0, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x711F: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x7122: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7123: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7123: Reg: 0x0000E820, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010005
>[drm] nouveau 0000:01:00.0: 0x7130: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7130: Reg: 0x0000E8A0, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010005
>[drm] nouveau 0000:01:00.0: 0x713D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x713D: Reg: 0x0000E830, Mask: 0x80000000, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E830, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E830, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 0x714A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x714A: Reg: 0x0000E8B0, Mask: 0x80000000, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8B0, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8B0, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 0x7157: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004700, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x7160: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 0x7169: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7169: Condition: 0x07, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x7169: Cond: 0x07, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x7169: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7169: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:01:00.0: 0x7169: Cond: 0x07, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x7169: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7169: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:01:00.0: 0x716C: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x716C: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x716D: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x716D: Condition: 0x09, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x716D: Cond: 0x09, Reg: 0x0000E8A0, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x716D: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x716D: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:01:00.0: 0x716D: Cond: 0x09, Reg: 0x0000E8A0, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x716D: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x716D: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:01:00.0: 0x7170: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7170: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x7171: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7171: Reg: 0x0000E820, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x717E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x717E: Reg: 0x0000E8A0, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x718B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x718B: Reg: 0x0000E820, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x7198: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7198: Reg: 0x0000E8A0, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010015
>[drm] nouveau 0000:01:00.0: 0x71A5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71A5: Reg: 0x0000E82C, Mask: 0xFFFFFFF7, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71B2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71B2: Reg: 0x0000E830, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E830, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E830, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 0x71BF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71BF: Reg: 0x0000E82C, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71CC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71CC: Reg: 0x0000E8AC, Mask: 0xFFFFFFF7, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8AC, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8AC, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71D9: Reg: 0x0000E8B0, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8B0, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8B0, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 0x71E6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71E6: Reg: 0x0000E8AC, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8AC, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8AC, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71F3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004198, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 0x71FC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004190, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 0x7205: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7205: Executing subroutine at 0x6E40
>[drm] nouveau 0000:01:00.0: 0x6E40: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A0, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x6E49: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7205: End of 0x6E40 subroutine
>[drm] nouveau 0000:01:00.0: 0x7208: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00020131
>[drm] nouveau 0000:01:00.0: 0x7211: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004160, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x721A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004168, Data: 0x00080121
>[drm] nouveau 0000:01:00.0: 0x7223: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7223: Executing subroutine at 0x6E4A
>[drm] nouveau 0000:01:00.0: 0x6E4A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004180, Data: 0x00002140
>[drm] nouveau 0000:01:00.0: 0x6E53: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004184, Data: 0x00002140
>[drm] nouveau 0000:01:00.0: 0x6E5C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7223: End of 0x6E4A subroutine
>[drm] nouveau 0000:01:00.0: 0x7226: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A4, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x722F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041B4, Data: 0x000E0131
>[drm] nouveau 0000:01:00.0: 0x7238: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7238: Executing subroutine at 0x6E5D
>[drm] nouveau 0000:01:00.0: 0x6E5D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041BC, Data: 0x001C0141
>[drm] nouveau 0000:01:00.0: 0x6E66: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7238: End of 0x6E5D subroutine
>[drm] nouveau 0000:01:00.0: 0x723B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x723B: Reg: 0x00004198, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004198, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004198, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 0x7248: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7248: Reg: 0x00004190, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004190, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004190, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 0x7255: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7255: Executing subroutine at 0x6E67
>[drm] nouveau 0000:01:00.0: 0x6E67: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E67: Reg: 0x000041A0, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041A0, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A0, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x6E74: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7255: End of 0x6E67 subroutine
>[drm] nouveau 0000:01:00.0: 0x7258: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7258: Reg: 0x00004164, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004164, Data: 0x00023030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00023130
>[drm] nouveau 0000:01:00.0: 0x7265: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7265: Reg: 0x00004160, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004160, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004160, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x7272: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7272: Reg: 0x00004168, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004168, Data: 0x00083121
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004168, Data: 0x00083121
>[drm] nouveau 0000:01:00.0: 0x727F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x727F: Reg: 0x000041A4, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041A4, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A4, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x728C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x728C: Reg: 0x000041B4, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041B4, Data: 0x000E3131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041B4, Data: 0x000E3131
>[drm] nouveau 0000:01:00.0: 0x7299: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010A020, Data: 0x00031704
>[drm] nouveau 0000:01:00.0: 0x72A2: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72A2: Executing subroutine at 0x6E75
>[drm] nouveau 0000:01:00.0: 0x6E75: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E75: Reg: 0x000041BC, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041BC, Data: 0x001C2141
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041BC, Data: 0x001C2141
>[drm] nouveau 0000:01:00.0: 0x6E82: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72A2: End of 0x6E75 subroutine
>[drm] nouveau 0000:01:00.0: 0x72A5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72A5: Reg: 0x00004200, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:01:00.0: 0x72B2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72B2: Reg: 0x00004220, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x0001001D
>[drm] nouveau 0000:01:00.0: 0x72BF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72BF: Reg: 0x00004000, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004000, Data: 0x18010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004000, Data: 0x18010008
>[drm] nouveau 0000:01:00.0: 0x72CC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004120, Data: 0x00063031
>[drm] nouveau 0000:01:00.0: 0x72D5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004124, Data: 0x00063031
>[drm] nouveau 0000:01:00.0: 0x72DE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004128, Data: 0x00063020
>[drm] nouveau 0000:01:00.0: 0x72E7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004140, Data: 0x001C0100
>[drm] nouveau 0000:01:00.0: 0x72F0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004144, Data: 0x001C0100
>[drm] nouveau 0000:01:00.0: 0x72F9: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72F9: Executing subroutine at 0x6E2D
>[drm] nouveau 0000:01:00.0: 0x6E2D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 0x6E36: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 0x6E3F: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72F9: End of 0x6E2D subroutine
>[drm] nouveau 0000:01:00.0: 0x72FC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72FC: Executing subroutine at 0x7312
>[drm] nouveau 0000:01:00.0: 0x7312: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7313: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7313: Reg: 0x00004124, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004124, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004124, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x7320: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004224, Data: 0x00021405
>[drm] nouveau 0000:01:00.0: 0x7329: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7329: Reg: 0x00004220, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010005
>[drm] nouveau 0000:01:00.0: 0x7336: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7336: Condition: 0x14, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x7336: Cond: 0x14, Reg: 0x00004220, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 0x7336: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7336: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:01:00.0: 0x7336: Cond: 0x14, Reg: 0x00004220, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 0x7336: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7336: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:01:00.0: 0x7339: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7339: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x733A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x733A: Reg: 0x00004220, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 0x7347: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7347: Reg: 0x00004220, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010015
>[drm] nouveau 0000:01:00.0: 0x7354: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7354: Reg: 0x00004164, Mask: 0xFFFFFEFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004164, Data: 0x00023030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00023030
>[drm] nouveau 0000:01:00.0: 0x7361: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7362: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72FC: End of 0x7312 subroutine
>[drm] nouveau 0000:01:00.0: 0x72FF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000C044, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7308: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001538, Data: 0x00011111
>[drm] nouveau 0000:01:00.0: 0x7311: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 1 at offset 0x7363
>[drm] nouveau 0000:01:00.0: 0x7363: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x7363: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7363: Reg: 0x00100710, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x738A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x738A: Reg: 0x00100718, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100718, Data: 0x40055F77
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010071C, Data: 0x40044F77
>[drm] nouveau 0000:01:00.0: 0x73D1: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x73D1: Reg: 0x00100720, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100720, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100724, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 0x7418: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7418: Reg: 0x001111E0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001111E0, Data: 0x02000101
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001111E4, Data: 0x02000101
>[drm] nouveau 0000:01:00.0: 0x745F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x745F: Reg: 0x00111120, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111120, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111124, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x74A6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x74A6: Reg: 0x00111380, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111380, Data: 0x80000606
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111384, Data: 0x80000606
>[drm] nouveau 0000:01:00.0: 0x74ED: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x74ED: Reg: 0x001008A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008A0, Data: 0x8700580A
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008A4, Data: 0x8700580A
>[drm] nouveau 0000:01:00.0: 0x7534: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7534: Reg: 0x00111180, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111180, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111184, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 0x757B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x757B: Reg: 0x00111000, RegIncrement: 0x08, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111000, Data: 0x70077007
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111008, Data: 0x70077007
>[drm] nouveau 0000:01:00.0: 0x75C2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x75C2: Reg: 0x00110560, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110560, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105C0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110620, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110680, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106E0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110740, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110800, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x76C9: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x76C9: Reg: 0x00110564, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110564, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105C4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110624, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110684, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106E4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110744, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107A4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110804, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x77D0: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x77D0: Reg: 0x001105A0, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105A0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110600, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110660, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106C0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110720, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110780, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107E0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110840, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 0x78D7: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x78D7: Reg: 0x001105A4, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105A4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110604, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110664, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106C4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110724, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110784, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107E4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110844, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 0x79DE: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x79DE: Reg: 0x00100D80, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100D80, Data: 0xAAAAAAAA
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100D84, Data: 0xAAAAAAAA
>[drm] nouveau 0000:01:00.0: 0x7A25: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7A25: Reg: 0x001009E4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7A4C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7A4C: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7A73: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x7A73: BaseReg: 0x00100920, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100920, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100924, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 0x7A81: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x7A81: BaseReg: 0x00100900, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100900, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100904, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 0x7A8F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7A8F: Reg: 0x00100940, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100940, Data: 0x90900000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100944, Data: 0x90900000
>[drm] nouveau 0000:01:00.0: 0x7AD6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7AD6: Reg: 0x00100A20, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A20, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A24, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7B1D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7B1D: Reg: 0x00100A40, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A40, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A44, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7B64: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7B64: Reg: 0x00100A60, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A60, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A64, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7BAB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7BAB: Reg: 0x00100A80, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A80, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A84, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7BF2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7BF2: Reg: 0x00100AA0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AA0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AA4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7C39: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7C39: Reg: 0x00100AC0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AC0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AC4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7C80: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7C80: Reg: 0x00111400, RegIncrement: 0x20, Count: 0x06, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111400, Data: 0x000F0F00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111420, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111440, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111460, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111480, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001114A0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7D47: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7D47: Reg: 0x00111404, RegIncrement: 0x20, Count: 0x06, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111404, Data: 0x000F0F00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111424, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111444, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111464, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111484, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001114A4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7E0E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7E0E: Reg: 0x00100DC0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DC0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DC4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7E55: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7E55: Reg: 0x001005A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001005A0, Data: 0x00918989
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001005A4, Data: 0x00001010
>[drm] nouveau 0000:01:00.0: 0x7E9C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7E9C: Reg: 0x0010F804, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010F804, Data: 0x80000005
>[drm] nouveau 0000:01:00.0: 0x7EC3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7EC3: Reg: 0x0010053C, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010053C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7EEA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7EEA: Reg: 0x00100760, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100760, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100764, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 0x7F31: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7F31: Reg: 0x00100780, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100780, Data: 0x27777774
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100784, Data: 0x27777774
>[drm] nouveau 0000:01:00.0: 0x7F78: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7F78: Reg: 0x001007A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007A0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007A4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7FBF: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7FBF: Reg: 0x001007C0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007C0, Data: 0x55555555
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007C4, Data: 0x55555555
>[drm] nouveau 0000:01:00.0: 0x8006: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8006: Reg: 0x001007E0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007E0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x804D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x804D: Reg: 0x00100800, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100800, Data: 0xDDDDDDDD
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100804, Data: 0xDDDDDDDD
>[drm] nouveau 0000:01:00.0: 0x8094: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8094: Reg: 0x00100820, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100820, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100824, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x80DB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x80DB: Reg: 0x00100840, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100840, Data: 0xBCCBCBBB
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100844, Data: 0xBCCBCBBB
>[drm] nouveau 0000:01:00.0: 0x8122: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8122: Reg: 0x00100860, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100860, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100864, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 0x8169: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8169: Reg: 0x00100880, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100880, Data: 0x98986997
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100884, Data: 0x98986997
>[drm] nouveau 0000:01:00.0: 0x81B0: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x81B0: Reg: 0x00100714, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100714, Data: 0xF0000001
>[drm] nouveau 0000:01:00.0: 0x81D7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100700, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x81E0: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x81E0: BaseReg: 0x00100740, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100740, Data: 0x07000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100744, Data: 0x07000000
>[drm] nouveau 0000:01:00.0: 0x81EE: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x81EE: BaseReg: 0x00100DA0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DA0, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DA4, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 0x81FC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x81FC: Reg: 0x00111104, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111104, Data: 0x000009FF
>[drm] nouveau 0000:01:00.0: 0x8223: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x8223: BaseReg: 0x001110C0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110C0, Data: 0x00001801
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110C4, Data: 0x00001801
>[drm] nouveau 0000:01:00.0: 0x8231: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x8231: BaseReg: 0x001110E0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110E0, Data: 0x80099000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110E4, Data: 0x80099000
>[drm] nouveau 0000:01:00.0: 0x823F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x823F: Reg: 0x00111100, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111100, Data: 0x08000004
>[drm] nouveau 0000:01:00.0: 0x8266: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010024C, Data: 0x0F000080
>[drm] nouveau 0000:01:00.0: 0x826F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x826F: Reg: 0x00100254, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100254, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8296: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8296: Reg: 0x00100500, Mask: 0xFFF0FF01, Data: 0x000A00FE
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100500, Data: 0x003A16FF
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100500, Data: 0x003A16FF
>[drm] nouveau 0000:01:00.0: 0x82A3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x82A3: Reg: 0x00100220, RegIncrement: 0x04, Count: 0x0B, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100220, Data: 0x050C2411
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100224, Data: 0x0C030A06
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100228, Data: 0x04040505
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010022C, Data: 0x362D1105
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100230, Data: 0x0F030A0A
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100234, Data: 0x24050B05
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100238, Data: 0x00600551
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010023C, Data: 0x0F120202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100240, Data: 0x111D0700
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100244, Data: 0x00000347
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100248, Data: 0x0200270C
>[drm] nouveau 0000:01:00.0: 0x840A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x840A: Reg: 0x00100258, RegIncrement: 0x08, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100258, Data: 0x00400200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100260, Data: 0x00C35000
>[drm] nouveau 0000:01:00.0: 0x8451: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8451: Reg: 0x00100268, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100268, Data: 0x30030200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100268, Data: 0x30030200
>[drm] nouveau 0000:01:00.0: 0x845E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x845E: Reg: 0x00100200, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x8485: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8485: Reg: 0x00100204, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100204, Data: 0x0155A020
>[drm] nouveau 0000:01:00.0: 0x84AC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x84AC: Reg: 0x00100250, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100250, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x84D3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000122C, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 0x84DC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84DC: Reg: 0x001008CC, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008CC, Data: 0x04000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008CC, Data: 0x04000009
>[drm] nouveau 0000:01:00.0: 0x84E9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84E9: Reg: 0x001008E0, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800C100F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008E0, Data: 0x000C100F
>[drm] nouveau 0000:01:00.0: 0x84F6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84F6: Reg: 0x001008CC, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008CC, Data: 0x04000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008CC, Data: 0x04000009
>[drm] nouveau 0000:01:00.0: 0x8503: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8503: Condition: 0x0C, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x8503: Cond: 0x0C, Reg: 0x001008E0, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800C100F
>[drm] nouveau 0000:01:00.0: 0x8503: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x8503: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x8503: Cond: 0x0C, Reg: 0x001008E0, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800C100F
>[drm] nouveau 0000:01:00.0: 0x8503: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x8506: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8507: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AE0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8510: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AE8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8519: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8522: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8522: Sleeping for 0x0FA0 microseconds
>[drm] nouveau 0000:01:00.0: 0x8525: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x8525: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8527: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 0x8530: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8530: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:01:00.0: 0x8533: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010021C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x853C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000100
>[drm] nouveau 0000:01:00.0: 0x8545: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8545: Sleeping for 0x01F4 microseconds
>[drm] nouveau 0000:01:00.0: 0x8548: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100080, Data: 0x00000020
>[drm] nouveau 0000:01:00.0: 0x8551: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100440, Data: 0x8050000B
>[drm] nouveau 0000:01:00.0: 0x855A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8563: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000101
>[drm] nouveau 0000:01:00.0: 0x856C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x856C: Reg: 0x001002E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002E0, Data: 0x00200080
>[drm] nouveau 0000:01:00.0: 0x8593: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8593: Reg: 0x001002E4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002E4, Data: 0x00300000
>[drm] nouveau 0000:01:00.0: 0x85BA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x85BA: Reg: 0x001002C4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002C4, Data: 0x00100002
>[drm] nouveau 0000:01:00.0: 0x85E1: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x85E1: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x85E3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x85E3: Reg: 0x001002C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002C0, Data: 0x00001520
>[drm] nouveau 0000:01:00.0: 0x860A: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x860A: Condition: 0x0D
>[drm] nouveau 0000:01:00.0: 0x860A: Cond: 0x0D, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x860A: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:01:00.0: 0x860A: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x860C: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8615: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x861E: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8627: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8630: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8630: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x8631: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x8631: Condition: 0x12
>[drm] nouveau 0000:01:00.0: 0x8631: Cond: 0x12, Reg: 0x00100710, Mask: 0x00000080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x8631: Checking if 0x00000000 equals 0x00000080
>[drm] nouveau 0000:01:00.0: 0x8631: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x8633: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8640: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8640: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x8641: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x864A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100264, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8653: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8653: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x8656: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x8656: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8658: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8658: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x865B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100210, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8664: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010025C, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x866D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x866D: Reg: 0x00004018, Mask: 0xFFFF3FFF, Data: 0x0000C000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 0x867A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x867A: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x867D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 2 at offset 0x867F
>[drm] nouveau 0000:01:00.0: 0x867F: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x867F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008C0, Data: 0x9D0A0293
>[drm] nouveau 0000:01:00.0: 0x8688: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000108C, Data: 0x000000D1
>[drm] nouveau 0000:01:00.0: 0x8691: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8691: Executing subroutine at 0x6E83
>[drm] nouveau 0000:01:00.0: 0x6E83: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xF0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 0x6E86: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:01:00.0: 0x6E86: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x08, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x08
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x09
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 0x6E8D: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:01:00.0: 0x6E8D: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x18, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x18
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 0x6E94: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:01:00.0: 0x6E94: Index: 0x88, Mask: 0xBF, Data: 0x40
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000040
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x40
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x40
>[drm] nouveau 0000:01:00.0: 0x6E98: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:01:00.0: 0x6E98: Index: 0x8A, Mask: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000040
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 0x6E9C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8691: End of 0x6E83 subroutine
>[drm] nouveau 0000:01:00.0: 0x8694: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E200, Data: 0x0003103C
>[drm] nouveau 0000:01:00.0: 0x869D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x869D: Executing subroutine at 0x6E9D
>[drm] nouveau 0000:01:00.0: 0x6E9D: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x30, Head: 0x00, Data: 0x10
>[drm] nouveau 0000:01:00.0: 0x6EA0: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x31, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 0x6EA3: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xAA, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 0x6EA6: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x869D: End of 0x6E9D subroutine
>[drm] nouveau 0000:01:00.0: 0x86A0: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 3 at offset 0x86A1
>[drm] nouveau 0000:01:00.0: 0x86A1: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x86A1: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x86A1: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x86A1: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x86A4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x86A4: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x86A7: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x86A7: Executing subroutine at 0x867E
>[drm] nouveau 0000:01:00.0: 0x867E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x86A7: End of 0x867E subroutine
>[drm] nouveau 0000:01:00.0: 0x86AA: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AA: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86AC: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AC: Repeating following segment 10 times
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86B1: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B1: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B3: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B3: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B5: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B5: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100210, Data: 0x80000001
>[drm] nouveau 0000:01:00.0: 0x86C0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86C0: Condition: 0x0E
>[drm] nouveau 0000:01:00.0: 0x86C0: Cond: 0x0E, Reg: 0x00100268, Mask: 0x30000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100268, Data: 0x30030200
>[drm] nouveau 0000:01:00.0: 0x86C0: Checking if 0x30000000 equals 0x30000000
>[drm] nouveau 0000:01:00.0: 0x86C0: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x86C2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86C2: Reg: 0x00100C00, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100C00, Data: 0xFC84418B
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100C00, Data: 0xFC84418B
>[drm] nouveau 0000:01:00.0: 0x86CF: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86CF: Condition: 0x0F
>[drm] nouveau 0000:01:00.0: 0x86CF: Cond: 0x0F, Reg: 0x00001540, Mask: 0x00FF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x86CF: Checking if 0x00020000 equals 0x00030000
>[drm] nouveau 0000:01:00.0: 0x86CF: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x86D1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86DE: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x86DE: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x86DF: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86DF: Condition: 0x0F
>[drm] nouveau 0000:01:00.0: 0x86DF: Cond: 0x0F, Reg: 0x00001540, Mask: 0x00FF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x86DF: Checking if 0x00020000 equals 0x00030000
>[drm] nouveau 0000:01:00.0: 0x86DF: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x86E1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86EE: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86F0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86FD: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x86FD: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x86FE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86FE: Reg: 0x00100710, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x870B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x870B: Reg: 0x00100E04, Mask: 0xFFE0007F, Data: 0x00064C80
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100E04, Data: 0x80064C84
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100E04, Data: 0x80064C84
>[drm] nouveau 0000:01:00.0: 0x8718: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8718: Reg: 0x00100E08, Mask: 0xF01FFFFF, Data: 0x0B000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100E08, Data: 0x0B048808
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100E08, Data: 0x0B048808
>[drm] nouveau 0000:01:00.0: 0x8725: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8725: Reg: 0x00100200, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x8732: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8732: Reg: 0x00100600, Mask: 0xFFFFFFFF, Data: 0x00004000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:01:00.0: 0x873F: [ (0x63) - INIT_COMPUTE_MEM ]
>[drm] nouveau 0000:01:00.0: 0x8740: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8740: Executing subroutine at 0x6C21
>[drm] nouveau 0000:01:00.0: 0x6C21: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C21: Reg: 0x00614000, Mask: 0xFFFFEFFF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614000, Data: 0x01001210
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614000, Data: 0x01001210
>[drm] nouveau 0000:01:00.0: 0x6C2E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A008, Data: 0x03A502D1
>[drm] nouveau 0000:01:00.0: 0x6C37: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6C37: Condition: 0x0A
>[drm] nouveau 0000:01:00.0: 0x6C37: Cond: 0x0A, Reg: 0x00021218, Mask: 0x000000FF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021218, Data: 0x00000023
>[drm] nouveau 0000:01:00.0: 0x6C37: Checking if 0x00000023 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6C37: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x6C39: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C42: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C4B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:01:00.0: 0x6C4B: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x6C4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C4C: Reg: 0x0061A068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A068, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A068, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 0x6C59: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C59: Reg: 0x0061A868, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 0x6C66: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C66: SrcReg: 0x00021350, Shift: 0x00, SrcMask: 0x000001FF, Xor: 0x00000000, DstReg: 0x0061A870, DstMask: 0xFFFFFE00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021350, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A870, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A870, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6C7C: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C7C: SrcReg: 0x00021354, Shift: 0x00, SrcMask: 0x000001FF, Xor: 0x00000000, DstReg: 0x0061A070, DstMask: 0xFFFFFE00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021354, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A070, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A070, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6C92: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6C93: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A030, Data: 0x000415F1
>[drm] nouveau 0000:01:00.0: 0x6C9C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A830, Data: 0x000415F1
>[drm] nouveau 0000:01:00.0: 0x6CA5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CA5: Reg: 0x0000E50C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E50C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E50C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CB2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CB2: Reg: 0x0000E55C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E55C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E55C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CBF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CBF: Reg: 0x0000E5AC, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5AC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5AC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CCC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CCC: Reg: 0x0000E5FC, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5FC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5FC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CD9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CD9: Reg: 0x0000E500, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E500, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E500, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6CE6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CE6: Reg: 0x0000E550, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E550, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E550, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6CF3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CF3: Reg: 0x0000E5A0, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5A0, Data: 0x0000E461
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5A0, Data: 0x0000E461
>[drm] nouveau 0000:01:00.0: 0x6D00: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D00: Reg: 0x0000E5F0, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5F0, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5F0, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6D0D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D0D: Reg: 0x0061E818, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 0x6D1A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D1A: Reg: 0x0061F018, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 0x6D27: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8740: End of 0x6C21 subroutine
>[drm] nouveau 0000:01:00.0: 0x8743: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8743: Reg: 0x00100674, Mask: 0xFFFF0000, Data: 0x00000404
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100674, Data: 0x00020404
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100674, Data: 0x00020404
>[drm] nouveau 0000:01:00.0: 0x8750: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8750: Reg: 0x00001558, Mask: 0xFFFFFFFC, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001558, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001558, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 0x875D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001588, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8766: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8766: Reg: 0x00020060, Mask: 0x00C0FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 0x8773: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020080, Data: 0x100C0736
>[drm] nouveau 0000:01:00.0: 0x877C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x877C: Reg: 0x00020018, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:01:00.0: 0x8789: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8789: Reg: 0x0008814C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:01:00.0: 0x8796: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088154, Data: 0x00007120
>[drm] nouveau 0000:01:00.0: 0x879F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x879F: Reg: 0x0008813C, Mask: 0x0FFFFFFF, Data: 0x60000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008813C, Data: 0x63FF0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008813C, Data: 0x63FF0000
>[drm] nouveau 0000:01:00.0: 0x87AC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87AC: Reg: 0x00088150, Mask: 0xFFFFFE7F, Data: 0x00000180
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088150, Data: 0x0E00FF95
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088150, Data: 0x0E00FF95
>[drm] nouveau 0000:01:00.0: 0x87B9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008845C, Data: 0x90000000
>[drm] nouveau 0000:01:00.0: 0x87C2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87C2: Reg: 0x00088158, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088158, Data: 0x00000F02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088158, Data: 0x00000F02
>[drm] nouveau 0000:01:00.0: 0x87CF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00082000, Data: 0x00000002
>[drm] nouveau 0000:01:00.0: 0x87D8: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x87D8: Executing subroutine at 0x6D28
>[drm] nouveau 0000:01:00.0: 0x6D28: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C080, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D31: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C084, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D3A: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x85, Head: 0x00, Data: 0xFF
>[drm] nouveau 0000:01:00.0: 0x6D3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x87D8: End of 0x6D28 subroutine
>[drm] nouveau 0000:01:00.0: 0x87DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87DB: Reg: 0x0000E1E4, Mask: 0xFFFFFFFC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E1E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E1E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x87E8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87E8: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001084, Data: 0x00011469
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001084, Data: 0x00011469
>[drm] nouveau 0000:01:00.0: 0x87F5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87F5: Reg: 0x0000E690, Mask: 0xFF88FFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E690, Data: 0xF4000204
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E690, Data: 0xF4000204
>[drm] nouveau 0000:01:00.0: 0x8802: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 4 at offset 0x8803
>[drm] nouveau 0000:01:00.0: 0x8803: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x8803: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table at offset 0x8868
>[drm] nouveau 0000:01:00.0: 0x8868: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8868: Executing subroutine at 0x6D3E
>[drm] nouveau 0000:01:00.0: 0x6D3E: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x6D3E: Condition: 0x01, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x6D3E: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 0x6D3E: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D3E: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:01:00.0: 0x6D3E: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 0x6D3E: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D3E: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:01:00.0: 0x6D41: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6D41: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x6D42: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D42: SrcReg: 0x00610000, Shift: 0x00, SrcMask: 0x0000FFFF, Xor: 0x00000000, DstReg: 0x0061000C, DstMask: 0xFFFF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00610000, Data: 0x857D0150
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 0x6D58: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D58: Reg: 0x0061000C, Mask: 0xBFFFFFFF, Data: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061000C, Data: 0x40000150
>[drm] nouveau 0000:01:00.0: 0x6D65: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x6D65: Condition: 0x02, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x6D65: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 0x6D65: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D65: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x6D65: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:01:00.0: 0x6D65: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D68: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6D69: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8868: End of 0x6D3E subroutine
>[drm] nouveau 0000:01:00.0: 0x886B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 0 0 2
>[drm] nouveau 0000:01:00.0: output script 0 not found
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EB: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x57EB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:01:00.0: 0x5CE6: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x5CE6: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x5CE6: subop 0x00
>[drm] nouveau 0000:01:00.0: 0x5CE6: skipping following commands
>[drm] nouveau 0000:01:00.0: 0x5CE9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x5CF2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x5CFB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x5D08: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x5D15: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EB: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x57EB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:602 - Entry 0: 220: 0c1e5828 15050f0c 07060c0c 00000009
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:605 -          230: 20041414 580c0e0c 00000000 00000202
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:602 - Entry 1: 220: 050c2411 0c030a08 04040505 00000005
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:605 -          230: 0f030a0a 24050b05 00000000 00000202
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:602 - Entry 2: 220: 03050f07 0c030b08 05040303 00000005
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:605 -          230: 07030a0a 0f030c03 00000000 00000202
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:602 - Entry 3: 220: 0c1c5828 15050f0d 07060c0c 0000000a
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:605 -          230: 20041414 580c0e0c 00000000 00000202
>[drm] nouveau 0000:01:00.0: nv50_mem_timing_entry:606 -          240: 00000000
>[drm] nouveau 0000:01:00.0: nouveau_i2c_identify:540 - Probing monitoring devices on I2C bus: 2
>[drm] nouveau 0000:01:00.0: nouveau_i2c_identify:549 - No devices found.
>[drm] nouveau 0000:01:00.0: 3 available performance level(s)
>[drm] nouveau 0000:01:00.0: 0: core 135MHz shader 270MHz memory 135MHz timing 2 voltage 850mV
>[drm] nouveau 0000:01:00.0: 1: core 405MHz shader 810MHz memory 324MHz timing 1 voltage 870mV
>[drm] nouveau 0000:01:00.0: 3: core 450MHz shader 1125MHz memory 770MHz timing 0 voltage 920mV
>[drm] nouveau 0000:01:00.0: c: core 405MHz shader 810MHz memory 324MHz voltage 900mV fanspeed 40%
>[drm] nouveau 0000:01:00.0: nv50_vram_rblock:153 - memcfg 0x00222800 0x0155a020 0x00000001 0xf7020003
>[drm] nouveau 0000:01:00.0: nv50_vram_rblock:181 - rblock 196608 bytes
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_init:242 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000003
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fc7ff40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=131072 align=4096 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801100d0740
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00010200 vinst=0x0000070200 size=0x00004000 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff8801100d0a40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00014200 vinst=0x0000074200 size=0x00000100 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff8801100d0dc0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801100d0f40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880110b193c0
>[TTM] Zone  kernel: Available graphics memory: 1944932 kiB.
>[TTM] Initializing pool allocator.
>[TTM] Initializing DMA pool allocator.
>[drm] nouveau 0000:01:00.0: Detected 512MiB VRAM
>mtrr: type mismatch for e8000000,8000000 old: write-back new: write-combining
>[drm] nouveau 0000:01:00.0: 512 MiB GART (aperture)
>[drm] nouveau 0000:01:00.0: nv50_fb_create:59 - 959 tags available
>[drm] nouveau 0000:01:00.0: nv50_graph_init:131 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init:166 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88011005dcc0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801109bbe40
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_reset:99 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_intr:108 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_context_table:121 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch1
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch2
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch3
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch4
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch5
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch6
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch7
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch8
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch9
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch10
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch11
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch12
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch13
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch14
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch15
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch16
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch17
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch18
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch19
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch20
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch21
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch22
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch23
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch24
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch25
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch26
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch27
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch28
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch29
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch30
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch31
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch32
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch33
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch34
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch35
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch36
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch37
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch38
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch39
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch40
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch41
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch42
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch43
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch44
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch45
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch46
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch47
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch48
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch49
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch50
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch51
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch52
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch53
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch54
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch55
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch56
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch57
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch58
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch59
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch60
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch61
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch62
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch63
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch64
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch65
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch66
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch67
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch68
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch69
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch70
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch71
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch72
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch73
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch74
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch75
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch76
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch77
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch78
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch79
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch80
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch81
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch82
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch83
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch84
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch85
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch86
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch87
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch88
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch89
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch90
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch91
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch92
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch93
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch94
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch95
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch96
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch97
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch98
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch99
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch100
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch101
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch102
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch103
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch104
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch105
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch106
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch107
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch108
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch109
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch110
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch111
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch112
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch113
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch114
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch115
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch116
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch117
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch118
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch119
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch120
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch121
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch122
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch123
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch124
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch125
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch126
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:01:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_regs__nv:136 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_regs:144 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch127
>Slow work thread pool: Starting up
>Slow work thread pool: Ready
>[drm] nouveau 0000:01:00.0: nv50_display_create:330 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42f40
>[drm] nouveau 0000:01:00.0: nv50_crtc_create:718 - 
>[drm] nouveau 0000:01:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:01:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:01:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:01:00.0: nouveau_connector_create:883 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_create:306 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=32768 align=65536 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42a40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=16 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42940
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=0 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd428c0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42840
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000d30: h=0xcafe0000, c=0x00800000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd427c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000200
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000200: h=0x01000000, c=0x00808000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42740
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000218: h=0x01000003, c=0x00810000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd426c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000210: h=0x01000002, c=0x00818000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42640
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000208: h=0x01000001, c=0x00820000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42440
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000d38: h=0xcafe0000, c=0x10828001
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd423c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000220: h=0x01000003, c=0x10830001
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd42340
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000228: h=0x01000002, c=0x10838001
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd422c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000208: h=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000228: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000230: h=0x01000001, c=0x10840001
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd420c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d38: h=0xcafe0000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000d40: h=0xcafe0000, c=0x20848002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34f40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000238: h=0x01000003, c=0x20850002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34ec0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000240: h=0x01000002, c=0x20858002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34e40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000208: h=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000240: h=0x01000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000248: h=0x01000001, c=0x20860002
>[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[drm] No driver support for vblank timestamp query.
>[drm] nouveau 0000:01:00.0: nouveau_channel_alloc:157 - initialising channel 1
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_channel_init:752 - ch1 vram=0x80000002 tt=0x80000003
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_channel_init_pramin:660 - ch1
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=66560 align=4096 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34d40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x0013a200 vinst=0x00001ad200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88010fd34c40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34bc0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34b40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000010
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34ac0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000011
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34a40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000410
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000410: h=0x80000002, c=0x00000e04
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd349c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000418
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000418: h=0x80000003, c=0x00000e06
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd348c0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd345c0
>[drm] nouveau 0000:01:00.0: nv50_fifo_create_context:237 - ch1
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34540
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd344c0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch1
>[drm] nouveau 0000:01:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x5039
>[drm] nouveau 0000:01:00.0: nv50_graph_context_new:235 - ch1
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=348928 align=0 flags=0x00000006
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd343c0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd342c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000408: h=0x80000001, c=0x00100f40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd34240
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000006
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000430: h=0x80000006, c=0x00000f41
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x506e
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x8000000e
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_channel_alloc:215 - channel 1 initialised
>[drm] nouveau 0000:01:00.0: nv50_display_init:147 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000002a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000002b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000002b0
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>usb 8-1: new low speed USB device number 2 using uhci_hcd
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 71
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 10 ac 15 40 42 57 4c 41
> 	2e 10 01 03 80 26 1e 78 ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 130
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 13 enabled? yes
>[drm:drm_enable_connectors], connector 16 enabled? yes
>[drm:drm_target_preferred], looking for cmdline mode on connector 13
>[drm:drm_target_preferred], looking for preferred mode on connector 13
>[drm:drm_target_preferred], found mode 1280x1024
>[drm:drm_target_preferred], looking for cmdline mode on connector 16
>[drm:drm_target_preferred], looking for preferred mode on connector 16
>[drm:drm_target_preferred], found mode 1280x1024
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1280x1024 set on crtc 11
>[drm:drm_setup_crtcs], desired mode 1280x1024 set on crtc 12
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd1aec0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch1 class=0x502d
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch1 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88010fd1adc0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000007
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000438
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000438: h=0x80000007, c=0x00100f43
>[drm] nouveau 0000:01:00.0: allocated 1280x1024 fb: 0x320000, bo ffff88010fd33000
>fbcon: nouveaufb (fb0) is primary device
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:15:TMDS-15] set [MODE:43:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000002a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000002b0
>[drm] nouveau 0000:01:00.0: Loading PLL limits for register 0x00614100
>[drm] nouveau 0000:01:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:01:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:01:00.0: pll.vco1.min_inputfreq: 25000
>[drm] nouveau 0000:01:00.0: pll.vco1.max_inputfreq: 50000
>[drm] nouveau 0000:01:00.0: pll.vco1.min_n: 8
>[drm] nouveau 0000:01:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:01:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:01:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:01:00.0: pll.min_p: 1
>[drm] nouveau 0000:01:00.0: pll.max_p: 63
>[drm] nouveau 0000:01:00.0: pll.refclk: 27000
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_clock:326 - pclk 108000 out 108000 N 36 fN 0xf000 M 1 P 9
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x5743: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5743: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5743: BaseReg: 0x0061D918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D918, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D91C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x5751: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5751: BaseReg: 0x0061D998, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D998, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D99C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x575F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D920, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5768: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5771: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5771: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5771: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5774: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5774: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4740: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4760: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4780: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A0: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5774: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5777: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5777: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5777: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x577A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000002b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DVI-I-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:44:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000540
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000550
>[drm] nouveau 0000:01:00.0: Loading PLL limits for register 0x00614900
>[drm] nouveau 0000:01:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:01:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:01:00.0: pll.vco1.min_inputfreq: 25000
>[drm] nouveau 0000:01:00.0: pll.vco1.max_inputfreq: 50000
>[drm] nouveau 0000:01:00.0: pll.vco1.min_n: 8
>[drm] nouveau 0000:01:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:01:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:01:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:01:00.0: pll.min_p: 1
>[drm] nouveau 0000:01:00.0: pll.max_p: 63
>[drm] nouveau 0000:01:00.0: pll.refclk: 27000
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_clock:326 - pclk 108000 out 108000 N 36 fN 0xf000 M 1 P 9
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038800
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038800
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038800
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038400
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038400
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038400
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038200
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038200
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00830080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00830080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00870080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000550
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>Console: switching to colour frame buffer device 160x64
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>fb0: nouveaufb frame buffer device
>drm: registered panic notifier
>[drm] Initialized nouveau 0.0.16 20090420 for 0000:01:00.0 on minor 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Starting plymouth daemon
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>Switching to clocksource tsc
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>usb 8-1: New USB device found, idVendor=413c, idProduct=3012
>usb 8-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>usb 8-1: Product: Dell USB Optical Mouse
>usb 8-1: Manufacturer: Dell
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>usb 8-1: configuration #1 chosen from 1 choice
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>input: Dell Dell USB Optical Mouse as /devices/pci0000:00/0000:00:1d.2/usb8/8-1/8-1:1.0/input/input4
>generic-usb 0003:413C:3012.0001: input,hidraw0: USB HID v1.11 Mouse [Dell Dell USB Optical Mouse] on usb-0000:00:1d.2-1/input0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88011005d3c0
>[drm:drm_mode_addfb], [FB:31]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:31] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_mode_addfb], [FB:46]
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:46] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:31] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:46] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: rd_NO_DM: removing DM RAID activation
>dracut: rd_NO_MD: removing MD RAID activation
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ahci 0000:00:1f.2: version 3.0
>  alloc irq_desc for 18 on node -1
>  alloc kstat_irqs on node -1
>ahci 0000:00:1f.2: PCI INT B -> GSI 18 (level, low) -> IRQ 18
>  alloc irq_desc for 28 on node -1
>  alloc kstat_irqs on node -1
>ahci 0000:00:1f.2: irq 28 for MSI/MSI-X
>ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 6 ports 3 Gbps 0x3f impl SATA mode
>ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ccc sxs 
>ahci 0000:00:1f.2: setting latency timer to 64
>scsi0 : ahci
>scsi1 : ahci
>scsi2 : ahci
>scsi3 : ahci
>scsi4 : ahci
>scsi5 : ahci
>ata1: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204100 irq 28
>ata2: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204180 irq 28
>ata3: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204200 irq 28
>ata4: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204280 irq 28
>ata5: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204300 irq 28
>ata6: SATA max UDMA/133 abar m2048@0xf3204000 port 0xf3204380 irq 28
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>Switching to clocksource hpet
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ata4: SATA link down (SStatus 0 SControl 300)
>ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
>ata3: SATA link down (SStatus 0 SControl 300)
>ata6: SATA link down (SStatus 0 SControl 300)
>ata5: SATA link down (SStatus 0 SControl 300)
>ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>ata2.00: ATAPI: ATAPI   DVD D  DH16D3S, SH37, max UDMA/100
>ata1.00: ATA-7: ST3250410AS, 3.AHC, max UDMA/100
>ata1.00: 488397168 sectors, multi 16: LBA48 NCQ (depth 31/32)
>ata1.00: configured for UDMA/100
>scsi 0:0:0:0: Direct-Access     ATA      ST3250410AS      3.AH PQ: 0 ANSI: 5
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ata2.00: configured for UDMA/100
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>scsi 1:0:0:0: CD-ROM            ATAPI    DVD D  DH16D3S   SH37 PQ: 0 ANSI: 5
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_ohci 0000:10:0b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_ohci: Added fw-ohci device 0000:10:0b.0, OHCI version 1.0
>sd 0:0:0:0: [sda] 488397168 512-byte logical blocks: (250 GB/232 GiB)
>sd 0:0:0:0: [sda] Write Protect is off
>sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
> sda:
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
> sda1 sda2
>sd 0:0:0:0: [sda] Attached SCSI disk
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>sr0: scsi3-mmc drive: 48x/48x cd/rw xa/form2 cdda tray
>Uniform CD-ROM driver Revision: 3.20
>sr 1:0:0:0: Attached scsi CD-ROM sr0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Mounted root filesystem /dev/sda2
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Loading SELinux policy
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>firewire_core: created device fw0: GUID 0030bd051505e113, S400
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>type=1404 audit(1334837941.488:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux: 2048 avtab hash slots, 235311 rules.
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux: 2048 avtab hash slots, 235311 rules.
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux:  9 users, 12 roles, 3669 types, 185 bools, 1 sens, 1024 cats
>SELinux:  81 classes, 235311 rules
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>SELinux:  Completing initialization.
>SELinux:  Setting up existing superblocks.
>SELinux: initialized (dev sda2, type ext4), uses xattr
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev usbfs, type usbfs), uses genfs_contexts
>SELinux: initialized (dev selinuxfs, type selinuxfs), uses genfs_contexts
>SELinux: initialized (dev mqueue, type mqueue), uses transition SIDs
>SELinux: initialized (dev hugetlbfs, type hugetlbfs), uses transition SIDs
>SELinux: initialized (dev devpts, type devpts), uses transition SIDs
>SELinux: initialized (dev inotifyfs, type inotifyfs), uses genfs_contexts
>SELinux: initialized (dev anon_inodefs, type anon_inodefs), uses genfs_contexts
>SELinux: initialized (dev pipefs, type pipefs), uses task SIDs
>SELinux: initialized (dev debugfs, type debugfs), uses genfs_contexts
>SELinux: initialized (dev sockfs, type sockfs), uses task SIDs
>SELinux: initialized (dev devtmpfs, type devtmpfs), uses transition SIDs
>SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
>SELinux: initialized (dev proc, type proc), uses genfs_contexts
>SELinux: initialized (dev bdev, type bdev), uses genfs_contexts
>SELinux: initialized (dev rootfs, type rootfs), uses genfs_contexts
>SELinux: initialized (dev sysfs, type sysfs), uses genfs_contexts
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>type=1403 audit(1334837941.865:3): policy loaded auid=4294967295 ses=4294967295
>dracut: 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>dracut: Switching root
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>readahead: starting
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>udev: starting version 147
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EDAC MC: Ver: 2.1.0 Apr  8 2012
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>EDAC MC0: Giving out device to 'x38_edac' 'x38': DEV 0000:00:00.0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>snd_hda_intel 0000:01:00.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>hda_intel: Disabling MSI
>snd_hda_intel 0000:01:00.1: setting latency timer to 64
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>HDMI status: Codec=0 Pin=5 Presence_Detect=0 ELD_Valid=0
>HDMI status: Codec=1 Pin=5 Presence_Detect=0 ELD_Valid=0
>HDMI status: Codec=2 Pin=5 Presence_Detect=0 ELD_Valid=0
>HDMI status: Codec=3 Pin=5 Presence_Detect=0 ELD_Valid=0
>input: HDA NVidia HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card0/input5
>input: HDA NVidia HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card0/input6
>input: HDA NVidia HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card0/input7
>input: HDA NVidia HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card0/input8
>iTCO_vendor_support: vendor-support=0
>iTCO_wdt: Intel TCO WatchDog Timer Driver v1.05
>iTCO_wdt: Found a ICH9R TCO device (Version=2, TCOBASE=0xf860)
>iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>tg3.c:v3.122 (December 7, 2011)
>tg3 0000:34:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>tg3 0000:34:00.0: setting latency timer to 64
>tg3 0000:34:00.0: eth0: Tigon3 [partno(BCM95751A519FLP) rev 4201] (PCI Express) MAC address 00:10:18:48:2a:95
>tg3 0000:34:00.0: eth0: attached PHY is 5750 (10/100/1000Base-T Ethernet) (WireSpeed[1], EEE[0])
>tg3 0000:34:00.0: eth0: RXcsums[0] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>tg3 0000:34:00.0: eth0: dma_rwctrl[76180000] dma_mask[64-bit]
>microcode: CPU0 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>microcode: CPU1 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>microcode: CPU2 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>microcode: CPU3 sig=0x1067a, pf=0x10, revision=0xa07
>platform microcode: firmware: requesting intel-ucode/06-17-0a
>Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>microcode: CPU0 updated to revision 0xa0b, date = 2010-09-28 
>microcode: CPU1 updated to revision 0xa0b, date = 2010-09-28 
>microcode: CPU2 updated to revision 0xa0b, date = 2010-09-28 
>microcode: CPU3 updated to revision 0xa0b, date = 2010-09-28 
>sd 0:0:0:0: Attached scsi generic sg0 type 0
>sr 1:0:0:0: Attached scsi generic sg1 type 5
>parport_pc 00:07: reported by Plug and Play ACPI
>parport0: PC-style at 0x378 (0x778), irq 7 [PCSPP,TRISTATE]
>ppdev: user-space parallel port driver
>EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: 
>SELinux: initialized (dev sda1, type ext4), uses xattr
>SELinux: initialized (dev binfmt_misc, type binfmt_misc), uses genfs_contexts
>NET: Registered protocol family 10
>lo: Disabled Privacy Extensions
>ip6_tables: (C) 2000-2006 Netfilter Core Team
>nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
>ip_tables: (C) 2000-2006 Netfilter Core Team
>  alloc irq_desc for 29 on node -1
>  alloc kstat_irqs on node -1
>tg3 0000:34:00.0: irq 29 for MSI/MSI-X
>ADDRCONF(NETDEV_UP): eth0: link is not ready
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>tg3 0000:34:00.0: eth0: Link is up at 100 Mbps, full duplex
>tg3 0000:34:00.0: eth0: Flow control is off for TX and off for RX
>ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>RPC: Registered named UNIX socket transport module.
>RPC: Registered udp transport module.
>RPC: Registered tcp transport module.
>RPC: Registered tcp NFSv4.1 backchannel transport module.
>SELinux: initialized (dev rpc_pipefs, type rpc_pipefs), uses genfs_contexts
>SELinux: initialized (dev autofs, type autofs), uses genfs_contexts
>SELinux: initialized (dev autofs, type autofs), uses genfs_contexts
>SELinux: initialized (dev autofs, type autofs), uses genfs_contexts
>eth0: no IPv6 routers present
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [NOFB]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 3
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [NOFB]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_del:284 - gpuobj ffff88011005d3c0
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm] nouveau 0000:01:00.0: nouveau_channel_cleanup:378 - clearing FIFO enables from file_priv
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[4]
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801137765c0
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nouveau_channel_alloc:157 - initialising channel 2
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_channel_init:752 - ch2 vram=0xd8000001 tt=0xd8000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_channel_init_pramin:660 - ch2
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=66560 align=4096 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801101a0ec0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x003b1200 vinst=0x0000930200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff8801115b2a40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043dc0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2840
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000010
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b24c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000011
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2b40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006c8
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006c8: h=0xd8000001, c=0x00000e04
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2340
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000002
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006d0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006d0: h=0xd8000002, c=0x00000e06
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2440
>[drm] nouveau 0000:01:00.0: nv50_fifo_create_context:237 - ch2
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043cc0
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b25c0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch2
>[drm] nouveau 0000:01:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x5039
>[drm] nouveau 0000:01:00.0: nv50_graph_context_new:235 - ch2
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=348928 align=0 flags=0x00000006
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2e40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043ec0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000001
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000408: h=0x80000001, c=0x00100f40
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2240
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000006
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000430: h=0x80000006, c=0x00000f41
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x506e
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x8000000e
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_channel_alloc:215 - channel 2 initialised
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x0030
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043f40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000000: h=0x00000000, c=0x00100f43
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b20c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000003
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006d8
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006d8: h=0xd8000003, c=0x00000f44
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x502d
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2740
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000020
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000500
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000500: h=0x80000020, c=0x00100f46
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x5039
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043bc0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000018
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000004c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000004c0: h=0x80000018, c=0x00100f47
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x8597
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=16 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b22c0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000019
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000004c8
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000004c8: h=0x80000019, c=0x00100f48
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_gr_new:627 - ch2 class=0x506e
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x80000021
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000508
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000508: h=0x80000021, c=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch2 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff880112043e40
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xd8000004
>[drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:50 - hash=0x000006e0
>[drm] nouveau 0000:01:00.0: nouveau_ramht_insert:135 - insert ch2 0x000006e0: h=0xd8000004, c=0x00000f49
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:184 - gpuobj ffff8801115b2d40
>[drm:drm_mode_addfb], [FB:31]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:31] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x1024" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm:drm_crtc_helper_set_mode], [ENCODER:15:TMDS-15] set [MODE:46:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000028
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000028
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x5743: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5743: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5743: BaseReg: 0x0061D918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D918, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D91C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x5751: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5751: BaseReg: 0x0061D998, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D998, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D99C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x575F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D920, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5768: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5771: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5771: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5771: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5774: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5774: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4740: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4760: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4780: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A0: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5774: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5777: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5777: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5777: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x577A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DVI-I-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:31] #connectors=1 (x y) (1280 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:50:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00870080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00870080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00870080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00870080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>hda-intel: IRQ timing workaround is activated for card #0. Suggest a bigger bdl_pos_adj.
>Bridge firewalling registered
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] disconnected
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1152x864 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_prune_invalid], Not using 720x400 mode -3
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>fuse init (API version 7.13)
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 159
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 10 ac 15 40 42 57 4c 41
> 	2e 10 01 03 80 26 1e 78 ee de 95 a3 54 4c 99 26
> 	0f 50 54 a5 4b 00 71 4f 81 ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm:drm_mode_addfb], [FB:41]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:41] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [NOFB]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000001c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_mode_addfb], [FB:31]
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:31] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 53:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:53:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] disconnected
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1152x864 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_prune_invalid], Not using 720x400 mode -3
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 3
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [NOFB]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_mode_addfb], [FB:31]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:31] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:31] #connectors=1 (x y) (1280 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 41:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:41:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000014
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm:drm_mode_addfb], [FB:55]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:55] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [NOFB]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000001c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:55] #connectors=1 (x y) (1280 624)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 41:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 31:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 31:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:31:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] disconnected
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1280x1024 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1152x864 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_prune_invalid], Not using 720x400 mode -3
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 31:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:44:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:55] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:55] #connectors=1 (x y) (1280 624)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 58:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 58:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:58:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm:drm_crtc_helper_set_config], 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 58:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:44:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:55] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:55] #connectors=1 (x y) (1280 624)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 60:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 60:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:60:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000014
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm:drm_mode_addfb], [FB:61]
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:61] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:61] #connectors=1 (x y) (1280 624)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:61] #connectors=1 (x y) (1280 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 60:"" 0 28320 720 738 846 900 400 412 414 449 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 55:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 55:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:55:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000014
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 130
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:61] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 46:"1280x1024" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 64:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 64:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 3
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm:drm_crtc_helper_set_mode], 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[ENCODER:15:TMDS-15] set [MODE:64:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000028
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x5743: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5743: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5743: BaseReg: 0x0061D918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D918, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D91C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x5751: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5751: BaseReg: 0x0061D998, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D998, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D99C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x575F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D920, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5768: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5771: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5771: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5771: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5774: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5774: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4740: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4760: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4780: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001F00
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A0: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5774: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5777: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5777: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5777: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x577A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DVI-I-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 29
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 10 ac 15 40 42 57 4c 41
> 	2e 10 01 03 80 26 1e 78 ee de 95 a3 54 4c 99 26
> 	0f 50 54 a5 4b 00 71 4f ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:61] #connectors=1 (x y) (1280 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 55:"" 0 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 65:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 65:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:65:]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000024
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 3
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>tg3 0000:34:00.0: PME# enabled
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>PM: Syncing filesystems ... done.
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 64:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 3
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:15:TMDS-15] set [MODE:43:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x0000000c
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000028
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x000000a0
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x5743: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5743: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5743: BaseReg: 0x0061D918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D918, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D91C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x5751: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5751: BaseReg: 0x0061D998, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D998, Data: 0x30303030
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D99C, Data: 0x00000030
>[drm] nouveau 0000:01:00.0: 0x575F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D920, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5768: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x5771: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5771: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5771: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5774: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5774: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4740: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4760: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001D00
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00009D00
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00009D00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00009900
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001B00
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D810, Data: 0x00001B00
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A0: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5774: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5777: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5777: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615B00, Data: 0x00874080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5777: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x577A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000044
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x000000b0
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061D90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DVI-I-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 65:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[ENCODER:18:TMDS-18] set [MODE:44:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EC: parsing output script 1
>[drm] nouveau 0000:01:00.0: 0x57EC: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57ED: parsing output script 2
>[drm] nouveau 0000:01:00.0: 0x57ED: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57ED: Reg: 0x4061C00C, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000001
>[drm] nouveau 0000:01:00.0: 0x57FA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x57FA: Reg: 0x4061C014, Mask: 0xFF3FFFFF, Data: 0x00C00000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00C20000
>[drm] nouveau 0000:01:00.0: 0x5807: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:659 - 0x610030: 0x00000140
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:679 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk10_handler:702 - SOR-3 mc: 0x00000101
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:751 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:780 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_unk20_handler:803 - SOR-1 mc: 0x00000102
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x5609: parsing clock script 0
>[drm] nouveau 0000:01:00.0: 0x5609: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5609: BaseReg: 0x0061C918, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C918, Data: 0x28282828
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C91C, Data: 0x00000028
>[drm] nouveau 0000:01:00.0: 0x5617: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C920, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x5620: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5620: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5620: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x5623: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5623: Executing subroutine at 0x4E82
>[drm] nouveau 0000:01:00.0: 0x4E82: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E82: Executing subroutine at 0x4721
>[drm] nouveau 0000:01:00.0: 0x4721: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4721: Reg: 0x4061C010, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x472E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x472E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4731: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4731: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4731: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 0x4731: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4731: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4733: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4733: Reg: 0x4061C010, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00009100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4740: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4741: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4741: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x474E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x474E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4751: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4751: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4751: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 0x4751: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4751: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4753: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4753: Reg: 0x4061C010, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008900
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4760: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4761: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4761: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x476E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x476E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4771: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4771: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4771: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 0x4771: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4771: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4773: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4773: Reg: 0x4061C010, Mask: 0xFFFFFBFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x4780: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4781: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4781: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x478E: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x478E: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:01:00.0: 0x4791: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x4791: Condition: 0x15
>[drm] nouveau 0000:01:00.0: 0x4791: Cond: 0x15, Reg: 0x4061C010, Mask: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 0x4791: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:01:00.0: 0x4791: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x4793: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4793: Reg: 0x4061C010, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00008300
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00008100
>[drm] nouveau 0000:01:00.0: 0x47A0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x47A1: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E82: End of 0x4721 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E85: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E85: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E92: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5623: End of 0x4E82 subroutine
>[drm] nouveau 0000:01:00.0: 0x5626: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x5626: Executing subroutine at 0x4EA6
>[drm] nouveau 0000:01:00.0: 0x4EA6: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x4EA6: BaseReg: 0x4061C00C, Count: 0x04
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C80C, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C810, Data: 0x00001500
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C814, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C818, Data: 0x00245AF8
>[drm] nouveau 0000:01:00.0: 0x4EBC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: Executing subroutine at 0x4E50
>[drm] nouveau 0000:01:00.0: 0x4E50: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E50: Executing subroutine at 0x5808
>[drm] nouveau 0000:01:00.0: 0x5808: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x5808: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C840, Data: 0x1F0B0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C844, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C848, Data: 0x1E080000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C84C, Data: 0x1E042000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C850, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C854, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C858, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C85C, Data: 0x00008000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C860, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C864, Data: 0x1F002000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C868, Data: 0x1F0C0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C86C, Data: 0x1F0A0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C870, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C874, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C878, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C87C, Data: 0x1F0B8000
>[drm] nouveau 0000:01:00.0: 0x584E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E50: End of 0x5808 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E53: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E53: Reg: 0x4061C130, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C930, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E60: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E60: Reg: 0x4061C1B0, Mask: 0x00F00F00, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C9B0, Data: 0x00400600
>[drm] nouveau 0000:01:00.0: 0x4E6D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E6D: Reg: 0x40614300, Mask: 0xFCF3FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00878080
>[drm] nouveau 0000:01:00.0: 0x4E7A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4EBC: End of 0x4E50 subroutine
>[drm] nouveau 0000:01:00.0: 0x4EBF: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x5626: End of 0x4EA6 subroutine
>[drm] nouveau 0000:01:00.0: 0x5629: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000048
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:01:00.0: nv50_display_unk40_handler:906 - 0x610030: 0x00000150
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x4E7B: parsing clock script 1
>[drm] nouveau 0000:01:00.0: 0x4E7B: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: Executing subroutine at 0x4E93
>[drm] nouveau 0000:01:00.0: 0x4E93: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E93: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x4E93: Cond: 0x0B, Reg: 0x4061C030, Mask: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C830, Data: 0x00048800
>[drm] nouveau 0000:01:00.0: 0x4E93: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x4E96: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x4E97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7B: End of 0x4E93 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E7E: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: Executing subroutine at 0x4E98
>[drm] nouveau 0000:01:00.0: 0x4E98: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x4E98: Reg: 0x4061C10C, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C90C, Data: 0x00401100
>[drm] nouveau 0000:01:00.0: 0x4EA5: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x4E7E: End of 0x4E98 subroutine
>[drm] nouveau 0000:01:00.0: 0x4E81: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: nv50_display_bh:929 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>Freezing user space processes ... (elapsed 0.00 seconds) done.
>Freezing remaining freezable tasks ... 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>(elapsed 0.00 seconds) done.
>ACPI: Preparing to enter system sleep state S3
>Suspending console(s) (use no_console_suspend to debug)
>sd 0:0:0:0: [sda] Synchronizing SCSI cache
>sd 0:0:0:0: [sda] Stopping disk
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>ACPI handle has no context!
>serial 00:08: disabled
>parport_pc 00:07: disabled
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>snd_hda_intel 0000:01:00.1: PCI INT A disabled
>ACPI handle has no context!
>[drm] nouveau 0000:01:00.0: Disabling display...
>[drm] nouveau 0000:01:00.0: nv50_display_fini:262 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000008
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00000000 0x00000000
>[drm] nouveau 0000:01:00.0: Disabling fbcon...
>[drm] nouveau 0000:01:00.0: Unpinning framebuffer(s)...
>[drm] nouveau 0000:01:00.0: Evicting buffers...
>[drm] nouveau 0000:01:00.0: Idling channels...
>[drm] nouveau 0000:01:00.0: nv50_fifo_unload_context:424 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_unload_context:435 - ch1
>[drm] nouveau 0000:01:00.0: Suspending GPU objects...
>[drm] nouveau 0000:01:00.0: And we're gone!
>nouveau 0000:01:00.0: PCI INT A disabled
>ehci_hcd 0000:00:1d.7: PCI INT A disabled
>uhci_hcd 0000:00:1d.2: PCI INT C disabled
>uhci_hcd 0000:00:1d.1: PCI INT B disabled
>uhci_hcd 0000:00:1d.0: PCI INT A disabled
>ehci_hcd 0000:00:1a.7: PCI INT C disabled
>uhci_hcd 0000:00:1a.2: PCI INT C disabled
>uhci_hcd 0000:00:1a.1: PCI INT B disabled
>uhci_hcd 0000:00:1a.0: PCI INT A disabled
>Disabling non-boot CPUs ...
>CPU 1 is now offline
>CPU 2 is now offline
>Broke affinity for irq 22
>Broke affinity for irq 28
>CPU 3 is now offline
>SMP alternatives: switching to UP code
>Extended CMOS year: 2000
>Back to C!
>microcode: CPU0 updated to revision 0xa0b, date = 2010-09-28 
>Extended CMOS year: 2000
>Enabling non-boot CPUs ...
>SMP alternatives: switching to SMP code
>Booting Node 0 Processor 1 APIC 0x2
>microcode: CPU1 updated to revision 0xa0b, date = 2010-09-28 
>CPU1 is up
>Booting Node 0 Processor 2 APIC 0x1
>microcode: CPU2 updated to revision 0xa0b, date = 2010-09-28 
>CPU2 is up
>Booting Node 0 Processor 3 APIC 0x3
>microcode: CPU3 updated to revision 0xa0b, date = 2010-09-28 
>CPU3 is up
>ACPI: Waking up from system sleep state S3
>pcieport 0000:00:01.0: restoring config space at offset 0x7 (was 0x20001010, writing 0x1010)
>pcieport 0000:00:01.0: restoring config space at offset 0x3 (was 0x10000, writing 0x10010)
>pcieport 0000:00:01.0: restoring config space at offset 0x1 (was 0x100107, writing 0x100507)
>uhci_hcd 0000:00:1a.0: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>uhci_hcd 0000:00:1a.1: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>uhci_hcd 0000:00:1a.2: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>ehci_hcd 0000:00:1a.7: restoring config space at offset 0x4 (was 0xfef00000, writing 0xf3204800)
>ehci_hcd 0000:00:1a.7: restoring config space at offset 0x1 (was 0x2900106, writing 0x2900102)
>pcieport 0000:00:1c.0: restoring config space at offset 0x7 (was 0x20005050, writing 0x5050)
>pcieport 0000:00:1c.4: restoring config space at offset 0xf (was 0x100, writing 0x20105)
>pcieport 0000:00:1c.4: restoring config space at offset 0x9 (was 0x10001, writing 0xf801f801)
>pcieport 0000:00:1c.4: restoring config space at offset 0x8 (was 0x0, writing 0xf310f310)
>pcieport 0000:00:1c.4: restoring config space at offset 0x7 (was 0x0, writing 0x4040)
>pcieport 0000:00:1c.4: restoring config space at offset 0x6 (was 0x0, writing 0x343400)
>pcieport 0000:00:1c.4: restoring config space at offset 0x3 (was 0x810000, writing 0x810010)
>pcieport 0000:00:1c.4: restoring config space at offset 0x1 (was 0x100000, writing 0x100507)
>pcieport 0000:00:1c.5: restoring config space at offset 0xf (was 0x200, writing 0x2020a)
>pcieport 0000:00:1c.5: restoring config space at offset 0x9 (was 0x10001, writing 0xf841f831)
>pcieport 0000:00:1c.5: restoring config space at offset 0x8 (was 0x0, writing 0xf820f810)
>pcieport 0000:00:1c.5: restoring config space at offset 0x7 (was 0x20000000, writing 0x3030)
>pcieport 0000:00:1c.5: restoring config space at offset 0x6 (was 0xa0a00, writing 0x3f3f00)
>pcieport 0000:00:1c.5: restoring config space at offset 0x3 (was 0x810000, writing 0x810010)
>pcieport 0000:00:1c.5: restoring config space at offset 0x1 (was 0x100000, writing 0x100507)
>uhci_hcd 0000:00:1d.0: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>uhci_hcd 0000:00:1d.1: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>uhci_hcd 0000:00:1d.2: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>ehci_hcd 0000:00:1d.7: restoring config space at offset 0x4 (was 0xfef00000, writing 0xf3204c00)
>ehci_hcd 0000:00:1d.7: restoring config space at offset 0x1 (was 0x2900106, writing 0x2900102)
>nouveau 0000:01:00.0: restoring config space at offset 0xf (was 0x100, writing 0x10a)
>nouveau 0000:01:00.0: restoring config space at offset 0x9 (was 0x1, writing 0x1101)
>nouveau 0000:01:00.0: restoring config space at offset 0x7 (was 0xc, writing 0xf000000c)
>nouveau 0000:01:00.0: restoring config space at offset 0x5 (was 0xc, writing 0xe800000c)
>nouveau 0000:01:00.0: restoring config space at offset 0x4 (was 0x0, writing 0xf2000000)
>nouveau 0000:01:00.0: restoring config space at offset 0x3 (was 0x800000, writing 0x800010)
>nouveau 0000:01:00.0: restoring config space at offset 0x1 (was 0x100000, writing 0x100007)
>snd_hda_intel 0000:01:00.1: restoring config space at offset 0xf (was 0x100, writing 0x10a)
>snd_hda_intel 0000:01:00.1: restoring config space at offset 0x4 (was 0x0, writing 0xf3000000)
>snd_hda_intel 0000:01:00.1: restoring config space at offset 0x3 (was 0x800000, writing 0x800010)
>snd_hda_intel 0000:01:00.1: restoring config space at offset 0x1 (was 0x100000, writing 0x100002)
>tg3 0000:34:00.0: restoring config space at offset 0x3 (was 0x0, writing 0x10)
>tg3 0000:34:00.0: restoring config space at offset 0x1 (was 0x100000, writing 0x100006)
>firewire_ohci 0000:10:0b.0: restoring config space at offset 0xf (was 0x180c0100, writing 0x180c010b)
>firewire_ohci 0000:10:0b.0: restoring config space at offset 0x4 (was 0x0, writing 0xf3300000)
>firewire_ohci 0000:10:0b.0: restoring config space at offset 0x3 (was 0x0, writing 0x2010)
>firewire_ohci 0000:10:0b.0: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900106)
>uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1a.0: setting latency timer to 64
>usb usb3: root hub lost power or was reset
>uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1a.1: setting latency timer to 64
>usb usb4: root hub lost power or was reset
>uhci_hcd 0000:00:1a.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1a.2: setting latency timer to 64
>usb usb5: root hub lost power or was reset
>ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>ehci_hcd 0000:00:1a.7: setting latency timer to 64
>uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>uhci_hcd 0000:00:1d.0: setting latency timer to 64
>usb usb6: root hub lost power or was reset
>uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
>uhci_hcd 0000:00:1d.1: setting latency timer to 64
>usb usb7: root hub lost power or was reset
>uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
>uhci_hcd 0000:00:1d.2: setting latency timer to 64
>usb usb8: root hub lost power or was reset
>ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>ehci_hcd 0000:00:1d.7: setting latency timer to 64
>pci 0000:00:1e.0: setting latency timer to 64
>ahci 0000:00:1f.2: setting latency timer to 64
>[drm] nouveau 0000:01:00.0: We're back, enabling device...
>nouveau 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>nouveau 0000:01:00.0: setting latency timer to 64
>[drm] nouveau 0000:01:00.0: POSTing device...
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 0 at offset 0x6EA7
>[drm] nouveau 0000:01:00.0: 0x6EA7: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x6EA7: [ (0x8C) - INIT_8C ]
>[drm] nouveau 0000:01:00.0: 0x6EA8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EA8: Reg: 0x00022210, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6EB5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6EBE: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EBE: Repeating following segment 20 times
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EC0: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000000, Data: 0x0A5C00A2
>[drm] nouveau 0000:01:00.0: 0x6ECD: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x6ECE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6ECE: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001084, Data: 0x00011469
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001084, Data: 0x00011C69
>[drm] nouveau 0000:01:00.0: 0x6EDB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7030003
>[drm] nouveau 0000:01:00.0: 0x6EE4: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6EE4: Condition: 0x10
>[drm] nouveau 0000:01:00.0: 0x6EE4: Cond: 0x10, Reg: 0x00021148, Mask: 0x000000FF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021148, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6EE4: Checking if 0x00000001 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EE4: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x6EE6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EF3: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6EF3: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x6EF4: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6EF4: Condition: 0x11
>[drm] nouveau 0000:01:00.0: 0x6EF4: Cond: 0x11, Reg: 0x00021144, Mask: 0x00000FFF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021144, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EF4: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EF4: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x6EF6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6EF6: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x6F03: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6F04: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F04: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x6F11: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F11: Reg: 0x0000C040, Mask: 0xCFFFEFFF, Data: 0x20001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000C040, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000C040, Data: 0x20001000
>[drm] nouveau 0000:01:00.0: 0x6F1E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 0x6F27: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F27: Reg: 0x00022210, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6F34: [ (0x8D) - INIT_8D ]
>[drm] nouveau 0000:01:00.0: 0x6F35: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x6F35: Executing subroutine at 0x6D6A
>[drm] nouveau 0000:01:00.0: 0x6D6A: [ (0x69) - INIT_IO ]
>[drm] nouveau 0000:01:00.0: 0x6D6A: Port: 0x03C3, Mask: 0x00, Data: 0x01
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614100, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x00800100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x00800100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0x9FF3F113
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00000200, Data: 0x9FF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00000200, Data: 0xDFF3F113
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x00800018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x00800018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614280, Data: 0x04840484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A80, Data: 0x04840484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615280, Data: 0x04840484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614200, Data: 0x0080008F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614200, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A00, Data: 0x0080008F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614108, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614108, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D6F: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x3F, Head: 0x00, Data: 0x57
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061943C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061943C, Data: 0x57000000
>[drm] nouveau 0000:01:00.0: 0x6D72: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D72: Reg: 0x00614200, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614200, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6D7F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D7F: Reg: 0x00614A00, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6D8C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D8C: Reg: 0x00614280, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6D99: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D99: Reg: 0x00614A80, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DA6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DA6: Reg: 0x00615280, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DB3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DB3: Reg: 0x00614300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DC0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DC0: Reg: 0x00614B00, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DCD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DCD: Reg: 0x00615300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615300, Data: 0x00800484
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615300, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DDA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DDA: Reg: 0x00614380, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DE7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DE7: Reg: 0x00614B80, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6DF4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6DF4: Reg: 0x00615380, Mask: 0xFFFFF0F8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:01:00.0: 0x6E01: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x6F35: End of 0x6D6A subroutine
>[drm] nouveau 0000:01:00.0: 0x6F38: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F38: Reg: 0x0000E108, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E108, Data: 0x4444444C
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E108, Data: 0x4444444C
>[drm] nouveau 0000:01:00.0: 0x6F45: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6F45: Reg: 0x0000E300, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E300, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 0x6F52: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6F52: BaseReg: 0x00020480, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020480, Data: 0x0000006D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020484, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6F60: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204C0, Data: 0x00000068
>[drm] nouveau 0000:01:00.0: 0x6F69: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204D8, Data: 0x00000069
>[drm] nouveau 0000:01:00.0: 0x6F72: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000204E0, Data: 0x00000066
>[drm] nouveau 0000:01:00.0: 0x6F7B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002041C, Data: 0x00000055
>[drm] nouveau 0000:01:00.0: 0x6F84: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6F84: BaseReg: 0x0002010C, Count: 0x06
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002010C, Data: 0x00000049
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020110, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020114, Data: 0x00B46600
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020118, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002011C, Data: 0x00765481
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020120, Data: 0x00000241
>[drm] nouveau 0000:01:00.0: 0x6FA2: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6FA2: BaseReg: 0x00020074, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020074, Data: 0x00000014
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020078, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FB0: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x6FB0: BaseReg: 0x00020094, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020094, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020098, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FBE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6FBE: Reg: 0x0000E1F4, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E1F4, Data: 0x0000002C
>[drm] nouveau 0000:01:00.0: 0x6FCB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0002004C, Data: 0x4407220B
>[drm] nouveau 0000:01:00.0: 0x6FD4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020424, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FDD: [ (0x8E) - INIT_GPIO ]
>[drm] nouveau 0000:01:00.0: 0x6FDE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E114, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6FE7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E118, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6FF0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E11C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x6FF9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E120, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7002: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7002: Reg: 0x0000E100, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E100, Data: 0x00000100
>[drm] nouveau 0000:01:00.0: 0x700F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020004, Data: 0x00100028
>[drm] nouveau 0000:01:00.0: 0x7018: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7018: Reg: 0x0008818C, Mask: 0x0FFFFFFE, Data: 0xE0000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008818C, Data: 0x50000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008818C, Data: 0xE0000001
>[drm] nouveau 0000:01:00.0: 0x7025: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x7025: Condition: 0x13
>[drm] nouveau 0000:01:00.0: 0x7025: Cond: 0x13, Reg: 0x00101000, Mask: 0x001C0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x1F4060AA
>[drm] nouveau 0000:01:00.0: 0x7025: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7025: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x7027: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089014, Data: 0x0000E020
>[drm] nouveau 0000:01:00.0: 0x7030: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089018, Data: 0x2140ED20
>[drm] nouveau 0000:01:00.0: 0x7039: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:01:00.0: 0x7039: ------ Skipping following commands  ------
>[drm] nouveau 0000:01:00.0: 0x703A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x7043: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x704C: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x704C: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x704D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x704D: Reg: 0x00004B28, Mask: 0xFFF07FFF, Data: 0x00088000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004B28, Data: 0x0006A927
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004B28, Data: 0x0008A927
>[drm] nouveau 0000:01:00.0: 0x705A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x705A: Reg: 0x0008907C, Mask: 0xFFFF0000, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008907C, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008907C, Data: 0x00000F0F
>[drm] nouveau 0000:01:00.0: 0x7067: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008848C, Data: 0x0118008C
>[drm] nouveau 0000:01:00.0: 0x7070: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7070: Reg: 0x0008A088, Mask: 0xFFFFFFFC, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008A088, Data: 0x11010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008A088, Data: 0x1101000B
>[drm] nouveau 0000:01:00.0: 0x707D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00089008, Data: 0x00004810
>[drm] nouveau 0000:01:00.0: 0x7086: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7086: Reg: 0x00088610, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088610, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088610, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 0x7093: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7093: Reg: 0x00001530, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001530, Data: 0x800492F0
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001530, Data: 0x800492F0
>[drm] nouveau 0000:01:00.0: 0x70A0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009220, Data: 0x00000412
>[drm] nouveau 0000:01:00.0: 0x70A9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009200, Data: 0x00000804
>[drm] nouveau 0000:01:00.0: 0x70B2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00009210, Data: 0x00000271
>[drm] nouveau 0000:01:00.0: 0x70BB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70BB: Reg: 0x00101000, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x1F4060AA
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x70C8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70C8: Reg: 0x0010100C, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0010100C, Data: 0x0001B010
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010100C, Data: 0x8001B010
>[drm] nouveau 0000:01:00.0: 0x70D5: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x70D5: Condition: 0x16
>[drm] nouveau 0000:01:00.0: 0x70D5: Cond: 0x16, Reg: 0x00101000, Mask: 0x0000003C
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x70D5: Checking if 0x00000028 equals 0x0000001C
>[drm] nouveau 0000:01:00.0: 0x70D5: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x70D7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70E4: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x70E4: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x70E5: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x70E5: Executing subroutine at 0x6E02
>[drm] nouveau 0000:01:00.0: 0x6E02: [ (0x37) - INIT_COPY ]
>[drm] nouveau 0000:01:00.0: 0x6E02: Reg: 0x00101000, Shift: 0x18, SrcMask: 0x0F, Port: 0x03D4, Index: 0x8B, Mask: 0xF0
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8B, Head: 0x00, Data: 0x0F
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619488, Data: 0x0F000000
>[drm] nouveau 0000:01:00.0: 0x6E0D: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E0D: SrcReg: 0x00614004, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x00610184, DstMask: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614004, Data: 0x7F304777
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00610184, Data: 0x7F700000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00610184, Data: 0x7F304777
>[drm] nouveau 0000:01:00.0: 0x6E23: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619F00, Data: 0x00000009
>[drm] nouveau 0000:01:00.0: 0x6E2C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x70E5: End of 0x6E02 subroutine
>[drm] nouveau 0000:01:00.0: 0x70E8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:01:00.0: 0x70F1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70F1: Reg: 0x0000E820, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01030008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01030018
>[drm] nouveau 0000:01:00.0: 0x70FE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x70FE: Reg: 0x0000E8A0, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 0x710B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x710B: Reg: 0x00004220, Mask: 0xFFFFFFED, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010018
>[drm] nouveau 0000:01:00.0: 0x7118: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7118: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:01:00.0: 0x711B: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x711B: Condition: 0x06, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x711B: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 0x711B: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711B: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x711B: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 0x711B: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711E: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x711F: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x711F: Condition: 0x08, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x711F: Cond: 0x08, Reg: 0x0000E8A0, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 0x711F: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x711F: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x711F: Cond: 0x08, Reg: 0x0000E8A0, Mask: 0x00010000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 0x711F: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:01:00.0: 0x7122: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7123: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7123: Reg: 0x0000E820, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010009
>[drm] nouveau 0000:01:00.0: 0x7130: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7130: Reg: 0x0000E8A0, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01010018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01010009
>[drm] nouveau 0000:01:00.0: 0x713D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x713D: Reg: 0x0000E830, Mask: 0x80000000, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E830, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E830, Data: 0x80291301
>[drm] nouveau 0000:01:00.0: 0x714A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x714A: Reg: 0x0000E8B0, Mask: 0x80000000, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8B0, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8B0, Data: 0x80191F01
>[drm] nouveau 0000:01:00.0: 0x7157: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004700, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x7160: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 0x7169: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7169: Condition: 0x07, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x7169: Cond: 0x07, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 0x7169: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7169: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x7169: Cond: 0x07, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 0x7169: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x716C: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x716D: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x716D: Condition: 0x09, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x716D: Cond: 0x09, Reg: 0x0000E8A0, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 0x716D: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x716D: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x716D: Cond: 0x09, Reg: 0x0000E8A0, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 0x716D: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7170: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7171: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7171: Reg: 0x0000E820, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x0103000D
>[drm] nouveau 0000:01:00.0: 0x717E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x717E: Reg: 0x0000E8A0, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x01030009
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x0103000D
>[drm] nouveau 0000:01:00.0: 0x718B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x718B: Reg: 0x0000E820, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E820, Data: 0x0103000D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E820, Data: 0x01030015
>[drm] nouveau 0000:01:00.0: 0x7198: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7198: Reg: 0x0000E8A0, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8A0, Data: 0x0103000D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8A0, Data: 0x01030015
>[drm] nouveau 0000:01:00.0: 0x71A5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71A5: Reg: 0x0000E82C, Mask: 0xFFFFFFF7, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x0000000D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 0x71B2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71B2: Reg: 0x0000E830, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E830, Data: 0x80291301
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E830, Data: 0x00291301
>[drm] nouveau 0000:01:00.0: 0x71BF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71BF: Reg: 0x0000E82C, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71CC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71CC: Reg: 0x0000E8AC, Mask: 0xFFFFFFF7, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8AC, Data: 0x0000000D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8AC, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 0x71D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71D9: Reg: 0x0000E8B0, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8B0, Data: 0x80191F01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8B0, Data: 0x00191F01
>[drm] nouveau 0000:01:00.0: 0x71E6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x71E6: Reg: 0x0000E8AC, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E8AC, Data: 0x00000005
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E8AC, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x71F3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004198, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 0x71FC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004190, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 0x7205: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7205: Executing subroutine at 0x6E40
>[drm] nouveau 0000:01:00.0: 0x6E40: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A0, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x6E49: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7205: End of 0x6E40 subroutine
>[drm] nouveau 0000:01:00.0: 0x7208: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00020131
>[drm] nouveau 0000:01:00.0: 0x7211: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004160, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x721A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004168, Data: 0x00080121
>[drm] nouveau 0000:01:00.0: 0x7223: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7223: Executing subroutine at 0x6E4A
>[drm] nouveau 0000:01:00.0: 0x6E4A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004180, Data: 0x00002140
>[drm] nouveau 0000:01:00.0: 0x6E53: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004184, Data: 0x00002140
>[drm] nouveau 0000:01:00.0: 0x6E5C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7223: End of 0x6E4A subroutine
>[drm] nouveau 0000:01:00.0: 0x7226: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A4, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 0x722F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041B4, Data: 0x000E0131
>[drm] nouveau 0000:01:00.0: 0x7238: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7238: Executing subroutine at 0x6E5D
>[drm] nouveau 0000:01:00.0: 0x6E5D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041BC, Data: 0x001C0141
>[drm] nouveau 0000:01:00.0: 0x6E66: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7238: End of 0x6E5D subroutine
>[drm] nouveau 0000:01:00.0: 0x723B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x723B: Reg: 0x00004198, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004198, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004198, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 0x7248: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7248: Reg: 0x00004190, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004190, Data: 0x001C0131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004190, Data: 0x001C3131
>[drm] nouveau 0000:01:00.0: 0x7255: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x7255: Executing subroutine at 0x6E67
>[drm] nouveau 0000:01:00.0: 0x6E67: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E67: Reg: 0x000041A0, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041A0, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A0, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x6E74: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x7255: End of 0x6E67 subroutine
>[drm] nouveau 0000:01:00.0: 0x7258: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7258: Reg: 0x00004164, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004164, Data: 0x00020131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00023131
>[drm] nouveau 0000:01:00.0: 0x7265: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7265: Reg: 0x00004160, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004160, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004160, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x7272: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7272: Reg: 0x00004168, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004168, Data: 0x00080121
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004168, Data: 0x00083121
>[drm] nouveau 0000:01:00.0: 0x727F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x727F: Reg: 0x000041A4, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041A4, Data: 0x00060131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041A4, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x728C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x728C: Reg: 0x000041B4, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041B4, Data: 0x000E0131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041B4, Data: 0x000E3131
>[drm] nouveau 0000:01:00.0: 0x7299: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010A020, Data: 0x00031704
>[drm] nouveau 0000:01:00.0: 0x72A2: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72A2: Executing subroutine at 0x6E75
>[drm] nouveau 0000:01:00.0: 0x6E75: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6E75: Reg: 0x000041BC, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x000041BC, Data: 0x001C0141
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x000041BC, Data: 0x001C2141
>[drm] nouveau 0000:01:00.0: 0x6E82: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72A2: End of 0x6E75 subroutine
>[drm] nouveau 0000:01:00.0: 0x72A5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72A5: Reg: 0x00004200, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:01:00.0: 0x72B2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72B2: Reg: 0x00004220, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010018
>[drm] nouveau 0000:01:00.0: 0x72BF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x72BF: Reg: 0x00004000, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004000, Data: 0x18010008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004000, Data: 0x18010008
>[drm] nouveau 0000:01:00.0: 0x72CC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004120, Data: 0x00063031
>[drm] nouveau 0000:01:00.0: 0x72D5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004124, Data: 0x00063031
>[drm] nouveau 0000:01:00.0: 0x72DE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004128, Data: 0x00063020
>[drm] nouveau 0000:01:00.0: 0x72E7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004140, Data: 0x001C0100
>[drm] nouveau 0000:01:00.0: 0x72F0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004144, Data: 0x001C0100
>[drm] nouveau 0000:01:00.0: 0x72F9: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72F9: Executing subroutine at 0x6E2D
>[drm] nouveau 0000:01:00.0: 0x6E2D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614100, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 0x6E36: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:01:00.0: 0x6E3F: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72F9: End of 0x6E2D subroutine
>[drm] nouveau 0000:01:00.0: 0x72FC: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x72FC: Executing subroutine at 0x7312
>[drm] nouveau 0000:01:00.0: 0x7312: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7313: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7313: Reg: 0x00004124, Mask: 0xFFFFCEFF, Data: 0x00003100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004124, Data: 0x00063031
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004124, Data: 0x00063131
>[drm] nouveau 0000:01:00.0: 0x7320: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004224, Data: 0x00021405
>[drm] nouveau 0000:01:00.0: 0x7329: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7329: Reg: 0x00004220, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00010009
>[drm] nouveau 0000:01:00.0: 0x7336: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x7336: Condition: 0x14, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x7336: Cond: 0x14, Reg: 0x00004220, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00030009
>[drm] nouveau 0000:01:00.0: 0x7336: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7336: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x7336: Cond: 0x14, Reg: 0x00004220, Mask: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00030009
>[drm] nouveau 0000:01:00.0: 0x7336: Checking if 0x00020000 equals 0x00020000
>[drm] nouveau 0000:01:00.0: 0x7339: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x733A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x733A: Reg: 0x00004220, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x00030009
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x0003000D
>[drm] nouveau 0000:01:00.0: 0x7347: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7347: Reg: 0x00004220, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004220, Data: 0x0003000D
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004220, Data: 0x00030015
>[drm] nouveau 0000:01:00.0: 0x7354: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x7354: Reg: 0x00004164, Mask: 0xFFFFFEFE, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004164, Data: 0x00023131
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004164, Data: 0x00023030
>[drm] nouveau 0000:01:00.0: 0x7361: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x7362: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x72FC: End of 0x7312 subroutine
>[drm] nouveau 0000:01:00.0: 0x72FF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000C044, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7308: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001538, Data: 0x00011111
>[drm] nouveau 0000:01:00.0: 0x7311: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 1 at offset 0x7363
>[drm] nouveau 0000:01:00.0: 0x7363: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x7363: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7363: Reg: 0x00100710, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x738A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x738A: Reg: 0x00100718, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100718, Data: 0x40055F77
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010071C, Data: 0x40044F77
>[drm] nouveau 0000:01:00.0: 0x73D1: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x73D1: Reg: 0x00100720, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100720, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100724, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 0x7418: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7418: Reg: 0x001111E0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001111E0, Data: 0x02000101
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001111E4, Data: 0x02000101
>[drm] nouveau 0000:01:00.0: 0x745F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x745F: Reg: 0x00111120, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111120, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111124, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x74A6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x74A6: Reg: 0x00111380, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111380, Data: 0x80000606
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111384, Data: 0x80000606
>[drm] nouveau 0000:01:00.0: 0x74ED: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x74ED: Reg: 0x001008A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008A0, Data: 0x8700580A
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008A4, Data: 0x8700580A
>[drm] nouveau 0000:01:00.0: 0x7534: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7534: Reg: 0x00111180, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111180, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111184, Data: 0x77777777
>[drm] nouveau 0000:01:00.0: 0x757B: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x757B: Reg: 0x00111000, RegIncrement: 0x08, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111000, Data: 0x70077007
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111008, Data: 0x70077007
>[drm] nouveau 0000:01:00.0: 0x75C2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x75C2: Reg: 0x00110560, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110560, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105C0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110620, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110680, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106E0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110740, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107A0, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110800, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x76C9: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x76C9: Reg: 0x00110564, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110564, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105C4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110624, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110684, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106E4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110744, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107A4, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110804, Data: 0x02020202
>[drm] nouveau 0000:01:00.0: 0x77D0: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x77D0: Reg: 0x001105A0, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105A0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110600, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110660, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106C0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110720, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110780, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107E0, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110840, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 0x78D7: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x78D7: Reg: 0x001105A4, RegIncrement: 0x60, Count: 0x08, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001105A4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110604, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110664, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001106C4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110724, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110784, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001107E4, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00110844, Data: 0x00040302
>[drm] nouveau 0000:01:00.0: 0x79DE: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x79DE: Reg: 0x00100D80, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100D80, Data: 0xAAAAAAAA
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100D84, Data: 0xAAAAAAAA
>[drm] nouveau 0000:01:00.0: 0x7A25: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7A25: Reg: 0x001009E4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001009E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7A4C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7A4C: Reg: 0x001009DC, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001009DC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7A73: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x7A73: BaseReg: 0x00100920, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100920, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100924, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 0x7A81: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x7A81: BaseReg: 0x00100900, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100900, Data: 0x0F0F0F0F
>ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100904, Data: 0x0F0F0F0F
>[drm] nouveau 0000:01:00.0: 0x7A8F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7A8F: Reg: 0x00100940, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100940, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100944, Data: 0x00000000
>ata4: SATA link down (SStatus 0 SControl 300)
>[drm] nouveau 0000:01:00.0: 0x7AD6: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>ata5: SATA link down (SStatus 0 SControl 300)
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7AD6: Reg: 0x00100A20, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A20, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A24, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7B1D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7B1D: Reg: 0x00100A40, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A40, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A44, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7B64: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7B64: Reg: 0x00100A60, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>ata6: SATA link down (SStatus 0 SControl 300)
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A60, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A64, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7BAB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7BAB: Reg: 0x00100A80, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A80, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100A84, Data: 0x00000000
>ata3: SATA link down (SStatus 0 SControl 300)
>[drm] nouveau 0000:01:00.0: 0x7BF2: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>ata2.00: configured for UDMA/100
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7BF2: Reg: 0x00100AA0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AA0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AA4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7C39: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7C39: Reg: 0x00100AC0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AC0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AC4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7C80: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7C80: Reg: 0x00111400, RegIncrement: 0x20, Count: 0x06, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111400, Data: 0x000F0F00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111420, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111440, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111460, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111480, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001114A0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7D47: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7D47: Reg: 0x00111404, RegIncrement: 0x20, Count: 0x06, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111404, Data: 0x000F0F00
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111424, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111444, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111464, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111484, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001114A4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7E0E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7E0E: Reg: 0x00100DC0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DC0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DC4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7E55: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7E55: Reg: 0x001005A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001005A0, Data: 0x00202020
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001005A4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7E9C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0xFFFFFFFF
>[drm] nouveau 0000:01:00.0: 0x7E9C: Reg: 0x0010F804, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0F, Index: 0x07
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010F804, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x7EC3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7EC3: Reg: 0x0010053C, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010053C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7EEA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7EEA: Reg: 0x00100760, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100760, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100764, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 0x7F31: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7F31: Reg: 0x00100780, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100780, Data: 0x27777774
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100784, Data: 0x27777774
>[drm] nouveau 0000:01:00.0: 0x7F78: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7F78: Reg: 0x001007A0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007A0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007A4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x7FBF: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x7FBF: Reg: 0x001007C0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007C0, Data: 0x55555555
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007C4, Data: 0x55555555
>[drm] nouveau 0000:01:00.0: 0x8006: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8006: Reg: 0x001007E0, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007E0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001007E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x804D: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x804D: Reg: 0x00100800, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100800, Data: 0xDDDDDDDD
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100804, Data: 0xDDDDDDDD
>[drm] nouveau 0000:01:00.0: 0x8094: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8094: Reg: 0x00100820, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100820, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100824, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x80DB: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x80DB: Reg: 0x00100840, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100840, Data: 0xBCCBCBBB
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100844, Data: 0xBCCBCBBB
>[drm] nouveau 0000:01:00.0: 0x8122: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8122: Reg: 0x00100860, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100860, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100864, Data: 0x11111111
>[drm] nouveau 0000:01:00.0: 0x8169: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8169: Reg: 0x00100880, RegIncrement: 0x04, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100880, Data: 0x98986997
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100884, Data: 0x98986997
>[drm] nouveau 0000:01:00.0: 0x81B0: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x81B0: Reg: 0x00100714, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100714, Data: 0xF0000001
>[drm] nouveau 0000:01:00.0: 0x81D7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100700, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x81E0: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x81E0: BaseReg: 0x00100740, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100740, Data: 0x07000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100744, Data: 0x07000000
>[drm] nouveau 0000:01:00.0: 0x81EE: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x81EE: BaseReg: 0x00100DA0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DA0, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100DA4, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 0x81FC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x81FC: Reg: 0x00111104, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111104, Data: 0x000009FF
>[drm] nouveau 0000:01:00.0: 0x8223: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x8223: BaseReg: 0x001110C0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110C0, Data: 0x00001801
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110C4, Data: 0x00001801
>[drm] nouveau 0000:01:00.0: 0x8231: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:01:00.0: 0x8231: BaseReg: 0x001110E0, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110E0, Data: 0x80099000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001110E4, Data: 0x80099000
>[drm] nouveau 0000:01:00.0: 0x823F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x823F: Reg: 0x00111100, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00111100, Data: 0x08000004
>[drm] nouveau 0000:01:00.0: 0x8266: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010024C, Data: 0x0F000080
>[drm] nouveau 0000:01:00.0: 0x826F: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x826F: Reg: 0x00100254, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100254, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8296: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8296: Reg: 0x00100500, Mask: 0xFFF0FF01, Data: 0x000A00FE
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100500, Data: 0x00311621
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100500, Data: 0x003A16FF
>[drm] nouveau 0000:01:00.0: 0x82A3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x82A3: Reg: 0x00100220, RegIncrement: 0x04, Count: 0x0B, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100220, Data: 0x050C2411
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100224, Data: 0x0C030A06
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100228, Data: 0x04040505
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010022C, Data: 0x362D1105
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100230, Data: 0x0F030A0A
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100234, Data: 0x24050B05
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100238, Data: 0x00600551
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010023C, Data: 0x0F120202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100240, Data: 0x111D0700
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100244, Data: 0x00000347
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100248, Data: 0x0200270C
>[drm] nouveau 0000:01:00.0: 0x840A: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x840A: Reg: 0x00100258, RegIncrement: 0x08, Count: 0x02, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100258, Data: 0x00400200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100260, Data: 0x00C35000
>[drm] nouveau 0000:01:00.0: 0x8451: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8451: Reg: 0x00100268, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100268, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100268, Data: 0x30030200
>[drm] nouveau 0000:01:00.0: 0x845E: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x845E: Reg: 0x00100200, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x8485: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8485: Reg: 0x00100204, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100204, Data: 0x0155A020
>[drm] nouveau 0000:01:00.0: 0x84AC: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x84AC: Reg: 0x00100250, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100250, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x84D3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000122C, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 0x84DC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84DC: Reg: 0x001008CC, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008CC, Data: 0x04000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008CC, Data: 0x04000009
>[drm] nouveau 0000:01:00.0: 0x84E9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84E9: Reg: 0x001008E0, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800D1210
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008E0, Data: 0x000D1210
>[drm] nouveau 0000:01:00.0: 0x84F6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x84F6: Reg: 0x001008CC, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008CC, Data: 0x04000001
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008CC, Data: 0x04000009
>[drm] nouveau 0000:01:00.0: 0x8503: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8503: Condition: 0x0C, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x8503: Cond: 0x0C, Reg: 0x001008E0, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800D1211
>[drm] nouveau 0000:01:00.0: 0x8503: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x8503: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x8503: Cond: 0x0C, Reg: 0x001008E0, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x001008E0, Data: 0x800C1211
>[drm] nouveau 0000:01:00.0: 0x8503: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x8506: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8507: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AE0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8510: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AE8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8519: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100AF0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8522: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8522: Sleeping for 0x0FA0 microseconds
>[drm] nouveau 0000:01:00.0: 0x8525: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x8525: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8527: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000000
>[drm] nouveau 0000:01:00.0: 0x8530: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8530: Sleeping for 0x00C8 microseconds
>[drm] nouveau 0000:01:00.0: 0x8533: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010021C, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x853C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000100
>[drm] nouveau 0000:01:00.0: 0x8545: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8545: Sleeping for 0x01F4 microseconds
>[drm] nouveau 0000:01:00.0: 0x8548: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100080, Data: 0x00000020
>[drm] nouveau 0000:01:00.0: 0x8551: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100440, Data: 0x8050000B
>[drm] nouveau 0000:01:00.0: 0x855A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8563: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100218, Data: 0x01000101
>[drm] nouveau 0000:01:00.0: 0x856C: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x856C: Reg: 0x001002E0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002E0, Data: 0x00200080
>[drm] nouveau 0000:01:00.0: 0x8593: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x8593: Reg: 0x001002E4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002E4, Data: 0x00300000
>[drm] nouveau 0000:01:00.0: 0x85BA: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x85BA: Reg: 0x001002C4, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002C4, Data: 0x00100002
>[drm] nouveau 0000:01:00.0: 0x85E1: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x85E1: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x85E3: [ (0x8F) - INIT_RAM_RESTRICT_ZM_REG_GROUP ]
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00101000, Data: 0x9F4060AA
>[drm] nouveau 0000:01:00.0: 0x85E3: Reg: 0x001002C0, RegIncrement: 0x04, Count: 0x01, StrapRamCfg: 0x0A, Index: 0x02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002C0, Data: 0x00001520
>[drm] nouveau 0000:01:00.0: 0x860A: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x860A: Condition: 0x0D
>[drm] nouveau 0000:01:00.0: 0x860A: Cond: 0x0D, Reg: 0x00100200, Mask: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x860A: Checking if 0x00000000 equals 0x00000004
>[drm] nouveau 0000:01:00.0: 0x860A: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x860C: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8615: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x861E: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8627: [ (0x90) - INIT_COPY_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x8630: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8630: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x8631: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x8631: Condition: 0x12
>[drm] nouveau 0000:01:00.0: 0x8631: Cond: 0x12, Reg: 0x00100710, Mask: 0x00000080
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x8631: Checking if 0x00000000 equals 0x00000080
>[drm] nouveau 0000:01:00.0: 0x8631: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x8633: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8640: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x8640: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x8641: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D8, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x864A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100264, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8653: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8653: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x8656: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x8656: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8658: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x8658: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x865B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100210, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x8664: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0010025C, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x866D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x866D: Reg: 0x00004018, Mask: 0xFFFF3FFF, Data: 0x0000C000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00004018, Data: 0x1000D000
>[drm] nouveau 0000:01:00.0: 0x867A: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x867A: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x867D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 2 at offset 0x867F
>[drm] nouveau 0000:01:00.0: 0x867F: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x867F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001008C0, Data: 0x9D0A0293
>[drm] nouveau 0000:01:00.0: 0x8688: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000108C, Data: 0x000000D1
>[drm] nouveau 0000:01:00.0: 0x8691: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8691: Executing subroutine at 0x6E83
>[drm] nouveau 0000:01:00.0: 0x6E83: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xF0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194F0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194F0, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6E86: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:01:00.0: 0x6E86: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x08, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x08
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x09
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000008
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000009
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 0x6E8D: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:01:00.0: 0x6E8D: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x18, Count: 0x02
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x18
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000018
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A0, Data: 0x10000000
>[drm] nouveau 0000:01:00.0: 0x6E94: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:01:00.0: 0x6E94: Index: 0x88, Mask: 0xBF, Data: 0x40
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x0F000000
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x40
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x0F000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619488, Data: 0x0F000040
>[drm] nouveau 0000:01:00.0: 0x6E98: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:01:00.0: 0x6E98: Index: 0x8A, Mask: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x0F000040
>[drm] nouveau 0000:01:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619488, Data: 0x0F000040
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619488, Data: 0x0F000040
>[drm] nouveau 0000:01:00.0: 0x6E9C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8691: End of 0x6E83 subroutine
>[drm] nouveau 0000:01:00.0: 0x8694: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E200, Data: 0x0003103C
>[drm] nouveau 0000:01:00.0: 0x869D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x869D: Executing subroutine at 0x6E9D
>[drm] nouveau 0000:01:00.0: 0x6E9D: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x30, Head: 0x00, Data: 0x10
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619430, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 0x6EA0: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x31, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619430, Data: 0x00000010
>[drm] nouveau 0000:01:00.0: 0x6EA3: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xAA, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x006194A8, Data: 0x00020000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x006194A8, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6EA6: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x869D: End of 0x6E9D subroutine
>[drm] nouveau 0000:01:00.0: 0x86A0: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 3 at offset 0x86A1
>[drm] nouveau 0000:01:00.0: 0x86A1: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x86A1: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x86A1: Executing subroutine at 0x5EE3
>[drm] nouveau 0000:01:00.0: 0x5EE3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x86A1: End of 0x5EE3 subroutine
>[drm] nouveau 0000:01:00.0: 0x86A4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:01:00.0: 0x86A4: Sleeping for 0x03E8 microseconds
>[drm] nouveau 0000:01:00.0: 0x86A7: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x86A7: Executing subroutine at 0x867E
>[drm] nouveau 0000:01:00.0: 0x867E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x86A7: End of 0x867E subroutine
>[drm] nouveau 0000:01:00.0: 0x86AA: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AA: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86AC: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AC: Repeating following segment 10 times
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86AE: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86AE: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B0: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:01:00.0: 0x86B1: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B1: Macro: 0x00, MacroTableIndex: 0x00, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D4, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B3: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B3: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B5: [ (0x6F) - INIT_MACRO ]
>[drm] nouveau 0000:01:00.0: 0x86B5: Macro: 0x01, MacroTableIndex: 0x01, Count: 0x01
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x001002D0, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x86B7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100210, Data: 0x80000001
>[drm] nouveau 0000:01:00.0: 0x86C0: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86C0: Condition: 0x0E
>[drm] nouveau 0000:01:00.0: 0x86C0: Cond: 0x0E, Reg: 0x00100268, Mask: 0x30000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100268, Data: 0x30030200
>[drm] nouveau 0000:01:00.0: 0x86C0: Checking if 0x30000000 equals 0x30000000
>[drm] nouveau 0000:01:00.0: 0x86C0: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:01:00.0: 0x86C2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86C2: Reg: 0x00100C00, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100C00, Data: 0xFC84418F
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100C00, Data: 0xFC84418B
>[drm] nouveau 0000:01:00.0: 0x86CF: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86CF: Condition: 0x0F
>[drm] nouveau 0000:01:00.0: 0x86CF: Cond: 0x0F, Reg: 0x00001540, Mask: 0x00FF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x86CF: Checking if 0x00020000 equals 0x00030000
>[drm] nouveau 0000:01:00.0: 0x86CF: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x86D1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86DE: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x86DE: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x86DF: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86DF: Condition: 0x0F
>[drm] nouveau 0000:01:00.0: 0x86DF: Cond: 0x0F, Reg: 0x00001540, Mask: 0x00FF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7020003
>[drm] nouveau 0000:01:00.0: 0x86DF: Checking if 0x00020000 equals 0x00030000
>[drm] nouveau 0000:01:00.0: 0x86DF: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x86E1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86EE: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x86F0: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86FD: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x86FD: ---- Executing following commands ----
>[drm] nouveau 0000:01:00.0: 0x86FE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x86FE: Reg: 0x00100710, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100710, Data: 0x30000200
>[drm] nouveau 0000:01:00.0: 0x870B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x870B: Reg: 0x00100E04, Mask: 0xFFE0007F, Data: 0x00064C80
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100E04, Data: 0x800B1604
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100E04, Data: 0x80064C84
>[drm] nouveau 0000:01:00.0: 0x8718: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8718: Reg: 0x00100E08, Mask: 0xF01FFFFF, Data: 0x0B000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100E08, Data: 0x06448808
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100E08, Data: 0x0B048808
>[drm] nouveau 0000:01:00.0: 0x8725: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8725: Reg: 0x00100200, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100200, Data: 0x00222800
>[drm] nouveau 0000:01:00.0: 0x8732: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8732: Reg: 0x00100600, Mask: 0xFFFFFFFF, Data: 0x00004000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100600, Data: 0x97030610
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100600, Data: 0x97034610
>[drm] nouveau 0000:01:00.0: 0x873F: [ (0x63) - INIT_COMPUTE_MEM ]
>[drm] nouveau 0000:01:00.0: 0x8740: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8740: Executing subroutine at 0x6C21
>[drm] nouveau 0000:01:00.0: 0x6C21: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C21: Reg: 0x00614000, Mask: 0xFFFFEFFF, Data: 0x00001000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00614000, Data: 0x01000210
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00614000, Data: 0x01001210
>[drm] nouveau 0000:01:00.0: 0x6C2E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A008, Data: 0x03A502D1
>[drm] nouveau 0000:01:00.0: 0x6C37: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x6C37: Condition: 0x0A
>[drm] nouveau 0000:01:00.0: 0x6C37: Cond: 0x0A, Reg: 0x00021218, Mask: 0x000000FF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021218, Data: 0x00000023
>[drm] nouveau 0000:01:00.0: 0x6C37: Checking if 0x00000023 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6C37: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:01:00.0: 0x6C39: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C42: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C4B: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:01:00.0: 0x6C4B: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x6C4C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C4C: Reg: 0x0061A068, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A068, Data: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A068, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 0x6C59: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C59: Reg: 0x0061A868, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A868, Data: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A868, Data: 0x44000000
>[drm] nouveau 0000:01:00.0: 0x6C66: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C66: SrcReg: 0x00021350, Shift: 0x00, SrcMask: 0x000001FF, Xor: 0x00000000, DstReg: 0x0061A870, DstMask: 0xFFFFFE00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021350, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A870, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A870, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 0x6C7C: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6C7C: SrcReg: 0x00021354, Shift: 0x00, SrcMask: 0x000001FF, Xor: 0x00000000, DstReg: 0x0061A070, DstMask: 0xFFFFFE00
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00021354, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061A070, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A070, Data: 0x00000124
>[drm] nouveau 0000:01:00.0: 0x6C92: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6C93: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A030, Data: 0x000415F1
>[drm] nouveau 0000:01:00.0: 0x6C9C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061A830, Data: 0x000415F1
>[drm] nouveau 0000:01:00.0: 0x6CA5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CA5: Reg: 0x0000E50C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E50C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E50C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CB2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CB2: Reg: 0x0000E55C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E55C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E55C, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CBF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CBF: Reg: 0x0000E5AC, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5AC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5AC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CCC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CCC: Reg: 0x0000E5FC, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5FC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5FC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6CD9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CD9: Reg: 0x0000E500, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E500, Data: 0x00000462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E500, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6CE6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CE6: Reg: 0x0000E550, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E550, Data: 0x00000462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E550, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6CF3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6CF3: Reg: 0x0000E5A0, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5A0, Data: 0x00000462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5A0, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6D00: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D00: Reg: 0x0000E5F0, Mask: 0xFFFFCFFF, Data: 0x00002000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E5F0, Data: 0x00000462
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E5F0, Data: 0x00002462
>[drm] nouveau 0000:01:00.0: 0x6D0D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D0D: Reg: 0x0061E818, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061E818, Data: 0x00000302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061E818, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 0x6D1A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D1A: Reg: 0x0061F018, Mask: 0xFFFFFFF3, Data: 0x00000004
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061F018, Data: 0x00000302
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061F018, Data: 0x00000306
>[drm] nouveau 0000:01:00.0: 0x6D27: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8740: End of 0x6C21 subroutine
>[drm] nouveau 0000:01:00.0: 0x8743: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8743: Reg: 0x00100674, Mask: 0xFFFF0000, Data: 0x00000404
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00100674, Data: 0x00020202
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00100674, Data: 0x00020404
>[drm] nouveau 0000:01:00.0: 0x8750: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8750: Reg: 0x00001558, Mask: 0xFFFFFFFC, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001558, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001558, Data: 0x00000003
>[drm] nouveau 0000:01:00.0: 0x875D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001588, Data: 0x00000001
>[drm] nouveau 0000:01:00.0: 0x8766: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8766: Reg: 0x00020060, Mask: 0x00C0FFFF, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:01:00.0: 0x8773: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020080, Data: 0x100C0736
>[drm] nouveau 0000:01:00.0: 0x877C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x877C: Reg: 0x00020018, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00020018, Data: 0x9E9C9A98
>[drm] nouveau 0000:01:00.0: 0x8789: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x8789: Reg: 0x0008814C, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008814C, Data: 0x0300001B
>[drm] nouveau 0000:01:00.0: 0x8796: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088154, Data: 0x00007120
>[drm] nouveau 0000:01:00.0: 0x879F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x879F: Reg: 0x0008813C, Mask: 0x0FFFFFFF, Data: 0x60000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0008813C, Data: 0x33FF0000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008813C, Data: 0x63FF0000
>[drm] nouveau 0000:01:00.0: 0x87AC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87AC: Reg: 0x00088150, Mask: 0xFFFFFE7F, Data: 0x00000180
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088150, Data: 0x0E00FF95
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088150, Data: 0x0E00FF95
>[drm] nouveau 0000:01:00.0: 0x87B9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0008845C, Data: 0x90000000
>[drm] nouveau 0000:01:00.0: 0x87C2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87C2: Reg: 0x00088158, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00088158, Data: 0x00000F02
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00088158, Data: 0x00000F02
>[drm] nouveau 0000:01:00.0: 0x87CF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00082000, Data: 0x00000002
>[drm] nouveau 0000:01:00.0: 0x87D8: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x87D8: Executing subroutine at 0x6D28
>[drm] nouveau 0000:01:00.0: 0x6D28: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C080, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D31: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061C084, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D3A: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:01:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x85, Head: 0x00, Data: 0xFF
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00619484, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00619484, Data: 0x0000FF00
>[drm] nouveau 0000:01:00.0: 0x6D3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x87D8: End of 0x6D28 subroutine
>[drm] nouveau 0000:01:00.0: 0x87DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87DB: Reg: 0x0000E1E4, Mask: 0xFFFFFFFC, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E1E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E1E4, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 0x87E8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87E8: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00001084, Data: 0x00011C69
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x00001084, Data: 0x00011469
>[drm] nouveau 0000:01:00.0: 0x87F5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x87F5: Reg: 0x0000E690, Mask: 0xFF88FFFF, Data: 0x00000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0000E690, Data: 0xF4770204
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0000E690, Data: 0xF4000204
>[drm] nouveau 0000:01:00.0: 0x8802: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table 4 at offset 0x8803
>[drm] nouveau 0000:01:00.0: 0x8803: ------ Executing following commands ------
>[drm] nouveau 0000:01:00.0: 0x8803: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Parsing VBIOS init table at offset 0x8868
>[drm] nouveau 0000:01:00.0: 0x8868: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:01:00.0: 0x8868: Executing subroutine at 0x6D3E
>[drm] nouveau 0000:01:00.0: 0x6D3E: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x6D3E: Condition: 0x01, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x6D3E: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D3E: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D3E: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x6D3E: Cond: 0x01, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D3E: Checking if 0x80000000 equals 0x80000000
>[drm] nouveau 0000:01:00.0: 0x6D41: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6D42: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D42: SrcReg: 0x00610000, Shift: 0x00, SrcMask: 0x0000FFFF, Xor: 0x00000000, DstReg: 0x0061000C, DstMask: 0xFFFF0000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x00610000, Data: 0x857D0150
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000000
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061000C, Data: 0x80000150
>[drm] nouveau 0000:01:00.0: 0x6D58: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x6D58: Reg: 0x0061000C, Mask: 0xBFFFFFFF, Data: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000150
>[drm] nouveau 0000:01:00.0: 	Write: Reg: 0x0061000C, Data: 0xC0000150
>[drm] nouveau 0000:01:00.0: 0x6D65: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:01:00.0: 0x6D65: Condition: 0x02, Retries: 0x64
>[drm] nouveau 0000:01:00.0: 0x6D65: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0xC0000150
>[drm] nouveau 0000:01:00.0: 0x6D65: Checking if 0x40000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D65: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:01:00.0: 0x6D65: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000150
>[drm] nouveau 0000:01:00.0: 0x6D65: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D65: Condition met, continuing
>[drm] nouveau 0000:01:00.0: 0x6D65: Cond: 0x02, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:01:00.0: 	Read:  Reg: 0x0061000C, Data: 0x80000150
>[drm] nouveau 0000:01:00.0: 0x6D65: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:01:00.0: 0x6D68: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:01:00.0: 0x6D69: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: 0x8868: End of 0x6D3E subroutine
>[drm] nouveau 0000:01:00.0: 0x886B: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 0 0 2
>[drm] nouveau 0000:01:00.0: output script 0 not found
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 8
>[drm] nouveau 0000:01:00.0: 0x57EB: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x57EB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:01:00.0: 0x5CE6: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x5CE6: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:01:00.0: 0x5CE6: subop 0x00
>[drm] nouveau 0000:01:00.0: 0x5CE6: skipping following commands
>[drm] nouveau 0000:01:00.0: 0x5CE9: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x5CF2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:01:00.0: 0x5CFB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x5D08: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:01:00.0: 0x5D15: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:01:00.0: 0x57EB: parsing output script 0
>[drm] nouveau 0000:01:00.0: 0x57EB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:01:00.0: Restoring GPU objects...
>[drm] nouveau 0000:01:00.0: Reinitialising engines...
>[drm] nouveau 0000:01:00.0: nv50_graph_init:131 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init:166 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_reset:99 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_intr:108 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_context_table:121 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch1
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch2
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch3
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch4
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch5
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch6
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch7
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch8
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch9
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch10
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch11
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch12
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch13
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch14
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch15
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch16
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch17
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch18
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch19
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch20
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch21
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch22
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch23
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch24
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch25
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch26
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch27
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch28
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch29
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch30
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch31
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch32
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch33
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch34
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch35
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch36
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch37
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch38
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch39
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch40
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch41
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch42
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch43
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch44
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch45
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch46
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch47
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch48
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch49
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch50
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch51
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch52
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch53
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch54
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch55
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch56
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch57
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch58
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch59
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch60
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch61
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch62
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch63
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch64
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch65
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch66
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch67
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch68
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch69
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch70
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch71
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch72
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch73
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch74
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch75
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch76
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch77
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch78
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch79
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch80
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch81
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch82
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch83
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch84
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch85
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch86
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch87
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch88
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch89
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch90
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch91
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch92
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch93
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch94
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch95
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch96
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch97
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch98
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch99
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch100
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch101
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch102
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch103
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch104
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch105
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch106
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch107
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch108
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch109
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch110
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch111
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch112
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch113
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch114
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch115
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch116
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch117
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch118
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch119
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch120
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch121
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch122
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch123
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch124
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch125
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_disable:85 - ch126
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:01:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_regs__nv:136 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_init_regs:144 - 
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:01:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:01:00.0: Restoring mode...
>[drm] nouveau 0000:01:00.0: nouveau_sgdma_destroy:25 - 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:45] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020040000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020050000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020060000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020070000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020100000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020110000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020120000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020130000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020140000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020150000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020160000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020170000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020180000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020190000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201a0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201b0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201c0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201d0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201e0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x00201f0000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: nv50_display_init:147 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0100 Data 0x00000000 (0x0000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0104 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0108 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x010c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0110 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0114 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 3
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0100 Data 0x00000000 (0x0084 0x04)
>[drm:drm_crtc_helper_set_mode], 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[ENCODER:15:TMDS-15] set [MODE:43:1280x1024]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0124 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0128 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x012c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x011c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0120 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0124 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00060000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0128 Data 0x00000000 (0x1000 0x03)
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:44:1280x1024]
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0840 Data 0x00000000 (0x0000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00060000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x012c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0844 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00020000 0x00000000
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: EvoCh 1 Mthd 0x0000 Data 0x00000000 (0x1001 0x01)
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0874 Data 0x01000003 (0x1000 0x07)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0080 Data 0x00080860 (0x1084 0x04)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0080 Data 0x00000000 (0x1005 0x05)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0c6c Data 0x00040640 (0x1084 0x04)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0c70 Data 0x00000102 (0x1084 0x04)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0c74 Data 0x01000003 (0x1000 0x07)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0080 Data 0x00000000 (0x1005 0x05)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00040000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0c40 Data 0xc0000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nouveau_sgdma_destroy:25 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00040000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0840 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00040000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0844 Data 0xf00d000e (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00040000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 2 Mthd 0x0000 Data 0x00000000 (0x1001 0x01)
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>snd_hda_intel 0000:01:00.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>snd_hda_intel 0000:01:00.1: setting latency timer to 64
>tg3 0000:34:00.0: PME# disabled
>firewire_core: skipped bus generations, destroying all nodes
>parport_pc 00:07: activated
>serial 00:08: activated
>firewire_core: rediscovered device fw0
>usb 8-1: reset low speed USB device number 2 using uhci_hcd
>sd 0:0:0:0: [sda] Starting disk
>ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>ata1.00: configured for UDMA/100
>__ratelimit: 40 callbacks suppressed
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0020040000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/FB reason: PAGE_SYSTEM_ONLY
>Restarting tasks ... 
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP_M2MF NOTIFY
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP_M2MF 00304041 0000f410 00000000 06000e04
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP
>[drm] nouveau 0000:01:00.0: PGRAPH - ch 2 (0x0000930000) subc 0 class 0x5039 mthd 0x0100 data 0x00000000
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0000000010 on ch 2 [0x00000930] PGRAPH/DISPATCH/M2M_NOTIFY reason: PT_NOT_PRESENT
>[drm] nouveau 0000:01:00.0: magic set 0:
>[drm] nouveau 0000:01:00.0: 	0x00408604: 0x2008bf01
>[drm] nouveau 0000:01:00.0: 	0x00408608: 0x00009970
>[drm] nouveau 0000:01:00.0: 	0x0040860c: 0x80000e04
>[drm] nouveau 0000:01:00.0: 	0x00408610: 0x05500000
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP_TEXTURE - TP0: Unhandled ustatus 0x00000009
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP_TPDMA - TP0: Unhandled ustatus 0x00000800
>[drm] nouveau 0000:01:00.0: PGRAPH - TRAP
>[drm] nouveau 0000:01:00.0: PGRAPH - ch 2 (0x0000930000) subc 2 class 0x502d mthd 0x060c data 0x00000018
>done.
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: nouveau_sgdma_destroy:25 - 
>[drm:drm_mode_setcrtc], [CRTC:11]
>[drm:drm_mode_setcrtc], [CONNECTOR:13:DVI-I-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:11] [FB:61] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 66:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 66:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 3
>[drm:drm_crtc_helper_set_mode], [CRTC:11]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 3
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 0
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: VM: trapped write at 0x0000150000 on ch 0 [0x00000070] BAR/PFIFO_WRITE/IN reason: PAGE_SYSTEM_ONLY
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PFIFO_DMA_PUSHER - Ch 1 Get 0x0020008e94 Put 0xcd000002cf IbGet 0xffffffff IbPut 0x000002d0 State 0xc0000000 (err: MEM_FAULT) Push 0x00400040
>[drm:drm_crtc_helper_set_mode], [ENCODER:15:TMDS-15] set [MODE:66:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 3 type 2 -> crtc 0
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 3 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0080 Data 0x00000000 (0x1005 0x05)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a00 Data 0x0000a004 (0x1000 0x03)
>tg3 0000:34:00.0: irq 29 for MSI/MSI-X
>ADDRCONF(NETDEV_UP): eth0: link is not ready
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DVI-I-1] set DPMS on
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 129
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 10 ac 15 40 42 57 4c 41
> 	2e 10 01 03 80 26 1e 78 ee de 95 a3 54 4c 99 26
> 	0f 50 54 a5 4b 00 71 4f 81 80 01 01 01 01 01 01
> 	01 01 01 01 01 01 30 2a 00 98 51 00 2a 40 30 70
> 	13 00 78 2d 11 00 00 1e 00 00 00 ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_setcrtc], [CRTC:12]
>[drm:drm_mode_setcrtc], [CONNECTOR:16:DP-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:12] [FB:61] #connectors=1 (x y) (1280 0)
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 44:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 67:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm:drm_crtc_helper_set_config], [CONNECTOR:13:DVI-I-1] to [CRTC:11]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:16:DP-1] to [CRTC:12]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 67:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_fixup:156 - or 1
>[drm:drm_crtc_helper_set_mode], [CRTC:12]
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_sor_disconnect:51 - Disconnecting SOR 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_prepare:481 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_set_scale:203 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_do_mode_set_base:522 - index 1
>[drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:67:]
>[drm] nouveau 0000:01:00.0: nv50_sor_mode_set:203 - or 1 type 2 -> crtc 1
>[drm] nouveau 0000:01:00.0: nv50_sor_dpms:78 - or 1 type 2 mode 0
>[drm] nouveau 0000:01:00.0: nv50_crtc_commit:494 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:71 - index 1
>[drm] nouveau 0000:01:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:01:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a84 Data 0x00080c80 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a88 Data 0x05000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a8c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a90 Data 0x00040c9c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a94 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a98 Data 0x00080c40 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0a9c Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0aa0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0aa4 Data 0x00040c5c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0aa8 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0aac Data 0x00040c74 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ab0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ab4 Data 0x00040640 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ab8 Data 0x00080c40 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0abc Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ac0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ac4 Data 0x00080c80 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ac8 Data 0x05000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0acc Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ad0 Data 0x00040c9c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ad4 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ad8 Data 0x00080c40 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0adc Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ae0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ae4 Data 0x00040c5c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ae8 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0aec Data 0x00040c74 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0af0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0af4 Data 0x00080c04 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0af8 Data 0x0081a5e0 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0afc Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b00 Data 0x00180c10 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b04 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b08 Data 0x042a0698 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b0c Data 0x0002006f (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b10 Data 0x00280167 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b14 Data 0x04280667 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b18 Data 0x00000001 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b1c Data 0x00040c2c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b20 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b24 Data 0x00040d00 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b28 Data 0x00000311 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b2c Data 0x00040cc8 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b30 Data 0x04000500 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b34 Data 0x00040cd4 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b38 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b3c Data 0x00040ca0 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b40 Data 0x00000011 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b44 Data 0x00040ca4 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b48 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b4c Data 0x00080cd8 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b50 Data 0x04000500 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b54 Data 0x04000500 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b58 Data 0x00140c60 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b5c Data 0x00009c00 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b60 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b64 Data 0x04000a00 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b68 Data 0x0000a004 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b6c Data 0x0000cf00 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b70 Data 0x00040c40 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b74 Data 0xc0000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b78 Data 0x00040ca8 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b7c Data 0x00040000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b80 Data 0x00040cc0 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b84 Data 0x00000500 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b88 Data 0x00040640 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b8c Data 0x00000102 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b90 Data 0x00080c80 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b94 Data 0x05000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b98 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0b9c Data 0x00040c9c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ba0 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ba4 Data 0x00080c40 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0ba8 Data 0xc0000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0bac Data 0x00001970 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0bb0 Data 0x00040c5c (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0bb4 Data 0x01000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0bb8 Data 0x00000000 (0x1000 0x03)
>[drm] nouveau 0000:01:00.0: nv50_display_isr:979 - PDISPLAY_INTR 0x00010000 0x00000000
>[drm] nouveau 0000:01:00.0: EvoCh 0 Mthd 0x0bbc Data 0x00040c9c (0x1000 0x03)
>tg3 0000:34:00.0: eth0: Link is up at 100 Mbps, full duplex
>tg3 0000:34:00.0: eth0: Flow control is off for TX and off for RX
>ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:16:DP-1] set DPMS on
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:01:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:DVI-I-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 20:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 22:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 23:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 25:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1]
>[drm] nouveau 0000:01:00.0: nouveau_connector_native_mode:546 - native mode from preferred
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:DP-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 33:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: nouveau_sgdma_destroy:25 - 
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>eth0: no IPv6 routers present
>[drm:output_poll_execute], [CONNECTOR:13:DVI-I-1] status updated from 1 to 1
>[drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 130
>Raw EDID:
> 	00 ff ff ff ff ff ff 00 ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 	ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>[drm:output_poll_execute], [CONNECTOR:16:DP-1] status updated from 1 to 1
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: nv50_cursor_set_offset:120 - 
>[drm] nouveau 0000:01:00.0: nv50_cursor_show:44 - 
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000
>[drm] nouveau 0000:01:00.0: PGRAPH TLB flush idle timeout fail: 0x01000001 0x00000000 0x00000000 0x00200000

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Attachments on bug 814236: 578633 | 578635