Attachment 624325 Details for Bug 864704 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 2.67 MB, created by bhglee on 2012-10-09 23:20:45 UTC

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Creator: bhglee

Created: 2012-10-09 23:20:45 UTC

Size: 2.67 MB

patch

obsolete

>[    16.906] 
>X.Org X Server 1.12.3
>Release Date: 2012-07-09
>[    16.906] X Protocol Version 11, Revision 0
>[    16.906] Build Operating System:  2.6.32-220.17.1.el6.x86_64 
>[    16.906] Current Operating System: Linux berniehglee 3.5.4-2.fc17.x86_64 #1 SMP Wed Sep 26 21:58:50 UTC 2012 x86_64
>[    16.906] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.5.4-2.fc17.x86_64 root=UUID=d1cfb4a7-1f60-453c-b9d0-6b2febfbb194 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True KEYTABLE=us rd.luks=0 LANG=en_US.UTF-8 rhgb quiet
>[    16.906] Build Date: 20 September 2012  07:51:23AM
>[    16.907] Build ID: xorg-x11-server 1.12.3-2.fc17 
>[    16.907] Current version of pixman: 0.24.4
>[    16.907] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    16.907] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    16.907] (==) Log file: "/var/log/Xorg.0.log", Time: Sat Oct  6 01:37:41 2012
>[    16.924] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    16.924] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    16.925] (==) No Layout section.  Using the first Screen section.
>[    16.925] (==) No screen section available. Using defaults.
>[    16.925] (**) |-->Screen "Default Screen Section" (0)
>[    16.925] (**) |   |-->Monitor "<default monitor>"
>[    16.925] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    16.925] (==) Automatically adding devices
>[    16.925] (==) Automatically enabling devices
>[    16.925] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    16.925] (==) ModulePath set to "/usr/lib64/xorg/modules"
>[    16.925] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    16.925] (II) Loader magic: 0x7c6ac0
>[    16.925] (II) Module ABI versions:
>[    16.925] 	X.Org ANSI C Emulation: 0.4
>[    16.925] 	X.Org Video Driver: 12.0
>[    16.925] 	X.Org XInput driver : 16.0
>[    16.925] 	X.Org Server Extension : 6.0
>[    16.928] (--) PCI:*(0:1:0:0) 1002:9498:174b:9498 rev 0, Mem @ 0xd0000000/268435456, 0xfe9f0000/65536, I/O @ 0x0000c000/256, BIOS @ 0x????????/131072
>[    16.928] (II) LoadModule: "extmod"
>[    16.933] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so
>[    16.934] (II) Module extmod: vendor="X.Org Foundation"
>[    16.934] 	compiled for 1.12.3, module version = 1.0.0
>[    16.934] 	Module class: X.Org Server Extension
>[    16.934] 	ABI class: X.Org Server Extension, version 6.0
>[    16.934] (II) Loading extension SELinux
>[    16.934] (II) Loading extension MIT-SCREEN-SAVER
>[    16.934] (II) Loading extension XFree86-VidModeExtension
>[    16.934] (II) Loading extension XFree86-DGA
>[    16.934] (II) Loading extension DPMS
>[    16.934] (II) Loading extension XVideo
>[    16.934] (II) Loading extension XVideo-MotionCompensation
>[    16.934] (II) Loading extension X-Resource
>[    16.934] (II) LoadModule: "dbe"
>[    16.934] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so
>[    16.934] (II) Module dbe: vendor="X.Org Foundation"
>[    16.935] 	compiled for 1.12.3, module version = 1.0.0
>[    16.935] 	Module class: X.Org Server Extension
>[    16.935] 	ABI class: X.Org Server Extension, version 6.0
>[    16.935] (II) Loading extension DOUBLE-BUFFER
>[    16.935] (II) LoadModule: "glx"
>[    16.935] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
>[    16.935] (II) Module glx: vendor="X.Org Foundation"
>[    16.935] 	compiled for 1.12.3, module version = 1.0.0
>[    16.935] 	ABI class: X.Org Server Extension, version 6.0
>[    16.935] (==) AIGLX enabled
>[    16.935] (II) Loading extension GLX
>[    16.935] (II) LoadModule: "record"
>[    16.936] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so
>[    16.936] (II) Module record: vendor="X.Org Foundation"
>[    16.936] 	compiled for 1.12.3, module version = 1.13.0
>[    16.936] 	Module class: X.Org Server Extension
>[    16.936] 	ABI class: X.Org Server Extension, version 6.0
>[    16.936] (II) Loading extension RECORD
>[    16.936] (II) LoadModule: "dri"
>[    16.936] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so
>[    16.937] (II) Module dri: vendor="X.Org Foundation"
>[    16.937] 	compiled for 1.12.3, module version = 1.0.0
>[    16.937] 	ABI class: X.Org Server Extension, version 6.0
>[    16.937] (II) Loading extension XFree86-DRI
>[    16.937] (II) LoadModule: "dri2"
>[    16.937] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so
>[    16.938] (II) Module dri2: vendor="X.Org Foundation"
>[    16.938] 	compiled for 1.12.3, module version = 1.2.0
>[    16.938] 	ABI class: X.Org Server Extension, version 6.0
>[    16.938] (II) Loading extension DRI2
>[    16.938] (==) Matched ati as autoconfigured driver 0
>[    16.938] (==) Matched vesa as autoconfigured driver 1
>[    16.938] (==) Matched modesetting as autoconfigured driver 2
>[    16.938] (==) Matched fbdev as autoconfigured driver 3
>[    16.938] (==) Assigned the driver to the xf86ConfigLayout
>[    16.938] (II) LoadModule: "ati"
>[    16.938] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so
>[    16.938] (II) Module ati: vendor="X.Org Foundation"
>[    16.938] 	compiled for 1.12.0, module version = 6.14.99
>[    16.938] 	Module class: X.Org Video Driver
>[    16.938] 	ABI class: X.Org Video Driver, version 12.0
>[    16.938] (II) LoadModule: "radeon"
>[    16.939] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so
>[    16.939] (II) Module radeon: vendor="X.Org Foundation"
>[    16.939] 	compiled for 1.12.0, module version = 6.14.99
>[    16.939] 	Module class: X.Org Video Driver
>[    16.939] 	ABI class: X.Org Video Driver, version 12.0
>[    16.939] (II) LoadModule: "vesa"
>[    16.939] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so
>[    16.940] (II) Module vesa: vendor="X.Org Foundation"
>[    16.940] 	compiled for 1.12.0, module version = 2.3.1
>[    16.940] 	Module class: X.Org Video Driver
>[    16.940] 	ABI class: X.Org Video Driver, version 12.0
>[    16.940] (II) LoadModule: "modesetting"
>[    16.940] (WW) Warning, couldn't open module modesetting
>[    16.940] (II) UnloadModule: "modesetting"
>[    16.940] (II) Unloading modesetting
>[    16.940] (EE) Failed to load module "modesetting" (module does not exist, 0)
>[    16.940] (II) LoadModule: "fbdev"
>[    16.941] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so
>[    16.941] (II) Module fbdev: vendor="X.Org Foundation"
>[    16.941] 	compiled for 1.11.99.901, module version = 0.4.2
>[    16.941] 	ABI class: X.Org Video Driver, version 12.0
>[    16.941] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    16.944] (II) VESA: driver for VESA chipsets: vesa
>[    16.944] (II) FBDEV: driver for framebuffer: fbdev
>[    16.944] (++) using VT number 1
>
>[    16.946] (II) [KMS] Kernel modesetting enabled.
>[    16.946] (WW) Falling back to old probe method for vesa
>[    16.946] (WW) Falling back to old probe method for fbdev
>[    16.946] (II) Loading sub module "fbdevhw"
>[    16.946] (II) LoadModule: "fbdevhw"
>[    16.946] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so
>[    16.946] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    16.946] 	compiled for 1.12.3, module version = 0.0.2
>[    16.946] 	ABI class: X.Org Video Driver, version 12.0
>[    16.946] (II) RADEON(0): RADEONPreInit_KMS
>[    16.946] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    16.946] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    16.946] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    16.946] (==) RADEON(0): Default visual is TrueColor
>[    16.946] (==) RADEON(0): RGB weight 888
>[    16.946] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    16.946] (--) RADEON(0): Chipset: "ATI RV730 PRO [Radeon HD 4650]" (ChipID = 0x9498)
>[    16.946] (II) RADEON(0): PCIE card detected
>[    16.946] drmOpenDevice: node name is /dev/dri/card0
>[    16.946] drmOpenDevice: open result is 8, (OK)
>[    16.946] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    16.946] drmOpenDevice: node name is /dev/dri/card0
>[    16.946] drmOpenDevice: open result is 8, (OK)
>[    16.946] drmOpenByBusid: drmOpenMinor returns 8
>[    16.946] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    16.946] (II) Loading sub module "exa"
>[    16.946] (II) LoadModule: "exa"
>[    16.946] (II) Loading /usr/lib64/xorg/modules/libexa.so
>[    16.946] (II) Module exa: vendor="X.Org Foundation"
>[    16.946] 	compiled for 1.12.3, module version = 2.5.0
>[    16.946] 	ABI class: X.Org Video Driver, version 12.0
>[    16.946] (II) RADEON(0): KMS Color Tiling: enabled
>[    16.946] (II) RADEON(0): KMS Pageflipping: enabled
>[    16.946] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    16.960] (II) RADEON(0): Output VGA-0 has no monitor section
>[    16.962] (II) RADEON(0): Output HDMI-0 has no monitor section
>[    16.995] (II) RADEON(0): Output DVI-0 has no monitor section
>[    17.010] (II) RADEON(0): EDID for output VGA-0
>[    17.012] (II) RADEON(0): EDID for output HDMI-0
>[    17.045] (II) RADEON(0): EDID for output DVI-0
>[    17.045] (II) RADEON(0): Manufacturer: ACR  Model: 203  Serial#: 273135422
>[    17.045] (II) RADEON(0): Year: 2011  Week: 4
>[    17.045] (II) RADEON(0): EDID Version: 1.3
>[    17.045] (II) RADEON(0): Digital Display Input
>[    17.045] (II) RADEON(0): Max Image Size [cm]: horiz.: 51  vert.: 29
>[    17.045] (II) RADEON(0): Gamma: 2.20
>[    17.045] (II) RADEON(0): DPMS capabilities: Off
>[    17.045] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>[    17.045] (II) RADEON(0): First detailed timing is preferred mode
>[    17.045] (II) RADEON(0): redX: 0.640 redY: 0.330   greenX: 0.300 greenY: 0.600
>[    17.045] (II) RADEON(0): blueX: 0.150 blueY: 0.060   whiteX: 0.312 whiteY: 0.329
>[    17.045] (II) RADEON(0): Supported established timings:
>[    17.045] (II) RADEON(0): 720x400@70Hz
>[    17.045] (II) RADEON(0): 640x480@60Hz
>[    17.045] (II) RADEON(0): 640x480@67Hz
>[    17.045] (II) RADEON(0): 800x600@56Hz
>[    17.045] (II) RADEON(0): 800x600@60Hz
>[    17.045] (II) RADEON(0): 1024x768@60Hz
>[    17.045] (II) RADEON(0): 1024x768@70Hz
>[    17.045] (II) RADEON(0): Manufacturer's mask: 0
>[    17.045] (II) RADEON(0): Supported standard timings:
>[    17.045] (II) RADEON(0): #0: hsize: 1152  vsize 864  refresh: 75  vid: 20337
>[    17.045] (II) RADEON(0): #1: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
>[    17.045] (II) RADEON(0): #2: hsize: 1440  vsize 900  refresh: 60  vid: 149
>[    17.045] (II) RADEON(0): #3: hsize: 1280  vsize 800  refresh: 60  vid: 129
>[    17.045] (II) RADEON(0): #4: hsize: 1920  vsize 1080  refresh: 60  vid: 49361
>[    17.045] (II) RADEON(0): Supported detailed timing:
>[    17.045] (II) RADEON(0): clock: 148.5 MHz   Image Size:  510 x 287 mm
>[    17.045] (II) RADEON(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>[    17.045] (II) RADEON(0): v_active: 1080  v_sync: 1084  v_sync_end 1089 v_blanking: 1125 v_border: 0
>[    17.045] (II) RADEON(0): Ranges: V min: 56 V max: 75 Hz, H min: 30 H max: 83 kHz, PixClock max 185 MHz
>[    17.045] (II) RADEON(0): Serial No: LQY080094201
>[    17.046] (II) RADEON(0): Monitor name: Acer S232HL
>[    17.046] (II) RADEON(0): EDID (in hex):
>[    17.046] (II) RADEON(0): 	00ffffffffffff00047203023eb74710
>[    17.046] (II) RADEON(0): 	0415010380331d782aee91a3544c9926
>[    17.046] (II) RADEON(0): 	0f5054b30c00714f818095008100d1c0
>[    17.046] (II) RADEON(0): 	010101010101023a801871382d40582c
>[    17.046] (II) RADEON(0): 	4500fe1f1100001e000000fd00384b1e
>[    17.046] (II) RADEON(0): 	5312000a202020202020000000ff004c
>[    17.046] (II) RADEON(0): 	51593038303039343230310a000000fc
>[    17.046] (II) RADEON(0): 	00416365722053323332484c0a20007d
>[    17.046] (II) RADEON(0): Printing probed modes for output DVI-0
>[    17.046] (II) RADEON(0): Modeline "1920x1080"x60.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    17.046] (II) RADEON(0): Modeline "1680x1050"x59.9  119.00  1680 1728 1760 1840  1050 1053 1059 1080 +hsync -vsync (64.7 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1680x945"x60.0  131.48  1680 1784 1960 2240  945 946 949 978 -hsync +vsync (58.7 kHz)
>[    17.046] (II) RADEON(0): Modeline "1400x1050"x74.9  156.00  1400 1504 1648 1896  1050 1053 1057 1099 -hsync +vsync (82.3 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1400x1050"x59.9  101.00  1400 1448 1480 1560  1050 1053 1057 1080 +hsync -vsync (64.7 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1600x900"x60.0  118.96  1600 1696 1864 2128  900 901 904 932 -hsync +vsync (55.9 kHz)
>[    17.046] (II) RADEON(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1440x900"x75.0  136.75  1440 1536 1688 1936  900 903 909 942 -hsync +vsync (70.6 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1440x900"x59.9   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1366x768"x60.0   85.89  1366 1439 1583 1800  768 769 772 795 -hsync +vsync (47.7 kHz)
>[    17.046] (II) RADEON(0): Modeline "1360x768"x60.0   85.50  1360 1424 1536 1792  768 771 777 795 +hsync +vsync (47.7 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x800"x74.9  106.50  1280 1360 1488 1696  800 803 809 838 -hsync +vsync (62.8 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x800"x59.9   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x768"x74.9  102.25  1280 1360 1488 1696  768 771 778 805 +hsync -vsync (60.3 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1280x768"x60.0   68.25  1280 1328 1360 1440  768 771 778 790 +hsync -vsync (47.4 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    17.046] (II) RADEON(0): Modeline "1024x576"x60.0   46.97  1024 1064 1168 1312  576 577 580 597 -hsync +vsync (35.8 kHz)
>[    17.046] (II) RADEON(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    17.046] (II) RADEON(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    17.046] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    17.046] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    17.047] (II) RADEON(0): Modeline "848x480"x60.0   33.75  848 864 976 1088  480 486 494 517 +hsync +vsync (31.0 kHz e)
>[    17.047] (II) RADEON(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    17.047] (II) RADEON(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    17.047] (II) RADEON(0): Modeline "640x480"x66.7   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    17.047] (II) RADEON(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    17.047] (II) RADEON(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    17.047] (II) RADEON(0): Output VGA-0 disconnected
>[    17.047] (II) RADEON(0): Output HDMI-0 disconnected
>[    17.047] (II) RADEON(0): Output DVI-0 connected
>[    17.047] (II) RADEON(0): Using exact sizes for initial modes
>[    17.047] (II) RADEON(0): Output DVI-0 using initial mode 1920x1080 +0+0
>[    17.047] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    17.047] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:40000000 visible:f7d7000
>[    17.047] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    17.047] (==) RADEON(0): DPI set to (96, 96)
>[    17.047] (II) Loading sub module "fb"
>[    17.047] (II) LoadModule: "fb"
>[    17.047] (II) Loading /usr/lib64/xorg/modules/libfb.so
>[    17.048] (II) Module fb: vendor="X.Org Foundation"
>[    17.048] 	compiled for 1.12.3, module version = 1.0.0
>[    17.048] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    17.048] (II) Loading sub module "ramdac"
>[    17.048] (II) LoadModule: "ramdac"
>[    17.048] (II) Module "ramdac" already built-in
>[    17.048] (II) UnloadModule: "vesa"
>[    17.048] (II) Unloading vesa
>[    17.048] (II) UnloadModule: "fbdev"
>[    17.048] (II) Unloading fbdev
>[    17.048] (II) UnloadSubModule: "fbdevhw"
>[    17.048] (II) Unloading fbdevhw
>[    17.048] (--) Depth 24 pixmap format is 32 bpp
>[    17.048] (II) RADEON(0): [DRI2] Setup complete
>[    17.048] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    17.048] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    17.049] (II) RADEON(0): Front buffer size: 8100K
>[    17.049] (II) RADEON(0): VRAM usage limit set to 221119K
>[    17.049] (II) RADEON(0): Initializing backing store
>[    17.049] (==) RADEON(0): Backing store disabled
>[    17.049] (II) RADEON(0): Direct rendering enabled
>[    17.049] (II) RADEON(0): Initializing Acceleration
>[    17.049] (II) RADEON(0): Setting EXA maxPitchBytes
>[    17.049] (II) EXA(0): Driver allocated offscreen pixmaps
>[    17.049] (II) EXA(0): Driver registered support for the following operations:
>[    17.049] (II)         Solid
>[    17.049] (II)         Copy
>[    17.049] (II)         Composite (RENDER acceleration)
>[    17.049] (II)         UploadToScreen
>[    17.049] (II)         DownloadFromScreen
>[    17.049] (II) RADEON(0): Acceleration enabled
>[    17.049] (II) RADEON(0): Initializing DPMS
>[    17.049] (==) RADEON(0): DPMS enabled
>[    17.049] (II) RADEON(0): Initializing Cursor
>[    17.049] (==) RADEON(0): Silken mouse enabled
>[    17.049] (II) RADEON(0): Initializing Xv
>[    17.050] (II) RADEON(0): Set up textured video
>[    17.050] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    17.050] (II) RADEON(0): [XvMC] Extension initialized.
>[    17.050] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    17.050] (II) RADEON(0): Initializing kms color map
>[    17.050] (II) RADEON(0): RADEONScreenInit finished
>[    17.050] (--) RandR disabled
>[    17.050] (II) Initializing built-in extension Generic Event Extension
>[    17.050] (II) Initializing built-in extension SHAPE
>[    17.050] (II) Initializing built-in extension MIT-SHM
>[    17.050] (II) Initializing built-in extension XInputExtension
>[    17.050] (II) Initializing built-in extension XTEST
>[    17.050] (II) Initializing built-in extension BIG-REQUESTS
>[    17.050] (II) Initializing built-in extension SYNC
>[    17.050] (II) Initializing built-in extension XKEYBOARD
>[    17.050] (II) Initializing built-in extension XC-MISC
>[    17.050] (II) Initializing built-in extension XINERAMA
>[    17.050] (II) Initializing built-in extension XFIXES
>[    17.050] (II) Initializing built-in extension RENDER
>[    17.050] (II) Initializing built-in extension RANDR
>[    17.050] (II) Initializing built-in extension COMPOSITE
>[    17.050] (II) Initializing built-in extension DAMAGE
>[    17.053] (II) SELinux: Disabled by boolean
>[    17.313] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    17.313] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    17.313] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    17.313] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    17.313] (II) AIGLX: Loaded and initialized r600
>[    17.313] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    17.314] (II) RADEON(0): Setting screen physical size to 508 x 285
>[    17.376] (II) XKB: Reusing cached keymap
>[    17.384] (II) config/udev: Adding input device Power Button (/dev/input/event1)
>[    17.384] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    17.384] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    17.384] (II) LoadModule: "evdev"
>[    17.385] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so
>[    17.385] (II) Module evdev: vendor="X.Org Foundation"
>[    17.385] 	compiled for 1.12.0, module version = 2.7.0
>[    17.385] 	Module class: X.Org XInput Driver
>[    17.385] 	ABI class: X.Org XInput driver, version 16.0
>[    17.386] (II) Using input driver 'evdev' for 'Power Button'
>[    17.386] 	Option "XkbRules" "evdev"
>[    17.386] 	Option "XkbModel" "pc105+inet"
>[    17.386] 	Option "XkbLayout" "us"
>[    17.386] 	Option "_source" "server/udev"
>[    17.386] 	Option "name" "Power Button"
>[    17.386] 	Option "path" "/dev/input/event1"
>[    17.386] 	Option "device" "/dev/input/event1"
>[    17.386] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1"
>[    17.386] 	Option "driver" "evdev"
>[    17.386] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    17.386] (**) Power Button: always reports core events
>[    17.386] (**) evdev: Power Button: Device: "/dev/input/event1"
>[    17.386] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    17.386] (--) evdev: Power Button: Found keys
>[    17.386] (II) evdev: Power Button: Configuring as keyboard
>[    17.386] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1"
>[    17.386] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    17.386] (**) Option "xkb_rules" "evdev"
>[    17.386] (**) Option "xkb_model" "pc105+inet"
>[    17.386] (**) Option "xkb_layout" "us"
>[    17.386] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    17.419] (II) config/udev: Adding input device Power Button (/dev/input/event0)
>[    17.419] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    17.419] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    17.419] (II) Using input driver 'evdev' for 'Power Button'
>[    17.419] 	Option "XkbRules" "evdev"
>[    17.419] 	Option "XkbModel" "pc105+inet"
>[    17.419] 	Option "XkbLayout" "us"
>[    17.419] 	Option "_source" "server/udev"
>[    17.419] 	Option "name" "Power Button"
>[    17.419] 	Option "path" "/dev/input/event0"
>[    17.419] 	Option "device" "/dev/input/event0"
>[    17.419] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    17.419] 	Option "driver" "evdev"
>[    17.419] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    17.419] (**) Power Button: always reports core events
>[    17.419] (**) evdev: Power Button: Device: "/dev/input/event0"
>[    17.420] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    17.420] (--) evdev: Power Button: Found keys
>[    17.420] (II) evdev: Power Button: Configuring as keyboard
>[    17.420] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    17.420] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7)
>[    17.420] (**) Option "xkb_rules" "evdev"
>[    17.420] (**) Option "xkb_model" "pc105+inet"
>[    17.420] (**) Option "xkb_layout" "us"
>[    17.420] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    17.420] (II) XKB: Reusing cached keymap
>[    17.421] (II) config/udev: Adding input device HDA ATI HDMI HDMI/DP,pcm=3 (/dev/input/event11)
>[    17.421] (II) No input driver specified, ignoring this device.
>[    17.421] (II) This device may have been added with another device file.
>[    17.422] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event2)
>[    17.422] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[    17.422] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[    17.422] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[    17.422] 	Option "XkbRules" "evdev"
>[    17.422] 	Option "XkbModel" "pc105+inet"
>[    17.422] 	Option "XkbLayout" "us"
>[    17.422] 	Option "_source" "server/udev"
>[    17.422] 	Option "name" "HID 1267:0103"
>[    17.422] 	Option "path" "/dev/input/event2"
>[    17.422] 	Option "device" "/dev/input/event2"
>[    17.422] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb4/4-2/4-2:1.0/input/input2/event2"
>[    17.422] 	Option "driver" "evdev"
>[    17.422] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    17.422] (**) HID 1267:0103: always reports core events
>[    17.422] (**) evdev: HID 1267:0103: Device: "/dev/input/event2"
>[    17.422] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[    17.422] (--) evdev: HID 1267:0103: Found keys
>[    17.422] (II) evdev: HID 1267:0103: Configuring as keyboard
>[    17.423] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb4/4-2/4-2:1.0/input/input2/event2"
>[    17.423] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 8)
>[    17.423] (**) Option "xkb_rules" "evdev"
>[    17.423] (**) Option "xkb_model" "pc105+inet"
>[    17.423] (**) Option "xkb_layout" "us"
>[    17.423] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    17.423] (II) XKB: Reusing cached keymap
>[    17.424] (II) config/udev: Adding input device HID 1267:0103 (/dev/input/event3)
>[    17.424] (**) HID 1267:0103: Applying InputClass "evdev keyboard catchall"
>[    17.424] (**) HID 1267:0103: Applying InputClass "system-setup-keyboard"
>[    17.424] (II) Using input driver 'evdev' for 'HID 1267:0103'
>[    17.424] 	Option "XkbRules" "evdev"
>[    17.424] 	Option "XkbModel" "pc105+inet"
>[    17.424] 	Option "XkbLayout" "us"
>[    17.424] 	Option "_source" "server/udev"
>[    17.424] 	Option "name" "HID 1267:0103"
>[    17.424] 	Option "path" "/dev/input/event3"
>[    17.424] 	Option "device" "/dev/input/event3"
>[    17.424] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb4/4-2/4-2:1.1/input/input3/event3"
>[    17.424] 	Option "driver" "evdev"
>[    17.425] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    17.425] (**) HID 1267:0103: always reports core events
>[    17.425] (**) evdev: HID 1267:0103: Device: "/dev/input/event3"
>[    17.425] (--) evdev: HID 1267:0103: absolute axis 0x20 [572..0]
>[    17.425] (--) evdev: HID 1267:0103: Vendor 0x1267 Product 0x103
>[    17.425] (--) evdev: HID 1267:0103: Found 1 mouse buttons
>[    17.425] (--) evdev: HID 1267:0103: Found scroll wheel(s)
>[    17.425] (--) evdev: HID 1267:0103: Found relative axes
>[    17.425] (II) evdev: HID 1267:0103: Forcing relative x/y axes to exist.
>[    17.425] (--) evdev: HID 1267:0103: Found absolute axes
>[    17.425] (II) evdev: HID 1267:0103: Forcing absolute x/y axes to exist.
>[    17.425] (--) evdev: HID 1267:0103: Found keys
>[    17.425] (II) evdev: HID 1267:0103: Configuring as mouse
>[    17.425] (II) evdev: HID 1267:0103: Configuring as keyboard
>[    17.425] (II) evdev: HID 1267:0103: Adding scrollwheel support
>[    17.425] (**) evdev: HID 1267:0103: YAxisMapping: buttons 4 and 5
>[    17.425] (**) evdev: HID 1267:0103: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    17.425] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb4/4-2/4-2:1.1/input/input3/event3"
>[    17.425] (II) XINPUT: Adding extended input device "HID 1267:0103" (type: KEYBOARD, id 9)
>[    17.425] (**) Option "xkb_rules" "evdev"
>[    17.425] (**) Option "xkb_model" "pc105+inet"
>[    17.425] (**) Option "xkb_layout" "us"
>[    17.425] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    17.425] (II) XKB: Reusing cached keymap
>[    17.426] (II) evdev: HID 1267:0103: initialized for relative axes.
>[    17.426] (WW) evdev: HID 1267:0103: ignoring absolute axes.
>[    17.426] (**) HID 1267:0103: (accel) keeping acceleration scheme 1
>[    17.426] (**) HID 1267:0103: (accel) acceleration profile 0
>[    17.426] (**) HID 1267:0103: (accel) acceleration factor: 2.000
>[    17.426] (**) HID 1267:0103: (accel) acceleration threshold: 4
>[    17.427] (II) config/udev: Adding input device HDA ATI SB Line Out (/dev/input/event10)
>[    17.427] (II) No input driver specified, ignoring this device.
>[    17.427] (II) This device may have been added with another device file.
>[    17.428] (II) config/udev: Adding input device HDA ATI SB Line (/dev/input/event6)
>[    17.428] (II) No input driver specified, ignoring this device.
>[    17.428] (II) This device may have been added with another device file.
>[    17.428] (II) config/udev: Adding input device HDA ATI SB Front Mic (/dev/input/event7)
>[    17.429] (II) No input driver specified, ignoring this device.
>[    17.429] (II) This device may have been added with another device file.
>[    17.429] (II) config/udev: Adding input device HDA ATI SB Rear Mic (/dev/input/event8)
>[    17.429] (II) No input driver specified, ignoring this device.
>[    17.429] (II) This device may have been added with another device file.
>[    17.430] (II) config/udev: Adding input device HDA ATI SB Front Headphone (/dev/input/event9)
>[    17.430] (II) No input driver specified, ignoring this device.
>[    17.430] (II) This device may have been added with another device file.
>[    17.431] (II) config/udev: Adding input device Logitech Unifying Device. Wireless PID:1028 (/dev/input/event4)
>[    17.431] (**) Logitech Unifying Device. Wireless PID:1028: Applying InputClass "evdev pointer catchall"
>[    17.431] (II) Using input driver 'evdev' for 'Logitech Unifying Device. Wireless PID:1028'
>[    17.431] 	Option "XkbRules" "evdev"
>[    17.431] 	Option "XkbModel" "evdev"
>[    17.431] 	Option "XkbLayout" "us"
>[    17.431] 	Option "_source" "server/udev"
>[    17.431] 	Option "name" "Logitech Unifying Device. Wireless PID:1028"
>[    17.431] 	Option "path" "/dev/input/event4"
>[    17.431] 	Option "device" "/dev/input/event4"
>[    17.431] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:14.4/0000:03:07.0/usb9/9-1/9-1:1.2/0003:046D:C52B.0005/input/input4/event4"
>[    17.431] 	Option "driver" "evdev"
>[    17.431] (**) Logitech Unifying Device. Wireless PID:1028: always reports core events
>[    17.431] (**) evdev: Logitech Unifying Device. Wireless PID:1028: Device: "/dev/input/event4"
>[    17.431] (--) evdev: Logitech Unifying Device. Wireless PID:1028: Vendor 0x46d Product 0xc52b
>[    17.431] (--) evdev: Logitech Unifying Device. Wireless PID:1028: Found 20 mouse buttons
>[    17.431] (--) evdev: Logitech Unifying Device. Wireless PID:1028: Found scroll wheel(s)
>[    17.431] (--) evdev: Logitech Unifying Device. Wireless PID:1028: Found relative axes
>[    17.431] (--) evdev: Logitech Unifying Device. Wireless PID:1028: Found x and y relative axes
>[    17.431] (II) evdev: Logitech Unifying Device. Wireless PID:1028: Configuring as mouse
>[    17.431] (II) evdev: Logitech Unifying Device. Wireless PID:1028: Adding scrollwheel support
>[    17.431] (**) evdev: Logitech Unifying Device. Wireless PID:1028: YAxisMapping: buttons 4 and 5
>[    17.431] (**) evdev: Logitech Unifying Device. Wireless PID:1028: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    17.431] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:14.4/0000:03:07.0/usb9/9-1/9-1:1.2/0003:046D:C52B.0005/input/input4/event4"
>[    17.431] (II) XINPUT: Adding extended input device "Logitech Unifying Device. Wireless PID:1028" (type: MOUSE, id 10)
>[    17.431] (II) evdev: Logitech Unifying Device. Wireless PID:1028: initialized for relative axes.
>[    17.432] (**) Logitech Unifying Device. Wireless PID:1028: (accel) keeping acceleration scheme 1
>[    17.432] (**) Logitech Unifying Device. Wireless PID:1028: (accel) acceleration profile 0
>[    17.432] (**) Logitech Unifying Device. Wireless PID:1028: (accel) acceleration factor: 2.000
>[    17.432] (**) Logitech Unifying Device. Wireless PID:1028: (accel) acceleration threshold: 4
>[    17.433] (II) config/udev: Adding input device Logitech Unifying Device. Wireless PID:1028 (/dev/input/mouse0)
>[    17.433] (II) No input driver specified, ignoring this device.
>[    17.433] (II) This device may have been added with another device file.
>[    17.433] (II) config/udev: Adding input device UVC Camera (046d:0802) (/dev/input/event5)
>[    17.433] (**) UVC Camera (046d:0802): Applying InputClass "evdev keyboard catchall"
>[    17.433] (**) UVC Camera (046d:0802): Applying InputClass "system-setup-keyboard"
>[    17.433] (II) Using input driver 'evdev' for 'UVC Camera (046d:0802)'
>[    17.433] 	Option "XkbRules" "evdev"
>[    17.433] 	Option "XkbModel" "pc105+inet"
>[    17.433] 	Option "XkbLayout" "us"
>[    17.433] 	Option "_source" "server/udev"
>[    17.433] 	Option "name" "UVC Camera (046d:0802)"
>[    17.433] 	Option "path" "/dev/input/event5"
>[    17.433] 	Option "device" "/dev/input/event5"
>[    17.433] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:14.4/0000:03:07.2/usb3/3-2/3-2:1.0/input/input5/event5"
>[    17.433] 	Option "driver" "evdev"
>[    17.433] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    17.433] (**) UVC Camera (046d:0802): always reports core events
>[    17.433] (**) evdev: UVC Camera (046d:0802): Device: "/dev/input/event5"
>[    17.433] (--) evdev: UVC Camera (046d:0802): Vendor 0x46d Product 0x802
>[    17.433] (--) evdev: UVC Camera (046d:0802): Found keys
>[    17.433] (II) evdev: UVC Camera (046d:0802): Configuring as keyboard
>[    17.433] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:14.4/0000:03:07.2/usb3/3-2/3-2:1.0/input/input5/event5"
>[    17.433] (II) XINPUT: Adding extended input device "UVC Camera (046d:0802)" (type: KEYBOARD, id 11)
>[    17.433] (**) Option "xkb_rules" "evdev"
>[    17.433] (**) Option "xkb_model" "pc105+inet"
>[    17.433] (**) Option "xkb_layout" "us"
>[    17.433] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    17.433] (II) XKB: Reusing cached keymap
>[    17.436] (II) RADEON(0): RADEONSaveScreen(2)
>[    17.491] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[    17.491] (II) RADEON(0): Using EDID range info for horizontal sync
>[    17.491] (II) RADEON(0): Using EDID range info for vertical refresh
>[    17.492] (II) RADEON(0): Printing DDC gathered Modelines:
>[    17.492] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    17.492] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    17.492] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    17.492] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    17.492] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    17.492] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    17.492] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[    19.517] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[    19.517] (II) RADEON(0): Using hsync ranges from config file
>[    19.517] (II) RADEON(0): Using vrefresh ranges from config file
>[    19.517] (II) RADEON(0): Printing DDC gathered Modelines:
>[    19.517] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    19.517] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    19.517] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    19.517] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    19.517] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    19.517] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    19.517] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[    20.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    20.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    20.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    21.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91dd0]
>[    21.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91dd0] width 1920 pitch 7680 (/4 1920)
>[    21.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b91d70]
>[    21.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b91d70] width 1920 pitch 7680 (/4 1920)
>[    35.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b94a70]
>[    35.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b94a70] width 1920 pitch 7680 (/4 1920)
>[    67.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    67.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    67.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    67.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    67.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    68.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b98690]
>[    68.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b98690] width 1920 pitch 7680 (/4 1920)
>[    68.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b942b0]
>[    68.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b942b0] width 1920 pitch 7680 (/4 1920)
>[    69.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    69.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    69.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    69.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    69.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    69.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    70.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    70.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    70.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    70.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    70.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    70.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    71.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    71.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    71.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    71.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    71.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    71.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    71.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    71.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    71.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    71.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    72.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b99070]
>[    72.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b99070] width 1920 pitch 7680 (/4 1920)
>[    72.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b990d0]
>[    72.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b990d0] width 1920 pitch 7680 (/4 1920)
>[    73.986] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[    73.986] (II) RADEON(0): Using hsync ranges from config file
>[    73.986] (II) RADEON(0): Using vrefresh ranges from config file
>[    73.986] (II) RADEON(0): Printing DDC gathered Modelines:
>[    73.986] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    73.986] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    73.986] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    73.986] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    73.986] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    73.986] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    73.986] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[    75.263] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[    75.263] (II) RADEON(0): Using hsync ranges from config file
>[    75.263] (II) RADEON(0): Using vrefresh ranges from config file
>[    75.263] (II) RADEON(0): Printing DDC gathered Modelines:
>[    75.263] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    75.263] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    75.263] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    75.263] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    75.263] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    75.263] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    75.263] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    75.263] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    75.264] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    75.264] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    75.264] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    75.264] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    75.264] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[    75.394] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[    75.394] (II) RADEON(0): Using hsync ranges from config file
>[    75.394] (II) RADEON(0): Using vrefresh ranges from config file
>[    75.394] (II) RADEON(0): Printing DDC gathered Modelines:
>[    75.394] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    75.394] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    75.394] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    75.394] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    75.394] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    75.394] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[    75.394] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[    80.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbe50]
>[    80.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbe50] width 1920 pitch 7680 (/4 1920)
>[    88.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bea380]
>[    88.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bea380] width 1920 pitch 7680 (/4 1920)
>[    89.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf20c0]
>[    89.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf20c0] width 1920 pitch 7680 (/4 1920)
>[    89.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf67f0]
>[    89.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf67f0] width 1920 pitch 7680 (/4 1920)
>[    89.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beec70]
>[    89.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beec70] width 1920 pitch 7680 (/4 1920)
>[    89.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c60e0]
>[    89.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c60e0] width 1920 pitch 7680 (/4 1920)
>[    89.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05510]
>[    89.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05510] width 1920 pitch 7680 (/4 1920)
>[    92.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c054b0]
>[    92.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c054b0] width 1920 pitch 7680 (/4 1920)
>[    92.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c60e0]
>[    92.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c60e0] width 1920 pitch 7680 (/4 1920)
>[    92.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c054b0]
>[    92.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c054b0] width 1920 pitch 7680 (/4 1920)
>[    92.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c60e0]
>[    92.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c60e0] width 1920 pitch 7680 (/4 1920)
>[    92.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c054b0]
>[    92.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c054b0] width 1920 pitch 7680 (/4 1920)
>[    92.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92770]
>[    92.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92770] width 1920 pitch 7680 (/4 1920)
>[    92.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff690]
>[    92.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff690] width 1920 pitch 7680 (/4 1920)
>[    92.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92770]
>[    92.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92770] width 1920 pitch 7680 (/4 1920)
>[    93.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff690]
>[    93.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff690] width 1920 pitch 7680 (/4 1920)
>[    93.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92770]
>[    93.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92770] width 1920 pitch 7680 (/4 1920)
>[    93.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff690]
>[    93.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff690] width 1920 pitch 7680 (/4 1920)
>[    93.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05a70]
>[    93.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05a70] width 1920 pitch 7680 (/4 1920)
>[    93.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c6770]
>[    93.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c6770] width 1920 pitch 7680 (/4 1920)
>[    93.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05a70]
>[    93.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05a70] width 1920 pitch 7680 (/4 1920)
>[    95.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    95.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    95.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06120]
>[    95.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06120] width 1920 pitch 7680 (/4 1920)
>[    95.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    95.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    95.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c058d0]
>[    95.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c058d0] width 1920 pitch 7680 (/4 1920)
>[    96.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28e33f0]
>[    96.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28e33f0] width 1920 pitch 7680 (/4 1920)
>[    96.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b927a0]
>[    96.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b927a0] width 1920 pitch 7680 (/4 1920)
>[    96.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06240]
>[    96.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06240] width 1920 pitch 7680 (/4 1920)
>[    96.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c061f0]
>[    97.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c061f0] width 1920 pitch 7680 (/4 1920)
>[    97.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92770]
>[    97.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92770] width 1920 pitch 7680 (/4 1920)
>[    97.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c061f0]
>[    97.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c061f0] width 1920 pitch 7680 (/4 1920)
>[    97.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92770]
>[    97.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92770] width 1920 pitch 7680 (/4 1920)
>[    99.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06260]
>[    99.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06260] width 1920 pitch 7680 (/4 1920)
>[    99.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05930]
>[    99.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05930] width 1920 pitch 7680 (/4 1920)
>[    99.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c058d0]
>[    99.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c058d0] width 1920 pitch 7680 (/4 1920)
>[    99.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05930]
>[    99.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05930] width 1920 pitch 7680 (/4 1920)
>[    99.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c058d0]
>[    99.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c058d0] width 1920 pitch 7680 (/4 1920)
>[    99.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05930]
>[    99.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05930] width 1920 pitch 7680 (/4 1920)
>[    99.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c058d0]
>[    99.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c058d0] width 1920 pitch 7680 (/4 1920)
>[   100.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05e10]
>[   100.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05e10] width 1920 pitch 7680 (/4 1920)
>[   100.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c60e0]
>[   100.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c60e0] width 1920 pitch 7680 (/4 1920)
>[   101.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05b20]
>[   101.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05b20] width 1920 pitch 7680 (/4 1920)
>[   106.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ec80]
>[   106.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ec80] width 1920 pitch 7680 (/4 1920)
>[   107.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c064e0]
>[   107.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c064e0] width 1920 pitch 7680 (/4 1920)
>[   107.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b550]
>[   107.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b550] width 1920 pitch 7680 (/4 1920)
>[   110.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca1130]
>[   110.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca1130] width 1920 pitch 7680 (/4 1920)
>[   114.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d330]
>[   114.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d330] width 1920 pitch 7680 (/4 1920)
>[   119.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c764e0]
>[   119.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c764e0] width 1920 pitch 7680 (/4 1920)
>[   123.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7a510]
>[   123.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7a510] width 1920 pitch 7680 (/4 1920)
>[   128.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   128.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   128.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   128.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   128.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   128.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   128.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   128.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   128.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6cc40]
>[   128.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6cc40] width 1920 pitch 7680 (/4 1920)
>[   128.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   128.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   128.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   128.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   128.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c658c0]
>[   128.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c658c0] width 1920 pitch 7680 (/4 1920)
>[   128.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   128.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   128.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c658c0]
>[   128.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c658c0] width 1920 pitch 7680 (/4 1920)
>[   128.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   128.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   128.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c658c0]
>[   128.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c658c0] width 1920 pitch 7680 (/4 1920)
>[   129.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6cc40]
>[   129.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6cc40] width 1920 pitch 7680 (/4 1920)
>[   129.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ce50]
>[   129.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ce50] width 1920 pitch 7680 (/4 1920)
>[   129.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   129.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   129.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d700]
>[   129.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d700] width 1920 pitch 7680 (/4 1920)
>[   129.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   129.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e450]
>[   129.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e450] width 1920 pitch 7680 (/4 1920)
>[   199.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c877b0]
>[   199.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c877b0] width 1920 pitch 7680 (/4 1920)
>[   199.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   199.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   199.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   199.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   199.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   199.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   199.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   199.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   199.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   199.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   199.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   199.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   199.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   200.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   200.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   200.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   200.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   200.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   200.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   200.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   200.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86a70]
>[   200.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86a70] width 1920 pitch 7680 (/4 1920)
>[   200.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c862b0]
>[   200.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c862b0] width 1920 pitch 7680 (/4 1920)
>[   204.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   204.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380]
>[   204.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1920 pitch 7680 (/4 1920)
>[   204.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76bc0]
>[   204.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76bc0] width 1920 pitch 7680 (/4 1920)
>[   205.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c85a40]
>[   205.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c85a40] width 1920 pitch 7680 (/4 1920)
>[   206.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64cd0]
>[   206.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64cd0] width 1920 pitch 7680 (/4 1920)
>[   246.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6d920]
>[   246.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6d920] width 1920 pitch 7680 (/4 1920)
>[   246.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb3fb0]
>[   246.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb3fb0] width 1920 pitch 7680 (/4 1920)
>[   984.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   984.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   984.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   984.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   984.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   984.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   984.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   984.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   984.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   984.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   984.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   984.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   984.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   984.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   985.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   985.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   985.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   985.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   985.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   985.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   985.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   985.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   985.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   985.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   985.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   985.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   986.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   986.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[   986.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c736d0]
>[   986.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c736d0] width 1920 pitch 7680 (/4 1920)
>[   986.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cdb8b0]
>[   986.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cdb8b0] width 1920 pitch 7680 (/4 1920)
>[  4796.476] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[  4796.476] (II) RADEON(0): Using hsync ranges from config file
>[  4796.476] (II) RADEON(0): Using vrefresh ranges from config file
>[  4796.476] (II) RADEON(0): Printing DDC gathered Modelines:
>[  4796.476] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[  4796.476] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[  4796.476] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[  4796.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f7a0]
>[  4796.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f7a0] width 1920 pitch 7680 (/4 1920)
>[  4796.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d936a0]
>[  4796.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d936a0] width 1920 pitch 7680 (/4 1920)
>[  4886.925] (II) RADEON(0): RADEONSaveScreen(2)
>[  4886.925] (II) RADEON(0): RADEONSaveScreen(0)
>[ 32745.712] (II) RADEON(0): RADEONSaveScreen(1)
>[ 32749.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92fc0]
>[ 32749.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92fc0] width 1920 pitch 7680 (/4 1920)
>[ 32749.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92fc0]
>[ 32749.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92fc0] width 1920 pitch 7680 (/4 1920)
>[ 32749.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92fc0]
>[ 32749.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92fc0] width 1920 pitch 7680 (/4 1920)
>[ 32749.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92fc0]
>[ 32749.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92fc0] width 1920 pitch 7680 (/4 1920)
>[ 32749.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b92fc0]
>[ 32749.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b92fc0] width 1920 pitch 7680 (/4 1920)
>[ 32749.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b21ef0]
>[ 32749.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b21ef0] width 1920 pitch 7680 (/4 1920)
>[ 32749.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93c00]
>[ 32749.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93c00] width 1920 pitch 7680 (/4 1920)
>[ 32749.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfac70]
>[ 32749.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfac70] width 1920 pitch 7680 (/4 1920)
>[ 32749.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93c00]
>[ 32749.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93c00] width 1920 pitch 7680 (/4 1920)
>[ 32749.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfac70]
>[ 32749.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfac70] width 1920 pitch 7680 (/4 1920)
>[ 32749.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93c00]
>[ 32749.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93c00] width 1920 pitch 7680 (/4 1920)
>[ 32749.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93c00]
>[ 32749.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93c00] width 1920 pitch 7680 (/4 1920)
>[ 32749.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 32749.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93c00]
>[ 32749.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93c00] width 1920 pitch 7680 (/4 1920)
>[ 32749.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b93480]
>[ 32749.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b93480] width 1920 pitch 7680 (/4 1920)
>[ 34879.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf32e0]
>[ 34879.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf32e0] width 1920 pitch 7680 (/4 1920)
>[ 34879.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f340]
>[ 34879.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f340] width 1920 pitch 7680 (/4 1920)
>[ 37135.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37135.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37135.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37135.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37135.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37135.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37135.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37135.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37135.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37136.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37136.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37136.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37136.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37136.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37136.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37136.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37136.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37136.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37136.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37136.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37136.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37136.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37136.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37136.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37137.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37137.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37137.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37137.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37137.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37137.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f1a0]
>[ 37138.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f1a0] width 1920 pitch 7680 (/4 1920)
>[ 37138.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37138.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37138.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65d90]
>[ 37138.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65d90] width 1920 pitch 7680 (/4 1920)
>[ 37138.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b210e0]
>[ 37138.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b210e0] width 1920 pitch 7680 (/4 1920)
>[ 37138.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b210e0]
>[ 37138.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b210e0] width 1920 pitch 7680 (/4 1920)
>[ 37138.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37138.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37138.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d90bd0]
>[ 37138.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d90bd0] width 1920 pitch 7680 (/4 1920)
>[ 37138.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37139.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37139.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37139.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37139.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b210e0]
>[ 37139.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b210e0] width 1920 pitch 7680 (/4 1920)
>[ 37139.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37139.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37139.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37139.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37139.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37139.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37139.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d15020]
>[ 37139.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d15020] width 1920 pitch 7680 (/4 1920)
>[ 37139.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d153c0]
>[ 37139.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d153c0] width 1920 pitch 7680 (/4 1920)
>[ 37139.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a2f0]
>[ 37140.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a2f0] width 1920 pitch 7680 (/4 1920)
>[ 37140.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37140.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37140.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d20bb0]
>[ 37140.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d20bb0] width 1920 pitch 7680 (/4 1920)
>[ 37140.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22330]
>[ 37140.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22330] width 1920 pitch 7680 (/4 1920)
>[ 37140.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c222d0]
>[ 37140.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c222d0] width 1920 pitch 7680 (/4 1920)
>[ 37140.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45190]
>[ 37140.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45190] width 1920 pitch 7680 (/4 1920)
>[ 37140.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22580]
>[ 37140.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22580] width 1920 pitch 7680 (/4 1920)
>[ 37140.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22550]
>[ 37140.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22550] width 1920 pitch 7680 (/4 1920)
>[ 37140.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d20a20]
>[ 37140.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d20a20] width 1920 pitch 7680 (/4 1920)
>[ 37140.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c224f0]
>[ 37140.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c224f0] width 1920 pitch 7680 (/4 1920)
>[ 37140.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fef0]
>[ 37140.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fef0] width 1920 pitch 7680 (/4 1920)
>[ 37140.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fef0]
>[ 37140.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fef0] width 1920 pitch 7680 (/4 1920)
>[ 37140.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fc70]
>[ 37140.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fc70] width 1920 pitch 7680 (/4 1920)
>[ 37140.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37140.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37140.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fc70]
>[ 37140.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fc70] width 1920 pitch 7680 (/4 1920)
>[ 37140.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37140.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37140.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fc70]
>[ 37140.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fc70] width 1920 pitch 7680 (/4 1920)
>[ 37140.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22460]
>[ 37140.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22460] width 1920 pitch 7680 (/4 1920)
>[ 37140.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22460]
>[ 37140.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22460] width 1920 pitch 7680 (/4 1920)
>[ 37141.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fef0]
>[ 37141.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fef0] width 1920 pitch 7680 (/4 1920)
>[ 37141.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22460]
>[ 37141.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22460] width 1920 pitch 7680 (/4 1920)
>[ 37141.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fef0]
>[ 37141.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fef0] width 1920 pitch 7680 (/4 1920)
>[ 37141.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c224f0]
>[ 37141.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c224f0] width 1920 pitch 7680 (/4 1920)
>[ 37143.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c224f0]
>[ 37143.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c224f0] width 1920 pitch 7680 (/4 1920)
>[ 37143.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37143.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37143.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c224f0]
>[ 37143.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c224f0] width 1920 pitch 7680 (/4 1920)
>[ 37143.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22580]
>[ 37143.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22580] width 1920 pitch 7680 (/4 1920)
>[ 37143.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37143.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37143.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22580]
>[ 37143.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22580] width 1920 pitch 7680 (/4 1920)
>[ 37143.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d20a70]
>[ 37143.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d20a70] width 1920 pitch 7680 (/4 1920)
>[ 37143.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d20a70]
>[ 37143.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d20a70] width 1920 pitch 7680 (/4 1920)
>[ 37143.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37143.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37143.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1fef0]
>[ 37143.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1fef0] width 1920 pitch 7680 (/4 1920)
>[ 37143.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d20a70]
>[ 37143.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d20a70] width 1920 pitch 7680 (/4 1920)
>[ 37143.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33968c0]
>[ 37143.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33968c0] width 1920 pitch 7680 (/4 1920)
>[ 37143.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d209f0]
>[ 37143.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d209f0] width 1920 pitch 7680 (/4 1920)
>[ 37145.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72580]
>[ 37145.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72580] width 1920 pitch 7680 (/4 1920)
>[ 37145.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72580]
>[ 37145.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72580] width 1920 pitch 7680 (/4 1920)
>[ 37150.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7b0b0]
>[ 37150.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7b0b0] width 1920 pitch 7680 (/4 1920)
>[ 37150.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460c4a0]
>[ 37150.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460c4a0] width 1920 pitch 7680 (/4 1920)
>[ 37248.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c045b0]
>[ 37248.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c045b0] width 1920 pitch 7680 (/4 1920)
>[ 37260.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37260.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37260.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37260.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37260.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37260.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37260.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37260.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37260.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37261.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37261.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37261.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a4b0]
>[ 37261.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a4b0] width 1920 pitch 7680 (/4 1920)
>[ 37261.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37261.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37261.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589240]
>[ 37261.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589240] width 1920 pitch 7680 (/4 1920)
>[ 37261.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589240]
>[ 37261.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589240] width 1920 pitch 7680 (/4 1920)
>[ 37261.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37261.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37261.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589240]
>[ 37261.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589240] width 1920 pitch 7680 (/4 1920)
>[ 37261.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37261.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37262.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f290]
>[ 37262.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f290] width 1920 pitch 7680 (/4 1920)
>[ 37264.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37264.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37264.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80830]
>[ 37264.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80830] width 1920 pitch 7680 (/4 1920)
>[ 37264.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a760]
>[ 37264.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a760] width 1920 pitch 7680 (/4 1920)
>[ 37264.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80830]
>[ 37264.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80830] width 1920 pitch 7680 (/4 1920)
>[ 37264.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d35c00]
>[ 37264.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d35c00] width 1920 pitch 7680 (/4 1920)
>[ 37264.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37264.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37264.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a760]
>[ 37264.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a760] width 1920 pitch 7680 (/4 1920)
>[ 37264.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d35c00]
>[ 37264.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d35c00] width 1920 pitch 7680 (/4 1920)
>[ 37264.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a760]
>[ 37264.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a760] width 1920 pitch 7680 (/4 1920)
>[ 37264.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37264.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37264.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37264.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37264.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37264.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37264.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7a760]
>[ 37265.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7a760] width 1920 pitch 7680 (/4 1920)
>[ 37265.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d80d90]
>[ 37265.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d80d90] width 1920 pitch 7680 (/4 1920)
>[ 37265.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d24f20]
>[ 37265.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d24f20] width 1920 pitch 7680 (/4 1920)
>[ 37265.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589000]
>[ 37265.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589000] width 1920 pitch 7680 (/4 1920)
>[ 37265.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589240]
>[ 37265.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589240] width 1920 pitch 7680 (/4 1920)
>[ 37265.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37265.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37265.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d25240]
>[ 37265.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d25240] width 1920 pitch 7680 (/4 1920)
>[ 37265.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d25240]
>[ 37265.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d25240] width 1920 pitch 7680 (/4 1920)
>[ 37270.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46141d0]
>[ 37270.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46141d0] width 1920 pitch 7680 (/4 1920)
>[ 37272.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37272.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37272.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d75700]
>[ 37272.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d75700] width 1920 pitch 7680 (/4 1920)
>[ 37272.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d75700]
>[ 37272.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d75700] width 1920 pitch 7680 (/4 1920)
>[ 37272.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d8e2e0]
>[ 37272.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d8e2e0] width 1920 pitch 7680 (/4 1920)
>[ 37286.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d375c0]
>[ 37286.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d375c0] width 1920 pitch 7680 (/4 1920)
>[ 37287.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2fb40]
>[ 37287.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2fb40] width 1920 pitch 7680 (/4 1920)
>[ 37287.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d5ee20]
>[ 37287.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d5ee20] width 1920 pitch 7680 (/4 1920)
>[ 37287.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d75700]
>[ 37287.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d75700] width 1920 pitch 7680 (/4 1920)
>[ 37288.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37288.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37302.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4634140]
>[ 37302.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4634140] width 1920 pitch 7680 (/4 1920)
>[ 37332.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37332.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37332.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37333.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37333.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37333.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f420]
>[ 37333.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f420] width 1920 pitch 7680 (/4 1920)
>[ 37333.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37333.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37333.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4634610]
>[ 37333.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4634610] width 1920 pitch 7680 (/4 1920)
>[ 37333.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37333.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37333.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37333.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37333.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4634610]
>[ 37333.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4634610] width 1920 pitch 7680 (/4 1920)
>[ 37333.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37333.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37333.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37333.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37334.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37334.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37334.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37334.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37334.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9b510]
>[ 37334.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9b510] width 1920 pitch 7680 (/4 1920)
>[ 37334.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4634610]
>[ 37334.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4634610] width 1920 pitch 7680 (/4 1920)
>[ 37334.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387f30]
>[ 37334.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387f30] width 1920 pitch 7680 (/4 1920)
>[ 37334.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387f30]
>[ 37334.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387f30] width 1920 pitch 7680 (/4 1920)
>[ 37334.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d940a0]
>[ 37334.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d940a0] width 1920 pitch 7680 (/4 1920)
>[ 37334.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466ed10]
>[ 37334.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466ed10] width 1920 pitch 7680 (/4 1920)
>[ 37340.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d5c750]
>[ 37340.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d5c750] width 1920 pitch 7680 (/4 1920)
>[ 37341.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37341.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37341.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37341.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37341.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37341.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37341.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37341.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37341.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670780]
>[ 37341.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670780] width 1920 pitch 7680 (/4 1920)
>[ 37341.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37341.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37341.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670780]
>[ 37341.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670780] width 1920 pitch 7680 (/4 1920)
>[ 37341.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37341.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37341.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37341.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37341.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37341.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37341.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37341.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37341.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37342.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37342.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37342.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37342.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37342.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37342.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37342.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37342.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37342.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37342.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37342.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37342.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37342.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37342.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37343.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37343.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37343.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37343.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37343.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37343.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37343.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37343.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7dc90]
>[ 37343.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7dc90] width 1920 pitch 7680 (/4 1920)
>[ 37343.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37343.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37343.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37343.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37343.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37343.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37343.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83a30]
>[ 37343.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83a30] width 1920 pitch 7680 (/4 1920)
>[ 37343.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37343.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37343.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460fcb0]
>[ 37343.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460fcb0] width 1920 pitch 7680 (/4 1920)
>[ 37343.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d25040]
>[ 37343.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d25040] width 1920 pitch 7680 (/4 1920)
>[ 37343.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37343.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37343.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37343.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37343.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37343.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37343.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d25040]
>[ 37344.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d25040] width 1920 pitch 7680 (/4 1920)
>[ 37358.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfbf90]
>[ 37358.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfbf90] width 1920 pitch 7680 (/4 1920)
>[ 37360.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4623860]
>[ 37360.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4623860] width 1920 pitch 7680 (/4 1920)
>[ 37360.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4870]
>[ 37360.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4870] width 1920 pitch 7680 (/4 1920)
>[ 37369.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d36be0]
>[ 37369.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d36be0] width 1920 pitch 7680 (/4 1920)
>[ 37369.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37369.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37371.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4870]
>[ 37371.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4870] width 1920 pitch 7680 (/4 1920)
>[ 37371.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37371.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37371.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4870]
>[ 37371.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4870] width 1920 pitch 7680 (/4 1920)
>[ 37371.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37371.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37371.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4623860]
>[ 37371.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4623860] width 1920 pitch 7680 (/4 1920)
>[ 37371.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37371.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37371.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4623860]
>[ 37371.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4623860] width 1920 pitch 7680 (/4 1920)
>[ 37371.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37371.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37373.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94fe0]
>[ 37373.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94fe0] width 1920 pitch 7680 (/4 1920)
>[ 37373.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37373.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37373.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d36be0]
>[ 37373.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d36be0] width 1920 pitch 7680 (/4 1920)
>[ 37373.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4623860]
>[ 37373.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4623860] width 1920 pitch 7680 (/4 1920)
>[ 37374.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d36be0]
>[ 37374.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d36be0] width 1920 pitch 7680 (/4 1920)
>[ 37374.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94fe0]
>[ 37374.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94fe0] width 1920 pitch 7680 (/4 1920)
>[ 37375.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37375.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37375.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32af0]
>[ 37375.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32af0] width 1920 pitch 7680 (/4 1920)
>[ 37375.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37375.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37375.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37375.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37375.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d36be0]
>[ 37375.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d36be0] width 1920 pitch 7680 (/4 1920)
>[ 37375.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37375.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37375.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94fe0]
>[ 37375.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94fe0] width 1920 pitch 7680 (/4 1920)
>[ 37375.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37375.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37375.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37375.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37375.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4870]
>[ 37375.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4870] width 1920 pitch 7680 (/4 1920)
>[ 37375.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6fb10]
>[ 37375.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6fb10] width 1920 pitch 7680 (/4 1920)
>[ 37375.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d36be0]
>[ 37375.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d36be0] width 1920 pitch 7680 (/4 1920)
>[ 37405.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37405.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37405.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d848c0]
>[ 37405.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d848c0] width 1920 pitch 7680 (/4 1920)
>[ 37507.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfbef0]
>[ 37507.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfbef0] width 1920 pitch 7680 (/4 1920)
>[ 37507.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d8ec70]
>[ 37507.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d8ec70] width 1920 pitch 7680 (/4 1920)
>[ 37979.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d41e30]
>[ 37979.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d41e30] width 1920 pitch 7680 (/4 1920)
>[ 37979.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d26cf0]
>[ 37979.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d26cf0] width 1920 pitch 7680 (/4 1920)
>[ 38192.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d41e30]
>[ 38192.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d41e30] width 1920 pitch 7680 (/4 1920)
>[ 38192.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d26cf0]
>[ 38192.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d26cf0] width 1920 pitch 7680 (/4 1920)
>[ 38207.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d1da70]
>[ 38207.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d1da70] width 1920 pitch 7680 (/4 1920)
>[ 38207.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38207.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38207.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38207.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38207.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38207.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38207.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38207.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38207.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38207.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38207.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38207.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38208.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38208.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38208.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38208.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38208.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38208.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38208.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38208.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38208.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38208.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38208.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38208.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38208.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0f210]
>[ 38208.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0f210] width 1920 pitch 7680 (/4 1920)
>[ 38208.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38208.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38208.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 38208.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 38209.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 38209.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 38209.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 38209.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39625.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39625.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39625.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 39625.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39625.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39625.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39625.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 39625.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39625.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39625.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39625.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 39625.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 39625.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 39625.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39625.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39625.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 39626.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 39626.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 39626.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 39626.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 39626.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39626.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 39626.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 39626.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3350]
>[ 39626.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3350] width 1920 pitch 7680 (/4 1920)
>[ 39626.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39626.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39626.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 39627.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466f3c0]
>[ 39627.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466f3c0] width 1920 pitch 7680 (/4 1920)
>[ 39627.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 39627.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 43236.070] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[ 43236.070] (II) RADEON(0): Using hsync ranges from config file
>[ 43236.070] (II) RADEON(0): Using vrefresh ranges from config file
>[ 43236.070] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 43236.070] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 43236.070] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 43236.070] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 43236.071] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 43236.071] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 43236.071] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[ 43236.071] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[ 43236.071] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[ 43325.939] (II) RADEON(0): RADEONSaveScreen(2)
>[ 43325.939] (II) RADEON(0): RADEONSaveScreen(0)
>[ 45883.003] (II) RADEON(0): RADEONSaveScreen(1)
>[ 45887.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfa860]
>[ 45887.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfa860] width 1920 pitch 7680 (/4 1920)
>[ 46041.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3ce10]
>[ 46041.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3ce10] width 1920 pitch 7680 (/4 1920)
>[ 46041.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d12520]
>[ 46041.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d12520] width 1920 pitch 7680 (/4 1920)
>[ 46041.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46041.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46041.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46041.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46041.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46041.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46041.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46041.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46041.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46041.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46041.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46041.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46041.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46041.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46042.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46042.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46042.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46042.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46042.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46042.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46042.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46042.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46042.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db90]
>[ 46042.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db90] width 1920 pitch 7680 (/4 1920)
>[ 46042.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7db30]
>[ 46042.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7db30] width 1920 pitch 7680 (/4 1920)
>[ 46042.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46042.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46042.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3ce20]
>[ 46043.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3ce20] width 1920 pitch 7680 (/4 1920)
>[ 46043.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3ce20]
>[ 46043.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3ce20] width 1920 pitch 7680 (/4 1920)
>[ 46043.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3cdb0]
>[ 46043.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3cdb0] width 1920 pitch 7680 (/4 1920)
>[ 46043.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3cdb0]
>[ 46043.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3cdb0] width 1920 pitch 7680 (/4 1920)
>[ 46043.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d82570]
>[ 46043.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d82570] width 1920 pitch 7680 (/4 1920)
>[ 46043.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d82570]
>[ 46043.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d82570] width 1920 pitch 7680 (/4 1920)
>[ 46043.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x466fd80]
>[ 46043.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x466fd80] width 1920 pitch 7680 (/4 1920)
>[ 46043.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4636850]
>[ 46043.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4636850] width 1920 pitch 7680 (/4 1920)
>[ 46043.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46043.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46043.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4636850]
>[ 46043.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4636850] width 1920 pitch 7680 (/4 1920)
>[ 46044.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2c770]
>[ 46044.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2c770] width 1920 pitch 7680 (/4 1920)
>[ 46044.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cd60]
>[ 46044.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cd60] width 1920 pitch 7680 (/4 1920)
>[ 46044.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cd40]
>[ 46044.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cd40] width 1920 pitch 7680 (/4 1920)
>[ 46044.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4ccd0]
>[ 46044.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4ccd0] width 1920 pitch 7680 (/4 1920)
>[ 46044.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cc80]
>[ 46044.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cc80] width 1920 pitch 7680 (/4 1920)
>[ 46045.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cc40]
>[ 46045.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cc40] width 1920 pitch 7680 (/4 1920)
>[ 46045.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cbb0]
>[ 46045.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cbb0] width 1920 pitch 7680 (/4 1920)
>[ 46045.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cc40]
>[ 46045.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cc40] width 1920 pitch 7680 (/4 1920)
>[ 46045.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cbb0]
>[ 46045.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cbb0] width 1920 pitch 7680 (/4 1920)
>[ 46045.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cc40]
>[ 46045.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cc40] width 1920 pitch 7680 (/4 1920)
>[ 46045.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cca0]
>[ 46045.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cca0] width 1920 pitch 7680 (/4 1920)
>[ 46045.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a9ab00]
>[ 46045.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a9ab00] width 1920 pitch 7680 (/4 1920)
>[ 46048.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x473e190]
>[ 46048.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x473e190] width 1920 pitch 7680 (/4 1920)
>[ 46048.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d14e30]
>[ 46048.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d14e30] width 1920 pitch 7680 (/4 1920)
>[ 46052.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d139f0]
>[ 46052.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d139f0] width 1920 pitch 7680 (/4 1920)
>[ 46052.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 46052.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 46052.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776d50]
>[ 46052.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776d50] width 1920 pitch 7680 (/4 1920)
>[ 46052.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47777c0]
>[ 46052.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47777c0] width 1920 pitch 7680 (/4 1920)
>[ 46052.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776d50]
>[ 46052.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776d50] width 1920 pitch 7680 (/4 1920)
>[ 46052.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47777c0]
>[ 46052.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47777c0] width 1920 pitch 7680 (/4 1920)
>[ 46052.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b078f0]
>[ 46052.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b078f0] width 1920 pitch 7680 (/4 1920)
>[ 46052.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b073a0]
>[ 46052.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b073a0] width 1920 pitch 7680 (/4 1920)
>[ 46052.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b058a0]
>[ 46053.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b058a0] width 1920 pitch 7680 (/4 1920)
>[ 46053.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cb80]
>[ 46053.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cb80] width 1920 pitch 7680 (/4 1920)
>[ 46053.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b058a0]
>[ 46053.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b058a0] width 1920 pitch 7680 (/4 1920)
>[ 46053.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cb80]
>[ 46053.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cb80] width 1920 pitch 7680 (/4 1920)
>[ 46053.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b058a0]
>[ 46053.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b058a0] width 1920 pitch 7680 (/4 1920)
>[ 46053.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cb80]
>[ 46053.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cb80] width 1920 pitch 7680 (/4 1920)
>[ 46054.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4767320]
>[ 46054.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4767320] width 1920 pitch 7680 (/4 1920)
>[ 46054.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46840]
>[ 46054.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46840] width 1920 pitch 7680 (/4 1920)
>[ 46054.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0e180]
>[ 46054.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0e180] width 1920 pitch 7680 (/4 1920)
>[ 46054.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b09860]
>[ 46054.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b09860] width 1920 pitch 7680 (/4 1920)
>[ 46054.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44410]
>[ 46054.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44410] width 1920 pitch 7680 (/4 1920)
>[ 46054.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b09860]
>[ 46054.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b09860] width 1920 pitch 7680 (/4 1920)
>[ 46054.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b058a0]
>[ 46054.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b058a0] width 1920 pitch 7680 (/4 1920)
>[ 46054.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b09860]
>[ 46054.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b09860] width 1920 pitch 7680 (/4 1920)
>[ 46054.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46840]
>[ 46054.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46840] width 1920 pitch 7680 (/4 1920)
>[ 46054.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b09860]
>[ 46054.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b09860] width 1920 pitch 7680 (/4 1920)
>[ 46054.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4767320]
>[ 46054.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4767320] width 1920 pitch 7680 (/4 1920)
>[ 46054.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b09860]
>[ 46054.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b09860] width 1920 pitch 7680 (/4 1920)
>[ 46054.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0e180]
>[ 46054.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0e180] width 1920 pitch 7680 (/4 1920)
>[ 46054.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44410]
>[ 46054.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44410] width 1920 pitch 7680 (/4 1920)
>[ 46090.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46090.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46090.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46090.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46090.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46090.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46090.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46090.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46090.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46090.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46090.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46090.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46090.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46090.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46090.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46090.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46091.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46091.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46091.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46091.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46091.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46091.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46091.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46091.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46091.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46091.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46091.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46091.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46091.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46091.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46091.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46091.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46091.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46091.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46092.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46092.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46092.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4772a20]
>[ 46092.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4772a20] width 1920 pitch 7680 (/4 1920)
>[ 46092.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3cdb0]
>[ 46092.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3cdb0] width 1920 pitch 7680 (/4 1920)
>[ 46093.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47626c0]
>[ 46093.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47626c0] width 1920 pitch 7680 (/4 1920)
>[ 46125.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46125.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46125.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46125.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46125.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46126.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46126.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46126.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46126.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46126.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46126.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46126.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46126.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46126.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46126.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46126.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46126.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46127.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46127.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46127.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46127.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46127.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46127.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39cb0]
>[ 46127.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39cb0] width 1920 pitch 7680 (/4 1920)
>[ 46128.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b383c0]
>[ 46128.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b383c0] width 1920 pitch 7680 (/4 1920)
>[ 46129.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46129.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46129.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46129.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46129.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f8d0]
>[ 46129.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f8d0] width 1920 pitch 7680 (/4 1920)
>[ 46129.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46129.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46129.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f8d0]
>[ 46129.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f8d0] width 1920 pitch 7680 (/4 1920)
>[ 46129.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46129.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46129.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f8d0]
>[ 46129.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f8d0] width 1920 pitch 7680 (/4 1920)
>[ 46129.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b380a0]
>[ 46129.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b380a0] width 1920 pitch 7680 (/4 1920)
>[ 46129.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f8d0]
>[ 46130.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f8d0] width 1920 pitch 7680 (/4 1920)
>[ 46159.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476da00]
>[ 46159.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476da00] width 1920 pitch 7680 (/4 1920)
>[ 46159.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32d40]
>[ 46159.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32d40] width 1920 pitch 7680 (/4 1920)
>[ 46159.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32ce0]
>[ 46159.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32ce0] width 1920 pitch 7680 (/4 1920)
>[ 46159.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32d40]
>[ 46159.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32d40] width 1920 pitch 7680 (/4 1920)
>[ 46159.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32ce0]
>[ 46159.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32ce0] width 1920 pitch 7680 (/4 1920)
>[ 46159.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32d40]
>[ 46159.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32d40] width 1920 pitch 7680 (/4 1920)
>[ 46159.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32ce0]
>[ 46159.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32ce0] width 1920 pitch 7680 (/4 1920)
>[ 46159.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32d40]
>[ 46159.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32d40] width 1920 pitch 7680 (/4 1920)
>[ 46159.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[ 46159.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[ 46160.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33630]
>[ 46160.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33630] width 1920 pitch 7680 (/4 1920)
>[ 46160.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[ 46160.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[ 46160.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33630]
>[ 46160.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33630] width 1920 pitch 7680 (/4 1920)
>[ 46160.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[ 46160.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[ 46160.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33630]
>[ 46160.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33630] width 1920 pitch 7680 (/4 1920)
>[ 46160.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[ 46161.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[ 46161.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33630]
>[ 46161.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33630] width 1920 pitch 7680 (/4 1920)
>[ 46161.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49930]
>[ 46161.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49930] width 1920 pitch 7680 (/4 1920)
>[ 46161.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c03fd0]
>[ 46161.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c03fd0] width 1920 pitch 7680 (/4 1920)
>[ 46161.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49930]
>[ 46161.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49930] width 1920 pitch 7680 (/4 1920)
>[ 46161.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c03fd0]
>[ 46161.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c03fd0] width 1920 pitch 7680 (/4 1920)
>[ 46161.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49930]
>[ 46161.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49930] width 1920 pitch 7680 (/4 1920)
>[ 46161.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c03fd0]
>[ 46161.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c03fd0] width 1920 pitch 7680 (/4 1920)
>[ 46161.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49930]
>[ 46161.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49930] width 1920 pitch 7680 (/4 1920)
>[ 46161.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c03fd0]
>[ 46161.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c03fd0] width 1920 pitch 7680 (/4 1920)
>[ 46171.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8f4f0]
>[ 46171.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8f4f0] width 1920 pitch 7680 (/4 1920)
>[ 46184.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2e720]
>[ 46184.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2e720] width 1920 pitch 7680 (/4 1920)
>[ 46411.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d5a0]
>[ 46412.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d5a0] width 1920 pitch 7680 (/4 1920)
>[ 46430.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d2d0]
>[ 46430.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d2d0] width 1920 pitch 7680 (/4 1920)
>[ 46430.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aa00]
>[ 46430.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aa00] width 1920 pitch 7680 (/4 1920)
>[ 46437.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d780]
>[ 46437.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d780] width 1920 pitch 7680 (/4 1920)
>[ 46437.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d5e0]
>[ 46437.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d5e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46437.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46437.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46437.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46437.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46437.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46437.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46437.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46437.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46438.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46438.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46438.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46438.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46438.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46438.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46438.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46438.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46439.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46439.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46439.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46439.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46439.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46439.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46439.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46446.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46446.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46446.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a470]
>[ 46446.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a470] width 1920 pitch 7680 (/4 1920)
>[ 46446.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46446.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46446.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a470]
>[ 46446.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a470] width 1920 pitch 7680 (/4 1920)
>[ 46446.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46446.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46446.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a470]
>[ 46446.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a470] width 1920 pitch 7680 (/4 1920)
>[ 46446.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46446.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46446.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a470]
>[ 46446.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a470] width 1920 pitch 7680 (/4 1920)
>[ 46446.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46446.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46447.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46447.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46447.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46447.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46447.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46447.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46447.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46447.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46447.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46447.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46448.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0e0]
>[ 46448.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0e0] width 1920 pitch 7680 (/4 1920)
>[ 46448.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4eba0]
>[ 46448.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4eba0] width 1920 pitch 7680 (/4 1920)
>[ 46448.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4eba0]
>[ 46449.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4eba0] width 1920 pitch 7680 (/4 1920)
>[ 46449.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4d6f0]
>[ 46449.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4d6f0] width 1920 pitch 7680 (/4 1920)
>[ 46449.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4eba0]
>[ 46449.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4eba0] width 1920 pitch 7680 (/4 1920)
>[ 46449.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3b0e0]
>[ 46449.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3b0e0] width 1920 pitch 7680 (/4 1920)
>[ 46449.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4cc50]
>[ 46449.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4cc50] width 1920 pitch 7680 (/4 1920)
>[ 52467.167] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[ 52467.167] (II) RADEON(0): Using hsync ranges from config file
>[ 52467.167] (II) RADEON(0): Using vrefresh ranges from config file
>[ 52467.167] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 52467.167] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 52467.167] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[ 52467.167] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[ 52556.920] (II) RADEON(0): RADEONSaveScreen(2)
>[ 52556.920] (II) RADEON(0): RADEONSaveScreen(0)
>[ 54931.319] (II) RADEON(0): RADEONSaveScreen(1)
>[ 54934.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45962d0]
>[ 54934.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45962d0] width 1920 pitch 7680 (/4 1920)
>[ 54945.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54945.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54946.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54946.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54946.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54946.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54946.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54946.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54946.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54946.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54946.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54946.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54946.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54946.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54946.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54946.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54946.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54946.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54947.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54947.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54947.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54947.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54947.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54947.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54947.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54947.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54947.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54947.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54947.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54947.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54947.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54947.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54947.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54947.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54947.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54971.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54971.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54971.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54971.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54971.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54971.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54971.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54971.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54971.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54971.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54971.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54971.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54971.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54971.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54971.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54971.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54971.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54971.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54971.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54971.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54972.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54972.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54972.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54972.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 54972.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9260]
>[ 54972.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9260] width 1920 pitch 7680 (/4 1920)
>[ 54972.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d83510]
>[ 54972.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d83510] width 1920 pitch 7680 (/4 1920)
>[ 56499.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a910]
>[ 56499.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a910] width 1920 pitch 7680 (/4 1920)
>[ 56499.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4774820]
>[ 56499.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4774820] width 1920 pitch 7680 (/4 1920)
>[ 56514.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7d770]
>[ 56514.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7d770] width 1920 pitch 7680 (/4 1920)
>[ 56562.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b77420]
>[ 56562.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b77420] width 1920 pitch 7680 (/4 1920)
>[ 56562.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56563.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56563.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56563.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56563.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56563.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56563.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56563.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56563.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56563.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56563.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56563.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56563.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56563.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56563.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56563.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56563.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56563.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56563.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56563.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56564.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56564.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56564.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56564.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56564.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56564.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56565.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56565.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56565.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b76d40]
>[ 56565.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b76d40] width 1920 pitch 7680 (/4 1920)
>[ 56566.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40e20]
>[ 56566.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40e20] width 1920 pitch 7680 (/4 1920)
>[ 56566.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d74e90]
>[ 56566.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d74e90] width 1920 pitch 7680 (/4 1920)
>[ 56566.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3aef0]
>[ 56566.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3aef0] width 1920 pitch 7680 (/4 1920)
>[ 56566.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d74e90]
>[ 56566.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d74e90] width 1920 pitch 7680 (/4 1920)
>[ 56566.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3aef0]
>[ 56566.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3aef0] width 1920 pitch 7680 (/4 1920)
>[ 56566.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d74e90]
>[ 56566.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d74e90] width 1920 pitch 7680 (/4 1920)
>[ 56566.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3aef0]
>[ 56566.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3aef0] width 1920 pitch 7680 (/4 1920)
>[ 56566.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d74e90]
>[ 56566.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d74e90] width 1920 pitch 7680 (/4 1920)
>[ 58073.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58073.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58073.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 58073.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 58073.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58073.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58073.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58073.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58073.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58073.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58073.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58073.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58073.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58073.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58073.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58073.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58073.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58073.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58073.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58073.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58074.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58074.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58074.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58074.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58074.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58074.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58074.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58074.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58074.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58074.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58074.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 58074.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 58074.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58074.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58074.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58074.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58075.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f90]
>[ 58075.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f90] width 1920 pitch 7680 (/4 1920)
>[ 58075.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 58075.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 58076.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3ff00]
>[ 58076.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3ff00] width 1920 pitch 7680 (/4 1920)
>[ 58088.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d175f0]
>[ 58088.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d175f0] width 1920 pitch 7680 (/4 1920)
>[ 58088.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[ 58088.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[ 58107.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc3450]
>[ 58107.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc3450] width 1920 pitch 7680 (/4 1920)
>[ 58108.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baa9c0]
>[ 58108.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baa9c0] width 1920 pitch 7680 (/4 1920)
>[ 58111.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb8030]
>[ 58111.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb8030] width 1920 pitch 7680 (/4 1920)
>[ 58114.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c05a40]
>[ 58114.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c05a40] width 1920 pitch 7680 (/4 1920)
>[ 58115.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd45f0]
>[ 58115.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd45f0] width 1920 pitch 7680 (/4 1920)
>[ 58116.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0bc80]
>[ 58116.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0bc80] width 1920 pitch 7680 (/4 1920)
>[ 58116.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb61e0]
>[ 58116.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb61e0] width 1920 pitch 7680 (/4 1920)
>[ 58121.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c11720]
>[ 58121.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c11720] width 1920 pitch 7680 (/4 1920)
>[ 58121.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c98950]
>[ 58121.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c98950] width 1920 pitch 7680 (/4 1920)
>[ 58124.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be2d50]
>[ 58124.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be2d50] width 1920 pitch 7680 (/4 1920)
>[ 58124.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58124.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58124.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be2d50]
>[ 58124.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be2d50] width 1920 pitch 7680 (/4 1920)
>[ 58124.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58124.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58124.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0be90]
>[ 58124.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0be90] width 1920 pitch 7680 (/4 1920)
>[ 58124.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58124.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58124.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0be90]
>[ 58124.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0be90] width 1920 pitch 7680 (/4 1920)
>[ 58124.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58124.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58124.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0be90]
>[ 58124.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0be90] width 1920 pitch 7680 (/4 1920)
>[ 58124.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58124.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58124.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0be90]
>[ 58124.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0be90] width 1920 pitch 7680 (/4 1920)
>[ 58124.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58125.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58125.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0be90]
>[ 58125.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0be90] width 1920 pitch 7680 (/4 1920)
>[ 58125.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c140a0]
>[ 58125.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c140a0] width 1920 pitch 7680 (/4 1920)
>[ 58125.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be2c80]
>[ 58125.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be2c80] width 1920 pitch 7680 (/4 1920)
>[ 58125.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be2c20]
>[ 58125.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be2c20] width 1920 pitch 7680 (/4 1920)
>[ 58125.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c998c0]
>[ 58125.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c998c0] width 1920 pitch 7680 (/4 1920)
>[ 58125.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c996e0]
>[ 58125.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c996e0] width 1920 pitch 7680 (/4 1920)
>[ 58125.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58125.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58125.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58125.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58125.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58125.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df50]
>[ 58125.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df50] width 1920 pitch 7680 (/4 1920)
>[ 58125.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c99820]
>[ 58125.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c99820] width 1920 pitch 7680 (/4 1920)
>[ 58131.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb8680]
>[ 58131.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb8680] width 1920 pitch 7680 (/4 1920)
>[ 58136.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc280]
>[ 58136.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc280] width 1920 pitch 7680 (/4 1920)
>[ 58138.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b650]
>[ 58138.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b650] width 1920 pitch 7680 (/4 1920)
>[ 58138.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b77d80]
>[ 58138.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b77d80] width 1920 pitch 7680 (/4 1920)
>[ 58138.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb7890]
>[ 58138.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb7890] width 1920 pitch 7680 (/4 1920)
>[ 58138.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8d80]
>[ 58138.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8d80] width 1920 pitch 7680 (/4 1920)
>[ 58139.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b77d80]
>[ 58139.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b77d80] width 1920 pitch 7680 (/4 1920)
>[ 58139.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58139.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58139.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b77d80]
>[ 58139.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b77d80] width 1920 pitch 7680 (/4 1920)
>[ 58139.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58139.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58139.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5c030]
>[ 58139.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5c030] width 1920 pitch 7680 (/4 1920)
>[ 58140.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca4880]
>[ 58140.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca4880] width 1920 pitch 7680 (/4 1920)
>[ 58140.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58140.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58140.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[ 58140.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[ 58140.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58140.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58140.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[ 58140.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[ 58140.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58140.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58140.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[ 58140.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[ 58140.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58140.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58141.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[ 58141.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[ 58141.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83cf0]
>[ 58141.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83cf0] width 1920 pitch 7680 (/4 1920)
>[ 58141.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b970]
>[ 58141.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b970] width 1920 pitch 7680 (/4 1920)
>[ 58141.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb220]
>[ 58141.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb220] width 1920 pitch 7680 (/4 1920)
>[ 58141.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb220]
>[ 58141.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb220] width 1920 pitch 7680 (/4 1920)
>[ 58141.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc2f50]
>[ 58141.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc2f50] width 1920 pitch 7680 (/4 1920)
>[ 58141.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb220]
>[ 58142.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb220] width 1920 pitch 7680 (/4 1920)
>[ 58142.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb2170]
>[ 58142.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb2170] width 1920 pitch 7680 (/4 1920)
>[ 58142.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb220]
>[ 58142.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb220] width 1920 pitch 7680 (/4 1920)
>[ 58142.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b92a80]
>[ 58142.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b92a80] width 1920 pitch 7680 (/4 1920)
>[ 58142.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc6990]
>[ 58142.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc6990] width 1920 pitch 7680 (/4 1920)
>[ 58142.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc3d70]
>[ 58142.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc3d70] width 1920 pitch 7680 (/4 1920)
>[ 58147.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15890]
>[ 58147.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15890] width 1920 pitch 7680 (/4 1920)
>[ 58157.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15f00]
>[ 58157.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15f00] width 1920 pitch 7680 (/4 1920)
>[ 58157.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba0220]
>[ 58157.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba0220] width 1920 pitch 7680 (/4 1920)
>[ 58157.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ae0]
>[ 58157.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ae0] width 1920 pitch 7680 (/4 1920)
>[ 58158.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4588860]
>[ 58158.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4588860] width 1920 pitch 7680 (/4 1920)
>[ 58159.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2f3f0]
>[ 58159.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2f3f0] width 1920 pitch 7680 (/4 1920)
>[ 58168.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdde50]
>[ 58168.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdde50] width 1920 pitch 7680 (/4 1920)
>[ 58168.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdde50]
>[ 58168.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdde50] width 1920 pitch 7680 (/4 1920)
>[ 58168.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdde50]
>[ 58168.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdde50] width 1920 pitch 7680 (/4 1920)
>[ 58168.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdde50]
>[ 58168.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdde50] width 1920 pitch 7680 (/4 1920)
>[ 58168.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdde50]
>[ 58168.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdde50] width 1920 pitch 7680 (/4 1920)
>[ 58168.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58168.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58168.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58168.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58168.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58168.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58169.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58169.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58169.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58169.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58170.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58170.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58170.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58170.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58172.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58172.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58173.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbdf0]
>[ 58173.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbdf0] width 1920 pitch 7680 (/4 1920)
>[ 58173.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58173.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58173.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58173.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58173.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58173.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58175.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cdddd0]
>[ 58175.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cdddd0] width 1920 pitch 7680 (/4 1920)
>[ 58175.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58175.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58175.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09980]
>[ 58175.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09980] width 1920 pitch 7680 (/4 1920)
>[ 58175.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58175.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58175.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58175.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58175.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58175.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58175.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c091b0]
>[ 58175.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c091b0] width 1920 pitch 7680 (/4 1920)
>[ 58175.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58175.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58175.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58175.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58175.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58175.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58175.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58175.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58175.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58176.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58176.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58176.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58176.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58176.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58176.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58176.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58176.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58176.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58176.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58176.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58176.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58176.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58176.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d189a0]
>[ 58176.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d189a0] width 1920 pitch 7680 (/4 1920)
>[ 58176.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58176.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58176.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58176.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58176.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfbd70]
>[ 58176.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfbd70] width 1920 pitch 7680 (/4 1920)
>[ 58176.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d99420]
>[ 58176.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d99420] width 1920 pitch 7680 (/4 1920)
>[ 58176.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d93ba0]
>[ 58176.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d93ba0] width 1920 pitch 7680 (/4 1920)
>[ 58177.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce90d0]
>[ 58177.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce90d0] width 1920 pitch 7680 (/4 1920)
>[ 58177.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce90d0]
>[ 58177.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce90d0] width 1920 pitch 7680 (/4 1920)
>[ 58177.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce90d0]
>[ 58177.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce90d0] width 1920 pitch 7680 (/4 1920)
>[ 58178.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdfc30]
>[ 58178.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdfc30] width 1920 pitch 7680 (/4 1920)
>[ 58178.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf4030]
>[ 58178.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf4030] width 1920 pitch 7680 (/4 1920)
>[ 58178.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58178.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce93b0]
>[ 58178.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce93b0] width 1920 pitch 7680 (/4 1920)
>[ 58178.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58178.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce93b0]
>[ 58178.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce93b0] width 1920 pitch 7680 (/4 1920)
>[ 58178.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58178.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce93b0]
>[ 58178.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce93b0] width 1920 pitch 7680 (/4 1920)
>[ 58178.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58178.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce93b0]
>[ 58178.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce93b0] width 1920 pitch 7680 (/4 1920)
>[ 58178.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58178.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce93b0]
>[ 58178.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce93b0] width 1920 pitch 7680 (/4 1920)
>[ 58178.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d964a0]
>[ 58178.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d964a0] width 1920 pitch 7680 (/4 1920)
>[ 58181.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cef9d0]
>[ 58181.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 58184.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06390]
>[ 58184.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06390] width 1920 pitch 7680 (/4 1920)
>[ 58184.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58184.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58184.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e9b0]
>[ 58184.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e9b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58184.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58184.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cea6b0]
>[ 58184.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cea6b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cea6b0]
>[ 58184.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cea6b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cea6b0]
>[ 58184.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cea6b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cea6b0]
>[ 58184.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cea6b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cea6b0]
>[ 58184.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cea6b0] width 1920 pitch 7680 (/4 1920)
>[ 58184.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58184.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58184.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06390]
>[ 58184.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06390] width 1920 pitch 7680 (/4 1920)
>[ 58184.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58184.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58184.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58184.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58184.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58185.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58185.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58185.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58185.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58186.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58186.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58186.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58186.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58186.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58186.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58186.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58186.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58186.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58186.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58187.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58187.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58187.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58187.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58187.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58187.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58187.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58187.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58187.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58187.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58188.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d242d0]
>[ 58188.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d242d0] width 1920 pitch 7680 (/4 1920)
>[ 58188.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58188.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58188.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cefa30]
>[ 58188.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cefa30] width 1920 pitch 7680 (/4 1920)
>[ 58188.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58188.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58189.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d23c50]
>[ 58189.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d23c50] width 1920 pitch 7680 (/4 1920)
>[ 58189.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58189.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58189.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58189.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58189.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58189.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58189.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58189.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58189.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58189.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58189.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58189.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58189.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58189.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58189.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58189.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58189.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58189.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07140]
>[ 58189.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07140] width 1920 pitch 7680 (/4 1920)
>[ 58189.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58189.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58190.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58190.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58190.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58190.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58190.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58190.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58191.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58191.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58191.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58191.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58191.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58191.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58191.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58191.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58191.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58191.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58191.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58191.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06390]
>[ 58191.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06390] width 1920 pitch 7680 (/4 1920)
>[ 58191.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58191.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58191.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58191.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58191.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58192.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58192.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58192.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58192.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06390]
>[ 58202.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06390] width 1920 pitch 7680 (/4 1920)
>[ 58202.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58202.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58202.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58202.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58202.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58202.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58202.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c109d0]
>[ 58203.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c109d0] width 1920 pitch 7680 (/4 1920)
>[ 58203.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06390]
>[ 58203.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06390] width 1920 pitch 7680 (/4 1920)
>[ 58203.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bdf7f0]
>[ 58203.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bdf7f0] width 1920 pitch 7680 (/4 1920)
>[ 58203.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58203.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58203.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58203.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c7e770]
>[ 58203.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c7e770] width 1920 pitch 7680 (/4 1920)
>[ 58205.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c09110]
>[ 58205.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c09110] width 1920 pitch 7680 (/4 1920)
>[ 58205.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2cf00]
>[ 58205.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2cf00] width 1920 pitch 7680 (/4 1920)
>[ 58205.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15690]
>[ 58205.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15690] width 1920 pitch 7680 (/4 1920)
>[ 58205.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2cf00]
>[ 58205.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2cf00] width 1920 pitch 7680 (/4 1920)
>[ 58205.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15690]
>[ 58205.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15690] width 1920 pitch 7680 (/4 1920)
>[ 58205.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2cf00]
>[ 58205.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2cf00] width 1920 pitch 7680 (/4 1920)
>[ 58205.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15690]
>[ 58205.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15690] width 1920 pitch 7680 (/4 1920)
>[ 58205.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2cf00]
>[ 58205.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2cf00] width 1920 pitch 7680 (/4 1920)
>[ 58205.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58205.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58205.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58205.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58205.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58205.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58205.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58205.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58205.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58205.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58205.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58205.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58205.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58205.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58205.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58205.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58206.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58206.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58206.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58206.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58206.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58206.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58206.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58206.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58206.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58206.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58206.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58206.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58206.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58206.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58207.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58207.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58207.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58207.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58207.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58207.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58207.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58208.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58208.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58208.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58208.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58208.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58208.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58208.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58208.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58208.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58208.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58208.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58208.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58208.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58208.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58208.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58208.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58208.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58233.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58233.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58233.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58233.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58233.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58233.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58233.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58233.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58233.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58233.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58233.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58233.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58233.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58233.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58233.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58233.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58234.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58234.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58234.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58234.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58234.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58234.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58234.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58234.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58234.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58235.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58235.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58235.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58235.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58236.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3b9c0]
>[ 58236.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3b9c0] width 1920 pitch 7680 (/4 1920)
>[ 58236.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58236.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58236.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be62c0]
>[ 58236.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be62c0] width 1920 pitch 7680 (/4 1920)
>[ 58236.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58236.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58236.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be62c0]
>[ 58236.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be62c0] width 1920 pitch 7680 (/4 1920)
>[ 58236.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c44e40]
>[ 58236.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c44e40] width 1920 pitch 7680 (/4 1920)
>[ 58236.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be62c0]
>[ 58236.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be62c0] width 1920 pitch 7680 (/4 1920)
>[ 58239.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c18f80]
>[ 58239.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c18f80] width 1920 pitch 7680 (/4 1920)
>[ 58239.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da47f0]
>[ 58239.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da47f0] width 1920 pitch 7680 (/4 1920)
>[ 58239.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9c7d0]
>[ 58239.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9c7d0] width 1920 pitch 7680 (/4 1920)
>[ 58240.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce1720]
>[ 58240.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce1720] width 1920 pitch 7680 (/4 1920)
>[ 58252.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31f80]
>[ 58252.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31f80] width 1920 pitch 7680 (/4 1920)
>[ 58252.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a420]
>[ 58252.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a420] width 1920 pitch 7680 (/4 1920)
>[ 58252.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31f80]
>[ 58252.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31f80] width 1920 pitch 7680 (/4 1920)
>[ 58252.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a420]
>[ 58252.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a420] width 1920 pitch 7680 (/4 1920)
>[ 58252.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31f80]
>[ 58252.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31f80] width 1920 pitch 7680 (/4 1920)
>[ 58252.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a420]
>[ 58252.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a420] width 1920 pitch 7680 (/4 1920)
>[ 58252.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c14c10]
>[ 58252.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c14c10] width 1920 pitch 7680 (/4 1920)
>[ 58252.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58252.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58252.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c14c10]
>[ 58252.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c14c10] width 1920 pitch 7680 (/4 1920)
>[ 58252.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58252.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58252.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c14c10]
>[ 58252.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c14c10] width 1920 pitch 7680 (/4 1920)
>[ 58252.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58252.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58252.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c14c10]
>[ 58252.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c14c10] width 1920 pitch 7680 (/4 1920)
>[ 58252.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58253.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58253.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fdd0]
>[ 58253.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fdd0] width 1920 pitch 7680 (/4 1920)
>[ 58253.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58253.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58253.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fdd0]
>[ 58253.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fdd0] width 1920 pitch 7680 (/4 1920)
>[ 58253.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[ 58253.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[ 58253.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fdd0]
>[ 58253.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fdd0] width 1920 pitch 7680 (/4 1920)
>[ 58258.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5f200]
>[ 58258.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5f200] width 1920 pitch 7680 (/4 1920)
>[ 58258.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c95e20]
>[ 58258.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c95e20] width 1920 pitch 7680 (/4 1920)
>[ 58258.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06020]
>[ 58258.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06020] width 1920 pitch 7680 (/4 1920)
>[ 58259.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c36360]
>[ 58259.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c36360] width 1920 pitch 7680 (/4 1920)
>[ 58259.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c43070]
>[ 58259.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c43070] width 1920 pitch 7680 (/4 1920)
>[ 58268.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2d720]
>[ 58268.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2d720] width 1920 pitch 7680 (/4 1920)
>[ 58268.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba09c0]
>[ 58268.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba09c0] width 1920 pitch 7680 (/4 1920)
>[ 58268.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcf470]
>[ 58268.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcf470] width 1920 pitch 7680 (/4 1920)
>[ 58268.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba09c0]
>[ 58268.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba09c0] width 1920 pitch 7680 (/4 1920)
>[ 58268.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcf470]
>[ 58268.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcf470] width 1920 pitch 7680 (/4 1920)
>[ 58268.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba09c0]
>[ 58268.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba09c0] width 1920 pitch 7680 (/4 1920)
>[ 58268.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcf470]
>[ 58268.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcf470] width 1920 pitch 7680 (/4 1920)
>[ 58268.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca46f0]
>[ 58268.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca46f0] width 1920 pitch 7680 (/4 1920)
>[ 58268.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c30ca0]
>[ 58268.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c30ca0] width 1920 pitch 7680 (/4 1920)
>[ 58268.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5f1b0]
>[ 58268.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5f1b0] width 1920 pitch 7680 (/4 1920)
>[ 58268.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9f6f0]
>[ 58268.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9f6f0] width 1920 pitch 7680 (/4 1920)
>[ 58268.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96360]
>[ 58268.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96360] width 1920 pitch 7680 (/4 1920)
>[ 58268.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c30ca0]
>[ 58268.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c30ca0] width 1920 pitch 7680 (/4 1920)
>[ 58268.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96360]
>[ 58268.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96360] width 1920 pitch 7680 (/4 1920)
>[ 58268.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c30ca0]
>[ 58268.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c30ca0] width 1920 pitch 7680 (/4 1920)
>[ 58268.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96360]
>[ 58268.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96360] width 1920 pitch 7680 (/4 1920)
>[ 58268.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9f6f0]
>[ 58268.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9f6f0] width 1920 pitch 7680 (/4 1920)
>[ 58270.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58270.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58270.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58270.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58270.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58270.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58270.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58270.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58270.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58270.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58270.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58270.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58270.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58271.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58271.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58271.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58271.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58271.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58271.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58271.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58271.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58271.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58637.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 58637.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 58637.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58637.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58637.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 58637.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 58637.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58637.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58637.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 58637.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 58637.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a930]
>[ 58637.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a930] width 1920 pitch 7680 (/4 1920)
>[ 58637.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 58637.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 58638.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 58638.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 58638.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47494a0]
>[ 58638.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47494a0] width 1920 pitch 7680 (/4 1920)
>[ 58638.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 58638.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 58638.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47494a0]
>[ 58638.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47494a0] width 1920 pitch 7680 (/4 1920)
>[ 58638.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 58638.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 58638.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47494a0]
>[ 58638.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47494a0] width 1920 pitch 7680 (/4 1920)
>[ 58638.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 58638.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 58638.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47494a0]
>[ 58638.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47494a0] width 1920 pitch 7680 (/4 1920)
>[ 58638.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 58638.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 58638.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 58638.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 58639.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58639.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58639.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a420]
>[ 58639.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a420] width 1920 pitch 7680 (/4 1920)
>[ 58639.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da4e50]
>[ 58639.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da4e50] width 1920 pitch 7680 (/4 1920)
>[ 58640.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbc8c0]
>[ 58640.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbc8c0] width 1920 pitch 7680 (/4 1920)
>[ 58641.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bafb90]
>[ 58641.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bafb90] width 1920 pitch 7680 (/4 1920)
>[ 58641.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b68ed0]
>[ 58641.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b68ed0] width 1920 pitch 7680 (/4 1920)
>[ 58803.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0bb80]
>[ 58803.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0bb80] width 1920 pitch 7680 (/4 1920)
>[ 58803.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbb060]
>[ 58803.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbb060] width 1920 pitch 7680 (/4 1920)
>[ 58969.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d51c60]
>[ 58969.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d51c60] width 1920 pitch 7680 (/4 1920)
>[ 58969.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 58969.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 58969.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35920]
>[ 58969.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35920] width 1920 pitch 7680 (/4 1920)
>[ 58969.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35b20]
>[ 58969.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35b20] width 1920 pitch 7680 (/4 1920)
>[ 58969.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d51c60]
>[ 58969.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d51c60] width 1920 pitch 7680 (/4 1920)
>[ 58969.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 58969.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 58969.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2a210]
>[ 58969.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2a210] width 1920 pitch 7680 (/4 1920)
>[ 58969.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d40ed0]
>[ 58969.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d40ed0] width 1920 pitch 7680 (/4 1920)
>[ 58969.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d51c60]
>[ 58969.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d51c60] width 1920 pitch 7680 (/4 1920)
>[ 58969.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35920]
>[ 58969.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35920] width 1920 pitch 7680 (/4 1920)
>[ 58970.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2a210]
>[ 58970.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2a210] width 1920 pitch 7680 (/4 1920)
>[ 58970.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 58970.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 58970.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d40ed0]
>[ 58970.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d40ed0] width 1920 pitch 7680 (/4 1920)
>[ 58970.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2a210]
>[ 58970.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2a210] width 1920 pitch 7680 (/4 1920)
>[ 58970.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d51c60]
>[ 58970.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d51c60] width 1920 pitch 7680 (/4 1920)
>[ 58970.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 58970.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 58970.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35920]
>[ 58970.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35920] width 1920 pitch 7680 (/4 1920)
>[ 58970.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a3c0]
>[ 58971.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a3c0] width 1920 pitch 7680 (/4 1920)
>[ 58971.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd55e0]
>[ 58971.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd55e0] width 1920 pitch 7680 (/4 1920)
>[ 58971.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58971.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58971.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd55e0]
>[ 58971.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd55e0] width 1920 pitch 7680 (/4 1920)
>[ 58971.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5360]
>[ 58971.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5360] width 1920 pitch 7680 (/4 1920)
>[ 58971.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47494a0]
>[ 58971.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47494a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59048.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b93b90]
>[ 59048.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b93b90] width 1920 pitch 7680 (/4 1920)
>[ 59048.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59048.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59052.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59052.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59052.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59052.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5f10]
>[ 59052.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5f10] width 1920 pitch 7680 (/4 1920)
>[ 59053.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59053.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59053.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59053.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59053.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59055.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59055.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59055.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59055.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59055.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59055.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbdff0]
>[ 59055.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbdff0] width 1920 pitch 7680 (/4 1920)
>[ 59055.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59055.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59055.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x460cb80]
>[ 59055.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x460cb80] width 1920 pitch 7680 (/4 1920)
>[ 59055.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59055.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59055.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59055.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59055.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59055.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59056.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59056.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59056.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59056.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59057.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd55e0]
>[ 59057.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd55e0] width 1920 pitch 7680 (/4 1920)
>[ 59058.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a970]
>[ 59058.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a970] width 1920 pitch 7680 (/4 1920)
>[ 59058.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59058.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59058.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a970]
>[ 59058.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a970] width 1920 pitch 7680 (/4 1920)
>[ 59058.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59058.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59058.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a970]
>[ 59058.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a970] width 1920 pitch 7680 (/4 1920)
>[ 59058.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59058.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59058.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a970]
>[ 59058.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a970] width 1920 pitch 7680 (/4 1920)
>[ 59058.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59058.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59058.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a970]
>[ 59058.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a970] width 1920 pitch 7680 (/4 1920)
>[ 59058.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475ec40]
>[ 59058.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475ec40] width 1920 pitch 7680 (/4 1920)
>[ 59058.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b5dbb0]
>[ 59058.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b5dbb0] width 1920 pitch 7680 (/4 1920)
>[ 59058.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64e90]
>[ 59058.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64e90] width 1920 pitch 7680 (/4 1920)
>[ 59070.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b64d10]
>[ 59070.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b64d10] width 1920 pitch 7680 (/4 1920)
>[ 59070.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59070.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59070.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59070.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59070.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59070.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59070.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59070.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59070.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59071.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59071.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59071.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59071.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59071.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59071.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59071.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59071.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59071.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59071.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19520]
>[ 59071.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19520] width 1920 pitch 7680 (/4 1920)
>[ 59072.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19520]
>[ 59072.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19520] width 1920 pitch 7680 (/4 1920)
>[ 59072.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca4230]
>[ 59072.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca4230] width 1920 pitch 7680 (/4 1920)
>[ 59072.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35920]
>[ 59072.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35920] width 1920 pitch 7680 (/4 1920)
>[ 59072.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19520]
>[ 59072.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19520] width 1920 pitch 7680 (/4 1920)
>[ 59072.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19520]
>[ 59072.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19520] width 1920 pitch 7680 (/4 1920)
>[ 59072.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35920]
>[ 59072.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35920] width 1920 pitch 7680 (/4 1920)
>[ 59073.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71ac0]
>[ 59073.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71ac0] width 1920 pitch 7680 (/4 1920)
>[ 59073.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d51c60]
>[ 59073.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d51c60] width 1920 pitch 7680 (/4 1920)
>[ 59573.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c078e0]
>[ 59573.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c078e0] width 1920 pitch 7680 (/4 1920)
>[ 59573.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c078e0]
>[ 59573.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c078e0] width 1920 pitch 7680 (/4 1920)
>[ 59656.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca12c0]
>[ 59656.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca12c0] width 1920 pitch 7680 (/4 1920)
>[ 59656.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d40ae0]
>[ 59656.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d40ae0] width 1920 pitch 7680 (/4 1920)
>[ 59662.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce84d0]
>[ 59662.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce84d0] width 1920 pitch 7680 (/4 1920)
>[ 59675.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59675.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59785.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59785.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59786.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59786.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59816.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59816.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59816.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59816.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59816.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59816.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59816.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59816.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59816.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59816.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59816.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59816.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59817.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59817.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59817.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59817.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59817.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59817.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59817.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59817.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59817.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461f060]
>[ 59817.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461f060] width 1920 pitch 7680 (/4 1920)
>[ 59817.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59817.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59818.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59818.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59818.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b040]
>[ 59818.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b040] width 1920 pitch 7680 (/4 1920)
>[ 59818.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59818.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59823.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59823.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59824.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59824.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59824.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59824.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59824.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59824.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59824.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461efd0]
>[ 59824.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461efd0] width 1920 pitch 7680 (/4 1920)
>[ 59824.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59824.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59824.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59824.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59824.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461efd0]
>[ 59824.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461efd0] width 1920 pitch 7680 (/4 1920)
>[ 59824.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59824.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59824.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c690]
>[ 59824.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c690] width 1920 pitch 7680 (/4 1920)
>[ 59825.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba8cb0]
>[ 59825.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba8cb0] width 1920 pitch 7680 (/4 1920)
>[ 59825.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461efd0]
>[ 59825.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461efd0] width 1920 pitch 7680 (/4 1920)
>[ 59825.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59825.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59825.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461efd0]
>[ 59825.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461efd0] width 1920 pitch 7680 (/4 1920)
>[ 59825.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0f40]
>[ 59825.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0f40] width 1920 pitch 7680 (/4 1920)
>[ 59825.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461efd0]
>[ 59825.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461efd0] width 1920 pitch 7680 (/4 1920)
>[ 59841.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59841.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59841.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aeae0]
>[ 59841.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aeae0] width 1920 pitch 7680 (/4 1920)
>[ 59843.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ae990]
>[ 59843.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ae990] width 1920 pitch 7680 (/4 1920)
>[ 59843.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd0c90]
>[ 59843.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd0c90] width 1920 pitch 7680 (/4 1920)
>[ 59843.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ae990]
>[ 59843.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ae990] width 1920 pitch 7680 (/4 1920)
>[ 59843.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd0c90]
>[ 59843.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd0c90] width 1920 pitch 7680 (/4 1920)
>[ 59843.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd0c90]
>[ 59843.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd0c90] width 1920 pitch 7680 (/4 1920)
>[ 59843.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59843.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59843.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59843.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59843.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59843.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59843.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59843.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59843.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59843.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59843.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59843.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59843.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59843.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba1c10]
>[ 59843.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba1c10] width 1920 pitch 7680 (/4 1920)
>[ 59843.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f820]
>[ 59843.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f820] width 1920 pitch 7680 (/4 1920)
>[ 59844.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bed0]
>[ 59844.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bed0] width 1920 pitch 7680 (/4 1920)
>[ 59844.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59844.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59844.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59844.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59844.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59844.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59844.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc3ca0]
>[ 59844.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc3ca0] width 1920 pitch 7680 (/4 1920)
>[ 59844.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc3ca0]
>[ 59844.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc3ca0] width 1920 pitch 7680 (/4 1920)
>[ 59844.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c1d0]
>[ 59844.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c1d0] width 1920 pitch 7680 (/4 1920)
>[ 59844.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59844.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59844.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9b8c0]
>[ 59844.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9b8c0] width 1920 pitch 7680 (/4 1920)
>[ 59844.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59844.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59856.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0010]
>[ 59856.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0010] width 1920 pitch 7680 (/4 1920)
>[ 59856.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461ff30]
>[ 59856.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461ff30] width 1920 pitch 7680 (/4 1920)
>[ 59856.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3ab40]
>[ 59856.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3ab40] width 1920 pitch 7680 (/4 1920)
>[ 59856.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ceb1a0]
>[ 59856.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ceb1a0] width 1920 pitch 7680 (/4 1920)
>[ 59861.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da1da0]
>[ 59862.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da1da0] width 1920 pitch 7680 (/4 1920)
>[ 59862.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9b8c0]
>[ 59862.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9b8c0] width 1920 pitch 7680 (/4 1920)
>[ 59862.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced8d0]
>[ 59862.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced8d0] width 1920 pitch 7680 (/4 1920)
>[ 59862.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2beee20]
>[ 59862.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2beee20] width 1920 pitch 7680 (/4 1920)
>[ 59862.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced8d0]
>[ 59862.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced8d0] width 1920 pitch 7680 (/4 1920)
>[ 59863.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 59863.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 59863.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9b8c0]
>[ 59863.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9b8c0] width 1920 pitch 7680 (/4 1920)
>[ 59863.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 59863.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 59863.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7fd0]
>[ 59863.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7fd0] width 1920 pitch 7680 (/4 1920)
>[ 59863.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59863.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59864.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2c00]
>[ 59864.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2c00] width 1920 pitch 7680 (/4 1920)
>[ 59864.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59864.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59864.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2c00]
>[ 59864.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2c00] width 1920 pitch 7680 (/4 1920)
>[ 59864.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59864.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59864.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2c00]
>[ 59864.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2c00] width 1920 pitch 7680 (/4 1920)
>[ 59864.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59864.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59865.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2c00]
>[ 59865.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2c00] width 1920 pitch 7680 (/4 1920)
>[ 59865.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59865.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59865.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59865.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59865.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59865.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59865.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59866.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59866.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59866.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59866.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773ba0]
>[ 59866.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773ba0] width 1920 pitch 7680 (/4 1920)
>[ 59866.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59866.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59867.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59867.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59867.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59867.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59867.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59867.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59867.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 59867.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 59873.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcd870]
>[ 59873.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcd870] width 1920 pitch 7680 (/4 1920)
>[ 59879.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a81e0]
>[ 59879.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a81e0] width 1920 pitch 7680 (/4 1920)
>[ 59912.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59912.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59912.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59912.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59912.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59912.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59912.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59912.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59912.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59912.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59912.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59912.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59912.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59912.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59913.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59913.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59913.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59913.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59913.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59913.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59913.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59913.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59913.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 59913.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 59913.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59913.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59914.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59914.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59914.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca1260]
>[ 59914.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca1260] width 1920 pitch 7680 (/4 1920)
>[ 59914.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 59914.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 59914.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59915.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59916.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 59916.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 59916.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59916.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59916.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb7170]
>[ 59916.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb7170] width 1920 pitch 7680 (/4 1920)
>[ 59916.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcddf0]
>[ 59916.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcddf0] width 1920 pitch 7680 (/4 1920)
>[ 59916.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59916.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59916.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9da40]
>[ 59916.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9da40] width 1920 pitch 7680 (/4 1920)
>[ 59916.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 59916.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 59916.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9da40]
>[ 59916.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9da40] width 1920 pitch 7680 (/4 1920)
>[ 60410.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60410.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60410.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60411.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60411.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60411.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60411.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60411.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60411.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60411.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60411.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60411.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60411.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60411.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60411.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60411.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60411.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60411.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60411.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60411.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60411.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60411.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60411.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60412.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60412.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60412.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60412.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60412.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60412.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60412.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60412.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60412.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60412.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60412.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60412.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60412.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60412.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60412.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60412.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60412.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60414.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60414.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60414.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60414.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60414.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c23500]
>[ 60415.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c23500] width 1920 pitch 7680 (/4 1920)
>[ 60415.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60415.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60415.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60415.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60415.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60416.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e000]
>[ 60416.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e000] width 1920 pitch 7680 (/4 1920)
>[ 60416.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60416.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60422.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b83640]
>[ 60422.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b83640] width 1920 pitch 7680 (/4 1920)
>[ 60422.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60422.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60422.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60422.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60422.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60422.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60422.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60422.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60422.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60422.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60422.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60422.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60422.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60422.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60422.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60422.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60422.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60422.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60422.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60423.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60423.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60423.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60423.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd2d90]
>[ 60423.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd2d90] width 1920 pitch 7680 (/4 1920)
>[ 60423.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8580]
>[ 60423.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8580] width 1920 pitch 7680 (/4 1920)
>[ 60424.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 60424.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 60424.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 60424.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 60424.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 60424.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 60424.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 60424.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 60425.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 60425.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 60425.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 60425.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 60425.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 60425.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 60425.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 60425.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 60425.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 60425.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 60425.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 60425.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 60425.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 60425.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 60425.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 60425.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 60426.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be4160]
>[ 60426.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be4160] width 1920 pitch 7680 (/4 1920)
>[ 60426.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 60426.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 60426.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be4160]
>[ 60426.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be4160] width 1920 pitch 7680 (/4 1920)
>[ 60426.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 60426.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 60426.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be4160]
>[ 60426.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be4160] width 1920 pitch 7680 (/4 1920)
>[ 60426.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0ee0]
>[ 60426.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0ee0] width 1920 pitch 7680 (/4 1920)
>[ 60427.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be4160]
>[ 60427.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be4160] width 1920 pitch 7680 (/4 1920)
>[ 60427.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60427.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60427.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2be4160]
>[ 60427.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2be4160] width 1920 pitch 7680 (/4 1920)
>[ 60427.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 60427.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 60427.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6540]
>[ 60427.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6540] width 1920 pitch 7680 (/4 1920)
>[ 60442.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60442.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60442.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60442.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60442.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60442.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60442.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60442.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60442.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60442.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60442.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60442.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60442.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60442.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60442.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60442.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60443.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60443.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60443.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60443.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60443.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60443.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60444.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60444.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60445.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60445.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60446.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60446.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60446.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60446.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60446.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7fd0]
>[ 60446.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7fd0] width 1920 pitch 7680 (/4 1920)
>[ 60446.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60446.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60446.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7fd0]
>[ 60446.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7fd0] width 1920 pitch 7680 (/4 1920)
>[ 60446.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d73d90]
>[ 60446.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d73d90] width 1920 pitch 7680 (/4 1920)
>[ 60446.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7fd0]
>[ 60446.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7fd0] width 1920 pitch 7680 (/4 1920)
>[ 60461.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c15250]
>[ 60461.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c15250] width 1920 pitch 7680 (/4 1920)
>[ 60466.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60466.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60466.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60466.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60466.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60466.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60466.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60466.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60466.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60466.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60466.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60466.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60466.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60466.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60466.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60466.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60466.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60467.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60467.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60467.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 60467.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 60467.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0af0]
>[ 60467.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0af0] width 1920 pitch 7680 (/4 1920)
>[ 60467.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60467.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60467.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0af0]
>[ 60467.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0af0] width 1920 pitch 7680 (/4 1920)
>[ 60467.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60467.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60467.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0af0]
>[ 60467.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0af0] width 1920 pitch 7680 (/4 1920)
>[ 60467.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60467.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60467.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca0af0]
>[ 60467.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca0af0] width 1920 pitch 7680 (/4 1920)
>[ 60614.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60614.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60614.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60614.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60614.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60614.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60614.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60614.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60614.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60615.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60615.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60615.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60615.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60615.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60615.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60615.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60615.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60615.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60615.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60615.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60615.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60615.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60616.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60616.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60616.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54110]
>[ 60616.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54110] width 1920 pitch 7680 (/4 1920)
>[ 60616.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461b870]
>[ 60616.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461b870] width 1920 pitch 7680 (/4 1920)
>[ 60616.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60616.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60616.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461b870]
>[ 60616.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461b870] width 1920 pitch 7680 (/4 1920)
>[ 60616.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b80e70]
>[ 60616.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b80e70] width 1920 pitch 7680 (/4 1920)
>[ 60616.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461b870]
>[ 60616.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461b870] width 1920 pitch 7680 (/4 1920)
>[ 60674.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60674.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60674.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bc50]
>[ 60674.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bc50] width 1920 pitch 7680 (/4 1920)
>[ 60674.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60674.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60674.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bc50]
>[ 60674.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bc50] width 1920 pitch 7680 (/4 1920)
>[ 60675.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60675.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60675.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bc50]
>[ 60675.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bc50] width 1920 pitch 7680 (/4 1920)
>[ 60675.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60675.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60675.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bc50]
>[ 60675.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bc50] width 1920 pitch 7680 (/4 1920)
>[ 60675.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60675.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60675.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bc50]
>[ 60675.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bc50] width 1920 pitch 7680 (/4 1920)
>[ 60676.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60676.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60676.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60676.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60676.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3cf0]
>[ 60676.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3cf0] width 1920 pitch 7680 (/4 1920)
>[ 60676.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4430]
>[ 60676.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4430] width 1920 pitch 7680 (/4 1920)
>[ 60676.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bea8e0]
>[ 60676.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bea8e0] width 1920 pitch 7680 (/4 1920)
>[ 62916.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62916.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62916.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62916.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62916.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62916.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62916.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62916.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62916.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62916.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62916.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62916.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62916.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62916.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62917.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62917.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62917.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62917.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62917.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62917.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62917.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62917.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62917.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62917.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 62917.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb58a0]
>[ 62917.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb58a0] width 1920 pitch 7680 (/4 1920)
>[ 62917.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf5860]
>[ 62917.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf5860] width 1920 pitch 7680 (/4 1920)
>[ 62918.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf5860]
>[ 62918.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf5860] width 1920 pitch 7680 (/4 1920)
>[ 62918.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf9790]
>[ 62918.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf9790] width 1920 pitch 7680 (/4 1920)
>[ 63041.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30ef0]
>[ 63041.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30ef0] width 1920 pitch 7680 (/4 1920)
>[ 63049.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a59e0]
>[ 63049.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a59e0] width 1920 pitch 7680 (/4 1920)
>[ 63049.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0ca70]
>[ 63049.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0ca70] width 1920 pitch 7680 (/4 1920)
>[ 63131.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a5950]
>[ 63131.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a5950] width 1920 pitch 7680 (/4 1920)
>[ 63131.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63131.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63131.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63131.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63131.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63131.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63131.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63131.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63131.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63131.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63131.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63131.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63131.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63131.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63131.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63131.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63131.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63131.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63132.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63132.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63132.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63132.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63132.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63132.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63132.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63132.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63132.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63132.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63132.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63132.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63132.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce58c0]
>[ 63132.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce58c0] width 1920 pitch 7680 (/4 1920)
>[ 63132.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc7710]
>[ 63132.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc7710] width 1920 pitch 7680 (/4 1920)
>[ 63132.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf3fe0]
>[ 63132.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf3fe0] width 1920 pitch 7680 (/4 1920)
>[ 63133.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca1260]
>[ 63133.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca1260] width 1920 pitch 7680 (/4 1920)
>[ 63169.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2f9a0]
>[ 63169.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2f9a0] width 1920 pitch 7680 (/4 1920)
>[ 63169.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bee380]
>[ 63169.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bee380] width 1920 pitch 7680 (/4 1920)
>[ 63169.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63169.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63169.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63169.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63169.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63169.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63169.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63169.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63169.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63169.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63169.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63169.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63169.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63169.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63170.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63170.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63170.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63170.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63170.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63170.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63170.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63170.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63170.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63170.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63170.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63170.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63170.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec070]
>[ 63170.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec070] width 1920 pitch 7680 (/4 1920)
>[ 63170.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63170.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63171.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e30730]
>[ 63171.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e30730] width 1920 pitch 7680 (/4 1920)
>[ 63171.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e30730]
>[ 63171.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e30730] width 1920 pitch 7680 (/4 1920)
>[ 63171.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33780]
>[ 63171.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33780] width 1920 pitch 7680 (/4 1920)
>[ 63181.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b6c0]
>[ 63181.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b6c0] width 1920 pitch 7680 (/4 1920)
>[ 63186.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328bdd0]
>[ 63186.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328bdd0] width 1920 pitch 7680 (/4 1920)
>[ 63237.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[ 63237.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[ 63237.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63237.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63237.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0]
>[ 63237.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1920 pitch 7680 (/4 1920)
>[ 63237.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b360]
>[ 63237.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b360] width 1920 pitch 7680 (/4 1920)
>[ 63237.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b360]
>[ 63237.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b360] width 1920 pitch 7680 (/4 1920)
>[ 63237.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0]
>[ 63237.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1920 pitch 7680 (/4 1920)
>[ 63237.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b360]
>[ 63237.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b360] width 1920 pitch 7680 (/4 1920)
>[ 63237.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1320]
>[ 63237.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1320] width 1920 pitch 7680 (/4 1920)
>[ 63237.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b360]
>[ 63237.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b360] width 1920 pitch 7680 (/4 1920)
>[ 63237.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c263f0]
>[ 63237.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c263f0] width 1920 pitch 7680 (/4 1920)
>[ 63237.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2fb40]
>[ 63237.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2fb40] width 1920 pitch 7680 (/4 1920)
>[ 63302.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc930]
>[ 63302.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc930] width 1920 pitch 7680 (/4 1920)
>[ 63303.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63303.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63303.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328bd40]
>[ 63303.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328bd40] width 1920 pitch 7680 (/4 1920)
>[ 63303.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63303.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63303.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328bd40]
>[ 63303.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328bd40] width 1920 pitch 7680 (/4 1920)
>[ 63303.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63303.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63303.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328bd40]
>[ 63304.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328bd40] width 1920 pitch 7680 (/4 1920)
>[ 63304.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63304.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63304.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328bd40]
>[ 63304.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328bd40] width 1920 pitch 7680 (/4 1920)
>[ 63304.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63304.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63304.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a430]
>[ 63304.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a430] width 1920 pitch 7680 (/4 1920)
>[ 63304.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63304.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63305.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a430]
>[ 63305.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a430] width 1920 pitch 7680 (/4 1920)
>[ 63305.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63305.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63305.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a59e0]
>[ 63305.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a59e0] width 1920 pitch 7680 (/4 1920)
>[ 63305.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3ca20]
>[ 63305.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3ca20] width 1920 pitch 7680 (/4 1920)
>[ 63305.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a4f00]
>[ 63305.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a4f00] width 1920 pitch 7680 (/4 1920)
>[ 63305.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc60f0]
>[ 63305.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc60f0] width 1920 pitch 7680 (/4 1920)
>[ 63305.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a4f00]
>[ 63305.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a4f00] width 1920 pitch 7680 (/4 1920)
>[ 63329.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63329.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63329.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63329.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63329.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63329.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63329.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63329.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63329.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63329.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63329.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63329.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63329.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63329.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63330.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63330.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63330.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63330.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63330.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63330.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63330.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63330.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63330.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63330.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63331.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b99a10]
>[ 63332.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b99a10] width 1920 pitch 7680 (/4 1920)
>[ 63332.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63332.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63332.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc60f0]
>[ 63332.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc60f0] width 1920 pitch 7680 (/4 1920)
>[ 63332.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a4f00]
>[ 63332.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a4f00] width 1920 pitch 7680 (/4 1920)
>[ 63332.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c280d0]
>[ 63332.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c280d0] width 1920 pitch 7680 (/4 1920)
>[ 63332.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c078e0]
>[ 63332.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c078e0] width 1920 pitch 7680 (/4 1920)
>[ 63332.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3ca20]
>[ 63332.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3ca20] width 1920 pitch 7680 (/4 1920)
>[ 63332.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c078e0]
>[ 63332.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c078e0] width 1920 pitch 7680 (/4 1920)
>[ 67165.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67165.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67165.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67165.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67165.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67165.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67165.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67165.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67165.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67165.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67165.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67165.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67165.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67165.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67165.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67165.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67165.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67166.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67166.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67166.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67166.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67166.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67166.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67166.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67167.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67167.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67167.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67167.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67167.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67167.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67167.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67167.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 67167.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4657280]
>[ 67167.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4657280] width 1920 pitch 7680 (/4 1920)
>[ 67167.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46561b0]
>[ 67167.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46561b0] width 1920 pitch 7680 (/4 1920)
>[ 68022.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68022.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68022.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68022.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68022.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68022.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68022.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68022.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68022.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68022.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68022.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68022.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68022.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68022.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68022.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68022.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68023.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68023.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68023.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68023.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68023.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68023.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68023.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68023.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68024.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f240]
>[ 68024.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f240] width 1920 pitch 7680 (/4 1920)
>[ 68024.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387630]
>[ 68024.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387630] width 1920 pitch 7680 (/4 1920)
>[ 68024.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc730]
>[ 68024.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc730] width 1920 pitch 7680 (/4 1920)
>[ 68024.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc730]
>[ 68024.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc730] width 1920 pitch 7680 (/4 1920)
>[ 68024.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9af90]
>[ 68024.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9af90] width 1920 pitch 7680 (/4 1920)
>[ 68024.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc730]
>[ 68024.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc730] width 1920 pitch 7680 (/4 1920)
>[ 68025.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68025.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68025.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68025.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68025.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68025.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68025.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68025.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68025.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68025.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68025.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68025.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68026.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68026.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68026.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68026.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68026.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68026.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68026.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68026.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68027.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68027.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68027.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68027.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 68027.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32af740]
>[ 68027.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32af740] width 1920 pitch 7680 (/4 1920)
>[ 68027.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45969c0]
>[ 68027.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45969c0] width 1920 pitch 7680 (/4 1920)
>[ 68027.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7f950]
>[ 68027.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7f950] width 1920 pitch 7680 (/4 1920)
>[ 68027.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45969c0]
>[ 68027.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45969c0] width 1920 pitch 7680 (/4 1920)
>[ 68027.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b552a0]
>[ 68027.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b552a0] width 1920 pitch 7680 (/4 1920)
>[ 68027.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2f070]
>[ 68027.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2f070] width 1920 pitch 7680 (/4 1920)
>[ 71634.941] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[ 71634.941] (II) RADEON(0): Using hsync ranges from config file
>[ 71634.941] (II) RADEON(0): Using vrefresh ranges from config file
>[ 71634.941] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 71634.941] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 71634.941] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[ 71634.941] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[ 71634.942] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[ 71724.928] (II) RADEON(0): RADEONSaveScreen(2)
>[ 71724.928] (II) RADEON(0): RADEONSaveScreen(0)
>[ 76213.751] (II) RADEON(0): RADEONSaveScreen(1)
>[ 76220.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf4840]
>[ 76220.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf4840] width 1920 pitch 7680 (/4 1920)
>[ 76225.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0e10]
>[ 76225.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0e10] width 1920 pitch 7680 (/4 1920)
>[ 76225.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2e5d0]
>[ 76225.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2e5d0] width 1920 pitch 7680 (/4 1920)
>[ 76225.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b520]
>[ 76225.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b520] width 1920 pitch 7680 (/4 1920)
>[ 76225.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf4840]
>[ 76225.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf4840] width 1920 pitch 7680 (/4 1920)
>[ 76225.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2e5d0]
>[ 76225.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2e5d0] width 1920 pitch 7680 (/4 1920)
>[ 76225.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf4840]
>[ 76225.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf4840] width 1920 pitch 7680 (/4 1920)
>[ 76225.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2e600]
>[ 76225.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2e600] width 1920 pitch 7680 (/4 1920)
>[ 76225.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0e10]
>[ 76225.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0e10] width 1920 pitch 7680 (/4 1920)
>[ 76225.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b4f0]
>[ 76225.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b4f0] width 1920 pitch 7680 (/4 1920)
>[ 76225.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2e5d0]
>[ 76225.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2e5d0] width 1920 pitch 7680 (/4 1920)
>[ 76225.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328b4f0]
>[ 76225.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328b4f0] width 1920 pitch 7680 (/4 1920)
>[ 76225.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0e10]
>[ 76225.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0e10] width 1920 pitch 7680 (/4 1920)
>[ 76227.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461da40]
>[ 76227.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461da40] width 1920 pitch 7680 (/4 1920)
>[ 76228.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3bc10]
>[ 76228.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3bc10] width 1920 pitch 7680 (/4 1920)
>[ 76229.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3c130]
>[ 76229.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3c130] width 1920 pitch 7680 (/4 1920)
>[ 76229.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3c130]
>[ 76229.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3c130] width 1920 pitch 7680 (/4 1920)
>[ 76230.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x461da40]
>[ 76230.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x461da40] width 1920 pitch 7680 (/4 1920)
>[ 76230.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb830]
>[ 76230.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb830] width 1920 pitch 7680 (/4 1920)
>[ 76230.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4655cf0]
>[ 76230.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4655cf0] width 1920 pitch 7680 (/4 1920)
>[ 76230.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2e5d0]
>[ 76230.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2e5d0] width 1920 pitch 7680 (/4 1920)
>[ 76230.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6430]
>[ 76230.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6430] width 1920 pitch 7680 (/4 1920)
>[ 76230.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf91a0]
>[ 76230.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf91a0] width 1920 pitch 7680 (/4 1920)
>[ 76230.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6430]
>[ 76230.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6430] width 1920 pitch 7680 (/4 1920)
>[ 76230.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdb8e0]
>[ 76230.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdb8e0] width 1920 pitch 7680 (/4 1920)
>[ 76230.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d93240]
>[ 76230.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d93240] width 1920 pitch 7680 (/4 1920)
>[ 76230.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c2a10]
>[ 76230.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c2a10] width 1920 pitch 7680 (/4 1920)
>[ 76234.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bcf60]
>[ 76234.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bcf60] width 1920 pitch 7680 (/4 1920)
>[ 76236.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4890]
>[ 76236.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4890] width 1920 pitch 7680 (/4 1920)
>[ 76238.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8690]
>[ 76238.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8690] width 1920 pitch 7680 (/4 1920)
>[ 76240.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b73b0]
>[ 76240.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b73b0] width 1920 pitch 7680 (/4 1920)
>[ 76249.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76249.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76249.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76249.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76249.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76249.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76249.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76249.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76249.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76249.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76249.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76249.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76250.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76250.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76250.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76250.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76250.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b75f0]
>[ 76250.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b75f0] width 1920 pitch 7680 (/4 1920)
>[ 76250.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76250.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76250.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c64ad0]
>[ 76250.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c64ad0] width 1920 pitch 7680 (/4 1920)
>[ 76251.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76251.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76251.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76251.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76251.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76251.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76253.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76253.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76253.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76253.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76253.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76253.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76254.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76254.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76254.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1ad0]
>[ 76254.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1ad0] width 1920 pitch 7680 (/4 1920)
>[ 76254.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76254.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76254.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76254.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76254.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76254.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76254.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6450]
>[ 76254.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6450] width 1920 pitch 7680 (/4 1920)
>[ 76254.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1ad0]
>[ 76254.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1ad0] width 1920 pitch 7680 (/4 1920)
>[ 76254.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76254.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76254.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6450]
>[ 76254.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6450] width 1920 pitch 7680 (/4 1920)
>[ 76254.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76254.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76254.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76254.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76254.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6450]
>[ 76254.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6450] width 1920 pitch 7680 (/4 1920)
>[ 76254.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76254.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76254.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76254.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76254.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1ad0]
>[ 76254.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1ad0] width 1920 pitch 7680 (/4 1920)
>[ 76254.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76254.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76254.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76255.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76255.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bd1ad0]
>[ 76255.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bd1ad0] width 1920 pitch 7680 (/4 1920)
>[ 76255.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32834e0]
>[ 76255.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32834e0] width 1920 pitch 7680 (/4 1920)
>[ 76255.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76255.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76255.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6450]
>[ 76255.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6450] width 1920 pitch 7680 (/4 1920)
>[ 76255.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be6450]
>[ 76255.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be6450] width 1920 pitch 7680 (/4 1920)
>[ 76255.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76255.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76255.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76255.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76255.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76255.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76255.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76255.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76272.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76272.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76272.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76272.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76272.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76272.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76272.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76272.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76272.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76272.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76272.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76272.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76272.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76272.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76272.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76272.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76273.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76273.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76273.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76273.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76273.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76273.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76273.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76273.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76273.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76273.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76273.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76273.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76273.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76273.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76273.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76273.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76273.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76273.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76273.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76273.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76274.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76274.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76274.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfac90]
>[ 76274.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfac90] width 1920 pitch 7680 (/4 1920)
>[ 76274.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76274.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76274.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76274.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76274.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76274.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76274.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[ 76275.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[ 76275.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfac90]
>[ 76275.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfac90] width 1920 pitch 7680 (/4 1920)
>[ 76275.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2e330]
>[ 76275.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2e330] width 1920 pitch 7680 (/4 1920)
>[ 76275.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76275.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76275.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[ 76275.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[ 76275.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76275.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76276.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76276.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76276.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ad30]
>[ 76276.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ad30] width 1920 pitch 7680 (/4 1920)
>[ 76276.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5a40]
>[ 76276.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5a40] width 1920 pitch 7680 (/4 1920)
>[ 76276.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c31800]
>[ 76276.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c31800] width 1920 pitch 7680 (/4 1920)
>[ 76276.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8430]
>[ 76276.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8430] width 1920 pitch 7680 (/4 1920)
>[ 76477.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c9740]
>[ 76477.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c9740] width 1920 pitch 7680 (/4 1920)
>[ 76478.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd9e90]
>[ 76478.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd9e90] width 1920 pitch 7680 (/4 1920)
>[ 76602.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c03420]
>[ 76602.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c03420] width 1920 pitch 7680 (/4 1920)
>[ 76602.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7ee70]
>[ 76602.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7ee70] width 1920 pitch 7680 (/4 1920)
>[ 81740.554] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[ 81740.554] (II) RADEON(0): Using hsync ranges from config file
>[ 81740.554] (II) RADEON(0): Using vrefresh ranges from config file
>[ 81740.554] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 81740.554] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 81740.554] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 81740.554] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 81740.555] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 81740.555] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[ 81740.555] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[ 81740.555] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[ 81830.935] (II) RADEON(0): RADEONSaveScreen(2)
>[ 81830.935] (II) RADEON(0): RADEONSaveScreen(0)
>[118234.839] (II) RADEON(0): RADEONSaveScreen(1)
>[118278.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118278.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118278.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118278.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118278.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118278.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118278.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118278.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118278.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118278.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118278.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118278.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118278.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118278.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118278.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118278.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118278.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118283.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118283.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118283.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118283.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118284.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d18420]
>[118284.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d18420] width 1920 pitch 7680 (/4 1920)
>[118284.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118284.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118323.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9a20]
>[118323.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9a20] width 1920 pitch 7680 (/4 1920)
>[118323.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118323.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118326.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118326.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118326.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bfb000]
>[118326.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bfb000] width 1920 pitch 7680 (/4 1920)
>[118328.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118328.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118328.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118328.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118328.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118328.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118328.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3bca0]
>[118328.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3bca0] width 1920 pitch 7680 (/4 1920)
>[118328.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118328.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118328.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d28fa0]
>[118328.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d28fa0] width 1920 pitch 7680 (/4 1920)
>[118328.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118328.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118328.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c62110]
>[118328.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c62110] width 1920 pitch 7680 (/4 1920)
>[118329.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c5be30]
>[118329.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c5be30] width 1920 pitch 7680 (/4 1920)
>[118329.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c61380]
>[118329.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c61380] width 1920 pitch 7680 (/4 1920)
>[118329.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c63f80]
>[118329.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c63f80] width 1920 pitch 7680 (/4 1920)
>[118329.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464edf0]
>[118329.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464edf0] width 1920 pitch 7680 (/4 1920)
>[118329.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c630c0]
>[118329.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c630c0] width 1920 pitch 7680 (/4 1920)
>[118329.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c63f50]
>[118329.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c63f50] width 1920 pitch 7680 (/4 1920)
>[118329.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c620b0]
>[118329.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c620b0] width 1920 pitch 7680 (/4 1920)
>[118329.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464d3d0]
>[118329.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464d3d0] width 1920 pitch 7680 (/4 1920)
>[118329.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c61030]
>[118329.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c61030] width 1920 pitch 7680 (/4 1920)
>[118329.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c610a0]
>[118329.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c610a0] width 1920 pitch 7680 (/4 1920)
>[118329.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464d400]
>[118329.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464d400] width 1920 pitch 7680 (/4 1920)
>[118329.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c61300]
>[118329.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c61300] width 1920 pitch 7680 (/4 1920)
>[118329.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c593b0]
>[118329.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c593b0] width 1920 pitch 7680 (/4 1920)
>[118341.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118341.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118350.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118350.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118350.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118350.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118350.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c670c0]
>[118350.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c670c0] width 1920 pitch 7680 (/4 1920)
>[118350.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c610f0]
>[118350.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c610f0] width 1920 pitch 7680 (/4 1920)
>[118350.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118350.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118350.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118351.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118351.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118351.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118351.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118351.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118351.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118351.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118351.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118351.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118351.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118351.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118351.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118351.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118351.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118351.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118356.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c65b20]
>[118356.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c65b20] width 1920 pitch 7680 (/4 1920)
>[118356.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6a520]
>[118356.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6a520] width 1920 pitch 7680 (/4 1920)
>[118356.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118356.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118356.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c610f0]
>[118356.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c610f0] width 1920 pitch 7680 (/4 1920)
>[118356.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118356.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118356.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c65b20]
>[118356.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c65b20] width 1920 pitch 7680 (/4 1920)
>[118356.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6a520]
>[118356.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6a520] width 1920 pitch 7680 (/4 1920)
>[118356.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118356.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118356.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c610f0]
>[118356.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c610f0] width 1920 pitch 7680 (/4 1920)
>[118356.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7fa00]
>[118356.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7fa00] width 1920 pitch 7680 (/4 1920)
>[118356.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c65b20]
>[118356.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c65b20] width 1920 pitch 7680 (/4 1920)
>[118356.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6a520]
>[118356.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6a520] width 1920 pitch 7680 (/4 1920)
>[118356.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118356.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118371.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118371.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118371.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c663c0]
>[118371.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c663c0] width 1920 pitch 7680 (/4 1920)
>[118371.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118371.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118371.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118371.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118371.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c663c0]
>[118371.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c663c0] width 1920 pitch 7680 (/4 1920)
>[118371.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118371.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118371.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118371.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118371.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c663c0]
>[118371.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c663c0] width 1920 pitch 7680 (/4 1920)
>[118371.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118371.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118371.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118372.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118372.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118372.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118372.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118372.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118372.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118372.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118372.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c663c0]
>[118372.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c663c0] width 1920 pitch 7680 (/4 1920)
>[118376.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118376.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118376.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118376.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118376.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118376.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118376.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118376.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118376.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118380.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d2af90]
>[118380.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d2af90] width 1920 pitch 7680 (/4 1920)
>[118380.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118380.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118474.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e880]
>[118474.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e880] width 1920 pitch 7680 (/4 1920)
>[118474.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118474.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118474.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118474.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118474.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118474.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118474.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118474.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118474.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118474.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118474.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118474.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118475.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118475.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118475.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118475.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118475.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118475.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118475.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118476.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118476.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118476.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118476.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c67820]
>[118476.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c67820] width 1920 pitch 7680 (/4 1920)
>[118476.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c67820]
>[118476.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c67820] width 1920 pitch 7680 (/4 1920)
>[118476.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118476.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118476.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118476.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118476.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c67820]
>[118476.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c67820] width 1920 pitch 7680 (/4 1920)
>[118476.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c67820]
>[118476.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c67820] width 1920 pitch 7680 (/4 1920)
>[118476.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6b280]
>[118476.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6b280] width 1920 pitch 7680 (/4 1920)
>[118478.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4750b40]
>[118478.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4750b40] width 1920 pitch 7680 (/4 1920)
>[118478.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3285100]
>[118478.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3285100] width 1920 pitch 7680 (/4 1920)
>[118478.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118478.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118478.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3285100]
>[118478.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3285100] width 1920 pitch 7680 (/4 1920)
>[118478.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c69800]
>[118478.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c69800] width 1920 pitch 7680 (/4 1920)
>[118479.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c69800]
>[118479.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c69800] width 1920 pitch 7680 (/4 1920)
>[118479.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3285100]
>[118479.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3285100] width 1920 pitch 7680 (/4 1920)
>[118507.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118507.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118507.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118507.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118507.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118508.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118508.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118508.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118508.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118508.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118508.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118508.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118508.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118508.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118508.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118508.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118508.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118508.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118508.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118508.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118509.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118509.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118509.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e5c0]
>[118509.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e5c0] width 1920 pitch 7680 (/4 1920)
>[118509.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118509.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118510.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118510.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118510.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c661a0]
>[118510.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c661a0] width 1920 pitch 7680 (/4 1920)
>[118510.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118510.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118510.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c661a0]
>[118510.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c661a0] width 1920 pitch 7680 (/4 1920)
>[118510.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[118510.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[118510.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c661a0]
>[118510.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c661a0] width 1920 pitch 7680 (/4 1920)
>[118518.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32df9d0]
>[118518.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32df9d0] width 1920 pitch 7680 (/4 1920)
>[118524.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce7840]
>[118524.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce7840] width 1920 pitch 7680 (/4 1920)
>[118524.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d11740]
>[118525.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d11740] width 1920 pitch 7680 (/4 1920)
>[118527.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fe10]
>[118527.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fe10] width 1920 pitch 7680 (/4 1920)
>[124214.666] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[124214.666] (II) RADEON(0): Using hsync ranges from config file
>[124214.666] (II) RADEON(0): Using vrefresh ranges from config file
>[124214.666] (II) RADEON(0): Printing DDC gathered Modelines:
>[124214.666] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[124214.666] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[124214.666] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[124214.666] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[124214.666] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[124214.666] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[124214.666] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[124214.666] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[124214.666] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[124214.667] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[124214.667] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[124214.667] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[124214.667] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[124304.925] (II) RADEON(0): RADEONSaveScreen(2)
>[124304.925] (II) RADEON(0): RADEONSaveScreen(0)
>[126500.038] (II) RADEON(0): RADEONSaveScreen(1)
>[126503.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e6f0]
>[126503.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e6f0] width 1920 pitch 7680 (/4 1920)
>[126530.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c76ed0]
>[126530.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c76ed0] width 1920 pitch 7680 (/4 1920)
>[126530.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126530.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126530.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126530.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126530.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126530.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126530.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126530.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126530.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126530.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126530.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126530.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126530.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126530.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126531.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126531.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126531.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126531.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126531.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126531.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126531.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1170]
>[126531.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1170] width 1920 pitch 7680 (/4 1920)
>[126532.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126532.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126532.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126532.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126532.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126532.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126532.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126532.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126532.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126532.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126532.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126532.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126532.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126532.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126533.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126533.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126533.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126533.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126533.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126533.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126533.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126533.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126533.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126533.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126533.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126533.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126533.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126533.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126534.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126534.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126534.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126534.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126534.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126534.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126534.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126534.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126534.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126534.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126534.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126534.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126534.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126534.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126534.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126534.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126534.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126534.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126534.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126535.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126535.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328cf20]
>[126535.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328cf20] width 1920 pitch 7680 (/4 1920)
>[126537.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3ac20]
>[126537.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3ac20] width 1920 pitch 7680 (/4 1920)
>[126571.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4656090]
>[126571.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4656090] width 1920 pitch 7680 (/4 1920)
>[126572.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[126572.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[126575.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42b10]
>[126575.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42b10] width 1920 pitch 7680 (/4 1920)
>[126603.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32edf50]
>[126603.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32edf50] width 1920 pitch 7680 (/4 1920)
>[126630.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126630.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126630.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126630.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126630.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126630.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126630.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126630.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126630.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126630.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126630.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126630.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126630.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126630.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126630.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126630.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126630.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126630.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126630.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126630.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126631.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126631.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126631.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126631.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126631.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126631.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126631.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126631.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126631.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474e400]
>[126631.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474e400] width 1920 pitch 7680 (/4 1920)
>[126632.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126632.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126632.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45070]
>[126632.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45070] width 1920 pitch 7680 (/4 1920)
>[126632.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126632.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126632.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45070]
>[126632.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45070] width 1920 pitch 7680 (/4 1920)
>[126632.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126632.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[126632.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45070]
>[126632.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45070] width 1920 pitch 7680 (/4 1920)
>[126632.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c94840]
>[126632.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c94840] width 1920 pitch 7680 (/4 1920)
>[127074.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127074.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127074.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127074.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127074.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127074.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127074.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127078.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127078.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127078.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127078.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127078.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127078.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127078.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127078.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127078.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127078.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127078.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127079.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127079.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127079.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127079.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127079.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127079.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127079.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127079.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127079.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127079.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fc80]
>[127079.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fc80] width 1920 pitch 7680 (/4 1920)
>[127079.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127079.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127079.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127079.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127324.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127324.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127324.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127324.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127328.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127328.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127328.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127328.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127341.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127341.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127341.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127341.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127345.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127345.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127345.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127345.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127345.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127345.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127345.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127345.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127345.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127345.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127345.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127345.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127405.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7a780]
>[127405.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7a780] width 1920 pitch 7680 (/4 1920)
>[127412.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127412.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127412.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127412.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127412.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127412.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127412.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127412.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127412.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127412.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127412.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127412.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127412.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127412.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127412.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127412.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127412.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127412.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127413.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127413.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127413.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127413.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127413.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4fb50]
>[127413.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4fb50] width 1920 pitch 7680 (/4 1920)
>[127413.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68e90]
>[127413.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68e90] width 1920 pitch 7680 (/4 1920)
>[127413.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127413.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127413.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127413.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127413.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127413.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127413.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127413.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127413.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[127413.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[127413.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[127413.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[127413.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[127413.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[127466.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e67220]
>[127466.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e67220] width 1920 pitch 7680 (/4 1920)
>[127660.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127660.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127660.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127660.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127660.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b440]
>[127661.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b440] width 1920 pitch 7680 (/4 1920)
>[127661.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127661.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127661.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371760]
>[127661.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371760] width 1920 pitch 7680 (/4 1920)
>[127661.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127661.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127661.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127661.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127661.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127661.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127661.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127661.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127662.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127662.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127662.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127662.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127663.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a8b0]
>[127663.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a8b0] width 1920 pitch 7680 (/4 1920)
>[127663.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127663.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127663.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127663.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127663.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127663.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127663.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127663.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127663.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127663.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127663.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127663.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127664.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127664.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127664.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127664.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127664.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127664.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127664.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127664.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127664.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127664.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127665.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127665.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127665.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127665.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127665.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127665.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127665.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127665.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127665.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b440]
>[127665.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b440] width 1920 pitch 7680 (/4 1920)
>[127666.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127666.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127666.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371760]
>[127666.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371760] width 1920 pitch 7680 (/4 1920)
>[127666.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127666.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127666.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127666.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127666.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec070]
>[127666.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec070] width 1920 pitch 7680 (/4 1920)
>[127666.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50]
>[127666.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1920 pitch 7680 (/4 1920)
>[127667.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127667.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127667.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127667.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127667.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323af70]
>[127667.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323af70] width 1920 pitch 7680 (/4 1920)
>[127668.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336e560]
>[127668.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336e560] width 1920 pitch 7680 (/4 1920)
>[127668.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[127668.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[127668.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a200]
>[127668.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a200] width 1920 pitch 7680 (/4 1920)
>[127668.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3365470]
>[127668.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3365470] width 1920 pitch 7680 (/4 1920)
>[127669.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e69f70]
>[127669.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e69f70] width 1920 pitch 7680 (/4 1920)
>[127670.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369670]
>[127670.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369670] width 1920 pitch 7680 (/4 1920)
>[127671.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324aec0]
>[127671.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324aec0] width 1920 pitch 7680 (/4 1920)
>[127671.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324aec0]
>[127671.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324aec0] width 1920 pitch 7680 (/4 1920)
>[127671.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8be60]
>[127671.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8be60] width 1920 pitch 7680 (/4 1920)
>[127671.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324aec0]
>[127671.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324aec0] width 1920 pitch 7680 (/4 1920)
>[127671.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8be60]
>[127671.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8be60] width 1920 pitch 7680 (/4 1920)
>[127671.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324aec0]
>[127671.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324aec0] width 1920 pitch 7680 (/4 1920)
>[127671.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369670]
>[127671.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369670] width 1920 pitch 7680 (/4 1920)
>[127671.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367830]
>[127671.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367830] width 1920 pitch 7680 (/4 1920)
>[127671.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324aec0]
>[127671.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324aec0] width 1920 pitch 7680 (/4 1920)
>[127671.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367830]
>[127671.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367830] width 1920 pitch 7680 (/4 1920)
>[127671.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367830]
>[127671.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367830] width 1920 pitch 7680 (/4 1920)
>[127671.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367830]
>[127671.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367830] width 1920 pitch 7680 (/4 1920)
>[127671.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367830]
>[127671.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367830] width 1920 pitch 7680 (/4 1920)
>[127745.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e310]
>[127745.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e310] width 1920 pitch 7680 (/4 1920)
>[127773.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240d20]
>[127773.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240d20] width 1920 pitch 7680 (/4 1920)
>[127773.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255840]
>[127773.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255840] width 1920 pitch 7680 (/4 1920)
>[127773.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127773.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127773.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127773.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127773.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127773.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127773.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127773.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127773.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127773.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127774.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127774.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127774.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127774.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127774.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127774.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127774.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127774.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127774.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127774.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127775.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127775.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127775.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255610]
>[127775.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255610] width 1920 pitch 7680 (/4 1920)
>[127775.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127775.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127775.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127775.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127775.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c71e60]
>[127775.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c71e60] width 1920 pitch 7680 (/4 1920)
>[127775.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127775.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127775.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c71e60]
>[127775.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c71e60] width 1920 pitch 7680 (/4 1920)
>[127775.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258370]
>[127775.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258370] width 1920 pitch 7680 (/4 1920)
>[127775.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c71e60]
>[127775.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c71e60] width 1920 pitch 7680 (/4 1920)
>[127777.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31edf90]
>[127777.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31edf90] width 1920 pitch 7680 (/4 1920)
>[127865.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127865.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127865.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127865.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127866.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127866.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127866.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127866.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127866.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127866.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127866.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127866.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127866.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127866.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127866.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127866.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127866.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127866.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127866.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127866.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127866.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127866.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127866.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127866.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127867.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127867.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127867.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127867.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127867.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32508c0]
>[127867.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32508c0] width 1920 pitch 7680 (/4 1920)
>[127867.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ef9f0]
>[127867.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ef9f0] width 1920 pitch 7680 (/4 1920)
>[127867.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32508c0]
>[127867.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32508c0] width 1920 pitch 7680 (/4 1920)
>[127867.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e45e40]
>[127867.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e45e40] width 1920 pitch 7680 (/4 1920)
>[127867.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0580]
>[127867.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0580] width 1920 pitch 7680 (/4 1920)
>[127983.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6b230]
>[127983.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6b230] width 1920 pitch 7680 (/4 1920)
>[128001.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f33d0]
>[128001.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f33d0] width 1920 pitch 7680 (/4 1920)
>[128001.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0230]
>[128001.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0230] width 1920 pitch 7680 (/4 1920)
>[128005.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336e1a0]
>[128005.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336e1a0] width 1920 pitch 7680 (/4 1920)
>[128005.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336e1a0]
>[128005.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336e1a0] width 1920 pitch 7680 (/4 1920)
>[128005.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128005.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128005.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128005.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128005.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128005.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128005.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128005.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128005.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128005.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128005.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128005.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128005.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128005.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128006.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128006.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128006.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128006.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128006.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128006.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128006.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257320]
>[128006.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257320] width 1920 pitch 7680 (/4 1920)
>[128009.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128009.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128010.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128010.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128010.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350e00]
>[128010.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350e00] width 1920 pitch 7680 (/4 1920)
>[128010.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128010.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128010.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350e00]
>[128010.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350e00] width 1920 pitch 7680 (/4 1920)
>[128010.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128010.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128010.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350e00]
>[128010.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350e00] width 1920 pitch 7680 (/4 1920)
>[128010.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128010.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128010.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[128010.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[128011.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128011.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128011.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128011.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128011.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128011.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128011.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128011.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128011.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128011.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128011.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128011.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128011.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128011.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128012.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128012.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128012.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128012.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128012.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128012.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128012.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128012.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128012.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32500c0]
>[128012.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32500c0] width 1920 pitch 7680 (/4 1920)
>[128012.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bebb30]
>[128012.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bebb30] width 1920 pitch 7680 (/4 1920)
>[128013.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350e00]
>[128013.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350e00] width 1920 pitch 7680 (/4 1920)
>[128013.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128013.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128013.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128013.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128013.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128013.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128013.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128013.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128013.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128013.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128013.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128013.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128013.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128013.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128013.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128013.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128163.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128164.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128164.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128164.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128164.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128164.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128164.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128164.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128164.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128164.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128164.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128164.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128164.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128164.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128164.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128168.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128168.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128168.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128168.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128168.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128168.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128168.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128169.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128169.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128169.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128169.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128169.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128169.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128169.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128169.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128169.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128169.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128169.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128169.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128169.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128169.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128169.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128169.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128169.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128169.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128169.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128234.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66040]
>[128234.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66040] width 1920 pitch 7680 (/4 1920)
>[128237.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32323b0]
>[128237.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32323b0] width 1920 pitch 7680 (/4 1920)
>[128237.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efc70]
>[128237.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efc70] width 1920 pitch 7680 (/4 1920)
>[128237.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128237.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128237.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efc70]
>[128237.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efc70] width 1920 pitch 7680 (/4 1920)
>[128237.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efc70]
>[128237.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efc70] width 1920 pitch 7680 (/4 1920)
>[128237.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128237.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128237.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efc70]
>[128237.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efc70] width 1920 pitch 7680 (/4 1920)
>[128237.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128237.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128237.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128237.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128237.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128237.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128237.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31efc70]
>[128237.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31efc70] width 1920 pitch 7680 (/4 1920)
>[128237.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128238.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128238.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f3ad0]
>[128238.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f3ad0] width 1920 pitch 7680 (/4 1920)
>[128238.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128238.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128242.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128242.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128242.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128242.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128242.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128242.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128242.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128242.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128242.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128242.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128242.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128242.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128242.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128242.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128242.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128242.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128242.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128242.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c73340]
>[128242.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c73340] width 1920 pitch 7680 (/4 1920)
>[128242.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128242.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128289.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128289.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128289.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128289.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128289.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128289.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128289.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128289.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128289.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128289.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128289.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128289.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128289.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128289.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128289.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128289.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128290.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128290.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128290.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128290.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128290.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128290.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128290.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5020]
>[128290.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5020] width 1920 pitch 7680 (/4 1920)
>[128290.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1620]
>[128290.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1620] width 1920 pitch 7680 (/4 1920)
>[128291.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c96e20]
>[128291.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c96e20] width 1920 pitch 7680 (/4 1920)
>[128291.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4cf30]
>[128291.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4cf30] width 1920 pitch 7680 (/4 1920)
>[128291.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128291.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128291.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c82300]
>[128291.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c82300] width 1920 pitch 7680 (/4 1920)
>[128291.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128291.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128291.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128291.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128291.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128291.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128322.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5ae0]
>[128322.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5ae0] width 1920 pitch 7680 (/4 1920)
>[128325.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5ae0]
>[128325.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5ae0] width 1920 pitch 7680 (/4 1920)
>[128325.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128325.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128325.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efb90]
>[128325.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efb90] width 1920 pitch 7680 (/4 1920)
>[128325.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128325.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128325.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efb90]
>[128325.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efb90] width 1920 pitch 7680 (/4 1920)
>[128325.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128326.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128326.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efb90]
>[128326.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efb90] width 1920 pitch 7680 (/4 1920)
>[128326.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efb90]
>[128326.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efb90] width 1920 pitch 7680 (/4 1920)
>[128326.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128326.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128326.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128326.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128327.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f5ae0]
>[128327.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f5ae0] width 1920 pitch 7680 (/4 1920)
>[128327.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128327.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128327.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b600]
>[128327.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b600] width 1920 pitch 7680 (/4 1920)
>[128327.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128327.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128327.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128327.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128327.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128327.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128327.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c82300]
>[128327.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c82300] width 1920 pitch 7680 (/4 1920)
>[128327.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f07f0]
>[128327.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f07f0] width 1920 pitch 7680 (/4 1920)
>[128327.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128327.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128333.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3347740]
>[128333.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3347740] width 1920 pitch 7680 (/4 1920)
>[128357.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c610]
>[128357.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c610] width 1920 pitch 7680 (/4 1920)
>[128357.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c610]
>[128357.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c610] width 1920 pitch 7680 (/4 1920)
>[128357.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f86d0]
>[128357.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f86d0] width 1920 pitch 7680 (/4 1920)
>[128357.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c610]
>[128357.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c610] width 1920 pitch 7680 (/4 1920)
>[128357.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f86d0]
>[128357.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f86d0] width 1920 pitch 7680 (/4 1920)
>[128357.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c610]
>[128357.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c610] width 1920 pitch 7680 (/4 1920)
>[128357.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e67040]
>[128357.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e67040] width 1920 pitch 7680 (/4 1920)
>[128357.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128357.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128358.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[128358.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[128358.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128358.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128358.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e662f0]
>[128358.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e662f0] width 1920 pitch 7680 (/4 1920)
>[128358.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[128358.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[128358.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f86d0]
>[128359.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f86d0] width 1920 pitch 7680 (/4 1920)
>[128359.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324f530]
>[128359.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324f530] width 1920 pitch 7680 (/4 1920)
>[128359.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324f530]
>[128359.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324f530] width 1920 pitch 7680 (/4 1920)
>[128359.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128359.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128359.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128359.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128359.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128359.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128359.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128359.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128369.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128369.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128369.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e50090]
>[128369.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e50090] width 1920 pitch 7680 (/4 1920)
>[128369.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128369.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128369.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128369.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128369.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128369.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128369.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e50090]
>[128369.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e50090] width 1920 pitch 7680 (/4 1920)
>[128369.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128369.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128369.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128369.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128369.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e50090]
>[128369.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e50090] width 1920 pitch 7680 (/4 1920)
>[128369.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128369.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128369.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128369.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128369.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128369.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128369.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e50090]
>[128369.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e50090] width 1920 pitch 7680 (/4 1920)
>[128373.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128373.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128373.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128373.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128373.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128373.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128373.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128373.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128373.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128373.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128373.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128373.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128373.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128373.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128373.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128373.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128373.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128373.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128377.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128377.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128377.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128377.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128377.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9f40]
>[128377.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9f40] width 1920 pitch 7680 (/4 1920)
>[128377.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128378.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128378.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128378.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128378.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128378.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128378.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128378.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128378.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128378.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128378.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128378.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128378.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128378.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128378.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128378.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128378.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128378.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128378.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[128378.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[128451.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8cee0]
>[128451.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8cee0] width 1920 pitch 7680 (/4 1920)
>[128451.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128451.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128451.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128451.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128451.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8cee0]
>[128451.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8cee0] width 1920 pitch 7680 (/4 1920)
>[128451.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128451.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128451.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[128451.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[128451.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128451.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128452.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128452.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128452.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[128452.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[128452.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128452.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128452.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128452.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128452.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[128452.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[128452.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f190]
>[128452.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f190] width 1920 pitch 7680 (/4 1920)
>[128452.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c82300]
>[128452.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c82300] width 1920 pitch 7680 (/4 1920)
>[128452.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[128453.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[128453.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128453.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128453.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128453.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128453.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c82300]
>[128453.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c82300] width 1920 pitch 7680 (/4 1920)
>[128453.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[128453.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[128499.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128499.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128499.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128499.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128499.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128503.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128503.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128503.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128503.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128503.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128503.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128503.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128503.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128503.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128503.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128503.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128503.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128503.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128503.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128503.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128503.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128503.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128504.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128504.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128504.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128504.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128504.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128504.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[128504.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[128504.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128504.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128574.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128574.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128574.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128574.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128574.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128574.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128574.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128574.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128574.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128574.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128574.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128574.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128574.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128574.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128574.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128574.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128574.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128578.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128578.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128578.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128578.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128578.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128578.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128578.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128578.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128578.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128578.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128578.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128578.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128578.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128578.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128578.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128578.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128578.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128578.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128578.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128578.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128578.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128578.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128578.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128578.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128579.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128580.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128580.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128580.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128580.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128580.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128580.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128580.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128580.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128580.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128580.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128580.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128580.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128580.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128584.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128584.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128584.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128584.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128584.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128584.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128584.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128584.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128584.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128584.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128584.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128584.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128584.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128584.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128584.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128584.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128584.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128584.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128584.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128584.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128584.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128584.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128584.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128584.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128874.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128874.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128874.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a4c0]
>[128874.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a4c0] width 1920 pitch 7680 (/4 1920)
>[128881.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e67040]
>[128881.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e67040] width 1920 pitch 7680 (/4 1920)
>[128904.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128904.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128904.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43150]
>[128904.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43150] width 1920 pitch 7680 (/4 1920)
>[128904.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128904.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128904.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43150]
>[128904.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43150] width 1920 pitch 7680 (/4 1920)
>[128904.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128904.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128904.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128904.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128904.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334ebe0]
>[128904.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334ebe0] width 1920 pitch 7680 (/4 1920)
>[128905.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128905.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128905.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334ebe0]
>[128905.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334ebe0] width 1920 pitch 7680 (/4 1920)
>[128905.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128905.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128905.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128905.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128905.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128905.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128905.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128905.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128905.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128905.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128905.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128905.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128905.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128905.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128905.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128905.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128905.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[128905.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[128906.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128906.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128906.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128906.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128906.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128906.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128906.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128906.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128906.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[128906.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[128906.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128907.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128907.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[128907.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[128907.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128907.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128907.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[128907.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[128907.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128907.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128907.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128907.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128907.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128907.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128907.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64a30]
>[128907.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64a30] width 1920 pitch 7680 (/4 1920)
>[128907.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128907.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128908.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64a30]
>[128908.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64a30] width 1920 pitch 7680 (/4 1920)
>[128908.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128908.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128908.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128908.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[128908.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[128908.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[128908.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31edd70]
>[128908.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31edd70] width 1920 pitch 7680 (/4 1920)
>[128977.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[128977.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[128977.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[128977.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129041.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64e60]
>[129041.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64e60] width 1920 pitch 7680 (/4 1920)
>[129065.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129065.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129065.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129065.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129065.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129069.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129069.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129069.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129070.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129070.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129070.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129070.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129070.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129070.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129070.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129070.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129070.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129070.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129070.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129070.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129070.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129070.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129070.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129070.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129070.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129070.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129070.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129070.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129070.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129070.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129070.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129076.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129076.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129076.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129076.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129076.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129076.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129076.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129076.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129076.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129076.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129076.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129076.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129076.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129076.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129076.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129076.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129076.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129076.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129076.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129076.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129076.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129076.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129076.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c589d0]
>[129076.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c589d0] width 1920 pitch 7680 (/4 1920)
>[129080.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129080.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129080.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129080.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129080.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129080.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129080.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129080.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129080.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129080.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129080.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129080.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129080.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129080.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129080.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129081.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129081.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129081.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129081.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129081.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129081.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42100]
>[129081.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42100] width 1920 pitch 7680 (/4 1920)
>[129081.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[129081.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[129081.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[129081.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[129086.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e61660]
>[129086.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e61660] width 1920 pitch 7680 (/4 1920)
>[129158.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129158.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129158.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f2b60]
>[129158.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f2b60] width 1920 pitch 7680 (/4 1920)
>[129158.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129158.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129158.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129158.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129158.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129159.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129159.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129160.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f2b60]
>[129160.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f2b60] width 1920 pitch 7680 (/4 1920)
>[129160.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64a30]
>[129160.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64a30] width 1920 pitch 7680 (/4 1920)
>[129160.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a230]
>[129160.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a230] width 1920 pitch 7680 (/4 1920)
>[129160.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4be70]
>[129160.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4be70] width 1920 pitch 7680 (/4 1920)
>[129160.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3239950]
>[129160.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3239950] width 1920 pitch 7680 (/4 1920)
>[129160.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129160.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129160.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e413b0]
>[129160.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e413b0] width 1920 pitch 7680 (/4 1920)
>[129160.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31edd70]
>[129160.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31edd70] width 1920 pitch 7680 (/4 1920)
>[129220.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1780]
>[129220.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1780] width 1920 pitch 7680 (/4 1920)
>[129223.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129223.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47b70]
>[129223.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47b70] width 1920 pitch 7680 (/4 1920)
>[129223.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321fbe0]
>[129223.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321fbe0] width 1920 pitch 7680 (/4 1920)
>[129224.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e420e0]
>[129224.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e420e0] width 1920 pitch 7680 (/4 1920)
>[129224.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e420e0]
>[129224.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e420e0] width 1920 pitch 7680 (/4 1920)
>[129224.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253000]
>[129224.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253000] width 1920 pitch 7680 (/4 1920)
>[129225.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323e6a0]
>[129225.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323e6a0] width 1920 pitch 7680 (/4 1920)
>[129225.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0000]
>[129225.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0000] width 1920 pitch 7680 (/4 1920)
>[129225.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3239920]
>[129225.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3239920] width 1920 pitch 7680 (/4 1920)
>[129225.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3250750]
>[129225.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3250750] width 1920 pitch 7680 (/4 1920)
>[129225.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3239920]
>[129225.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3239920] width 1920 pitch 7680 (/4 1920)
>[129225.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129225.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129225.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e642a0]
>[129225.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e642a0] width 1920 pitch 7680 (/4 1920)
>[129225.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129225.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129225.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3250750]
>[129225.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3250750] width 1920 pitch 7680 (/4 1920)
>[129225.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e642a0]
>[129225.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e642a0] width 1920 pitch 7680 (/4 1920)
>[129225.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129225.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129225.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3250750]
>[129225.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3250750] width 1920 pitch 7680 (/4 1920)
>[129225.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e642a0]
>[129225.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e642a0] width 1920 pitch 7680 (/4 1920)
>[129225.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3250750]
>[129225.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3250750] width 1920 pitch 7680 (/4 1920)
>[129302.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3380f20]
>[129302.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3380f20] width 1920 pitch 7680 (/4 1920)
>[129342.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129342.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129375.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129376.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129376.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129376.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129376.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129376.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129376.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129376.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129376.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129376.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129376.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129376.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129376.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129376.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129376.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129376.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129376.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129376.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129376.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129376.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129376.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129376.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8d370]
>[129376.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8d370] width 1920 pitch 7680 (/4 1920)
>[129383.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129383.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255cb0]
>[129383.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255cb0] width 1920 pitch 7680 (/4 1920)
>[129383.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129383.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129383.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129383.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129383.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4f6a0]
>[129383.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4f6a0] width 1920 pitch 7680 (/4 1920)
>[129383.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129383.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129389.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ee5b0]
>[129389.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ee5b0] width 1920 pitch 7680 (/4 1920)
>[129398.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129399.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8c00]
>[129399.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8c00] width 1920 pitch 7680 (/4 1920)
>[129399.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[129399.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[129401.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346960]
>[129401.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346960] width 1920 pitch 7680 (/4 1920)
>[129402.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0710]
>[129402.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0710] width 1920 pitch 7680 (/4 1920)
>[129404.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346960]
>[129404.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346960] width 1920 pitch 7680 (/4 1920)
>[129404.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129404.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129404.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c390]
>[129404.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c390] width 1920 pitch 7680 (/4 1920)
>[129404.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c390]
>[129404.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c390] width 1920 pitch 7680 (/4 1920)
>[129404.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129404.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c390]
>[129404.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c390] width 1920 pitch 7680 (/4 1920)
>[129404.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129404.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129404.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c6c390]
>[129404.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c6c390] width 1920 pitch 7680 (/4 1920)
>[129404.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129404.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129457.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129457.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129531.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3252fc0]
>[129531.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3252fc0] width 1920 pitch 7680 (/4 1920)
>[129538.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fe50]
>[129538.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fe50] width 1920 pitch 7680 (/4 1920)
>[129538.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337faa0]
>[129538.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337faa0] width 1920 pitch 7680 (/4 1920)
>[129538.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337faa0]
>[129538.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337faa0] width 1920 pitch 7680 (/4 1920)
>[129538.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fe50]
>[129538.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fe50] width 1920 pitch 7680 (/4 1920)
>[129538.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fe50]
>[129538.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fe50] width 1920 pitch 7680 (/4 1920)
>[129538.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337faa0]
>[129538.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337faa0] width 1920 pitch 7680 (/4 1920)
>[129538.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337faa0]
>[129538.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337faa0] width 1920 pitch 7680 (/4 1920)
>[129538.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6eab0]
>[129538.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6eab0] width 1920 pitch 7680 (/4 1920)
>[129539.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216220]
>[129539.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216220] width 1920 pitch 7680 (/4 1920)
>[129539.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a580]
>[129539.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a580] width 1920 pitch 7680 (/4 1920)
>[129539.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333dfe0]
>[129539.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333dfe0] width 1920 pitch 7680 (/4 1920)
>[129539.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3252fc0]
>[129539.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3252fc0] width 1920 pitch 7680 (/4 1920)
>[129539.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346470]
>[129539.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346470] width 1920 pitch 7680 (/4 1920)
>[129539.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346470]
>[129539.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346470] width 1920 pitch 7680 (/4 1920)
>[129539.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129539.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129539.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346470]
>[129539.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346470] width 1920 pitch 7680 (/4 1920)
>[129539.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346470]
>[129539.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346470] width 1920 pitch 7680 (/4 1920)
>[129539.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129539.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129543.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0680]
>[129543.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0680] width 1920 pitch 7680 (/4 1920)
>[129546.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32116e0]
>[129546.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32116e0] width 1920 pitch 7680 (/4 1920)
>[129546.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e610]
>[129546.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e610] width 1920 pitch 7680 (/4 1920)
>[129546.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33513c0]
>[129546.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33513c0] width 1920 pitch 7680 (/4 1920)
>[129546.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6eab0]
>[129546.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6eab0] width 1920 pitch 7680 (/4 1920)
>[129546.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3252fc0]
>[129546.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3252fc0] width 1920 pitch 7680 (/4 1920)
>[129546.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e610]
>[129546.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e610] width 1920 pitch 7680 (/4 1920)
>[129546.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333dfe0]
>[129546.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333dfe0] width 1920 pitch 7680 (/4 1920)
>[129546.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a580]
>[129547.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a580] width 1920 pitch 7680 (/4 1920)
>[129547.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3252fc0]
>[129547.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3252fc0] width 1920 pitch 7680 (/4 1920)
>[129547.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129547.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129547.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129547.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129547.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129547.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129547.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e3d0]
>[129547.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e3d0] width 1920 pitch 7680 (/4 1920)
>[129547.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129547.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129547.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129547.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129550.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e3d0]
>[129550.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e3d0] width 1920 pitch 7680 (/4 1920)
>[129550.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129550.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129550.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129550.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129550.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e3d0]
>[129550.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e3d0] width 1920 pitch 7680 (/4 1920)
>[129550.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129550.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129550.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129550.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129550.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129550.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129550.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e3d0]
>[129550.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e3d0] width 1920 pitch 7680 (/4 1920)
>[129550.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129550.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129550.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129550.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129552.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129552.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129552.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129552.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129552.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129552.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129552.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129552.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129552.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129552.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129552.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129552.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129554.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129554.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129554.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129554.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129554.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129554.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129554.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129554.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129554.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129554.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129554.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129554.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129554.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129555.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129556.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129556.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129556.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129557.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129557.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129557.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129557.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129557.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129557.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129557.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129557.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129557.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129557.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129557.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129557.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129557.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129557.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129557.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129557.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129557.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129557.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f1450]
>[129558.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f1450] width 1920 pitch 7680 (/4 1920)
>[129558.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129558.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129559.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129559.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129559.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129559.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129560.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129560.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129560.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129560.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129560.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129560.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129560.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129560.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129560.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e60]
>[129560.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e60] width 1920 pitch 7680 (/4 1920)
>[129560.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129560.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129560.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f4010]
>[129560.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f4010] width 1920 pitch 7680 (/4 1920)
>[129560.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334e200]
>[129560.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334e200] width 1920 pitch 7680 (/4 1920)
>[129560.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da400]
>[129560.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da400] width 1920 pitch 7680 (/4 1920)
>[129560.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129560.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129560.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7b340]
>[129561.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7b340] width 1920 pitch 7680 (/4 1920)
>[129561.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c57e60]
>[129561.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c57e60] width 1920 pitch 7680 (/4 1920)
>[129561.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334da90]
>[129561.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334da90] width 1920 pitch 7680 (/4 1920)
>[129561.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c57e60]
>[129561.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c57e60] width 1920 pitch 7680 (/4 1920)
>[129561.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129561.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129561.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129561.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129561.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129561.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129561.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129561.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129561.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129561.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129561.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129561.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129561.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129561.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3282220]
>[129561.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3282220] width 1920 pitch 7680 (/4 1920)
>[129562.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7c300]
>[129562.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7c300] width 1920 pitch 7680 (/4 1920)
>[129563.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d11740]
>[129563.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d11740] width 1920 pitch 7680 (/4 1920)
>[129563.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3215750]
>[129563.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3215750] width 1920 pitch 7680 (/4 1920)
>[129563.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e310]
>[129563.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e310] width 1920 pitch 7680 (/4 1920)
>[129563.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129563.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129563.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e310]
>[129563.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e310] width 1920 pitch 7680 (/4 1920)
>[129563.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129563.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129563.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129563.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129563.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e310]
>[129563.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e310] width 1920 pitch 7680 (/4 1920)
>[129563.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129563.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129563.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fcc0]
>[129563.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fcc0] width 1920 pitch 7680 (/4 1920)
>[129563.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129563.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129563.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e310]
>[129563.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e310] width 1920 pitch 7680 (/4 1920)
>[129563.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129563.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129563.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129563.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129563.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e310]
>[129563.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e310] width 1920 pitch 7680 (/4 1920)
>[129563.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129563.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129587.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129587.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129588.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129588.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129588.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[129588.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[129588.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7560]
>[129588.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7560] width 1920 pitch 7680 (/4 1920)
>[129588.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129588.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129588.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129588.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129588.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e60]
>[129588.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e60] width 1920 pitch 7680 (/4 1920)
>[129588.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129588.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129588.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129588.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129588.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129588.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129588.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[129588.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[129588.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e60]
>[129588.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e60] width 1920 pitch 7680 (/4 1920)
>[129588.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7560]
>[129588.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7560] width 1920 pitch 7680 (/4 1920)
>[129588.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129588.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129588.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129588.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129592.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[129592.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[129592.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7fdb0]
>[129592.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7fdb0] width 1920 pitch 7680 (/4 1920)
>[129592.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129592.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129592.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e60]
>[129592.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e60] width 1920 pitch 7680 (/4 1920)
>[129592.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29850]
>[129592.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29850] width 1920 pitch 7680 (/4 1920)
>[129592.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129592.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129592.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129592.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129592.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e60]
>[129592.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e60] width 1920 pitch 7680 (/4 1920)
>[129592.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129592.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129592.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129592.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129592.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129592.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129592.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c66440]
>[129592.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c66440] width 1920 pitch 7680 (/4 1920)
>[129593.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33513c0]
>[129593.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33513c0] width 1920 pitch 7680 (/4 1920)
>[129593.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6d670]
>[129593.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6d670] width 1920 pitch 7680 (/4 1920)
>[129601.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0db0]
>[129601.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0db0] width 1920 pitch 7680 (/4 1920)
>[129601.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0db0]
>[129601.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0db0] width 1920 pitch 7680 (/4 1920)
>[129601.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333dfe0]
>[129601.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333dfe0] width 1920 pitch 7680 (/4 1920)
>[129602.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0db0]
>[129602.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0db0] width 1920 pitch 7680 (/4 1920)
>[129602.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6a580]
>[129602.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6a580] width 1920 pitch 7680 (/4 1920)
>[129602.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33513c0]
>[129602.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33513c0] width 1920 pitch 7680 (/4 1920)
>[129602.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e610]
>[129602.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e610] width 1920 pitch 7680 (/4 1920)
>[129602.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333dfe0]
>[129602.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333dfe0] width 1920 pitch 7680 (/4 1920)
>[129602.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0db0]
>[129602.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0db0] width 1920 pitch 7680 (/4 1920)
>[129602.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0db0]
>[129603.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0db0] width 1920 pitch 7680 (/4 1920)
>[129603.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e610]
>[129603.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e610] width 1920 pitch 7680 (/4 1920)
>[129603.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129603.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129603.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8570]
>[129603.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8570] width 1920 pitch 7680 (/4 1920)
>[129603.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e150]
>[129603.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e150] width 1920 pitch 7680 (/4 1920)
>[129603.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c66440]
>[129603.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c66440] width 1920 pitch 7680 (/4 1920)
>[129603.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f0a60]
>[129603.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f0a60] width 1920 pitch 7680 (/4 1920)
>[129603.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129603.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129628.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129628.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129645.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c66440]
>[129645.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c66440] width 1920 pitch 7680 (/4 1920)
>[129646.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d1d0]
>[129646.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d1d0] width 1920 pitch 7680 (/4 1920)
>[129646.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7560]
>[129646.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7560] width 1920 pitch 7680 (/4 1920)
>[129646.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e150]
>[129646.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e150] width 1920 pitch 7680 (/4 1920)
>[129646.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129646.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129646.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7560]
>[129646.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7560] width 1920 pitch 7680 (/4 1920)
>[129646.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337e150]
>[129646.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337e150] width 1920 pitch 7680 (/4 1920)
>[129646.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d1d0]
>[129646.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d1d0] width 1920 pitch 7680 (/4 1920)
>[129646.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129646.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129646.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c66440]
>[129646.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c66440] width 1920 pitch 7680 (/4 1920)
>[129646.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e42bb0]
>[129646.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e42bb0] width 1920 pitch 7680 (/4 1920)
>[129646.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129646.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129647.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d1d0]
>[129647.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d1d0] width 1920 pitch 7680 (/4 1920)
>[129647.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7560]
>[129647.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7560] width 1920 pitch 7680 (/4 1920)
>[129647.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129647.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129685.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129685.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129685.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x329fb90]
>[129685.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x329fb90] width 1920 pitch 7680 (/4 1920)
>[129685.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129685.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129685.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129685.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129685.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129685.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129685.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129685.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129686.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129686.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129686.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e68b60]
>[129686.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e68b60] width 1920 pitch 7680 (/4 1920)
>[129686.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341dd0]
>[129686.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341dd0] width 1920 pitch 7680 (/4 1920)
>[129686.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333dfe0]
>[129686.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333dfe0] width 1920 pitch 7680 (/4 1920)
>[129686.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340a00]
>[129686.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340a00] width 1920 pitch 7680 (/4 1920)
>[129686.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340c60]
>[129686.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340c60] width 1920 pitch 7680 (/4 1920)
>[129686.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c80980]
>[129686.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c80980] width 1920 pitch 7680 (/4 1920)
>[129686.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340a00]
>[129686.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340a00] width 1920 pitch 7680 (/4 1920)
>[129686.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c480]
>[129686.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c480] width 1920 pitch 7680 (/4 1920)
>[129686.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c80980]
>[129686.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c80980] width 1920 pitch 7680 (/4 1920)
>[129686.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340c60]
>[129686.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340c60] width 1920 pitch 7680 (/4 1920)
>[129692.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129692.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129692.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129692.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129692.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129692.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129692.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129692.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129692.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129693.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200310]
>[129693.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200310] width 1920 pitch 7680 (/4 1920)
>[129693.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffa10]
>[129693.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffa10] width 1920 pitch 7680 (/4 1920)
>[129693.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32001c0]
>[129693.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32001c0] width 1920 pitch 7680 (/4 1920)
>[129693.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffa10]
>[129693.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffa10] width 1920 pitch 7680 (/4 1920)
>[129693.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32001c0]
>[129693.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32001c0] width 1920 pitch 7680 (/4 1920)
>[129693.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129693.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129693.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129693.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129693.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129693.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129693.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129693.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129693.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129693.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129693.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129693.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129693.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129693.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129693.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e4c0]
>[129693.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e4c0] width 1920 pitch 7680 (/4 1920)
>[129702.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff340]
>[129702.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff340] width 1920 pitch 7680 (/4 1920)
>[129702.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb2150]
>[129702.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb2150] width 1920 pitch 7680 (/4 1920)
>[129710.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01dc0]
>[129710.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01dc0] width 1920 pitch 7680 (/4 1920)
>[129721.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d490]
>[129721.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d490] width 1920 pitch 7680 (/4 1920)
>[129723.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0310]
>[129723.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0310] width 1920 pitch 7680 (/4 1920)
>[129723.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334daa0]
>[129723.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334daa0] width 1920 pitch 7680 (/4 1920)
>[129723.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e484b0]
>[129723.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e484b0] width 1920 pitch 7680 (/4 1920)
>[129723.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340a00]
>[129723.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340a00] width 1920 pitch 7680 (/4 1920)
>[129723.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334daa0]
>[129723.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334daa0] width 1920 pitch 7680 (/4 1920)
>[129723.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e484b0]
>[129723.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e484b0] width 1920 pitch 7680 (/4 1920)
>[129723.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340a00]
>[129723.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340a00] width 1920 pitch 7680 (/4 1920)
>[129723.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0310]
>[129723.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0310] width 1920 pitch 7680 (/4 1920)
>[129724.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334daa0]
>[129724.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334daa0] width 1920 pitch 7680 (/4 1920)
>[129724.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340c60]
>[129724.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340c60] width 1920 pitch 7680 (/4 1920)
>[129724.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226d00]
>[129724.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226d00] width 1920 pitch 7680 (/4 1920)
>[129724.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3226d90]
>[129724.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3226d90] width 1920 pitch 7680 (/4 1920)
>[129724.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f008c0]
>[129724.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f008c0] width 1920 pitch 7680 (/4 1920)
>[129724.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c480]
>[129724.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c480] width 1920 pitch 7680 (/4 1920)
>[129724.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129724.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129725.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129725.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129782.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7c0c0]
>[129782.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7c0c0] width 1920 pitch 7680 (/4 1920)
>[129808.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b760]
>[129808.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b760] width 1920 pitch 7680 (/4 1920)
>[129808.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219570]
>[129808.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219570] width 1920 pitch 7680 (/4 1920)
>[129808.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b760]
>[129808.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b760] width 1920 pitch 7680 (/4 1920)
>[129808.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341dd0]
>[129808.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341dd0] width 1920 pitch 7680 (/4 1920)
>[129808.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b760]
>[129808.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b760] width 1920 pitch 7680 (/4 1920)
>[129808.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341dd0]
>[129808.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341dd0] width 1920 pitch 7680 (/4 1920)
>[129808.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129808.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129808.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341dd0]
>[129808.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341dd0] width 1920 pitch 7680 (/4 1920)
>[129809.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129809.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129809.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129809.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129809.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219570]
>[129809.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219570] width 1920 pitch 7680 (/4 1920)
>[129809.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219570]
>[129809.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219570] width 1920 pitch 7680 (/4 1920)
>[129809.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129809.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129809.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219570]
>[129809.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219570] width 1920 pitch 7680 (/4 1920)
>[129809.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129809.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129809.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219570]
>[129809.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219570] width 1920 pitch 7680 (/4 1920)
>[129809.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[129809.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[129844.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333fd30]
>[129844.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333fd30] width 1920 pitch 7680 (/4 1920)
>[129920.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[129920.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[129920.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129920.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129920.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129920.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129920.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129920.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129920.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129920.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129920.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129920.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129920.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129920.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129920.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129920.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129920.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129920.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129921.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129921.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129921.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129921.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129921.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129921.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129921.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221060]
>[129921.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221060] width 1920 pitch 7680 (/4 1920)
>[129921.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129922.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129922.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[129922.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[129922.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129922.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129922.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[129922.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[129922.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129922.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129922.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[129922.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[129924.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129924.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129926.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[129926.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[129926.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[129926.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[129999.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[129999.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[129999.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[129999.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130000.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130000.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130000.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130000.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130000.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130000.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130000.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130000.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130000.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130000.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130000.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130000.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130000.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130000.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130001.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130001.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130001.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130001.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130001.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130001.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130001.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130001.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130001.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130001.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130001.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130001.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130001.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130003.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130003.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130003.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130003.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130003.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130003.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130003.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130003.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130003.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130003.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130003.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130003.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130003.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130003.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130004.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130004.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130004.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130004.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130004.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130004.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130004.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130004.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130004.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130004.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130004.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130004.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130005.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130005.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130005.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130005.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130005.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130005.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130005.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[130005.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130019.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f9ce0]
>[130019.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f9ce0] width 1920 pitch 7680 (/4 1920)
>[130059.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[130059.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[130060.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130060.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efce0]
>[130060.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efce0] width 1920 pitch 7680 (/4 1920)
>[130060.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130060.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130064.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130064.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130064.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130064.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130064.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130125.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130125.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130125.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130125.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130125.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130125.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130125.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130125.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130125.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130125.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130125.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130125.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130125.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130125.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130125.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[130125.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[130125.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130125.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130126.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[130126.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[130127.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[130127.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130129.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219bf0]
>[130129.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219bf0] width 1920 pitch 7680 (/4 1920)
>[130129.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[130129.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[130129.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[130129.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[130129.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[130129.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[130129.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[130129.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130129.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[130129.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130129.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130129.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4b0]
>[130129.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4b0] width 1920 pitch 7680 (/4 1920)
>[130129.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece090]
>[130129.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece090] width 1920 pitch 7680 (/4 1920)
>[130231.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64e00]
>[130231.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64e00] width 1920 pitch 7680 (/4 1920)
>[130516.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[130516.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[130516.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130516.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130516.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130516.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130516.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130516.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130516.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130516.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130516.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[130516.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[130516.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130516.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130516.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66090]
>[130516.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66090] width 1920 pitch 7680 (/4 1920)
>[130516.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130516.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130516.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130516.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130516.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130516.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130516.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130516.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130516.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130516.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130516.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130517.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130520.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130521.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130521.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130521.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130521.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130521.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130521.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130521.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130521.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130521.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130521.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[130521.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[130521.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66090]
>[130521.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66090] width 1920 pitch 7680 (/4 1920)
>[130521.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130521.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130521.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130521.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130521.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130521.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130521.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130521.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130521.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[130521.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[130521.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130521.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130531.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130531.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130531.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130531.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130531.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130531.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130531.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130531.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130531.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130531.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130531.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[130531.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[130531.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130531.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130531.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebccc0]
>[130531.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebccc0] width 1920 pitch 7680 (/4 1920)
>[130531.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[130531.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[130531.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130531.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130531.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d29f10]
>[130531.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d29f10] width 1920 pitch 7680 (/4 1920)
>[130531.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130531.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130534.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321e940]
>[130534.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321e940] width 1920 pitch 7680 (/4 1920)
>[130535.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130535.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130536.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fe4f0]
>[130536.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fe4f0] width 1920 pitch 7680 (/4 1920)
>[130536.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130536.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130536.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff470]
>[130536.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff470] width 1920 pitch 7680 (/4 1920)
>[130536.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f5b0]
>[130536.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f5b0] width 1920 pitch 7680 (/4 1920)
>[130536.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff470]
>[130536.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff470] width 1920 pitch 7680 (/4 1920)
>[130536.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f5b0]
>[130536.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f5b0] width 1920 pitch 7680 (/4 1920)
>[130536.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff470]
>[130536.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff470] width 1920 pitch 7680 (/4 1920)
>[130536.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f5b0]
>[130536.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f5b0] width 1920 pitch 7680 (/4 1920)
>[130536.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3221bd0]
>[130536.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3221bd0] width 1920 pitch 7680 (/4 1920)
>[130536.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130536.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130536.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130536.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130536.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130537.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130537.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130537.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130537.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130537.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130537.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130537.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130537.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e65380]
>[130537.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e65380] width 1920 pitch 7680 (/4 1920)
>[130537.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130537.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb0b60]
>[130537.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb0b60] width 1920 pitch 7680 (/4 1920)
>[130588.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8e490]
>[130588.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8e490] width 1920 pitch 7680 (/4 1920)
>[130999.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219eb0]
>[130999.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219eb0] width 1920 pitch 7680 (/4 1920)
>[131245.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d3d0]
>[131245.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d3d0] width 1920 pitch 7680 (/4 1920)
>[131248.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131248.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131248.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3219b90]
>[131248.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3219b90] width 1920 pitch 7680 (/4 1920)
>[131248.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131248.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131248.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131248.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131248.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f50e0]
>[131248.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f50e0] width 1920 pitch 7680 (/4 1920)
>[131248.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131248.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131248.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131248.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131249.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[131249.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[131249.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32234c0]
>[131249.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32234c0] width 1920 pitch 7680 (/4 1920)
>[131249.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9f60]
>[131249.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9f60] width 1920 pitch 7680 (/4 1920)
>[131250.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9f60]
>[131250.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9f60] width 1920 pitch 7680 (/4 1920)
>[131406.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[131406.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[131406.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[131406.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[131406.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131406.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131406.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131406.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131406.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131406.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131406.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131406.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131406.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131406.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131406.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131406.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131406.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131406.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131406.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131406.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131406.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131406.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131407.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131407.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131407.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131407.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131407.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131407.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131407.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131407.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131407.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131407.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131408.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[131408.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[131408.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[131408.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[131408.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131408.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131408.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[131408.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[131408.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131408.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131408.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[131408.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[131408.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[131408.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[131408.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[131408.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[132507.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[132507.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133035.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133035.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32141c0]
>[133035.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32141c0] width 1920 pitch 7680 (/4 1920)
>[133035.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d00]
>[133035.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d00] width 1920 pitch 7680 (/4 1920)
>[133039.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133039.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133039.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133039.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133039.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133039.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133039.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133040.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133040.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133040.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133040.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133040.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133040.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133040.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133040.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133040.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133040.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133040.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133040.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133040.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133040.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133040.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[133040.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[133040.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[133040.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e46220]
>[133040.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e46220] width 1920 pitch 7680 (/4 1920)
>[134317.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0610]
>[134317.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0610] width 1920 pitch 7680 (/4 1920)
>[135297.105] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[135297.105] (II) RADEON(0): Using hsync ranges from config file
>[135297.105] (II) RADEON(0): Using vrefresh ranges from config file
>[135297.105] (II) RADEON(0): Printing DDC gathered Modelines:
>[135297.105] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[135297.105] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[135297.105] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[135297.105] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[135297.105] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[135297.105] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[135297.105] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[135356.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f4ea0]
>[135356.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f4ea0] width 1920 pitch 7680 (/4 1920)
>[135356.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd320]
>[135356.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd320] width 1920 pitch 7680 (/4 1920)
>[135356.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322b250]
>[135356.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322b250] width 1920 pitch 7680 (/4 1920)
>[135356.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c72180]
>[135356.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c72180] width 1920 pitch 7680 (/4 1920)
>[135356.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334b1f0]
>[135356.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334b1f0] width 1920 pitch 7680 (/4 1920)
>[135356.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd320]
>[135356.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd320] width 1920 pitch 7680 (/4 1920)
>[135356.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322b250]
>[135356.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322b250] width 1920 pitch 7680 (/4 1920)
>[135356.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f4ea0]
>[135356.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f4ea0] width 1920 pitch 7680 (/4 1920)
>[135356.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c99f00]
>[135356.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c99f00] width 1920 pitch 7680 (/4 1920)
>[135356.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8ddd0]
>[135356.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8ddd0] width 1920 pitch 7680 (/4 1920)
>[135358.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464ed60]
>[135358.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464ed60] width 1920 pitch 7680 (/4 1920)
>[135359.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c72180]
>[135359.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c72180] width 1920 pitch 7680 (/4 1920)
>[135360.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220f10]
>[135360.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220f10] width 1920 pitch 7680 (/4 1920)
>[135360.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135360.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135360.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135360.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135360.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135360.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135360.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135360.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135360.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135360.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135360.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135361.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135361.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135361.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135361.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135361.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135361.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135361.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135361.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135361.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135361.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135361.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135361.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4649eb0]
>[135361.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4649eb0] width 1920 pitch 7680 (/4 1920)
>[135361.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e47ee0]
>[135361.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e47ee0] width 1920 pitch 7680 (/4 1920)
>[135482.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135482.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135482.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135482.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135482.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135482.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135482.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135482.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135482.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135482.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135482.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135482.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135482.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135482.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135483.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135483.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135483.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135483.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135483.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135483.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135483.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240840]
>[135483.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240840] width 1920 pitch 7680 (/4 1920)
>[135483.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135483.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135483.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135483.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135483.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135483.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135483.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135483.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135483.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[135483.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[135483.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135483.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135483.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339cf0]
>[135483.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339cf0] width 1920 pitch 7680 (/4 1920)
>[135495.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135495.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135495.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135495.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135495.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135495.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135495.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135495.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135495.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135495.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135495.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135495.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135495.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135495.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135495.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135495.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135495.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135495.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135496.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135496.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135496.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135496.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135496.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135496.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135496.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135496.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135497.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135497.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135497.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135497.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135497.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135497.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135497.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135497.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135497.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135497.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135497.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135498.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135498.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135498.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135498.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[135498.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[135710.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[135710.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[135802.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135802.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135802.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135802.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135802.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135802.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135802.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135802.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135802.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135802.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135802.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135802.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135802.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135802.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135802.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135802.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135802.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135802.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135802.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135802.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135803.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135803.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135803.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135803.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135803.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135803.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135803.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135803.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135803.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[135803.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[135804.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[135804.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[135804.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d1a0]
>[135804.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d1a0] width 1920 pitch 7680 (/4 1920)
>[135804.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d1a0]
>[135804.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d1a0] width 1920 pitch 7680 (/4 1920)
>[135804.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[135804.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[135804.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d1a0]
>[135804.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d1a0] width 1920 pitch 7680 (/4 1920)
>[135804.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[135804.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[135804.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d1a0]
>[135804.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d1a0] width 1920 pitch 7680 (/4 1920)
>[136126.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136126.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136476.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[136476.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[136476.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[136476.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[136476.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[136476.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[136476.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[136476.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[136476.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f30b0]
>[136476.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f30b0] width 1920 pitch 7680 (/4 1920)
>[136476.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136476.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136476.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136476.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136476.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136476.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136480.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136480.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136480.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136480.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136480.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136480.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136480.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136480.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136480.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e62920]
>[136480.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e62920] width 1920 pitch 7680 (/4 1920)
>[136480.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136480.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136480.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136480.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136480.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136480.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136480.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136480.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136480.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136480.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136480.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136480.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136480.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136480.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136480.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136480.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136516.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136516.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136516.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136516.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136516.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136516.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136520.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136520.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136520.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136520.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136520.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136520.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136520.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136520.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136520.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136520.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136520.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136520.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136520.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136520.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136520.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136520.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136520.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136520.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136520.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136520.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136520.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[136520.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[136520.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136520.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136708.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136708.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136708.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[136708.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[136708.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[136708.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[136708.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[136708.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[136708.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[136708.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[136708.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[136708.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[136708.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[136708.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[136708.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[136709.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[136709.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136709.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136709.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[136709.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[136709.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136709.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136709.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136709.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136709.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136709.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136709.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136709.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136709.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136709.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136709.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136709.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136709.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136709.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136709.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136709.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136709.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136709.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136728.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136728.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136728.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136728.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136728.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136728.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136728.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136728.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136728.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136728.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136728.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136728.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136728.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136728.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136729.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136729.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136729.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136729.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136729.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136729.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136729.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136729.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136729.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[136729.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[136729.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136729.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136729.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d3daa0]
>[136729.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d3daa0] width 1920 pitch 7680 (/4 1920)
>[136729.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136729.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136729.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136730.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136730.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136730.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136730.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136730.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136730.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136730.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136736.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32214a0]
>[136736.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32214a0] width 1920 pitch 7680 (/4 1920)
>[136736.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bef0]
>[136736.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bef0] width 1920 pitch 7680 (/4 1920)
>[136742.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e040]
>[136742.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e040] width 1920 pitch 7680 (/4 1920)
>[136756.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e97420]
>[136756.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e97420] width 1920 pitch 7680 (/4 1920)
>[136757.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136757.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136757.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04010]
>[136757.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04010] width 1920 pitch 7680 (/4 1920)
>[136757.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e489f0]
>[136757.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e489f0] width 1920 pitch 7680 (/4 1920)
>[136757.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32214a0]
>[136757.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32214a0] width 1920 pitch 7680 (/4 1920)
>[136757.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3377900]
>[136757.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3377900] width 1920 pitch 7680 (/4 1920)
>[136768.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136768.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136768.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136768.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136768.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334dca0]
>[136768.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334dca0] width 1920 pitch 7680 (/4 1920)
>[136768.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136768.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136768.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136768.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136768.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136768.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334dca0]
>[136768.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334dca0] width 1920 pitch 7680 (/4 1920)
>[136768.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136768.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136768.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136768.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136768.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136768.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334dca0]
>[136768.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334dca0] width 1920 pitch 7680 (/4 1920)
>[136768.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136768.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136768.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136768.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136768.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136768.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334dca0]
>[136768.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334dca0] width 1920 pitch 7680 (/4 1920)
>[136768.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136768.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136768.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136768.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136768.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136768.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136768.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136768.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136768.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136768.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136771.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e97360]
>[136771.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e97360] width 1920 pitch 7680 (/4 1920)
>[136776.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62a00]
>[136776.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62a00] width 1920 pitch 7680 (/4 1920)
>[136776.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206910]
>[136776.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206910] width 1920 pitch 7680 (/4 1920)
>[136782.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eeafe0]
>[136782.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eeafe0] width 1920 pitch 7680 (/4 1920)
>[136798.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5910]
>[136798.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5910] width 1920 pitch 7680 (/4 1920)
>[136813.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee94b0]
>[136813.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee94b0] width 1920 pitch 7680 (/4 1920)
>[136836.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206d10]
>[136836.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206d10] width 1920 pitch 7680 (/4 1920)
>[136836.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136836.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136836.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206d10]
>[136836.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206d10] width 1920 pitch 7680 (/4 1920)
>[136836.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33677d0]
>[136836.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33677d0] width 1920 pitch 7680 (/4 1920)
>[136836.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b626b0]
>[136836.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b626b0] width 1920 pitch 7680 (/4 1920)
>[136836.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32078b0]
>[136836.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32078b0] width 1920 pitch 7680 (/4 1920)
>[136836.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136836.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136836.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136836.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136836.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e97360]
>[136836.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e97360] width 1920 pitch 7680 (/4 1920)
>[136836.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136836.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136836.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e489f0]
>[136836.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e489f0] width 1920 pitch 7680 (/4 1920)
>[136836.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136836.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136836.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206d10]
>[136836.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206d10] width 1920 pitch 7680 (/4 1920)
>[136836.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33677d0]
>[136836.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33677d0] width 1920 pitch 7680 (/4 1920)
>[136836.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b626b0]
>[136836.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b626b0] width 1920 pitch 7680 (/4 1920)
>[136836.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32078b0]
>[136836.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32078b0] width 1920 pitch 7680 (/4 1920)
>[136836.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337c950]
>[136836.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337c950] width 1920 pitch 7680 (/4 1920)
>[136836.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8bf20]
>[136836.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8bf20] width 1920 pitch 7680 (/4 1920)
>[136836.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e97360]
>[136836.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e97360] width 1920 pitch 7680 (/4 1920)
>[136836.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e489f0]
>[136836.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e489f0] width 1920 pitch 7680 (/4 1920)
>[136836.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0c50]
>[136836.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0c50] width 1920 pitch 7680 (/4 1920)
>[136836.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3206d10]
>[136836.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3206d10] width 1920 pitch 7680 (/4 1920)
>[136836.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33677d0]
>[136836.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33677d0] width 1920 pitch 7680 (/4 1920)
>[136836.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32078b0]
>[136836.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32078b0] width 1920 pitch 7680 (/4 1920)
>[136836.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e97360]
>[136836.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e97360] width 1920 pitch 7680 (/4 1920)
>[136836.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f7490]
>[136836.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f7490] width 1920 pitch 7680 (/4 1920)
>[136857.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320b3c0]
>[136857.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320b3c0] width 1920 pitch 7680 (/4 1920)
>[136857.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ccf0]
>[136857.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ccf0] width 1920 pitch 7680 (/4 1920)
>[136865.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c910]
>[136865.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c910] width 1920 pitch 7680 (/4 1920)
>[136865.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c910]
>[136865.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c910] width 1920 pitch 7680 (/4 1920)
>[136865.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fe5a0]
>[136865.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fe5a0] width 1920 pitch 7680 (/4 1920)
>[136865.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464cb70]
>[136865.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464cb70] width 1920 pitch 7680 (/4 1920)
>[136866.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464cb70]
>[136866.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464cb70] width 1920 pitch 7680 (/4 1920)
>[136877.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4080]
>[136877.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4080] width 1920 pitch 7680 (/4 1920)
>[136877.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a4d0]
>[136877.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a4d0] width 1920 pitch 7680 (/4 1920)
>[136880.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fe5a0]
>[136880.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fe5a0] width 1920 pitch 7680 (/4 1920)
>[136880.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464cb70]
>[136880.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464cb70] width 1920 pitch 7680 (/4 1920)
>[136880.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464cb70]
>[136880.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464cb70] width 1920 pitch 7680 (/4 1920)
>[136880.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464cb70]
>[136880.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464cb70] width 1920 pitch 7680 (/4 1920)
>[136880.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31fe5a0]
>[136880.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31fe5a0] width 1920 pitch 7680 (/4 1920)
>[136882.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136882.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136891.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136891.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136891.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136891.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357840]
>[136891.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357840] width 1920 pitch 7680 (/4 1920)
>[136891.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136891.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136891.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136891.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136891.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136892.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136892.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136892.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136892.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136893.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136893.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136893.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136894.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136894.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136894.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136894.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136894.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136894.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136894.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136894.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136894.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136894.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136894.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136894.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136894.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136894.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136894.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136894.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136895.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136895.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136895.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136895.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136895.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136895.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136895.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136895.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136895.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136895.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136895.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136895.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136895.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136895.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136895.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136895.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136895.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136895.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ed1d0]
>[136895.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ed1d0] width 1920 pitch 7680 (/4 1920)
>[136895.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136896.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136896.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136896.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136896.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f180]
>[136896.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f180] width 1920 pitch 7680 (/4 1920)
>[136896.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ed1d0]
>[136896.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ed1d0] width 1920 pitch 7680 (/4 1920)
>[136896.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f180]
>[136896.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f180] width 1920 pitch 7680 (/4 1920)
>[136896.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f180]
>[136896.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f180] width 1920 pitch 7680 (/4 1920)
>[136896.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f180]
>[136896.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f180] width 1920 pitch 7680 (/4 1920)
>[136896.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136896.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136896.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136896.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136896.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136896.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136896.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136896.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136896.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136897.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136897.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136897.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136897.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136897.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136897.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136897.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136897.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136897.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136897.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136897.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136897.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136897.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136897.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136897.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136897.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136898.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136898.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136898.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a470]
>[136898.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a470] width 1920 pitch 7680 (/4 1920)
>[136898.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136898.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136898.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136898.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136898.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136898.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136898.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136898.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136898.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136898.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136898.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136898.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136898.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136898.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136898.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136898.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136898.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f180]
>[136898.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f180] width 1920 pitch 7680 (/4 1920)
>[136899.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e701d0]
>[136899.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e701d0] width 1920 pitch 7680 (/4 1920)
>[136900.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136900.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136900.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136900.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136900.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3207670]
>[136900.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3207670] width 1920 pitch 7680 (/4 1920)
>[136900.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3207840]
>[136900.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3207840] width 1920 pitch 7680 (/4 1920)
>[136900.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3207840]
>[136900.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3207840] width 1920 pitch 7680 (/4 1920)
>[136900.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3207840]
>[136900.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3207840] width 1920 pitch 7680 (/4 1920)
>[136900.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32077c0]
>[136900.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32077c0] width 1920 pitch 7680 (/4 1920)
>[136900.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136900.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136900.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba4210]
>[136900.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba4210] width 1920 pitch 7680 (/4 1920)
>[136900.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba4210]
>[136900.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba4210] width 1920 pitch 7680 (/4 1920)
>[136900.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[136900.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[136900.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ecee0]
>[136900.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ecee0] width 1920 pitch 7680 (/4 1920)
>[136900.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee68c0]
>[136900.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee68c0] width 1920 pitch 7680 (/4 1920)
>[137035.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137035.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137035.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc360]
>[137035.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc360] width 1920 pitch 7680 (/4 1920)
>[137035.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137035.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137035.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc360]
>[137035.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc360] width 1920 pitch 7680 (/4 1920)
>[137035.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137035.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137035.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc360]
>[137035.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc360] width 1920 pitch 7680 (/4 1920)
>[137035.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137035.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137035.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc360]
>[137035.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc360] width 1920 pitch 7680 (/4 1920)
>[137035.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137035.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137036.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc360]
>[137036.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc360] width 1920 pitch 7680 (/4 1920)
>[137036.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137036.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137036.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb310]
>[137036.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb310] width 1920 pitch 7680 (/4 1920)
>[137036.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2470]
>[137036.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2470] width 1920 pitch 7680 (/4 1920)
>[137036.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb310]
>[137036.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb310] width 1920 pitch 7680 (/4 1920)
>[137036.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2470]
>[137036.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2470] width 1920 pitch 7680 (/4 1920)
>[137036.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f8ab0]
>[137036.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f8ab0] width 1920 pitch 7680 (/4 1920)
>[137036.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6a30]
>[137036.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6a30] width 1920 pitch 7680 (/4 1920)
>[137040.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8640]
>[137040.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8640] width 1920 pitch 7680 (/4 1920)
>[137068.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d3a040]
>[137068.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d3a040] width 1920 pitch 7680 (/4 1920)
>[137068.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137068.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137068.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d3a040]
>[137068.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d3a040] width 1920 pitch 7680 (/4 1920)
>[137068.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137068.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137068.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137068.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137068.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137068.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137068.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137068.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137068.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137068.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137069.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137069.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137069.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137069.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137069.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137069.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137069.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137069.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137069.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d950]
>[137069.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d950] width 1920 pitch 7680 (/4 1920)
>[137070.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334cdd0]
>[137070.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334cdd0] width 1920 pitch 7680 (/4 1920)
>[137070.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ed5e0]
>[137070.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ed5e0] width 1920 pitch 7680 (/4 1920)
>[137070.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200420]
>[137070.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200420] width 1920 pitch 7680 (/4 1920)
>[137070.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ed5e0]
>[137070.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ed5e0] width 1920 pitch 7680 (/4 1920)
>[137070.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200420]
>[137070.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200420] width 1920 pitch 7680 (/4 1920)
>[137070.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ed5e0]
>[137070.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ed5e0] width 1920 pitch 7680 (/4 1920)
>[137091.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c8b0]
>[137091.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c8b0] width 1920 pitch 7680 (/4 1920)
>[137119.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf05d0]
>[137119.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf05d0] width 1920 pitch 7680 (/4 1920)
>[137160.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137160.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137160.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137160.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137160.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec3340]
>[137160.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec3340] width 1920 pitch 7680 (/4 1920)
>[137160.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137160.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137160.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137160.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137160.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137160.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137160.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137160.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137161.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137161.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137161.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137161.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137161.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137161.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137161.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356310]
>[137161.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356310] width 1920 pitch 7680 (/4 1920)
>[137161.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137161.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137161.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[137161.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[137161.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356310]
>[137161.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356310] width 1920 pitch 7680 (/4 1920)
>[137161.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e570]
>[137161.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e570] width 1920 pitch 7680 (/4 1920)
>[137181.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e570]
>[137181.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e570] width 1920 pitch 7680 (/4 1920)
>[137181.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e400]
>[137181.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e400] width 1920 pitch 7680 (/4 1920)
>[137182.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356310]
>[137182.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356310] width 1920 pitch 7680 (/4 1920)
>[137185.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137185.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137185.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137185.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137185.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8200]
>[137185.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8200] width 1920 pitch 7680 (/4 1920)
>[137185.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137185.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137185.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137185.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137185.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4de80]
>[137185.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4de80] width 1920 pitch 7680 (/4 1920)
>[137185.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137185.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137185.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4de80]
>[137185.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4de80] width 1920 pitch 7680 (/4 1920)
>[137185.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137185.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137186.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4de80]
>[137186.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4de80] width 1920 pitch 7680 (/4 1920)
>[137186.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137186.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137186.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4de80]
>[137186.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4de80] width 1920 pitch 7680 (/4 1920)
>[137186.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137186.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137186.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137186.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137186.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea7f00]
>[137187.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea7f00] width 1920 pitch 7680 (/4 1920)
>[137187.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137187.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137187.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea7f00]
>[137187.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea7f00] width 1920 pitch 7680 (/4 1920)
>[137187.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e570]
>[137187.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e570] width 1920 pitch 7680 (/4 1920)
>[137199.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e570]
>[137199.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e570] width 1920 pitch 7680 (/4 1920)
>[137199.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f434d0]
>[137199.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f434d0] width 1920 pitch 7680 (/4 1920)
>[137239.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137239.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137239.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137239.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137239.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137239.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137239.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137239.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137239.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137239.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137239.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137239.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137239.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137239.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137239.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137239.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137239.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137239.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137239.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137239.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137239.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137243.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137243.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137243.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137243.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137243.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137243.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137243.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137243.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137243.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137243.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137243.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137243.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137243.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137243.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137243.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137243.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137243.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137243.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137243.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137243.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137243.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137243.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137243.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137243.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137243.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137243.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137534.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8200]
>[137534.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8200] width 1920 pitch 7680 (/4 1920)
>[137534.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137534.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137534.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137534.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137534.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137534.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137534.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137534.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137534.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8200]
>[137534.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8200] width 1920 pitch 7680 (/4 1920)
>[137534.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137534.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137534.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137534.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137534.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8200]
>[137534.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8200] width 1920 pitch 7680 (/4 1920)
>[137535.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137535.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137535.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137535.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137535.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137535.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137535.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137535.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137539.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137539.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137539.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf0630]
>[137539.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf0630] width 1920 pitch 7680 (/4 1920)
>[137539.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137539.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137539.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137539.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137539.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8200]
>[137539.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8200] width 1920 pitch 7680 (/4 1920)
>[137539.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137539.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137539.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137539.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137539.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137539.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137539.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137539.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137539.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137539.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137539.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b8fb10]
>[137539.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b8fb10] width 1920 pitch 7680 (/4 1920)
>[137539.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49180]
>[137539.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49180] width 1920 pitch 7680 (/4 1920)
>[137539.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8120]
>[137539.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8120] width 1920 pitch 7680 (/4 1920)
>[137576.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464eb80]
>[137576.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464eb80] width 1920 pitch 7680 (/4 1920)
>[137588.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec30e0]
>[137588.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec30e0] width 1920 pitch 7680 (/4 1920)
>[137967.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335c3f0]
>[137967.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335c3f0] width 1920 pitch 7680 (/4 1920)
>[137967.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2c620]
>[137967.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2c620] width 1920 pitch 7680 (/4 1920)
>[137967.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[137967.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[137967.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335c3f0]
>[137967.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335c3f0] width 1920 pitch 7680 (/4 1920)
>[137967.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64d10]
>[137967.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64d10] width 1920 pitch 7680 (/4 1920)
>[137967.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec3890]
>[137967.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec3890] width 1920 pitch 7680 (/4 1920)
>[137967.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee1240]
>[137967.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee1240] width 1920 pitch 7680 (/4 1920)
>[137968.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2c620]
>[137968.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2c620] width 1920 pitch 7680 (/4 1920)
>[137968.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e64d10]
>[137968.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e64d10] width 1920 pitch 7680 (/4 1920)
>[137968.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee1240]
>[137968.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee1240] width 1920 pitch 7680 (/4 1920)
>[137969.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[137969.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[137969.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee1240]
>[137969.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee1240] width 1920 pitch 7680 (/4 1920)
>[137969.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec3890]
>[137969.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec3890] width 1920 pitch 7680 (/4 1920)
>[137969.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335c3f0]
>[137969.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335c3f0] width 1920 pitch 7680 (/4 1920)
>[137969.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec3890]
>[137969.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec3890] width 1920 pitch 7680 (/4 1920)
>[137969.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee1240]
>[137969.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee1240] width 1920 pitch 7680 (/4 1920)
>[137976.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335c3f0]
>[137976.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335c3f0] width 1920 pitch 7680 (/4 1920)
>[138067.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebdd90]
>[138067.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebdd90] width 1920 pitch 7680 (/4 1920)
>[138067.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebdd90]
>[138067.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebdd90] width 1920 pitch 7680 (/4 1920)
>[138068.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80400]
>[138068.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80400] width 1920 pitch 7680 (/4 1920)
>[138068.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138068.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138068.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138068.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138068.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138068.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138068.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138068.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138068.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138068.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138069.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80400]
>[138069.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80400] width 1920 pitch 7680 (/4 1920)
>[138069.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80400]
>[138069.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80400] width 1920 pitch 7680 (/4 1920)
>[138069.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138069.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138069.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138069.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138069.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80400]
>[138069.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80400] width 1920 pitch 7680 (/4 1920)
>[138069.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138069.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138069.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138069.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138070.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f354a0]
>[138070.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f354a0] width 1920 pitch 7680 (/4 1920)
>[138070.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138070.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138070.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eafb20]
>[138070.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eafb20] width 1920 pitch 7680 (/4 1920)
>[138200.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138200.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138200.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138200.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138201.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138201.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138201.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138201.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138201.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138201.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138201.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138201.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138201.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138201.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138201.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138201.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138201.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138201.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138201.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138201.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138202.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138202.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138202.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138202.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138202.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138202.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138202.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138202.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138202.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[138202.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[138203.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138203.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138203.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[138203.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[138203.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138203.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138203.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[138203.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[138203.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[138203.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[138203.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[138203.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[138883.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[138883.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[138883.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138883.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138883.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[138883.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[138883.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138883.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138883.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[138883.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[138883.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138883.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138883.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[138883.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[138883.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138883.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138883.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[138884.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[138884.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138884.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138884.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e620e0]
>[138884.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e620e0] width 1920 pitch 7680 (/4 1920)
>[138884.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138884.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138884.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e620e0]
>[138884.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e620e0] width 1920 pitch 7680 (/4 1920)
>[138884.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3350040]
>[138884.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3350040] width 1920 pitch 7680 (/4 1920)
>[138884.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e620e0]
>[138884.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e620e0] width 1920 pitch 7680 (/4 1920)
>[138884.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf530]
>[138884.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf530] width 1920 pitch 7680 (/4 1920)
>[138889.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f017b0]
>[138889.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f017b0] width 1920 pitch 7680 (/4 1920)
>[138923.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c74fc0]
>[138923.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c74fc0] width 1920 pitch 7680 (/4 1920)
>[138923.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3209610]
>[138923.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3209610] width 1920 pitch 7680 (/4 1920)
>[138923.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c74fc0]
>[138923.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c74fc0] width 1920 pitch 7680 (/4 1920)
>[138923.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5440]
>[138923.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5440] width 1920 pitch 7680 (/4 1920)
>[138923.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138923.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138923.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5440]
>[138923.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5440] width 1920 pitch 7680 (/4 1920)
>[138923.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138923.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138923.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5440]
>[138923.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5440] width 1920 pitch 7680 (/4 1920)
>[138923.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138923.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138923.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5440]
>[138923.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5440] width 1920 pitch 7680 (/4 1920)
>[138923.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138923.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138923.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5440]
>[138923.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5440] width 1920 pitch 7680 (/4 1920)
>[138923.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138924.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138924.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c74fc0]
>[138924.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c74fc0] width 1920 pitch 7680 (/4 1920)
>[138924.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138924.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138924.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138924.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138925.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138925.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138925.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138925.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138925.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138925.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138925.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138925.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138925.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138925.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138925.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138925.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138925.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138925.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138925.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138925.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138925.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138925.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138925.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138926.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138926.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138926.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138926.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138926.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138926.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138926.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138926.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138926.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138926.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138926.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138926.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138926.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138926.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138926.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138926.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138926.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138926.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5020]
>[138926.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5020] width 1920 pitch 7680 (/4 1920)
>[138926.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138926.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138927.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138927.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138927.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[138927.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[138927.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f099d0]
>[138927.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f099d0] width 1920 pitch 7680 (/4 1920)
>[138927.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3380]
>[138927.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3380] width 1920 pitch 7680 (/4 1920)
>[138945.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e316e0]
>[138945.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e316e0] width 1920 pitch 7680 (/4 1920)
>[138945.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138945.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138945.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e316e0]
>[138945.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e316e0] width 1920 pitch 7680 (/4 1920)
>[138945.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef2190]
>[138945.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef2190] width 1920 pitch 7680 (/4 1920)
>[138945.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138945.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138945.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138945.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138946.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e316e0]
>[138946.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e316e0] width 1920 pitch 7680 (/4 1920)
>[138946.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138946.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e316e0]
>[138946.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e316e0] width 1920 pitch 7680 (/4 1920)
>[138946.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138946.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec8020]
>[138946.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec8020] width 1920 pitch 7680 (/4 1920)
>[138946.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e316e0]
>[138946.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e316e0] width 1920 pitch 7680 (/4 1920)
>[138946.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f35250]
>[138946.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f35250] width 1920 pitch 7680 (/4 1920)
>[138946.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138946.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335a240]
>[138946.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335a240] width 1920 pitch 7680 (/4 1920)
>[138946.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f35250]
>[138946.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f35250] width 1920 pitch 7680 (/4 1920)
>[138947.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec8020]
>[138947.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec8020] width 1920 pitch 7680 (/4 1920)
>[139032.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c920b0]
>[139032.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c920b0] width 1920 pitch 7680 (/4 1920)
>[139032.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32088f0]
>[139032.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32088f0] width 1920 pitch 7680 (/4 1920)
>[139032.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139032.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139032.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f21730]
>[139032.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f21730] width 1920 pitch 7680 (/4 1920)
>[139032.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32088f0]
>[139033.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32088f0] width 1920 pitch 7680 (/4 1920)
>[139033.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139033.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139033.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32088f0]
>[139033.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32088f0] width 1920 pitch 7680 (/4 1920)
>[139033.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139033.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139033.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32088f0]
>[139033.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32088f0] width 1920 pitch 7680 (/4 1920)
>[139033.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139033.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139033.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32088f0]
>[139033.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32088f0] width 1920 pitch 7680 (/4 1920)
>[139034.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139034.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139034.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eeb6e0]
>[139034.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eeb6e0] width 1920 pitch 7680 (/4 1920)
>[139034.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eeb6e0]
>[139034.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eeb6e0] width 1920 pitch 7680 (/4 1920)
>[139034.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edd9d0]
>[139034.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edd9d0] width 1920 pitch 7680 (/4 1920)
>[139034.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edfa00]
>[139034.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edfa00] width 1920 pitch 7680 (/4 1920)
>[139034.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef2730]
>[139034.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef2730] width 1920 pitch 7680 (/4 1920)
>[139052.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57e80]
>[139052.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57e80] width 1920 pitch 7680 (/4 1920)
>[139054.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5a580]
>[139054.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5a580] width 1920 pitch 7680 (/4 1920)
>[139054.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d573f0]
>[139054.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d573f0] width 1920 pitch 7680 (/4 1920)
>[139054.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d56910]
>[139054.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d56910] width 1920 pitch 7680 (/4 1920)
>[139054.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eaf670]
>[139054.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eaf670] width 1920 pitch 7680 (/4 1920)
>[139077.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f35210]
>[139077.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f35210] width 1920 pitch 7680 (/4 1920)
>[139087.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec5fe0]
>[139087.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec5fe0] width 1920 pitch 7680 (/4 1920)
>[139088.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4638450]
>[139088.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4638450] width 1920 pitch 7680 (/4 1920)
>[139240.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f35420]
>[139240.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f35420] width 1920 pitch 7680 (/4 1920)
>[139240.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c8eea0]
>[139240.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c8eea0] width 1920 pitch 7680 (/4 1920)
>[139276.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d542d0]
>[139276.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d542d0] width 1920 pitch 7680 (/4 1920)
>[139276.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139276.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139276.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d542d0]
>[139276.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d542d0] width 1920 pitch 7680 (/4 1920)
>[139276.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139276.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139276.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d542d0]
>[139276.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d542d0] width 1920 pitch 7680 (/4 1920)
>[139276.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139276.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139276.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d542d0]
>[139276.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d542d0] width 1920 pitch 7680 (/4 1920)
>[139276.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139276.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139276.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d542d0]
>[139276.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d542d0] width 1920 pitch 7680 (/4 1920)
>[139276.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139276.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139278.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139278.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139279.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139279.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139279.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139279.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139279.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139279.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139279.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139279.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139279.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8750]
>[139279.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8750] width 1920 pitch 7680 (/4 1920)
>[139279.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c10]
>[139279.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c10] width 1920 pitch 7680 (/4 1920)
>[139443.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef9bf0]
>[139443.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef9bf0] width 1920 pitch 7680 (/4 1920)
>[139913.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b782f0]
>[139913.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b782f0] width 1920 pitch 7680 (/4 1920)
>[139914.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509ca50]
>[139914.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509ca50] width 1920 pitch 7680 (/4 1920)
>[139914.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b782f0]
>[139914.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b782f0] width 1920 pitch 7680 (/4 1920)
>[139914.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4360]
>[139914.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4360] width 1920 pitch 7680 (/4 1920)
>[139914.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139914.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139914.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4360]
>[139914.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4360] width 1920 pitch 7680 (/4 1920)
>[139914.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139914.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139914.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4360]
>[139914.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4360] width 1920 pitch 7680 (/4 1920)
>[139914.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139914.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139914.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4360]
>[139914.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4360] width 1920 pitch 7680 (/4 1920)
>[139915.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139915.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139915.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139915.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139915.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f32520]
>[139915.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f32520] width 1920 pitch 7680 (/4 1920)
>[139915.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139915.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139915.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f32520]
>[139915.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f32520] width 1920 pitch 7680 (/4 1920)
>[139915.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139915.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139915.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[139915.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[139915.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139915.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139918.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139918.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139918.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139918.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139918.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139918.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139918.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139918.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139918.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139918.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139918.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139918.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139918.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139918.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139918.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139918.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139919.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139919.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139919.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139919.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139919.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[139919.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[139919.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139919.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139919.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea64e0]
>[139919.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea64e0] width 1920 pitch 7680 (/4 1920)
>[139919.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139919.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139919.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea64e0]
>[139919.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea64e0] width 1920 pitch 7680 (/4 1920)
>[139919.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139919.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139919.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6560]
>[139919.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6560] width 1920 pitch 7680 (/4 1920)
>[139919.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea69f0]
>[139919.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea69f0] width 1920 pitch 7680 (/4 1920)
>[139919.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b78620]
>[139919.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b78620] width 1920 pitch 7680 (/4 1920)
>[139938.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139938.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139938.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139938.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139938.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139938.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139938.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139938.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139938.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139938.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139938.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139938.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139938.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139938.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139938.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139938.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139939.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139939.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139939.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139939.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139939.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139939.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139939.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[139939.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[139939.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[139939.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[139939.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[139939.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[139939.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[139939.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[139939.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[139939.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[139939.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[139939.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[139940.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[139940.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[139940.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[139940.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140348.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[140348.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[140597.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140597.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140604.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140604.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140604.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d482d0]
>[140604.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d482d0] width 1920 pitch 7680 (/4 1920)
>[140604.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140604.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140604.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d482d0]
>[140604.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d482d0] width 1920 pitch 7680 (/4 1920)
>[140604.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140604.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140604.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d482d0]
>[140604.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d482d0] width 1920 pitch 7680 (/4 1920)
>[140604.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140604.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140604.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d482d0]
>[140604.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d482d0] width 1920 pitch 7680 (/4 1920)
>[140604.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140604.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140605.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140605.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140607.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140607.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140607.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140607.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140607.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140607.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140607.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140607.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140607.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140608.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140608.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140608.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140608.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140608.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140609.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140609.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140609.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140609.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140609.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140609.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140609.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140609.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140609.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140609.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140609.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140609.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140609.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140609.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140609.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140609.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140609.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140609.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140609.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140609.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140609.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140609.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140610.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140610.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140610.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140610.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140610.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140610.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140612.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140612.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140612.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140612.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140612.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140612.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140613.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[140613.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[140613.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[140613.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[140613.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[140613.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[140613.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140613.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140613.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edb540]
>[140613.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edb540] width 1920 pitch 7680 (/4 1920)
>[140613.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140613.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140613.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140613.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140616.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f4ea0]
>[140616.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f4ea0] width 1920 pitch 7680 (/4 1920)
>[140616.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f730]
>[140616.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f730] width 1920 pitch 7680 (/4 1920)
>[140616.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f4ea0]
>[140616.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f4ea0] width 1920 pitch 7680 (/4 1920)
>[140616.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee5d60]
>[140616.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee5d60] width 1920 pitch 7680 (/4 1920)
>[140616.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d43840]
>[140616.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d43840] width 1920 pitch 7680 (/4 1920)
>[140616.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee5d60]
>[140616.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee5d60] width 1920 pitch 7680 (/4 1920)
>[140616.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d43840]
>[140616.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d43840] width 1920 pitch 7680 (/4 1920)
>[140616.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee5d60]
>[140616.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee5d60] width 1920 pitch 7680 (/4 1920)
>[140616.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d43840]
>[140616.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d43840] width 1920 pitch 7680 (/4 1920)
>[140617.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8930]
>[140617.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8930] width 1920 pitch 7680 (/4 1920)
>[140617.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3780]
>[140617.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3780] width 1920 pitch 7680 (/4 1920)
>[140629.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101a50]
>[140629.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101a50] width 1920 pitch 7680 (/4 1920)
>[140629.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506dbf0]
>[140629.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506dbf0] width 1920 pitch 7680 (/4 1920)
>[140637.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077ae0]
>[140637.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077ae0] width 1920 pitch 7680 (/4 1920)
>[140641.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101b30]
>[140641.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101b30] width 1920 pitch 7680 (/4 1920)
>[140643.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140643.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140643.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140643.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140643.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140644.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140644.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140644.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140644.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140644.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140661.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140661.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140661.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140661.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140661.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140661.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140661.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140661.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140661.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140661.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140661.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140661.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140661.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140661.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140661.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140661.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140661.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140661.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140661.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140661.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140661.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140661.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140665.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140665.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140665.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140665.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140665.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140665.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140665.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140665.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140665.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140665.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140665.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140665.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140665.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140665.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140665.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140665.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140665.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140665.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140665.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140665.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140665.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140665.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140665.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140666.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140666.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140666.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140666.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140666.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140666.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140666.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140666.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140666.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140666.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140666.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140666.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140666.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140666.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140666.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140666.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140674.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140674.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140674.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140674.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140674.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140674.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140674.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140674.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140674.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140674.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140674.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140674.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140674.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140674.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140674.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140674.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140674.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140674.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140675.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140675.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140675.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140675.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140675.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140675.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140675.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140675.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140675.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140675.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140676.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140676.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140676.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140676.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140676.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140676.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140676.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140676.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140676.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140677.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140677.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140677.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140677.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140677.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140677.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140677.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140677.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140677.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140677.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140677.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140677.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[140677.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[140677.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140677.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140677.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140677.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140677.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140677.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140677.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140677.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140677.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140677.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140677.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140677.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140677.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140677.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140677.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140677.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140677.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140677.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140678.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140678.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140678.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140678.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140678.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140678.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140678.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140678.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140678.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140678.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140678.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140678.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140678.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140678.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140678.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140678.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140678.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140678.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140678.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140678.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140679.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[140679.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[140679.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140679.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140679.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[140679.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[140679.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140679.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140679.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140679.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140679.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140679.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140679.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140679.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140679.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x464c3d0]
>[140679.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x464c3d0] width 1920 pitch 7680 (/4 1920)
>[140679.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140679.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140679.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140679.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140679.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140679.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140679.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140679.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140679.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140679.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140679.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140679.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140679.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140679.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140679.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140679.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140679.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140679.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140679.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140679.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140679.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140679.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140679.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140679.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140679.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07bf0]
>[140679.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07bf0] width 1920 pitch 7680 (/4 1920)
>[140679.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140679.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140679.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3200730]
>[140679.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3200730] width 1920 pitch 7680 (/4 1920)
>[140680.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140680.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140680.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140680.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140680.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140680.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140680.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140680.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140680.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140680.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140680.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140680.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140680.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140680.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140680.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140680.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140680.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140680.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140680.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb85b0]
>[140680.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb85b0] width 1920 pitch 7680 (/4 1920)
>[140680.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea95c0]
>[140680.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea95c0] width 1920 pitch 7680 (/4 1920)
>[140680.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140680.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140681.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140681.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140681.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140681.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140681.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140681.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140681.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337b0f0]
>[140681.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337b0f0] width 1920 pitch 7680 (/4 1920)
>[140689.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d10]
>[140689.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d10] width 1920 pitch 7680 (/4 1920)
>[140689.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140689.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140689.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140689.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140689.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140689.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140689.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140689.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140689.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c58ac0]
>[140689.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c58ac0] width 1920 pitch 7680 (/4 1920)
>[140689.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3216e20]
>[140689.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3216e20] width 1920 pitch 7680 (/4 1920)
>[140690.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140690.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140705.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b310]
>[140705.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b310] width 1920 pitch 7680 (/4 1920)
>[140711.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef60]
>[140711.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef60] width 1920 pitch 7680 (/4 1920)
>[140711.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96340]
>[140711.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96340] width 1920 pitch 7680 (/4 1920)
>[140711.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef00]
>[140711.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef00] width 1920 pitch 7680 (/4 1920)
>[140711.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef60]
>[140711.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef60] width 1920 pitch 7680 (/4 1920)
>[140711.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eceeb0]
>[140711.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eceeb0] width 1920 pitch 7680 (/4 1920)
>[140711.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96340]
>[140711.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96340] width 1920 pitch 7680 (/4 1920)
>[140711.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef00]
>[140711.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef00] width 1920 pitch 7680 (/4 1920)
>[140711.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2170]
>[140711.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2170] width 1920 pitch 7680 (/4 1920)
>[140711.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da0840]
>[140711.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da0840] width 1920 pitch 7680 (/4 1920)
>[140711.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da0840]
>[140711.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da0840] width 1920 pitch 7680 (/4 1920)
>[140712.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2fc0]
>[140712.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2fc0] width 1920 pitch 7680 (/4 1920)
>[140712.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f51f0]
>[140712.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f51f0] width 1920 pitch 7680 (/4 1920)
>[140712.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366940]
>[140712.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366940] width 1920 pitch 7680 (/4 1920)
>[140712.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f51f0]
>[140712.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f51f0] width 1920 pitch 7680 (/4 1920)
>[140712.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da0840]
>[140712.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da0840] width 1920 pitch 7680 (/4 1920)
>[140712.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da11c0]
>[140712.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da11c0] width 1920 pitch 7680 (/4 1920)
>[140713.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eaeed0]
>[140713.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eaeed0] width 1920 pitch 7680 (/4 1920)
>[140713.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57050]
>[140713.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57050] width 1920 pitch 7680 (/4 1920)
>[140713.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51970]
>[140713.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51970] width 1920 pitch 7680 (/4 1920)
>[140713.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eaeed0]
>[140713.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eaeed0] width 1920 pitch 7680 (/4 1920)
>[140721.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f830]
>[140721.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f830] width 1920 pitch 7680 (/4 1920)
>[140721.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef60]
>[140721.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef60] width 1920 pitch 7680 (/4 1920)
>[140721.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5980]
>[140721.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5980] width 1920 pitch 7680 (/4 1920)
>[140721.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f830]
>[140721.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f830] width 1920 pitch 7680 (/4 1920)
>[140721.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa20]
>[140721.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa20] width 1920 pitch 7680 (/4 1920)
>[140721.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef60]
>[140721.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef60] width 1920 pitch 7680 (/4 1920)
>[140721.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da11c0]
>[140721.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da11c0] width 1920 pitch 7680 (/4 1920)
>[140721.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da11c0]
>[140721.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da11c0] width 1920 pitch 7680 (/4 1920)
>[140721.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa20]
>[140721.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa20] width 1920 pitch 7680 (/4 1920)
>[140722.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eba070]
>[140722.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eba070] width 1920 pitch 7680 (/4 1920)
>[140722.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da11c0]
>[140722.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da11c0] width 1920 pitch 7680 (/4 1920)
>[140722.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eba070]
>[140722.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eba070] width 1920 pitch 7680 (/4 1920)
>[140722.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecef60]
>[140722.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecef60] width 1920 pitch 7680 (/4 1920)
>[140722.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da11c0]
>[140722.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da11c0] width 1920 pitch 7680 (/4 1920)
>[140723.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f830]
>[140723.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f830] width 1920 pitch 7680 (/4 1920)
>[140723.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f830]
>[140723.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f830] width 1920 pitch 7680 (/4 1920)
>[140724.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d1b400]
>[140724.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d1b400] width 1920 pitch 7680 (/4 1920)
>[140724.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3f830]
>[140724.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3f830] width 1920 pitch 7680 (/4 1920)
>[140724.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d1b400]
>[140724.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d1b400] width 1920 pitch 7680 (/4 1920)
>[140724.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa20]
>[140724.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa20] width 1920 pitch 7680 (/4 1920)
>[140724.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d1b400]
>[140724.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d1b400] width 1920 pitch 7680 (/4 1920)
>[140724.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa20]
>[140724.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa20] width 1920 pitch 7680 (/4 1920)
>[140724.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa20]
>[140724.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa20] width 1920 pitch 7680 (/4 1920)
>[140725.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140725.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140727.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587ef0]
>[140727.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587ef0] width 1920 pitch 7680 (/4 1920)
>[140729.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140729.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140729.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140729.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140729.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140729.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140729.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140729.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140729.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366e40]
>[140729.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366e40] width 1920 pitch 7680 (/4 1920)
>[140729.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366e40]
>[140729.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366e40] width 1920 pitch 7680 (/4 1920)
>[140729.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140729.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140729.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140729.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140729.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140729.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140729.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140729.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140731.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b580]
>[140731.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b580] width 1920 pitch 7680 (/4 1920)
>[140731.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140731.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140732.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140732.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140732.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140732.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140732.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140732.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077900]
>[140732.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077900] width 1920 pitch 7680 (/4 1920)
>[140732.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf70]
>[140732.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf70] width 1920 pitch 7680 (/4 1920)
>[140732.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140732.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c210]
>[140733.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c210] width 1920 pitch 7680 (/4 1920)
>[140733.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c210]
>[140733.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c210] width 1920 pitch 7680 (/4 1920)
>[140733.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c210]
>[140733.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c210] width 1920 pitch 7680 (/4 1920)
>[140733.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c901e0]
>[140733.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c901e0] width 1920 pitch 7680 (/4 1920)
>[140733.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140733.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140733.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c901e0]
>[140733.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c901e0] width 1920 pitch 7680 (/4 1920)
>[140736.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b310]
>[140736.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b310] width 1920 pitch 7680 (/4 1920)
>[140740.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505acd0]
>[140740.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505acd0] width 1920 pitch 7680 (/4 1920)
>[140811.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140811.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140811.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6770]
>[140811.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6770] width 1920 pitch 7680 (/4 1920)
>[140815.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253f40]
>[140815.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253f40] width 1920 pitch 7680 (/4 1920)
>[140815.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8e20]
>[140815.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8e20] width 1920 pitch 7680 (/4 1920)
>[140853.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105a00]
>[140853.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105a00] width 1920 pitch 7680 (/4 1920)
>[140853.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140853.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140853.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105a00]
>[140853.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105a00] width 1920 pitch 7680 (/4 1920)
>[140853.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140853.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140853.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140853.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140853.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140853.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140853.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140853.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140853.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105a00]
>[140853.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105a00] width 1920 pitch 7680 (/4 1920)
>[140853.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140853.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140853.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140853.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140853.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140853.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140853.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140853.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140853.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140853.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140855.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140855.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140858.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140858.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140860.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140860.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140860.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140860.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140860.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140860.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140860.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140860.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140860.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140860.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140860.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140860.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140860.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140860.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140860.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140860.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075460]
>[140860.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075460] width 1920 pitch 7680 (/4 1920)
>[140860.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075460]
>[140861.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075460] width 1920 pitch 7680 (/4 1920)
>[140861.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075460]
>[140861.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075460] width 1920 pitch 7680 (/4 1920)
>[140861.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140861.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140861.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075460]
>[140861.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075460] width 1920 pitch 7680 (/4 1920)
>[140861.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140861.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140861.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140861.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140861.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140861.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140861.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140861.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140861.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140861.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140861.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140861.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140861.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140861.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140862.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140862.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140862.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140862.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140862.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140862.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140862.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140862.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140862.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140862.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140862.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140862.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140862.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140862.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140862.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140862.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140862.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140862.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140862.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140862.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140862.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140862.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140862.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140863.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140863.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140863.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140863.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140863.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140863.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140863.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140863.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140863.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140863.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140863.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140863.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140863.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140863.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140863.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140863.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140863.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140864.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140864.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140864.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140864.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140864.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140864.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140864.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140864.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140864.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140864.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140864.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140864.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140864.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140864.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140864.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140864.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140864.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140864.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140864.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140864.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140865.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140865.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140865.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140865.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140865.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140865.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140865.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140865.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140865.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140865.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140865.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140865.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140865.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140865.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140865.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140865.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140866.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140866.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140866.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140866.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140866.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140866.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140866.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140866.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140866.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140866.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140866.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140866.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140866.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140866.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140866.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140866.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140866.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140867.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140867.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140867.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140867.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140867.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140867.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d8f0]
>[140867.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d8f0] width 1920 pitch 7680 (/4 1920)
>[140867.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140867.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140867.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320bd10]
>[140867.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320bd10] width 1920 pitch 7680 (/4 1920)
>[140867.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b530]
>[140867.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b530] width 1920 pitch 7680 (/4 1920)
>[140867.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140867.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140869.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140869.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140871.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357ac0]
>[140871.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357ac0] width 1920 pitch 7680 (/4 1920)
>[140871.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140871.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140871.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140871.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140871.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140871.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140871.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140871.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140871.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140871.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140872.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140872.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140872.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140872.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140872.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140872.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140872.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140872.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140873.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140873.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140873.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344170]
>[140873.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344170] width 1920 pitch 7680 (/4 1920)
>[140873.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140873.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140873.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140873.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140873.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106cd0]
>[140873.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106cd0] width 1920 pitch 7680 (/4 1920)
>[140873.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140873.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140873.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7aba0]
>[140873.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7aba0] width 1920 pitch 7680 (/4 1920)
>[140873.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[140873.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[140881.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2e90]
>[140881.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2e90] width 1920 pitch 7680 (/4 1920)
>[140890.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50652a0]
>[140890.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50652a0] width 1920 pitch 7680 (/4 1920)
>[140890.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f5e0]
>[140891.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f5e0] width 1920 pitch 7680 (/4 1920)
>[140894.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f60570]
>[140894.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f60570] width 1920 pitch 7680 (/4 1920)
>[140910.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50650b0]
>[140910.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50650b0] width 1920 pitch 7680 (/4 1920)
>[140934.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e5850]
>[140934.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e5850] width 1920 pitch 7680 (/4 1920)
>[140943.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068f20]
>[140943.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068f20] width 1920 pitch 7680 (/4 1920)
>[140945.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2edc0]
>[140945.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2edc0] width 1920 pitch 7680 (/4 1920)
>[140945.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e325e0]
>[140945.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e325e0] width 1920 pitch 7680 (/4 1920)
>[140945.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f478a0]
>[140945.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f478a0] width 1920 pitch 7680 (/4 1920)
>[140945.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96c70]
>[140945.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96c70] width 1920 pitch 7680 (/4 1920)
>[140945.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f478a0]
>[140945.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f478a0] width 1920 pitch 7680 (/4 1920)
>[140945.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f478a0]
>[140945.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f478a0] width 1920 pitch 7680 (/4 1920)
>[140945.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96c70]
>[140945.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96c70] width 1920 pitch 7680 (/4 1920)
>[140945.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94570]
>[140945.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94570] width 1920 pitch 7680 (/4 1920)
>[140945.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94570]
>[140945.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94570] width 1920 pitch 7680 (/4 1920)
>[140945.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87f00]
>[140945.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87f00] width 1920 pitch 7680 (/4 1920)
>[140945.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6760]
>[140945.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6760] width 1920 pitch 7680 (/4 1920)
>[140945.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e5690]
>[140945.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e5690] width 1920 pitch 7680 (/4 1920)
>[140945.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6760]
>[140945.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6760] width 1920 pitch 7680 (/4 1920)
>[140945.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e5690]
>[140945.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e5690] width 1920 pitch 7680 (/4 1920)
>[140945.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a6760]
>[140945.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a6760] width 1920 pitch 7680 (/4 1920)
>[140950.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106cd0]
>[140950.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106cd0] width 1920 pitch 7680 (/4 1920)
>[140950.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90dd0]
>[140950.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90dd0] width 1920 pitch 7680 (/4 1920)
>[140950.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140950.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140950.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90dd0]
>[140950.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90dd0] width 1920 pitch 7680 (/4 1920)
>[140950.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140950.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140959.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f197d0]
>[140959.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f197d0] width 1920 pitch 7680 (/4 1920)
>[140959.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103490]
>[140959.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103490] width 1920 pitch 7680 (/4 1920)
>[140962.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0640]
>[140962.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0640] width 1920 pitch 7680 (/4 1920)
>[140963.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b840]
>[140963.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b840] width 1920 pitch 7680 (/4 1920)
>[140963.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4cfa0]
>[140963.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4cfa0] width 1920 pitch 7680 (/4 1920)
>[140963.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e35890]
>[140963.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e35890] width 1920 pitch 7680 (/4 1920)
>[140963.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e35840]
>[140963.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e35840] width 1920 pitch 7680 (/4 1920)
>[140965.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366bf0]
>[140965.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366bf0] width 1920 pitch 7680 (/4 1920)
>[140967.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140967.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140967.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335aa30]
>[140967.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335aa30] width 1920 pitch 7680 (/4 1920)
>[140967.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f252a0]
>[140967.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f252a0] width 1920 pitch 7680 (/4 1920)
>[140967.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf760]
>[140967.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf760] width 1920 pitch 7680 (/4 1920)
>[140968.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33540a0]
>[140968.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33540a0] width 1920 pitch 7680 (/4 1920)
>[140968.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ff640]
>[140968.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ff640] width 1920 pitch 7680 (/4 1920)
>[140968.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e66830]
>[140968.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e66830] width 1920 pitch 7680 (/4 1920)
>[140968.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321d990]
>[140968.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321d990] width 1920 pitch 7680 (/4 1920)
>[140968.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c90180]
>[140968.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c90180] width 1920 pitch 7680 (/4 1920)
>[140976.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335aa30]
>[140976.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335aa30] width 1920 pitch 7680 (/4 1920)
>[140976.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00b60]
>[140976.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00b60] width 1920 pitch 7680 (/4 1920)
>[140989.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140989.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140989.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140989.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140989.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140989.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140989.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140989.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140989.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140989.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140989.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140989.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140989.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140989.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140989.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140989.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140990.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140990.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140990.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140990.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140990.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e48b60]
>[140990.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e48b60] width 1920 pitch 7680 (/4 1920)
>[140991.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25770]
>[140991.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25770] width 1920 pitch 7680 (/4 1920)
>[140991.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140991.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140991.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[140991.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[140991.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140991.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140991.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[140991.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[140991.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4edc080]
>[140991.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4edc080] width 1920 pitch 7680 (/4 1920)
>[140991.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e620e0]
>[140991.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e620e0] width 1920 pitch 7680 (/4 1920)
>[141004.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141004.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141004.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141004.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141004.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141004.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141004.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141004.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141004.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367150]
>[141004.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367150] width 1920 pitch 7680 (/4 1920)
>[141004.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141004.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141004.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367150]
>[141004.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367150] width 1920 pitch 7680 (/4 1920)
>[141005.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141005.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141005.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367150]
>[141005.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367150] width 1920 pitch 7680 (/4 1920)
>[141005.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141005.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141005.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367150]
>[141006.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367150] width 1920 pitch 7680 (/4 1920)
>[141006.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141006.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141006.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141006.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141006.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141006.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141006.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141006.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141006.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141006.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141006.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141006.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141006.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e43680]
>[141006.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e43680] width 1920 pitch 7680 (/4 1920)
>[141006.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32315b0]
>[141006.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32315b0] width 1920 pitch 7680 (/4 1920)
>[141020.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066510]
>[141020.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066510] width 1920 pitch 7680 (/4 1920)
>[141021.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141021.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141021.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f24010]
>[141021.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f24010] width 1920 pitch 7680 (/4 1920)
>[141021.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141021.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141021.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f24010]
>[141021.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f24010] width 1920 pitch 7680 (/4 1920)
>[141022.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141022.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141026.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141026.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141026.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506eac0]
>[141026.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506eac0] width 1920 pitch 7680 (/4 1920)
>[141026.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141026.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141026.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141026.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbc50]
>[141026.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbc50] width 1920 pitch 7680 (/4 1920)
>[141026.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec8c0]
>[141026.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec8c0] width 1920 pitch 7680 (/4 1920)
>[141027.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388dd0]
>[141027.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388dd0] width 1920 pitch 7680 (/4 1920)
>[141027.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388dd0]
>[141027.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388dd0] width 1920 pitch 7680 (/4 1920)
>[141027.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388dd0]
>[141027.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388dd0] width 1920 pitch 7680 (/4 1920)
>[141027.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef9e0]
>[141027.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef9e0] width 1920 pitch 7680 (/4 1920)
>[141027.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef9e0]
>[141027.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef9e0] width 1920 pitch 7680 (/4 1920)
>[141027.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef9e0]
>[141027.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef9e0] width 1920 pitch 7680 (/4 1920)
>[141027.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d71c50]
>[141027.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d71c50] width 1920 pitch 7680 (/4 1920)
>[141027.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076af0]
>[141027.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076af0] width 1920 pitch 7680 (/4 1920)
>[141031.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33783d0]
>[141031.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33783d0] width 1920 pitch 7680 (/4 1920)
>[141066.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec980]
>[141066.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec980] width 1920 pitch 7680 (/4 1920)
>[141087.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356be0]
>[141087.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356be0] width 1920 pitch 7680 (/4 1920)
>[141087.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141087.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141087.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141087.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141087.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141087.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141087.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141087.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141087.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141087.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141087.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141087.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141087.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141088.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141088.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141088.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141088.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141088.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141088.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141088.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141088.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141088.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141088.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141088.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141088.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca01b0]
>[141088.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca01b0] width 1920 pitch 7680 (/4 1920)
>[141088.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc240]
>[141088.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc240] width 1920 pitch 7680 (/4 1920)
>[141089.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141089.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141089.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141089.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141089.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62cf0]
>[141089.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62cf0] width 1920 pitch 7680 (/4 1920)
>[141089.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc8940]
>[141089.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc8940] width 1920 pitch 7680 (/4 1920)
>[141108.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3356be0]
>[141108.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3356be0] width 1920 pitch 7680 (/4 1920)
>[141111.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066ec0]
>[141111.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066ec0] width 1920 pitch 7680 (/4 1920)
>[141129.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e2de20]
>[141129.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e2de20] width 1920 pitch 7680 (/4 1920)
>[141142.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecd160]
>[141142.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecd160] width 1920 pitch 7680 (/4 1920)
>[141413.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd1c0]
>[141413.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd1c0] width 1920 pitch 7680 (/4 1920)
>[141430.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141430.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141430.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141430.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141430.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141430.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141430.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141430.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141430.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141430.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141430.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141431.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141431.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141431.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141431.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141431.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141431.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141431.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141431.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141431.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141432.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141432.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141432.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b62bc0]
>[141432.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b62bc0] width 1920 pitch 7680 (/4 1920)
>[141433.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141433.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141433.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f600]
>[141433.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f600] width 1920 pitch 7680 (/4 1920)
>[141433.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141433.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141433.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f600]
>[141433.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f600] width 1920 pitch 7680 (/4 1920)
>[141433.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141433.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141433.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f600]
>[141433.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f600] width 1920 pitch 7680 (/4 1920)
>[141433.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31f55a0]
>[141433.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31f55a0] width 1920 pitch 7680 (/4 1920)
>[141433.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f600]
>[141433.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f600] width 1920 pitch 7680 (/4 1920)
>[141741.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141742.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141742.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141742.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141742.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141742.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141742.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141742.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141742.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141742.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141742.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141742.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141742.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141742.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141742.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141742.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141742.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141743.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141743.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141743.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141743.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141743.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141743.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141743.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141743.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141743.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141743.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141744.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141744.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141745.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2eb0]
>[141745.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2eb0] width 1920 pitch 7680 (/4 1920)
>[141745.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08820]
>[141745.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08820] width 1920 pitch 7680 (/4 1920)
>[141745.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08880]
>[141745.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08880] width 1920 pitch 7680 (/4 1920)
>[141745.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08820]
>[141745.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08820] width 1920 pitch 7680 (/4 1920)
>[141745.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08880]
>[141745.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08880] width 1920 pitch 7680 (/4 1920)
>[141745.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08820]
>[141745.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08820] width 1920 pitch 7680 (/4 1920)
>[141745.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e950]
>[141745.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e950] width 1920 pitch 7680 (/4 1920)
>[141745.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08820]
>[141745.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08820] width 1920 pitch 7680 (/4 1920)
>[141745.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eea4b0]
>[141745.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eea4b0] width 1920 pitch 7680 (/4 1920)
>[141748.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bd0]
>[141748.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bd0] width 1920 pitch 7680 (/4 1920)
>[141752.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069a60]
>[141752.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069a60] width 1920 pitch 7680 (/4 1920)
>[141752.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e20]
>[141752.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e20] width 1920 pitch 7680 (/4 1920)
>[141755.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea1750]
>[141755.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea1750] width 1920 pitch 7680 (/4 1920)
>[141757.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e30]
>[141757.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e30] width 1920 pitch 7680 (/4 1920)
>[141757.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0e110]
>[141757.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0e110] width 1920 pitch 7680 (/4 1920)
>[141757.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcc0a0]
>[141757.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcc0a0] width 1920 pitch 7680 (/4 1920)
>[141757.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0e110]
>[141757.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0e110] width 1920 pitch 7680 (/4 1920)
>[141761.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f31de0]
>[141761.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f31de0] width 1920 pitch 7680 (/4 1920)
>[141764.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d1ac60]
>[141764.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d1ac60] width 1920 pitch 7680 (/4 1920)
>[141791.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7c010]
>[141791.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7c010] width 1920 pitch 7680 (/4 1920)
>[141857.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c11d50]
>[141857.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c11d50] width 1920 pitch 7680 (/4 1920)
>[141995.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141995.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141995.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141995.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141995.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141996.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141996.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141996.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141996.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141996.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141997.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141997.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141997.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141997.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141997.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141997.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141997.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141997.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141997.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141997.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141997.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141997.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x321f400]
>[141997.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x321f400] width 1920 pitch 7680 (/4 1920)
>[141997.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141997.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141998.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141998.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[141998.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9bf0]
>[141998.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9bf0] width 1920 pitch 7680 (/4 1920)
>[142085.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f386b0]
>[142085.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f386b0] width 1920 pitch 7680 (/4 1920)
>[142085.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f386b0]
>[142085.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f386b0] width 1920 pitch 7680 (/4 1920)
>[142085.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f386b0]
>[142085.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f386b0] width 1920 pitch 7680 (/4 1920)
>[142085.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f386b0]
>[142085.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f386b0] width 1920 pitch 7680 (/4 1920)
>[142085.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f386b0]
>[142085.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f386b0] width 1920 pitch 7680 (/4 1920)
>[142085.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5540]
>[142085.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5540] width 1920 pitch 7680 (/4 1920)
>[142085.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142085.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5540]
>[142085.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5540] width 1920 pitch 7680 (/4 1920)
>[142085.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b476c0]
>[142085.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b476c0] width 1920 pitch 7680 (/4 1920)
>[142087.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82e20]
>[142087.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82e20] width 1920 pitch 7680 (/4 1920)
>[142087.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c840e0]
>[142088.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c840e0] width 1920 pitch 7680 (/4 1920)
>[142088.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142088.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142089.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142089.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142089.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142089.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142089.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142089.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142089.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142089.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142089.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142091.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba320]
>[142091.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba320] width 1920 pitch 7680 (/4 1920)
>[142091.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069760]
>[142091.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069760] width 1920 pitch 7680 (/4 1920)
>[142091.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069760]
>[142091.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069760] width 1920 pitch 7680 (/4 1920)
>[142091.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba320]
>[142091.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba320] width 1920 pitch 7680 (/4 1920)
>[142091.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b47780]
>[142091.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b47780] width 1920 pitch 7680 (/4 1920)
>[142091.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142091.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142091.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b47780]
>[142091.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b47780] width 1920 pitch 7680 (/4 1920)
>[142091.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142091.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142091.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b47780]
>[142091.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b47780] width 1920 pitch 7680 (/4 1920)
>[142091.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142091.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142091.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b47780]
>[142091.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b47780] width 1920 pitch 7680 (/4 1920)
>[142092.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9e890]
>[142092.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9e890] width 1920 pitch 7680 (/4 1920)
>[142092.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f384f0]
>[142092.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f384f0] width 1920 pitch 7680 (/4 1920)
>[142092.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069760]
>[142092.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069760] width 1920 pitch 7680 (/4 1920)
>[142092.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba320]
>[142092.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba320] width 1920 pitch 7680 (/4 1920)
>[142092.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11780]
>[142093.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11780] width 1920 pitch 7680 (/4 1920)
>[142093.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba320]
>[142093.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba320] width 1920 pitch 7680 (/4 1920)
>[142093.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069760]
>[142093.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069760] width 1920 pitch 7680 (/4 1920)
>[142093.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142093.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142093.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142093.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142093.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c460]
>[142093.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c460] width 1920 pitch 7680 (/4 1920)
>[142093.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142093.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142093.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142093.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142093.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142093.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142093.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142093.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142093.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142095.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142095.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142095.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142095.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142095.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142095.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142095.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142095.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142095.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142095.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142095.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142095.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142095.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142095.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142095.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142095.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142095.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142095.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142096.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142096.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142096.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142096.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142096.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142096.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142096.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142096.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142096.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142096.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142097.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142097.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142097.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142097.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142097.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c189d0]
>[142097.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c189d0] width 1920 pitch 7680 (/4 1920)
>[142097.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c189d0]
>[142097.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c189d0] width 1920 pitch 7680 (/4 1920)
>[142097.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142097.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142097.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142097.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142097.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142097.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2ecf0]
>[142098.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2ecf0] width 1920 pitch 7680 (/4 1920)
>[142098.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d6d0]
>[142098.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d6d0] width 1920 pitch 7680 (/4 1920)
>[142098.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142098.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142098.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142098.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142098.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142098.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142098.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142098.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142098.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142098.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[142098.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[142098.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[142098.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[142099.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61550]
>[142099.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61550] width 1920 pitch 7680 (/4 1920)
>[142105.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142105.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142105.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142105.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142105.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142105.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142105.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142105.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142105.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142105.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142105.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142105.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142105.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142105.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142106.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142106.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142106.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142106.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142106.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142106.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142106.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142106.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142106.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142106.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142107.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142107.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142107.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142107.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142107.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142107.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142107.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142107.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142107.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142107.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142107.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142107.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142107.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142107.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142110.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142110.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142110.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142110.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142111.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142111.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142111.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142111.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142111.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142111.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142111.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142111.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142111.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142111.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142111.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142111.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142111.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142111.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142111.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142111.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142111.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142111.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142111.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142111.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142112.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142112.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142112.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142112.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142113.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103680]
>[142113.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103680] width 1920 pitch 7680 (/4 1920)
>[142114.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142114.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142114.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5240]
>[142114.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5240] width 1920 pitch 7680 (/4 1920)
>[142114.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142114.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142114.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5240]
>[142114.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5240] width 1920 pitch 7680 (/4 1920)
>[142114.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142114.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142114.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5240]
>[142114.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5240] width 1920 pitch 7680 (/4 1920)
>[142114.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142114.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142121.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f8a0]
>[142121.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f8a0] width 1920 pitch 7680 (/4 1920)
>[142133.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507d2f0]
>[142133.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507d2f0] width 1920 pitch 7680 (/4 1920)
>[142138.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142138.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142139.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142139.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142139.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142139.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142139.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142139.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142139.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142139.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142139.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142139.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142139.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142139.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142139.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142139.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142139.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142139.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142139.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142140.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142140.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103f90]
>[142140.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103f90] width 1920 pitch 7680 (/4 1920)
>[142140.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142140.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142140.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9faa0]
>[142141.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9faa0] width 1920 pitch 7680 (/4 1920)
>[142141.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3365860]
>[142141.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3365860] width 1920 pitch 7680 (/4 1920)
>[142141.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142141.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142141.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142141.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142141.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142141.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142141.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103390]
>[142141.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103390] width 1920 pitch 7680 (/4 1920)
>[142150.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b371e0]
>[142150.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b371e0] width 1920 pitch 7680 (/4 1920)
>[142154.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142154.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142157.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142157.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142157.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142157.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142157.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142157.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142157.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142157.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142157.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142157.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142157.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142157.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142157.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142157.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142157.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142157.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142157.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142157.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142158.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142158.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142158.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142158.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142158.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142158.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142158.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cbd0]
>[142158.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cbd0] width 1920 pitch 7680 (/4 1920)
>[142159.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142159.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142159.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61200]
>[142159.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61200] width 1920 pitch 7680 (/4 1920)
>[142159.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37f70]
>[142159.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37f70] width 1920 pitch 7680 (/4 1920)
>[142159.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61200]
>[142159.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61200] width 1920 pitch 7680 (/4 1920)
>[142159.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37f70]
>[142159.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37f70] width 1920 pitch 7680 (/4 1920)
>[142159.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61200]
>[142159.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61200] width 1920 pitch 7680 (/4 1920)
>[142159.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37f70]
>[142159.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37f70] width 1920 pitch 7680 (/4 1920)
>[142159.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142159.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142172.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142172.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142172.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142172.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142172.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142172.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142172.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142172.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142172.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142172.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142172.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142172.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142172.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142172.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142172.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[142172.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[142172.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142172.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142173.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142173.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142173.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61200]
>[142173.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61200] width 1920 pitch 7680 (/4 1920)
>[142173.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142173.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142173.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61200]
>[142173.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61200] width 1920 pitch 7680 (/4 1920)
>[142173.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142173.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142173.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142173.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142173.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142173.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142173.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142173.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142173.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142173.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142173.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142173.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142173.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142173.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142173.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46d00]
>[142173.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46d00] width 1920 pitch 7680 (/4 1920)
>[142175.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142175.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142175.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142175.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142175.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142175.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142175.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142175.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142175.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[142175.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[142175.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142175.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142175.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142175.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142175.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142176.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142176.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142176.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142176.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142176.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142176.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142176.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142176.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142176.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142176.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142177.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142177.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142177.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142177.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035e0]
>[142177.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035e0] width 1920 pitch 7680 (/4 1920)
>[142177.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328caf0]
>[142177.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328caf0] width 1920 pitch 7680 (/4 1920)
>[142177.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142177.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142177.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcf910]
>[142177.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcf910] width 1920 pitch 7680 (/4 1920)
>[142193.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43d60]
>[142193.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43d60] width 1920 pitch 7680 (/4 1920)
>[142194.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142194.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142194.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142194.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142194.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142194.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee70a0]
>[142194.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee70a0] width 1920 pitch 7680 (/4 1920)
>[142194.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9ae0]
>[142194.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9ae0] width 1920 pitch 7680 (/4 1920)
>[142195.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3343400]
>[142195.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3343400] width 1920 pitch 7680 (/4 1920)
>[142195.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6b80]
>[142195.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6b80] width 1920 pitch 7680 (/4 1920)
>[142196.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06ee0]
>[142196.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06ee0] width 1920 pitch 7680 (/4 1920)
>[142196.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142196.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f35f0]
>[142196.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f35f0] width 1920 pitch 7680 (/4 1920)
>[142196.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142196.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142200.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142200.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142200.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e5cc0]
>[142200.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e5cc0] width 1920 pitch 7680 (/4 1920)
>[142204.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e5cc0]
>[142204.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e5cc0] width 1920 pitch 7680 (/4 1920)
>[142204.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142204.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142209.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[142209.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[142209.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[142209.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[142280.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06ee0]
>[142280.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06ee0] width 1920 pitch 7680 (/4 1920)
>[142280.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142280.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[142356.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[142356.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[142356.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[142356.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[143850.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[143850.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[143850.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e5cc0]
>[143850.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e5cc0] width 1920 pitch 7680 (/4 1920)
>[143850.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[143850.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[143850.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068940]
>[143850.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068940] width 1920 pitch 7680 (/4 1920)
>[143850.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06ee0]
>[143850.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06ee0] width 1920 pitch 7680 (/4 1920)
>[143850.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068940]
>[143850.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068940] width 1920 pitch 7680 (/4 1920)
>[143850.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06ee0]
>[143850.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06ee0] width 1920 pitch 7680 (/4 1920)
>[143850.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068940]
>[143850.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068940] width 1920 pitch 7680 (/4 1920)
>[143850.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e5cc0]
>[143850.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e5cc0] width 1920 pitch 7680 (/4 1920)
>[143854.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36130]
>[143854.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36130] width 1920 pitch 7680 (/4 1920)
>[143854.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143854.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143854.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcf8f0]
>[143854.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcf8f0] width 1920 pitch 7680 (/4 1920)
>[143854.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94480]
>[143854.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94480] width 1920 pitch 7680 (/4 1920)
>[143854.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143854.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143854.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143854.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143854.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143854.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143854.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143854.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143854.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143855.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143855.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143855.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143855.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143855.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143855.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdd00]
>[143855.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdd00] width 1920 pitch 7680 (/4 1920)
>[143855.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143855.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143855.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143855.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143855.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143855.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143855.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143855.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143855.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143855.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143855.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143855.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143855.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143856.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143856.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143856.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143856.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143856.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[143860.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[143860.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[143860.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[143860.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144467.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066200]
>[144467.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066200] width 1920 pitch 7680 (/4 1920)
>[144467.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf0250]
>[144467.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf0250] width 1920 pitch 7680 (/4 1920)
>[144468.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144468.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144468.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144468.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144468.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144468.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144468.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144468.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144468.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144468.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144468.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144468.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144468.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144468.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144468.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144468.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144468.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144468.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144468.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144468.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144469.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144469.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144469.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144469.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144469.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144469.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144469.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144469.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144469.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144469.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144470.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144470.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144470.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144470.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144470.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144470.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144470.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144470.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144470.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144470.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144470.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144470.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144470.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d770]
>[144470.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d770] width 1920 pitch 7680 (/4 1920)
>[144470.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144470.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144471.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144471.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144471.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144471.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[144471.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[144471.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b536f0]
>[144471.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b536f0] width 1920 pitch 7680 (/4 1920)
>[144570.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f614f0]
>[144570.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f614f0] width 1920 pitch 7680 (/4 1920)
>[144719.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[144719.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[144749.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11800]
>[144749.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11800] width 1920 pitch 7680 (/4 1920)
>[144804.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144804.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144805.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36170]
>[144805.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36170] width 1920 pitch 7680 (/4 1920)
>[144805.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36170]
>[144805.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36170] width 1920 pitch 7680 (/4 1920)
>[144805.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36170]
>[144805.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36170] width 1920 pitch 7680 (/4 1920)
>[144805.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144805.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144805.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144805.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144805.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144805.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144805.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee10]
>[144805.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee10] width 1920 pitch 7680 (/4 1920)
>[144805.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144805.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144808.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144808.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144808.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144808.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144809.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144809.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144809.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32efa40]
>[144809.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32efa40] width 1920 pitch 7680 (/4 1920)
>[144836.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[144836.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[144836.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[144836.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[144949.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e39510]
>[144949.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e39510] width 1920 pitch 7680 (/4 1920)
>[145217.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3fe70]
>[145217.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3fe70] width 1920 pitch 7680 (/4 1920)
>[145217.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145217.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145217.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145217.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145217.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145217.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145217.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145217.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145217.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145217.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145217.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145217.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145217.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145217.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145217.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145217.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145217.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145218.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145218.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145218.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145218.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145218.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145218.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145218.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145218.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ff20]
>[145218.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ff20] width 1920 pitch 7680 (/4 1920)
>[145218.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145218.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145222.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145222.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145222.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bca4b0]
>[145222.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bca4b0] width 1920 pitch 7680 (/4 1920)
>[145226.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145226.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145227.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145227.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145247.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145247.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145247.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145247.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145247.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145247.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145247.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145247.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145247.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145247.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145247.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145247.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145247.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145247.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145247.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145247.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145247.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145247.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145248.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145248.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145248.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145248.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145248.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145248.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145248.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145248.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145248.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145248.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145248.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145249.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145249.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145249.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145249.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145249.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145249.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145249.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145250.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba2e50]
>[145250.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba2e50] width 1920 pitch 7680 (/4 1920)
>[145250.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145250.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145250.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145250.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145250.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc560]
>[145250.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc560] width 1920 pitch 7680 (/4 1920)
>[145251.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145251.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145251.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc560]
>[145251.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc560] width 1920 pitch 7680 (/4 1920)
>[145251.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145251.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145251.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc560]
>[145251.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc560] width 1920 pitch 7680 (/4 1920)
>[145251.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe1c0]
>[145251.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe1c0] width 1920 pitch 7680 (/4 1920)
>[145259.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f38700]
>[145259.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f38700] width 1920 pitch 7680 (/4 1920)
>[145260.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f38700]
>[145260.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f38700] width 1920 pitch 7680 (/4 1920)
>[145260.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb9940]
>[145260.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb9940] width 1920 pitch 7680 (/4 1920)
>[145260.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324e500]
>[145260.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324e500] width 1920 pitch 7680 (/4 1920)
>[145260.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f188b0]
>[145260.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f188b0] width 1920 pitch 7680 (/4 1920)
>[145260.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f38700]
>[145260.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f38700] width 1920 pitch 7680 (/4 1920)
>[145260.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f188f0]
>[145260.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f188f0] width 1920 pitch 7680 (/4 1920)
>[145260.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e86340]
>[145260.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e86340] width 1920 pitch 7680 (/4 1920)
>[145260.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f188f0]
>[145260.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f188f0] width 1920 pitch 7680 (/4 1920)
>[145260.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e86340]
>[145260.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e86340] width 1920 pitch 7680 (/4 1920)
>[145260.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f188f0]
>[145260.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f188f0] width 1920 pitch 7680 (/4 1920)
>[145260.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e86340]
>[145260.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e86340] width 1920 pitch 7680 (/4 1920)
>[145260.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f188f0]
>[145260.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f188f0] width 1920 pitch 7680 (/4 1920)
>[145260.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e86340]
>[145260.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e86340] width 1920 pitch 7680 (/4 1920)
>[145265.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145265.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145265.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145265.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145265.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145265.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145265.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145265.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145265.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145265.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145265.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145265.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145265.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145266.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145266.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145266.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145266.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145266.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145266.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145266.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145266.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145266.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145266.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145266.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145266.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b46f10]
>[145266.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b46f10] width 1920 pitch 7680 (/4 1920)
>[145266.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[145266.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1920 pitch 7680 (/4 1920)
>[145273.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145273.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145273.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145273.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145273.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145273.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145273.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145273.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145273.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145273.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145273.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145273.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145273.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145273.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145274.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145274.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145274.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145274.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145274.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145274.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145274.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e87280]
>[145274.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e87280] width 1920 pitch 7680 (/4 1920)
>[145274.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eb30]
>[145274.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eb30] width 1920 pitch 7680 (/4 1920)
>[145274.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145274.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145274.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eb30]
>[145274.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eb30] width 1920 pitch 7680 (/4 1920)
>[145274.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145274.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145274.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145274.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145274.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145274.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145275.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145275.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145275.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145275.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145293.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc9f80]
>[145293.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc9f80] width 1920 pitch 7680 (/4 1920)
>[145383.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145383.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145383.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145383.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145383.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145383.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145383.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145383.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145383.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145383.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145383.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145383.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145383.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145383.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145383.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145383.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145383.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145383.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145384.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145384.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145384.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afec0]
>[145384.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afec0] width 1920 pitch 7680 (/4 1920)
>[145384.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145384.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145384.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145384.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145384.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145384.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145384.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145384.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145384.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145384.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145384.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145384.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145384.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145384.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145456.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145456.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145456.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145456.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145499.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145499.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145499.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145499.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145499.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145499.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145499.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145499.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145499.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145499.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145499.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145499.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145499.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145500.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145500.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145500.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145500.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145500.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145500.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145500.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145500.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145500.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145501.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145501.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145501.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145501.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145501.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475da90]
>[145501.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475da90] width 1920 pitch 7680 (/4 1920)
>[145501.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145501.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145501.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145501.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145501.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145501.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145501.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145501.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145501.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf17a0]
>[145501.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf17a0] width 1920 pitch 7680 (/4 1920)
>[145501.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145501.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145501.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10b60]
>[145501.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10b60] width 1920 pitch 7680 (/4 1920)
>[145501.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c13c30]
>[145501.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c13c30] width 1920 pitch 7680 (/4 1920)
>[145501.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145501.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145501.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c13c30]
>[145501.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c13c30] width 1920 pitch 7680 (/4 1920)
>[145501.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145501.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145502.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49e30]
>[145502.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49e30] width 1920 pitch 7680 (/4 1920)
>[145506.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145506.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145506.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145507.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145507.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145507.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322c3b0]
>[145507.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322c3b0] width 1920 pitch 7680 (/4 1920)
>[145669.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[145669.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[145826.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f06360]
>[145826.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f06360] width 1920 pitch 7680 (/4 1920)
>[145826.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145826.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145826.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f06360]
>[145827.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f06360] width 1920 pitch 7680 (/4 1920)
>[145827.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b1e0]
>[145827.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b1e0] width 1920 pitch 7680 (/4 1920)
>[145827.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145827.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145827.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145827.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145827.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145827.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145827.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145827.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145827.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145827.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145827.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145827.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145827.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145827.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145827.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145827.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145827.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145828.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145828.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145828.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145828.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336ef70]
>[145828.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336ef70] width 1920 pitch 7680 (/4 1920)
>[145828.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145828.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145828.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336ef70]
>[145828.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336ef70] width 1920 pitch 7680 (/4 1920)
>[145828.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c83f10]
>[145828.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c83f10] width 1920 pitch 7680 (/4 1920)
>[145828.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336ef70]
>[145828.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336ef70] width 1920 pitch 7680 (/4 1920)
>[145828.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145828.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145846.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145846.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145846.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea16a0]
>[145846.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea16a0] width 1920 pitch 7680 (/4 1920)
>[145846.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145847.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145847.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145847.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145847.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145847.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145847.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145847.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145847.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145847.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145847.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145847.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145847.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145848.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145848.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145848.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145848.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145848.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145848.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc220]
>[145848.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc220] width 1920 pitch 7680 (/4 1920)
>[145849.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51019c0]
>[145849.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51019c0] width 1920 pitch 7680 (/4 1920)
>[145849.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0680]
>[145849.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0680] width 1920 pitch 7680 (/4 1920)
>[145849.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb61c0]
>[145849.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb61c0] width 1920 pitch 7680 (/4 1920)
>[145849.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0680]
>[145849.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0680] width 1920 pitch 7680 (/4 1920)
>[145849.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb61c0]
>[145849.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb61c0] width 1920 pitch 7680 (/4 1920)
>[145849.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0680]
>[145849.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0680] width 1920 pitch 7680 (/4 1920)
>[145849.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb61c0]
>[145849.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb61c0] width 1920 pitch 7680 (/4 1920)
>[145849.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0680]
>[145849.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0680] width 1920 pitch 7680 (/4 1920)
>[146108.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322b770]
>[146108.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322b770] width 1920 pitch 7680 (/4 1920)
>[146109.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146109.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb5260]
>[146109.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb5260] width 1920 pitch 7680 (/4 1920)
>[146109.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146109.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146113.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e940]
>[146113.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e940] width 1920 pitch 7680 (/4 1920)
>[146113.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1180]
>[146113.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1180] width 1920 pitch 7680 (/4 1920)
>[146163.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068fb0]
>[146164.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068fb0] width 1920 pitch 7680 (/4 1920)
>[146164.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5fe40]
>[146164.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5fe40] width 1920 pitch 7680 (/4 1920)
>[146164.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0920]
>[146164.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0920] width 1920 pitch 7680 (/4 1920)
>[146165.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb61b0]
>[146165.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb61b0] width 1920 pitch 7680 (/4 1920)
>[146168.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb61b0]
>[146168.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb61b0] width 1920 pitch 7680 (/4 1920)
>[146168.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146168.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146168.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146168.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5108950]
>[146168.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5108950] width 1920 pitch 7680 (/4 1920)
>[146459.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e960]
>[146459.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e960] width 1920 pitch 7680 (/4 1920)
>[146841.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[146841.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[146841.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146841.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146841.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[146841.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[146841.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed320]
>[146841.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed320] width 1920 pitch 7680 (/4 1920)
>[146841.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146841.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146841.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed320]
>[146841.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed320] width 1920 pitch 7680 (/4 1920)
>[146841.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146841.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146841.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed320]
>[146841.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed320] width 1920 pitch 7680 (/4 1920)
>[146841.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146841.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146841.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed320]
>[146841.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed320] width 1920 pitch 7680 (/4 1920)
>[146841.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[146841.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[146845.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146845.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146845.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146845.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146845.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146864.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146864.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146864.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146864.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146864.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146864.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146864.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146864.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146864.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146865.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146865.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146865.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146865.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146865.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146865.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146865.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146865.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146865.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146865.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146865.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146865.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146865.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146865.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146865.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146869.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146869.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146869.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146869.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146904.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146904.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146904.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146904.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146908.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146908.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146908.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146908.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146908.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146908.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146908.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146908.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146908.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146908.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146908.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146908.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146908.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146908.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146908.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146909.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146909.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146909.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146909.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146909.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146909.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146909.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[146909.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[146909.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[146909.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[146909.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147059.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147059.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147059.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147059.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147059.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147059.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147059.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147059.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147063.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147063.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147063.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147063.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147075.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147075.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147075.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147075.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147079.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147079.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147079.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147079.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147234.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147234.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147234.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147234.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147234.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147234.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147234.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147234.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147234.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147234.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147238.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147238.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147238.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147238.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147241.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147241.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147241.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147241.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147241.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147241.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147241.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147241.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147242.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147242.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147242.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147242.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147242.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147242.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147242.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147242.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147242.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147243.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147243.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147243.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147243.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147243.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147243.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6f10]
>[147244.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6f10] width 1920 pitch 7680 (/4 1920)
>[147244.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147244.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147244.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147244.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147244.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147244.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147244.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147244.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147244.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147244.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147244.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147328.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147328.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147328.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147328.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147328.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147328.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147328.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147328.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147328.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147328.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147328.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147328.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147328.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0930]
>[147328.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0930] width 1920 pitch 7680 (/4 1920)
>[147329.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147329.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147329.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147329.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147329.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147329.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147329.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147329.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147329.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147329.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147330.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147330.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147330.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147330.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147330.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147330.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147331.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147331.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147331.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506cdc0]
>[147331.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506cdc0] width 1920 pitch 7680 (/4 1920)
>[147331.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147331.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147331.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506cdc0]
>[147331.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506cdc0] width 1920 pitch 7680 (/4 1920)
>[147331.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92160]
>[147331.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92160] width 1920 pitch 7680 (/4 1920)
>[147331.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0b50]
>[147331.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0b50] width 1920 pitch 7680 (/4 1920)
>[147331.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506cdc0]
>[147331.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506cdc0] width 1920 pitch 7680 (/4 1920)
>[147343.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147343.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b460]
>[147343.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b460] width 1920 pitch 7680 (/4 1920)
>[147343.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10da0]
>[147343.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10da0] width 1920 pitch 7680 (/4 1920)
>[147345.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506cdc0]
>[147345.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506cdc0] width 1920 pitch 7680 (/4 1920)
>[147346.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507c400]
>[147346.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507c400] width 1920 pitch 7680 (/4 1920)
>[147346.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589f60]
>[147346.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589f60] width 1920 pitch 7680 (/4 1920)
>[147346.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b060]
>[147346.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b060] width 1920 pitch 7680 (/4 1920)
>[147346.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101a40]
>[147346.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101a40] width 1920 pitch 7680 (/4 1920)
>[147346.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50791b0]
>[147346.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50791b0] width 1920 pitch 7680 (/4 1920)
>[147346.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b060]
>[147346.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b060] width 1920 pitch 7680 (/4 1920)
>[147346.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101a40]
>[147346.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101a40] width 1920 pitch 7680 (/4 1920)
>[147346.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b03250]
>[147346.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b03250] width 1920 pitch 7680 (/4 1920)
>[147346.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b060]
>[147346.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b060] width 1920 pitch 7680 (/4 1920)
>[147346.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101a40]
>[147346.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101a40] width 1920 pitch 7680 (/4 1920)
>[147346.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51066b0]
>[147346.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51066b0] width 1920 pitch 7680 (/4 1920)
>[147359.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b060]
>[147359.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b060] width 1920 pitch 7680 (/4 1920)
>[147397.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147397.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147397.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147397.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147397.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147397.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147397.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147397.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147397.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147397.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147397.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147397.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147397.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147397.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147397.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147397.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147397.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147398.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147398.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147398.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147398.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147398.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147398.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147398.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147398.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505f6e0]
>[147398.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505f6e0] width 1920 pitch 7680 (/4 1920)
>[147398.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147398.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147398.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147398.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147402.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147402.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147402.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32104d0]
>[147402.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32104d0] width 1920 pitch 7680 (/4 1920)
>[147403.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147403.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147403.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147403.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147403.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147403.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147403.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147403.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147403.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147403.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147403.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147403.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147403.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147403.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147403.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147403.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147403.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147403.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147403.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147403.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147404.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147404.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147404.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147404.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147404.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147404.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147404.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147404.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147404.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147404.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147404.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147404.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147404.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147404.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147404.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147404.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147404.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147404.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147404.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147404.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147404.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147404.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147404.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147404.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147404.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147404.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147404.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85350]
>[147404.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85350] width 1920 pitch 7680 (/4 1920)
>[147412.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147412.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147412.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147412.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147425.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147425.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147425.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcbac0]
>[147425.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcbac0] width 1920 pitch 7680 (/4 1920)
>[147438.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85300]
>[147438.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85300] width 1920 pitch 7680 (/4 1920)
>[147439.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147439.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147463.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147463.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147463.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147463.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147466.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147466.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147476.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85c80]
>[147476.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85c80] width 1920 pitch 7680 (/4 1920)
>[147476.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147476.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147476.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147476.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147476.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147476.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147476.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85c80]
>[147476.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85c80] width 1920 pitch 7680 (/4 1920)
>[147476.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147476.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147476.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147476.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147476.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147476.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147476.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85c80]
>[147476.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85c80] width 1920 pitch 7680 (/4 1920)
>[147476.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147476.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147476.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147476.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147476.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85c80]
>[147476.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85c80] width 1920 pitch 7680 (/4 1920)
>[147476.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147476.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147476.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147476.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147480.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147480.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147481.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147481.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147481.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147481.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147481.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32104d0]
>[147481.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32104d0] width 1920 pitch 7680 (/4 1920)
>[147481.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10550]
>[147481.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10550] width 1920 pitch 7680 (/4 1920)
>[147481.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147481.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147481.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10550]
>[147481.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10550] width 1920 pitch 7680 (/4 1920)
>[147481.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147481.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147481.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147482.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147482.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e851d0]
>[147482.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e851d0] width 1920 pitch 7680 (/4 1920)
>[147482.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147482.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147482.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10550]
>[147482.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10550] width 1920 pitch 7680 (/4 1920)
>[147490.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147490.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147491.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147491.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147491.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147491.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147491.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147491.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147491.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147491.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147491.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147491.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147491.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147491.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147491.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147491.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147491.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147491.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147491.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147491.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147491.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147491.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147491.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147491.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147491.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147491.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147491.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147491.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147491.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147491.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147491.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147491.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147495.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147495.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147495.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147495.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147495.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147495.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147495.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147495.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147495.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147495.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147495.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147495.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147495.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147495.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147495.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147495.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147495.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147495.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147495.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147495.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147495.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147495.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147495.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147495.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147495.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147495.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147556.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147556.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147557.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147557.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147557.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147557.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147557.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59210]
>[147557.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59210] width 1920 pitch 7680 (/4 1920)
>[147557.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147557.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147557.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147557.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147557.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147557.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147557.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147557.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147557.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147557.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147557.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147557.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147557.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59210]
>[147557.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59210] width 1920 pitch 7680 (/4 1920)
>[147557.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147557.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147557.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147557.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147557.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147557.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147557.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147557.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147557.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147557.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147561.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147561.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147561.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147561.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147561.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147561.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147561.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147561.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147561.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147561.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147561.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147561.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147561.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9fb60]
>[147561.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9fb60] width 1920 pitch 7680 (/4 1920)
>[147561.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8820]
>[147561.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8820] width 1920 pitch 7680 (/4 1920)
>[147561.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147561.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147561.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147561.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147561.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147561.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147561.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147561.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147561.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147561.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147591.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147591.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147597.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147597.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147651.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147651.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147652.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147652.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147652.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147652.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147656.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147656.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147656.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147656.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587e20]
>[147656.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587e20] width 1920 pitch 7680 (/4 1920)
>[147656.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147656.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147656.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147656.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147656.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147656.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147656.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb580]
>[147656.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb580] width 1920 pitch 7680 (/4 1920)
>[147670.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147670.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147670.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147670.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147670.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147670.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147670.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147670.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147670.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147670.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147670.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147670.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147670.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147671.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147671.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147671.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147675.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147675.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147675.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147675.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147675.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147675.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147675.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147675.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147697.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147697.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147697.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e85330]
>[147697.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e85330] width 1920 pitch 7680 (/4 1920)
>[147697.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147697.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147697.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147697.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147697.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147697.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147697.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147697.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147697.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147701.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147701.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147701.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147701.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10310]
>[147701.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10310] width 1920 pitch 7680 (/4 1920)
>[147701.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147701.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147701.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147701.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147701.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147701.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147701.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd420]
>[147701.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd420] width 1920 pitch 7680 (/4 1920)
>[147701.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147701.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147701.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65ce0]
>[147701.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65ce0] width 1920 pitch 7680 (/4 1920)
>[147702.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147702.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147702.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147702.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147702.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147702.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147702.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147702.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59600]
>[147702.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59600] width 1920 pitch 7680 (/4 1920)
>[147702.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d650a0]
>[147702.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d650a0] width 1920 pitch 7680 (/4 1920)
>[147702.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147702.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147702.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9f570]
>[147702.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9f570] width 1920 pitch 7680 (/4 1920)
>[147702.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147702.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147703.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147703.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147703.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147703.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147703.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147703.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147703.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59600]
>[147703.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59600] width 1920 pitch 7680 (/4 1920)
>[147703.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147703.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147703.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147703.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147703.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147703.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147703.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147703.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147704.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147704.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147704.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147704.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147704.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147704.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147704.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147704.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147704.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bba3c0]
>[147704.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bba3c0] width 1920 pitch 7680 (/4 1920)
>[147704.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147704.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147704.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147704.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147704.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147704.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147704.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bba3c0]
>[147704.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bba3c0] width 1920 pitch 7680 (/4 1920)
>[147704.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147704.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147706.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147706.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147706.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bba3c0]
>[147706.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bba3c0] width 1920 pitch 7680 (/4 1920)
>[147706.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147706.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147706.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147706.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147706.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147706.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147706.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147706.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147706.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bba3c0]
>[147706.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bba3c0] width 1920 pitch 7680 (/4 1920)
>[147706.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147706.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147706.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147707.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147707.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147707.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147707.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bba3c0]
>[147707.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bba3c0] width 1920 pitch 7680 (/4 1920)
>[147707.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147707.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147707.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147707.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147707.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb340]
>[147707.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb340] width 1920 pitch 7680 (/4 1920)
>[147729.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147729.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147730.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147730.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147730.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147730.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147730.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59070]
>[147730.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59070] width 1920 pitch 7680 (/4 1920)
>[147730.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147730.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147730.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147730.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147730.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147730.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147730.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147730.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147730.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147730.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147730.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147730.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147731.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147731.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147731.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb9ce0]
>[147731.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb9ce0] width 1920 pitch 7680 (/4 1920)
>[147731.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd9c0]
>[147731.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd9c0] width 1920 pitch 7680 (/4 1920)
>[147731.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147731.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147731.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147731.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147732.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147732.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147732.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147732.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147732.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147732.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147732.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147732.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147732.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[147732.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[147732.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147732.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147732.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147732.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147732.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bb20]
>[147732.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bb20] width 1920 pitch 7680 (/4 1920)
>[147732.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb9ce0]
>[147732.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb9ce0] width 1920 pitch 7680 (/4 1920)
>[147792.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d64800]
>[147792.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d64800] width 1920 pitch 7680 (/4 1920)
>[147792.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d60ce0]
>[147792.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d60ce0] width 1920 pitch 7680 (/4 1920)
>[147792.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5078e30]
>[147792.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5078e30] width 1920 pitch 7680 (/4 1920)
>[147792.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147792.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147792.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d60ce0]
>[147792.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d60ce0] width 1920 pitch 7680 (/4 1920)
>[147792.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147793.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147793.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5078e30]
>[147793.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5078e30] width 1920 pitch 7680 (/4 1920)
>[147793.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d60ce0]
>[147793.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d60ce0] width 1920 pitch 7680 (/4 1920)
>[147793.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147793.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147793.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147793.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147793.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147793.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147793.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147793.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147793.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147793.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147793.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147793.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147793.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147793.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147796.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147796.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147797.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca3f10]
>[147797.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca3f10] width 1920 pitch 7680 (/4 1920)
>[147875.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147875.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147875.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147875.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147875.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147875.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147875.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e520]
>[147875.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e520] width 1920 pitch 7680 (/4 1920)
>[147875.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147875.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147875.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147875.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147875.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147875.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147875.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e520]
>[147875.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e520] width 1920 pitch 7680 (/4 1920)
>[147875.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147875.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147875.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147876.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147876.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a80]
>[147876.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a80] width 1920 pitch 7680 (/4 1920)
>[147876.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e520]
>[147876.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e520] width 1920 pitch 7680 (/4 1920)
>[147876.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147876.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147876.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101c60]
>[147876.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101c60] width 1920 pitch 7680 (/4 1920)
>[147926.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20b40]
>[147926.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20b40] width 1920 pitch 7680 (/4 1920)
>[147926.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147927.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147927.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147927.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[147927.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc6c30]
>[147927.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc6c30] width 1920 pitch 7680 (/4 1920)
>[147927.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20b40]
>[147927.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20b40] width 1920 pitch 7680 (/4 1920)
>[147927.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147927.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147927.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147927.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[147927.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc6c30]
>[147927.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc6c30] width 1920 pitch 7680 (/4 1920)
>[147927.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20b40]
>[147927.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20b40] width 1920 pitch 7680 (/4 1920)
>[147927.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147927.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147927.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc6c30]
>[147927.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc6c30] width 1920 pitch 7680 (/4 1920)
>[147927.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20b40]
>[147927.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20b40] width 1920 pitch 7680 (/4 1920)
>[147927.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83fa0]
>[147927.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83fa0] width 1920 pitch 7680 (/4 1920)
>[147927.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc6c30]
>[147927.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc6c30] width 1920 pitch 7680 (/4 1920)
>[147927.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20b40]
>[147927.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20b40] width 1920 pitch 7680 (/4 1920)
>[147930.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d645b0]
>[147930.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d645b0] width 1920 pitch 7680 (/4 1920)
>[147930.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d645b0]
>[147930.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d645b0] width 1920 pitch 7680 (/4 1920)
>[147931.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2670]
>[147931.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2670] width 1920 pitch 7680 (/4 1920)
>[147931.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2670]
>[147931.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2670] width 1920 pitch 7680 (/4 1920)
>[147931.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147931.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147931.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147931.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147931.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147931.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[147931.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d645b0]
>[147931.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d645b0] width 1920 pitch 7680 (/4 1920)
>[147931.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147931.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147931.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147931.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[147931.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d645b0]
>[147931.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d645b0] width 1920 pitch 7680 (/4 1920)
>[147931.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147931.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147931.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147931.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[147931.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d645b0]
>[147931.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d645b0] width 1920 pitch 7680 (/4 1920)
>[147931.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33796f0]
>[147931.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33796f0] width 1920 pitch 7680 (/4 1920)
>[147931.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9c8d0]
>[147931.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9c8d0] width 1920 pitch 7680 (/4 1920)
>[148206.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb3310]
>[148206.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb3310] width 1920 pitch 7680 (/4 1920)
>[148206.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d64650]
>[148206.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d64650] width 1920 pitch 7680 (/4 1920)
>[148207.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353870]
>[148207.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353870] width 1920 pitch 7680 (/4 1920)
>[148366.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced1b0]
>[148366.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced1b0] width 1920 pitch 7680 (/4 1920)
>[148366.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced130]
>[148366.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced130] width 1920 pitch 7680 (/4 1920)
>[148366.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148366.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148366.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced130]
>[148366.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced130] width 1920 pitch 7680 (/4 1920)
>[148366.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148366.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148366.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced1a0]
>[148366.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced1a0] width 1920 pitch 7680 (/4 1920)
>[148366.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148366.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148366.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ced1a0]
>[148366.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ced1a0] width 1920 pitch 7680 (/4 1920)
>[148368.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148368.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148368.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2c90]
>[148368.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2c90] width 1920 pitch 7680 (/4 1920)
>[148368.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2930]
>[148369.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2930] width 1920 pitch 7680 (/4 1920)
>[148369.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2b60]
>[148369.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2b60] width 1920 pitch 7680 (/4 1920)
>[148369.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca2b60]
>[148369.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca2b60] width 1920 pitch 7680 (/4 1920)
>[148369.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffca0]
>[148369.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffca0] width 1920 pitch 7680 (/4 1920)
>[148369.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148369.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148369.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d509e0]
>[148369.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d509e0] width 1920 pitch 7680 (/4 1920)
>[148369.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148369.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148369.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ffca0]
>[148369.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ffca0] width 1920 pitch 7680 (/4 1920)
>[148369.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3df0]
>[148369.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3df0] width 1920 pitch 7680 (/4 1920)
>[148369.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d509e0]
>[148369.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d509e0] width 1920 pitch 7680 (/4 1920)
>[148369.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3299230]
>[148369.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3299230] width 1920 pitch 7680 (/4 1920)
>[148759.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e35e80]
>[148759.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e35e80] width 1920 pitch 7680 (/4 1920)
>[148759.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e35e80]
>[148759.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e35e80] width 1920 pitch 7680 (/4 1920)
>[148764.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50795b0]
>[148764.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50795b0] width 1920 pitch 7680 (/4 1920)
>[148765.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50795b0]
>[148765.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50795b0] width 1920 pitch 7680 (/4 1920)
>[148915.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148915.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148915.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148915.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148915.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148915.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148915.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148915.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148915.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148915.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148915.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148915.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148915.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148915.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148915.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148915.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148916.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148916.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148916.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148916.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148916.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148916.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148916.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148916.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148916.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148916.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148917.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148917.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148917.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148917.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148917.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148917.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148917.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148918.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148918.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148918.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148918.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148918.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148920.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148920.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148922.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148922.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148922.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148922.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148922.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148922.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148922.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148922.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148922.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148922.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148922.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148922.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148922.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148923.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148923.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148923.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148923.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148923.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148923.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148923.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148923.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148923.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[148923.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148923.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148924.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6fe0]
>[148924.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6fe0] width 1920 pitch 7680 (/4 1920)
>[148924.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148924.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148924.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6fe0]
>[148924.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6fe0] width 1920 pitch 7680 (/4 1920)
>[148924.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148924.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148924.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6fe0]
>[148924.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6fe0] width 1920 pitch 7680 (/4 1920)
>[148924.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341890]
>[148924.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341890] width 1920 pitch 7680 (/4 1920)
>[148924.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd1320]
>[148924.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd1320] width 1920 pitch 7680 (/4 1920)
>[149093.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ef2e0]
>[149093.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ef2e0] width 1920 pitch 7680 (/4 1920)
>[149099.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f440]
>[149099.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f440] width 1920 pitch 7680 (/4 1920)
>[149276.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149276.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149276.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149277.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149277.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149277.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149277.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149278.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149278.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17a00]
>[149278.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17a00] width 1920 pitch 7680 (/4 1920)
>[149278.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13af0]
>[149278.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13af0] width 1920 pitch 7680 (/4 1920)
>[149278.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149278.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149278.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13af0]
>[149278.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13af0] width 1920 pitch 7680 (/4 1920)
>[149278.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149278.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149278.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13af0]
>[149278.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13af0] width 1920 pitch 7680 (/4 1920)
>[149278.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149278.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149278.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149278.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a640]
>[149314.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a640] width 1920 pitch 7680 (/4 1920)
>[149314.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a640]
>[149314.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a640] width 1920 pitch 7680 (/4 1920)
>[149314.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a640]
>[149314.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a640] width 1920 pitch 7680 (/4 1920)
>[149314.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149314.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149314.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a640]
>[149314.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a640] width 1920 pitch 7680 (/4 1920)
>[149314.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149314.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149314.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149314.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149314.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149315.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149315.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149315.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149315.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149316.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149316.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149316.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149316.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149316.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b18c70]
>[149317.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b18c70] width 1920 pitch 7680 (/4 1920)
>[149317.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149317.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149317.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149317.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149317.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149317.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d350]
>[149317.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d350] width 1920 pitch 7680 (/4 1920)
>[149317.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca1dd0]
>[149317.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca1dd0] width 1920 pitch 7680 (/4 1920)
>[149318.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14150]
>[149318.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14150] width 1920 pitch 7680 (/4 1920)
>[149318.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40220]
>[149318.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40220] width 1920 pitch 7680 (/4 1920)
>[149318.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40220]
>[149318.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40220] width 1920 pitch 7680 (/4 1920)
>[149318.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40220]
>[149318.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40220] width 1920 pitch 7680 (/4 1920)
>[149909.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3217a40]
>[149909.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3217a40] width 1920 pitch 7680 (/4 1920)
>[149909.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149909.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149909.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149909.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149909.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149909.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149909.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149909.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149909.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149909.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149909.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149909.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149909.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149909.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149909.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149909.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149909.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149909.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149910.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149910.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149910.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149910.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149910.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e37100]
>[149910.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e37100] width 1920 pitch 7680 (/4 1920)
>[149910.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149910.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149910.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149910.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149910.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149910.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149910.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149910.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149910.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149910.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149910.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149910.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149910.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f740]
>[149910.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f740] width 1920 pitch 7680 (/4 1920)
>[149954.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149954.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149954.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149954.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149954.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149954.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149954.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149954.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149954.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149954.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149954.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149955.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149955.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149955.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149955.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149955.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149955.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e560]
>[149955.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e560] width 1920 pitch 7680 (/4 1920)
>[149955.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149955.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149955.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149955.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149955.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf7550]
>[149956.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf7550] width 1920 pitch 7680 (/4 1920)
>[149956.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149956.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149961.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17020]
>[149961.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17020] width 1920 pitch 7680 (/4 1920)
>[149961.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[149961.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[149963.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81660]
>[149963.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81660] width 1920 pitch 7680 (/4 1920)
>[149978.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149978.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149978.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac780]
>[149978.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac780] width 1920 pitch 7680 (/4 1920)
>[149978.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149978.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149978.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac780]
>[149978.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac780] width 1920 pitch 7680 (/4 1920)
>[149978.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149978.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149978.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac780]
>[149978.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac780] width 1920 pitch 7680 (/4 1920)
>[149978.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149978.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149978.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac780]
>[149978.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac780] width 1920 pitch 7680 (/4 1920)
>[149978.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149978.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149979.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebe140]
>[149979.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebe140] width 1920 pitch 7680 (/4 1920)
>[149979.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3110]
>[149979.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3110] width 1920 pitch 7680 (/4 1920)
>[149979.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149979.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149979.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da3110]
>[149979.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da3110] width 1920 pitch 7680 (/4 1920)
>[149980.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53390]
>[149980.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53390] width 1920 pitch 7680 (/4 1920)
>[149980.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[149980.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[149980.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150000.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150000.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150000.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150000.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150000.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150000.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150000.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150000.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150000.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150000.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150000.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150001.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150001.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150001.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150001.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150001.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150001.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150001.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150001.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150001.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150001.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150001.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150001.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150001.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150002.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150002.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150002.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150002.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150002.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca30a0]
>[150002.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca30a0] width 1920 pitch 7680 (/4 1920)
>[150002.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150002.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150002.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca30a0]
>[150002.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca30a0] width 1920 pitch 7680 (/4 1920)
>[150002.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150002.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150002.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca30a0]
>[150002.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca30a0] width 1920 pitch 7680 (/4 1920)
>[150002.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150002.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150002.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca30a0]
>[150002.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca30a0] width 1920 pitch 7680 (/4 1920)
>[150002.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca30a0]
>[150002.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca30a0] width 1920 pitch 7680 (/4 1920)
>[150003.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150003.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150003.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150003.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150003.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150003.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150003.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150003.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150003.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150003.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150003.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150003.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150003.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150003.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150003.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150003.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150003.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150003.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150003.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150003.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150004.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150004.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150004.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150004.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150004.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150004.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150004.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150004.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d890]
>[150004.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d890] width 1920 pitch 7680 (/4 1920)
>[150059.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150059.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150059.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[150059.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[150059.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3c980]
>[150059.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3c980] width 1920 pitch 7680 (/4 1920)
>[150059.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d890]
>[150059.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d890] width 1920 pitch 7680 (/4 1920)
>[150059.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150059.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150059.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150059.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150059.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[150059.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[150059.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e6d0]
>[150059.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e6d0] width 1920 pitch 7680 (/4 1920)
>[150059.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d890]
>[150059.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d890] width 1920 pitch 7680 (/4 1920)
>[150059.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fec0]
>[150059.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fec0] width 1920 pitch 7680 (/4 1920)
>[150059.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d890]
>[150059.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d890] width 1920 pitch 7680 (/4 1920)
>[150059.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150059.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150059.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[150059.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[150059.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e6d0]
>[150059.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e6d0] width 1920 pitch 7680 (/4 1920)
>[150059.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3c980]
>[150059.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3c980] width 1920 pitch 7680 (/4 1920)
>[150059.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d890]
>[150059.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d890] width 1920 pitch 7680 (/4 1920)
>[150059.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3374110]
>[150059.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3374110] width 1920 pitch 7680 (/4 1920)
>[150059.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fa50]
>[150059.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fa50] width 1920 pitch 7680 (/4 1920)
>[150060.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3dd00]
>[150060.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3dd00] width 1920 pitch 7680 (/4 1920)
>[150600.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[150600.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151695.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151695.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151697.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151697.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151697.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151697.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151697.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151697.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151697.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151697.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151697.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151697.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151697.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151697.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151697.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151697.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151697.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151697.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151698.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151698.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151698.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151698.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151698.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151698.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151698.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151698.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81600]
>[151698.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81600] width 1920 pitch 7680 (/4 1920)
>[151698.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151698.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151698.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3e010]
>[151699.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3e010] width 1920 pitch 7680 (/4 1920)
>[151699.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3236210]
>[151699.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3236210] width 1920 pitch 7680 (/4 1920)
>[151699.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151699.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151699.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3236210]
>[151699.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3236210] width 1920 pitch 7680 (/4 1920)
>[151699.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151699.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151699.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3236210]
>[151699.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3236210] width 1920 pitch 7680 (/4 1920)
>[151699.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3aec0]
>[151699.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3aec0] width 1920 pitch 7680 (/4 1920)
>[151699.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3236210]
>[151699.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3236210] width 1920 pitch 7680 (/4 1920)
>[151798.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151798.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151798.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151798.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151798.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151798.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151798.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151798.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151798.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151798.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151798.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151798.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151798.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151798.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151798.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151798.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151798.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151798.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151798.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151798.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151799.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151799.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151799.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151799.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151799.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151799.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151799.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151799.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151799.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151799.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151799.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151799.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151799.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151799.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151799.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151799.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151799.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151800.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151800.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151800.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[151800.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[151800.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[151800.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fcd50]
>[151800.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fcd50] width 1920 pitch 7680 (/4 1920)
>[152208.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3220230]
>[152208.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3220230] width 1920 pitch 7680 (/4 1920)
>[152229.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152229.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152230.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152230.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152230.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152230.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152230.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152230.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152230.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152230.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152230.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152230.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152230.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152230.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152231.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152231.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152231.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152231.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152231.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fee0]
>[152231.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fee0] width 1920 pitch 7680 (/4 1920)
>[152231.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152231.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152231.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fee0]
>[152231.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fee0] width 1920 pitch 7680 (/4 1920)
>[152231.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152231.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[152231.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093c10]
>[152231.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093c10] width 1920 pitch 7680 (/4 1920)
>[152231.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4674900]
>[152231.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4674900] width 1920 pitch 7680 (/4 1920)
>[153059.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094400]
>[153059.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094400] width 1920 pitch 7680 (/4 1920)
>[153069.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5af60]
>[153069.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5af60] width 1920 pitch 7680 (/4 1920)
>[153069.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0b60]
>[153069.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0b60] width 1920 pitch 7680 (/4 1920)
>[153069.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0b60]
>[153069.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0b60] width 1920 pitch 7680 (/4 1920)
>[153069.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50912b0]
>[153069.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50912b0] width 1920 pitch 7680 (/4 1920)
>[153090.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153090.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153090.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153090.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153090.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153090.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153090.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153090.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153090.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153090.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153090.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153090.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153090.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153090.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153090.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153090.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153090.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153090.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153090.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153090.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153091.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153091.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153091.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153091.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153091.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153091.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153091.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e40070]
>[153091.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e40070] width 1920 pitch 7680 (/4 1920)
>[153092.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153092.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153093.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7f10]
>[153093.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7f10] width 1920 pitch 7680 (/4 1920)
>[153093.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153093.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153093.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7f10]
>[153093.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7f10] width 1920 pitch 7680 (/4 1920)
>[153093.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7f10]
>[153093.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7f10] width 1920 pitch 7680 (/4 1920)
>[153093.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7f10]
>[153093.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7f10] width 1920 pitch 7680 (/4 1920)
>[153093.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebeb80]
>[153093.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebeb80] width 1920 pitch 7680 (/4 1920)
>[153093.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153093.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153093.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153093.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153093.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153093.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153094.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153094.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153094.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153094.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153094.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153094.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153094.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153094.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153094.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153094.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153094.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153094.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153094.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153094.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153094.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153094.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153094.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153094.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153094.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4d3b0]
>[153094.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4d3b0] width 1920 pitch 7680 (/4 1920)
>[153095.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32174b0]
>[153095.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32174b0] width 1920 pitch 7680 (/4 1920)
>[153095.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06cf0]
>[153095.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06cf0] width 1920 pitch 7680 (/4 1920)
>[153095.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06cf0]
>[153095.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06cf0] width 1920 pitch 7680 (/4 1920)
>[153095.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06cf0]
>[153095.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06cf0] width 1920 pitch 7680 (/4 1920)
>[153095.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06cf0]
>[153095.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06cf0] width 1920 pitch 7680 (/4 1920)
>[153095.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06cf0]
>[153095.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06cf0] width 1920 pitch 7680 (/4 1920)
>[153203.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ead00]
>[153203.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ead00] width 1920 pitch 7680 (/4 1920)
>[153203.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153203.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153203.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ead00]
>[153203.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ead00] width 1920 pitch 7680 (/4 1920)
>[153203.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153203.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153203.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153203.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153203.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153203.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153203.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153203.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153203.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153203.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153203.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153203.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153204.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153204.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153204.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153204.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153204.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153204.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153204.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153204.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153204.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153204.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153204.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3235cc0]
>[153205.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3235cc0] width 1920 pitch 7680 (/4 1920)
>[153205.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153205.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153205.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d454f0]
>[153205.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d454f0] width 1920 pitch 7680 (/4 1920)
>[153205.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d44890]
>[153205.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d44890] width 1920 pitch 7680 (/4 1920)
>[153205.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153205.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153205.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d44890]
>[153205.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d44890] width 1920 pitch 7680 (/4 1920)
>[153205.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153205.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153205.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d44890]
>[153205.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d44890] width 1920 pitch 7680 (/4 1920)
>[153205.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322dbe0]
>[153205.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322dbe0] width 1920 pitch 7680 (/4 1920)
>[153998.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277fb0]
>[153998.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277fb0] width 1920 pitch 7680 (/4 1920)
>[154034.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3279930]
>[154034.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3279930] width 1920 pitch 7680 (/4 1920)
>[154034.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154034.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154034.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154034.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154034.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154034.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154034.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154034.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154035.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154035.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154035.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154035.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154035.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154035.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154035.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154035.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154035.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154035.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154035.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154035.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154035.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154035.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154036.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154036.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154036.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e20]
>[154036.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e20] width 1920 pitch 7680 (/4 1920)
>[154036.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094210]
>[154036.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094210] width 1920 pitch 7680 (/4 1920)
>[154036.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154036.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154036.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094210]
>[154036.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094210] width 1920 pitch 7680 (/4 1920)
>[154037.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154037.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154037.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094210]
>[154037.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094210] width 1920 pitch 7680 (/4 1920)
>[154037.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363c30]
>[154037.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363c30] width 1920 pitch 7680 (/4 1920)
>[154037.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094210]
>[154037.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094210] width 1920 pitch 7680 (/4 1920)
>[154323.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b57fa0]
>[154323.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b57fa0] width 1920 pitch 7680 (/4 1920)
>[154323.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b57fa0]
>[154323.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b57fa0] width 1920 pitch 7680 (/4 1920)
>[154324.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c221c0]
>[154324.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c221c0] width 1920 pitch 7680 (/4 1920)
>[154385.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154385.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154385.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154385.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154385.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154385.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154385.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154385.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154385.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154385.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154385.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154385.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154385.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154385.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154385.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154385.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154385.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154385.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154386.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154386.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154386.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154386.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154386.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154386.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154386.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154386.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154386.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154386.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154386.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154386.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154386.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154386.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154387.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154387.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154387.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154387.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154408.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154408.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154408.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154408.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154410.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327ab20]
>[154410.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327ab20] width 1920 pitch 7680 (/4 1920)
>[154410.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154410.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154410.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327ab20]
>[154410.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327ab20] width 1920 pitch 7680 (/4 1920)
>[154410.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154410.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154410.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327ab20]
>[154410.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327ab20] width 1920 pitch 7680 (/4 1920)
>[154410.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bef730]
>[154410.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bef730] width 1920 pitch 7680 (/4 1920)
>[154410.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154410.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154410.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154410.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154410.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154410.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154410.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154411.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154411.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154411.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154411.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f59070]
>[154411.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f59070] width 1920 pitch 7680 (/4 1920)
>[154411.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154411.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154411.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154411.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154411.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327eeb0]
>[154411.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327eeb0] width 1920 pitch 7680 (/4 1920)
>[154411.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca45f0]
>[154411.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca45f0] width 1920 pitch 7680 (/4 1920)
>[154411.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154411.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154411.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca45f0]
>[154411.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca45f0] width 1920 pitch 7680 (/4 1920)
>[154411.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154411.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154732.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bef730]
>[154732.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bef730] width 1920 pitch 7680 (/4 1920)
>[154756.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154756.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327b120]
>[154757.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327b120] width 1920 pitch 7680 (/4 1920)
>[154757.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154757.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154757.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154757.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154757.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154757.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154757.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154757.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154757.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154757.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154757.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154757.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154757.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154757.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154757.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154758.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154758.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d19580]
>[154758.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d19580] width 1920 pitch 7680 (/4 1920)
>[154758.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c85810]
>[154758.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c85810] width 1920 pitch 7680 (/4 1920)
>[154758.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154758.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154758.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c85810]
>[154758.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c85810] width 1920 pitch 7680 (/4 1920)
>[154758.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154758.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154758.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154758.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154758.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154758.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154758.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154758.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154759.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3278190]
>[154759.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3278190] width 1920 pitch 7680 (/4 1920)
>[154768.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154768.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154768.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154768.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154768.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154769.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154769.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154769.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154769.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154769.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154769.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154769.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154769.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154769.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154769.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154769.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154769.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154769.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154769.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154769.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154769.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154769.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154769.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154769.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154769.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154770.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154770.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e34d20]
>[154770.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e34d20] width 1920 pitch 7680 (/4 1920)
>[154770.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c85810]
>[154770.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c85810] width 1920 pitch 7680 (/4 1920)
>[154770.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327d940]
>[154770.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327d940] width 1920 pitch 7680 (/4 1920)
>[154770.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c85810]
>[154770.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c85810] width 1920 pitch 7680 (/4 1920)
>[154770.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4690]
>[154770.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4690] width 1920 pitch 7680 (/4 1920)
>[154770.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x327dc00]
>[154770.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x327dc00] width 1920 pitch 7680 (/4 1920)
>[154936.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154936.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154936.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154936.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154936.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154936.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154936.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154936.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154936.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154936.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154936.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e3fb10]
>[154936.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e3fb10] width 1920 pitch 7680 (/4 1920)
>[154936.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154936.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154938.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf6190]
>[154938.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf6190] width 1920 pitch 7680 (/4 1920)
>[154941.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b627f0]
>[154941.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b627f0] width 1920 pitch 7680 (/4 1920)
>[154941.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363160]
>[154941.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363160] width 1920 pitch 7680 (/4 1920)
>[154943.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3362c50]
>[154943.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3362c50] width 1920 pitch 7680 (/4 1920)
>[154943.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[154943.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7c70]
>[154943.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7c70] width 1920 pitch 7680 (/4 1920)
>[154943.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c06e10]
>[154943.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c06e10] width 1920 pitch 7680 (/4 1920)
>[155087.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf6730]
>[155087.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf6730] width 1920 pitch 7680 (/4 1920)
>[155122.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d60800]
>[155122.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d60800] width 1920 pitch 7680 (/4 1920)
>[155149.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3362140]
>[155149.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3362140] width 1920 pitch 7680 (/4 1920)
>[155149.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c20c40]
>[155149.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c20c40] width 1920 pitch 7680 (/4 1920)
>[155264.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155264.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155264.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155264.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155264.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155264.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155264.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155264.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155264.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155265.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155265.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155265.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155265.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155265.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155265.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155265.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155265.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155265.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155265.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155265.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155265.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155265.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155265.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155265.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155266.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155266.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155266.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155266.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155266.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155266.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155267.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155267.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155267.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155267.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155267.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebeb80]
>[155267.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebeb80] width 1920 pitch 7680 (/4 1920)
>[155267.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155267.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155267.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155267.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155267.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155267.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155269.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155269.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155269.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155269.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155269.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155269.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155269.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155269.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155269.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155269.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155269.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155270.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155270.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155270.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155270.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155270.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155270.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155270.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155270.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155270.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155270.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155270.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155270.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155270.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155270.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155270.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155271.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155271.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155271.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155271.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155271.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155271.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155271.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155271.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155271.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155271.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155271.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea930]
>[155271.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea930] width 1920 pitch 7680 (/4 1920)
>[155271.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f534b0]
>[155271.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f534b0] width 1920 pitch 7680 (/4 1920)
>[155276.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155276.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155276.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155276.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155276.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155276.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155276.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155276.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155276.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155276.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155276.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155276.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155276.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155276.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155276.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155276.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155276.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155277.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155277.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155277.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155277.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155277.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155277.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155277.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155277.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155277.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155278.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155278.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155278.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce520]
>[155278.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce520] width 1920 pitch 7680 (/4 1920)
>[155286.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155286.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155286.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12590]
>[155286.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12590] width 1920 pitch 7680 (/4 1920)
>[155286.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155286.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155286.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12590]
>[155286.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12590] width 1920 pitch 7680 (/4 1920)
>[155286.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155286.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155286.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12590]
>[155286.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12590] width 1920 pitch 7680 (/4 1920)
>[155287.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155287.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155287.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12590]
>[155287.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12590] width 1920 pitch 7680 (/4 1920)
>[155292.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155292.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155292.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155292.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155292.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155292.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155292.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155292.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155292.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155292.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155292.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155292.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155292.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155292.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155292.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e4f0]
>[155292.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e4f0] width 1920 pitch 7680 (/4 1920)
>[155292.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155292.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155293.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155293.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155293.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155293.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155293.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155293.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155293.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155293.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155293.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155293.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155293.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155293.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155294.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155294.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155294.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155294.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155294.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155294.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155294.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155294.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155294.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f544a0]
>[155294.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f544a0] width 1920 pitch 7680 (/4 1920)
>[155294.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155294.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155358.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53870]
>[155358.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53870] width 1920 pitch 7680 (/4 1920)
>[155358.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155358.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155358.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53870]
>[155358.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53870] width 1920 pitch 7680 (/4 1920)
>[155358.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155358.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155358.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155358.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155358.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155358.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155358.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155358.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155358.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155358.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155358.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155358.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155359.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155359.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155359.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155359.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155359.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155359.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155359.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155359.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155359.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155359.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155359.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155359.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155360.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50642d0]
>[155360.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50642d0] width 1920 pitch 7680 (/4 1920)
>[155360.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155360.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155360.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3357030]
>[155360.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3357030] width 1920 pitch 7680 (/4 1920)
>[155360.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f616a0]
>[155360.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f616a0] width 1920 pitch 7680 (/4 1920)
>[155360.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f616a0]
>[155360.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f616a0] width 1920 pitch 7680 (/4 1920)
>[155360.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238bd0]
>[155360.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238bd0] width 1920 pitch 7680 (/4 1920)
>[155412.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e69a30]
>[155412.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e69a30] width 1920 pitch 7680 (/4 1920)
>[155567.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155567.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155567.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155567.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155567.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155567.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155567.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155567.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155567.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155567.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155567.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155567.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155567.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155567.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155567.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155567.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155567.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155568.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155568.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155568.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155568.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103220]
>[155568.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103220] width 1920 pitch 7680 (/4 1920)
>[155568.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155568.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155568.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c067c0]
>[155568.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c067c0] width 1920 pitch 7680 (/4 1920)
>[155568.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c067c0]
>[155568.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c067c0] width 1920 pitch 7680 (/4 1920)
>[155568.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155568.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155568.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c067c0]
>[155568.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c067c0] width 1920 pitch 7680 (/4 1920)
>[155568.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cf4380]
>[155568.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cf4380] width 1920 pitch 7680 (/4 1920)
>[155569.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155569.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[155569.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e68ee0]
>[155569.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e68ee0] width 1920 pitch 7680 (/4 1920)
>[155569.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64b80]
>[155569.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64b80] width 1920 pitch 7680 (/4 1920)
>[156404.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67fb0]
>[156404.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67fb0] width 1920 pitch 7680 (/4 1920)
>[156443.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e66e70]
>[156443.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e66e70] width 1920 pitch 7680 (/4 1920)
>[156443.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3c80]
>[156443.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3c80] width 1920 pitch 7680 (/4 1920)
>[156443.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156443.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156443.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156443.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156443.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156443.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156443.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156443.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156443.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156443.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156443.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156443.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156443.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156443.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156444.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156444.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156444.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156444.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156444.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156444.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156444.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156444.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156444.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e404e0]
>[156444.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e404e0] width 1920 pitch 7680 (/4 1920)
>[156445.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156445.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156445.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f050]
>[156445.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f050] width 1920 pitch 7680 (/4 1920)
>[156445.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50625c0]
>[156445.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50625c0] width 1920 pitch 7680 (/4 1920)
>[156445.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8c30]
>[156445.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8c30] width 1920 pitch 7680 (/4 1920)
>[156445.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec11d0]
>[156445.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec11d0] width 1920 pitch 7680 (/4 1920)
>[156445.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3c80]
>[156445.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3c80] width 1920 pitch 7680 (/4 1920)
>[156445.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec11d0]
>[156445.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec11d0] width 1920 pitch 7680 (/4 1920)
>[156525.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3fb10]
>[156525.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3fb10] width 1920 pitch 7680 (/4 1920)
>[156530.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3308890]
>[156530.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3308890] width 1920 pitch 7680 (/4 1920)
>[156530.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330a7c0]
>[156530.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330a7c0] width 1920 pitch 7680 (/4 1920)
>[156550.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309aa0]
>[156550.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309aa0] width 1920 pitch 7680 (/4 1920)
>[156551.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305840]
>[156551.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305840] width 1920 pitch 7680 (/4 1920)
>[156552.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ee40]
>[156552.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ee40] width 1920 pitch 7680 (/4 1920)
>[156552.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156552.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156552.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156552.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156553.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156553.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156553.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156553.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156553.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156553.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156553.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156553.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156553.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156553.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156553.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156553.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156553.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156553.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156553.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156553.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156553.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156553.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156553.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156553.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156554.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156554.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156554.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156554.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156554.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156554.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156554.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156555.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156555.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156555.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156556.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156556.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156557.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156557.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156557.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156557.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156557.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156557.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156557.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156557.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156557.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156557.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156557.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3940]
>[156557.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3940] width 1920 pitch 7680 (/4 1920)
>[156557.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3328630]
>[156557.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3328630] width 1920 pitch 7680 (/4 1920)
>[156637.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50637d0]
>[156637.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50637d0] width 1920 pitch 7680 (/4 1920)
>[156910.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508dbd0]
>[156910.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508dbd0] width 1920 pitch 7680 (/4 1920)
>[156910.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508dbd0]
>[156910.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508dbd0] width 1920 pitch 7680 (/4 1920)
>[157110.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157110.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157110.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157110.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157110.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157110.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064960]
>[157110.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064960] width 1920 pitch 7680 (/4 1920)
>[157110.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157110.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157111.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080740]
>[157111.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080740] width 1920 pitch 7680 (/4 1920)
>[157111.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33191a0]
>[157111.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33191a0] width 1920 pitch 7680 (/4 1920)
>[157111.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080740]
>[157111.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080740] width 1920 pitch 7680 (/4 1920)
>[157111.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bd8b0]
>[157111.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bd8b0] width 1920 pitch 7680 (/4 1920)
>[157111.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a3b0]
>[157111.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a3b0] width 1920 pitch 7680 (/4 1920)
>[157111.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b9db0]
>[157111.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b9db0] width 1920 pitch 7680 (/4 1920)
>[157111.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a3b0]
>[157111.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a3b0] width 1920 pitch 7680 (/4 1920)
>[157126.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e9ae0]
>[157126.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e9ae0] width 1920 pitch 7680 (/4 1920)
>[157142.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3315830]
>[157142.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3315830] width 1920 pitch 7680 (/4 1920)
>[157142.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae710]
>[157142.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae710] width 1920 pitch 7680 (/4 1920)
>[157142.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1d90]
>[157142.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1d90] width 1920 pitch 7680 (/4 1920)
>[157142.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3315830]
>[157142.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3315830] width 1920 pitch 7680 (/4 1920)
>[157142.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae710]
>[157142.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae710] width 1920 pitch 7680 (/4 1920)
>[157142.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157142.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157142.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae4e0]
>[157142.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae4e0] width 1920 pitch 7680 (/4 1920)
>[157142.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157142.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157142.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae4e0]
>[157142.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae4e0] width 1920 pitch 7680 (/4 1920)
>[157142.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157142.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157142.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae4e0]
>[157142.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae4e0] width 1920 pitch 7680 (/4 1920)
>[157142.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157143.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157143.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eae4e0]
>[157143.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eae4e0] width 1920 pitch 7680 (/4 1920)
>[157143.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8410]
>[157143.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8410] width 1920 pitch 7680 (/4 1920)
>[157143.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157143.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157143.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157143.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157143.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157143.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157143.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157143.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157143.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8d50]
>[157143.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8d50] width 1920 pitch 7680 (/4 1920)
>[157207.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef39a0]
>[157207.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef39a0] width 1920 pitch 7680 (/4 1920)
>[157299.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec3e00]
>[157299.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec3e00] width 1920 pitch 7680 (/4 1920)
>[157299.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157299.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157299.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157299.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157299.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157300.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157300.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157300.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157300.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157300.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157300.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157300.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157300.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157300.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157300.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157300.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157300.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157300.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157300.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157300.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157300.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e64550]
>[157300.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e64550] width 1920 pitch 7680 (/4 1920)
>[157301.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157301.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157301.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157301.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157301.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157301.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157301.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157301.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157301.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157301.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157301.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3306770]
>[157301.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3306770] width 1920 pitch 7680 (/4 1920)
>[157301.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157301.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157301.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3306770]
>[157301.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3306770] width 1920 pitch 7680 (/4 1920)
>[157533.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e68f40]
>[157533.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e68f40] width 1920 pitch 7680 (/4 1920)
>[157597.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157597.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157597.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157597.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157597.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157597.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157597.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157597.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157597.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157597.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157597.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157597.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157597.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157597.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157597.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157597.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157597.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157597.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157597.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157597.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157597.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157598.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157598.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157598.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157598.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157598.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157598.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157598.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157598.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157598.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157598.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157598.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157598.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157598.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157598.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157599.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157599.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a7cc0]
>[157599.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a7cc0] width 1920 pitch 7680 (/4 1920)
>[157599.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157599.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157599.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a7cc0]
>[157599.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a7cc0] width 1920 pitch 7680 (/4 1920)
>[157599.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[157599.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[157599.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a7cc0]
>[157599.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a7cc0] width 1920 pitch 7680 (/4 1920)
>[157599.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157599.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157602.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157602.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157602.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102cd0]
>[157602.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102cd0] width 1920 pitch 7680 (/4 1920)
>[157602.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157602.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157602.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102cd0]
>[157602.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102cd0] width 1920 pitch 7680 (/4 1920)
>[157602.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fdc0]
>[157602.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fdc0] width 1920 pitch 7680 (/4 1920)
>[157603.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[157603.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[157603.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102cd0]
>[157603.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102cd0] width 1920 pitch 7680 (/4 1920)
>[157603.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157603.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157603.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157603.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157603.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157603.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157603.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157603.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157603.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157603.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157603.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157603.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157603.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157603.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157603.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157603.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157603.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157603.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157603.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157604.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157604.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157604.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157604.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157604.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157604.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157604.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157604.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157604.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157604.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32970f0]
>[157604.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32970f0] width 1920 pitch 7680 (/4 1920)
>[157604.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cd0]
>[157604.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cd0] width 1920 pitch 7680 (/4 1920)
>[157604.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cd0]
>[157604.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cd0] width 1920 pitch 7680 (/4 1920)
>[157604.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330ffa0]
>[157604.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330ffa0] width 1920 pitch 7680 (/4 1920)
>[157604.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157604.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cd0]
>[157908.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cd0] width 1920 pitch 7680 (/4 1920)
>[157908.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157908.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157908.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157908.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cd0]
>[157908.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cd0] width 1920 pitch 7680 (/4 1920)
>[157908.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[157908.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[157912.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157912.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157912.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157912.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157912.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157912.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157912.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157912.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157912.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157912.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157912.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157912.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157912.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157912.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157912.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157912.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157912.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157912.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157912.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157912.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157912.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157912.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157912.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157912.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157952.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157952.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157952.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157952.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157952.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157952.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157952.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157952.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157952.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157952.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157952.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157952.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157952.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157952.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157952.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157952.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157952.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157952.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157952.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157952.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157952.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157952.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157952.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157952.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157952.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157952.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157952.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157952.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157956.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157956.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157956.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157956.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157956.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157956.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157956.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157956.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157956.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157956.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157956.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157956.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157956.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157956.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157956.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157956.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[157956.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[157956.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[157956.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[157956.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[157956.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[157956.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[157956.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[157956.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[157956.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[157956.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[158033.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158033.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158033.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158033.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158033.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[158033.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[158033.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158033.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158033.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[158033.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[158033.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158033.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158033.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158033.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158033.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[158033.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[158033.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158033.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158033.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[158033.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[158033.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158033.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158033.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[158033.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[158033.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158033.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158037.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158037.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158037.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158038.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158038.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[158038.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[158038.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[158038.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[158038.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158038.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158038.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158038.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158038.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158038.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158038.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158038.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158038.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158038.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158038.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158038.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158038.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf09c0]
>[158038.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf09c0] width 1920 pitch 7680 (/4 1920)
>[158038.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cec320]
>[158038.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cec320] width 1920 pitch 7680 (/4 1920)
>[158038.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158038.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158038.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158038.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158084.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158084.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158084.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158084.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158084.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158084.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158084.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158084.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158084.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158084.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158084.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158084.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158084.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158084.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158084.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158084.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158084.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158084.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158084.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158084.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158084.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158084.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158084.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158084.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158084.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158084.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158084.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158084.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158088.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158088.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158088.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158088.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158088.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158088.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158088.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158088.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158088.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158088.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[158088.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[158088.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158088.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158088.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbad0]
>[158088.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbad0] width 1920 pitch 7680 (/4 1920)
>[158246.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f52220]
>[158246.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f52220] width 1920 pitch 7680 (/4 1920)
>[158246.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158246.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158246.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158246.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158246.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158246.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158246.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158246.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158246.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158246.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f52220]
>[158246.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f52220] width 1920 pitch 7680 (/4 1920)
>[158246.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158246.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158246.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158246.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158246.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b6e20]
>[158246.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b6e20] width 1920 pitch 7680 (/4 1920)
>[158246.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158246.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158250.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b6e20]
>[158250.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b6e20] width 1920 pitch 7680 (/4 1920)
>[158250.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158250.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158250.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158250.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158250.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158250.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158250.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158250.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158250.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158250.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158250.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158250.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158250.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158250.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158250.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158250.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158250.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158250.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158250.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158250.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158250.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158250.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158250.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158250.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158250.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e653c0]
>[158250.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e653c0] width 1920 pitch 7680 (/4 1920)
>[158360.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158360.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158360.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158360.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158360.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158360.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158360.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158360.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158360.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158360.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158360.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32337b0]
>[158360.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32337b0] width 1920 pitch 7680 (/4 1920)
>[158360.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158360.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158360.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158360.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32337b0]
>[158360.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32337b0] width 1920 pitch 7680 (/4 1920)
>[158360.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158360.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158360.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158360.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158360.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a0cb0]
>[158360.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a0cb0] width 1920 pitch 7680 (/4 1920)
>[158360.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5519bd0]
>[158360.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5519bd0] width 1920 pitch 7680 (/4 1920)
>[158364.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158364.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158364.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158364.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158364.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158364.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158364.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158364.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158364.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158364.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158364.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32337b0]
>[158364.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32337b0] width 1920 pitch 7680 (/4 1920)
>[158364.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158364.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158364.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158364.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158364.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330ffa0]
>[158364.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330ffa0] width 1920 pitch 7680 (/4 1920)
>[158364.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[158364.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[158364.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32337b0]
>[158364.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32337b0] width 1920 pitch 7680 (/4 1920)
>[158364.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b0cf0]
>[158364.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b0cf0] width 1920 pitch 7680 (/4 1920)
>[158544.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158544.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158544.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158545.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158545.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158545.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158545.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158545.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158545.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158545.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158545.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158545.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158545.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158545.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158545.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158545.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158545.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158545.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158545.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba300]
>[158545.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba300] width 1920 pitch 7680 (/4 1920)
>[158545.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330ffa0]
>[158545.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330ffa0] width 1920 pitch 7680 (/4 1920)
>[158545.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158545.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158545.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158545.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158545.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e2af0]
>[158545.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e2af0] width 1920 pitch 7680 (/4 1920)
>[158549.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158549.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158549.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158549.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158549.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330ffa0]
>[158549.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330ffa0] width 1920 pitch 7680 (/4 1920)
>[158549.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158549.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158549.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158549.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158549.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158549.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158549.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e2af0]
>[158549.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e2af0] width 1920 pitch 7680 (/4 1920)
>[158549.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158549.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158549.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158549.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158549.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158549.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158549.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158549.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158549.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e2af0]
>[158549.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e2af0] width 1920 pitch 7680 (/4 1920)
>[158549.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158549.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158549.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158549.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158666.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158666.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158666.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158666.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158666.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158666.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158666.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158666.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158666.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158666.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158666.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158666.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158666.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158666.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158666.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158666.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158666.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158666.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330ffa0]
>[158666.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330ffa0] width 1920 pitch 7680 (/4 1920)
>[158666.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158666.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba300]
>[158670.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba300] width 1920 pitch 7680 (/4 1920)
>[158670.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158670.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158670.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158670.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158670.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bba300]
>[158670.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bba300] width 1920 pitch 7680 (/4 1920)
>[158670.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158670.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158670.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158670.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158670.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158670.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf020]
>[158670.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf020] width 1920 pitch 7680 (/4 1920)
>[158759.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158759.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158759.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158759.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158759.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158759.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158759.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158759.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158759.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158759.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158759.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158759.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158759.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158759.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158759.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158759.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158759.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158759.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158759.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158759.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158759.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158759.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158759.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158759.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158759.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158759.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158759.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158759.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158763.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158763.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158763.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158763.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158763.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158763.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158763.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158763.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158763.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158763.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158763.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158763.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158763.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158763.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158763.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158763.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158763.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158763.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158763.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5b60]
>[158763.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5b60] width 1920 pitch 7680 (/4 1920)
>[158763.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158763.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158763.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158764.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158764.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158764.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158872.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158872.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158872.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158872.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158872.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158872.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158872.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158872.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158872.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158872.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158872.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158872.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158872.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158872.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158872.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158872.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158872.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50691c0]
>[158872.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50691c0] width 1920 pitch 7680 (/4 1920)
>[158872.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158872.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158872.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158872.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158872.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81890]
>[158872.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81890] width 1920 pitch 7680 (/4 1920)
>[158872.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158872.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158879.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158879.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158879.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158879.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158879.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158879.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158879.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158879.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158879.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158879.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158879.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158879.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158879.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158879.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158879.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158879.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158879.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158879.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158879.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158879.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158879.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158879.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158879.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158879.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158879.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158879.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158993.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158993.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158993.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158993.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158993.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158993.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158993.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158993.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158993.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158993.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158993.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158993.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158993.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158993.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158993.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158993.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158993.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158993.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158993.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158993.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158993.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158993.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[158993.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c40ca0]
>[158993.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c40ca0] width 1920 pitch 7680 (/4 1920)
>[158993.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[158993.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[158997.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158997.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158997.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158997.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158997.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158997.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158997.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158997.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158997.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158997.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158997.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[158997.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[158997.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158997.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158997.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158997.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158997.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51035b0]
>[158997.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51035b0] width 1920 pitch 7680 (/4 1920)
>[158997.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[158997.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[158997.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b9f4a0]
>[158997.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b9f4a0] width 1920 pitch 7680 (/4 1920)
>[158997.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[158997.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[158997.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aed30]
>[158997.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aed30] width 1920 pitch 7680 (/4 1920)
>[159321.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159321.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159321.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159321.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159321.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159321.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159321.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159321.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159321.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159321.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159321.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159321.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159321.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159321.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159321.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159321.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159321.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159321.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159321.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159321.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159321.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159321.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51200]
>[159321.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51200] width 1920 pitch 7680 (/4 1920)
>[159325.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[159325.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[159325.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159325.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159325.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[159325.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[159325.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159325.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159325.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[159326.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[159326.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159326.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159326.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159326.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159326.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[159326.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[159326.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159326.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159326.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159326.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[159326.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd83a0]
>[159326.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd83a0] width 1920 pitch 7680 (/4 1920)
>[159326.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc4670]
>[159326.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc4670] width 1920 pitch 7680 (/4 1920)
>[159326.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3387920]
>[159326.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3387920] width 1920 pitch 7680 (/4 1920)
>[160268.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160268.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160268.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160268.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160268.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160268.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160268.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160268.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f920]
>[160268.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f920] width 1920 pitch 7680 (/4 1920)
>[160269.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f980]
>[160269.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f980] width 1920 pitch 7680 (/4 1920)
>[160269.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bfc7c0]
>[160269.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bfc7c0] width 1920 pitch 7680 (/4 1920)
>[160273.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[160273.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbc80]
>[160273.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbc80] width 1920 pitch 7680 (/4 1920)
>[160273.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bce630]
>[160273.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bce630] width 1920 pitch 7680 (/4 1920)
>[161208.561] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[161208.561] (II) RADEON(0): Using hsync ranges from config file
>[161208.561] (II) RADEON(0): Using vrefresh ranges from config file
>[161208.561] (II) RADEON(0): Printing DDC gathered Modelines:
>[161208.561] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[161208.561] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[161208.561] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[161208.561] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[161208.561] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[161208.561] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[161208.561] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[161298.938] (II) RADEON(0): RADEONSaveScreen(2)
>[161298.938] (II) RADEON(0): RADEONSaveScreen(0)
>[166304.353] (II) RADEON(0): RADEONSaveScreen(1)
>[166312.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166312.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166312.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[166312.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[166312.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166312.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166312.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[166312.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[166312.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee010]
>[166312.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee010] width 1920 pitch 7680 (/4 1920)
>[166312.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[166312.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[166312.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[166312.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[166312.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[166312.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[166312.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee010]
>[166312.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee010] width 1920 pitch 7680 (/4 1920)
>[166312.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166312.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166312.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[166312.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[166312.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[166312.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[166312.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166312.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166317.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[166317.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[166317.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166317.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166317.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166317.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166317.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[166317.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[166317.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8f20]
>[166317.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8f20] width 1920 pitch 7680 (/4 1920)
>[166317.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[166317.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[166317.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8f20]
>[166317.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8f20] width 1920 pitch 7680 (/4 1920)
>[166317.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9170]
>[166317.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9170] width 1920 pitch 7680 (/4 1920)
>[166317.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[166317.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[166317.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee010]
>[166317.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee010] width 1920 pitch 7680 (/4 1920)
>[166317.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[166317.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[166317.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[166317.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[166317.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166317.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166317.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166317.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166319.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee010]
>[166319.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee010] width 1920 pitch 7680 (/4 1920)
>[166319.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[166320.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[166320.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166320.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166320.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166320.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166320.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[166320.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[166320.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8f20]
>[166320.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8f20] width 1920 pitch 7680 (/4 1920)
>[166320.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c410a0]
>[166320.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c410a0] width 1920 pitch 7680 (/4 1920)
>[166320.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9170]
>[166320.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9170] width 1920 pitch 7680 (/4 1920)
>[166320.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[166320.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[166321.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[166321.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[166321.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[166321.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[166321.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bd150]
>[166321.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bd150] width 1920 pitch 7680 (/4 1920)
>[166321.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e68470]
>[166321.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e68470] width 1920 pitch 7680 (/4 1920)
>[166321.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c30aa0]
>[166321.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c30aa0] width 1920 pitch 7680 (/4 1920)
>[166321.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bd150]
>[166321.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bd150] width 1920 pitch 7680 (/4 1920)
>[166321.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9df50]
>[166321.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9df50] width 1920 pitch 7680 (/4 1920)
>[166414.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166414.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166414.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc3470]
>[166414.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc3470] width 1920 pitch 7680 (/4 1920)
>[166414.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166414.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166414.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166414.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166414.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166414.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166414.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166414.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166414.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166414.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166414.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166414.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166415.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166415.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166415.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166415.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166415.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166415.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166415.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166415.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166415.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[166415.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[166416.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166416.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166416.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e37500]
>[166416.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e37500] width 1920 pitch 7680 (/4 1920)
>[166416.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166416.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166416.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e37500]
>[166416.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e37500] width 1920 pitch 7680 (/4 1920)
>[166416.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ddf0]
>[166416.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ddf0] width 1920 pitch 7680 (/4 1920)
>[166416.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e37500]
>[166416.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e37500] width 1920 pitch 7680 (/4 1920)
>[166418.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c163c0]
>[166418.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c163c0] width 1920 pitch 7680 (/4 1920)
>[166437.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d49510]
>[166437.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d49510] width 1920 pitch 7680 (/4 1920)
>[167891.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08140]
>[167891.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08140] width 1920 pitch 7680 (/4 1920)
>[167891.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167891.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167891.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167891.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167891.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167891.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167891.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167891.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167891.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167891.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167891.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167891.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167891.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167891.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167891.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167891.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167891.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167891.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167891.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167891.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167891.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167892.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167892.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53ff0]
>[167892.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53ff0] width 1920 pitch 7680 (/4 1920)
>[167892.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5511df0]
>[167892.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5511df0] width 1920 pitch 7680 (/4 1920)
>[167892.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8a70]
>[167892.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8a70] width 1920 pitch 7680 (/4 1920)
>[167892.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd8a70]
>[167892.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd8a70] width 1920 pitch 7680 (/4 1920)
>[167893.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068850]
>[167893.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068850] width 1920 pitch 7680 (/4 1920)
>[168103.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9f90]
>[168103.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9f90] width 1920 pitch 7680 (/4 1920)
>[168103.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168103.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168103.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168103.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168103.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168103.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168103.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168103.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168103.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168103.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168103.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168103.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168103.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168103.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168103.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168103.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168103.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168104.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168104.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168104.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168104.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168104.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168104.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168104.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168104.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168104.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168104.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168104.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168104.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168104.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168104.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x328e3a0]
>[168104.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x328e3a0] width 1920 pitch 7680 (/4 1920)
>[168104.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168104.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168105.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5470]
>[168105.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5470] width 1920 pitch 7680 (/4 1920)
>[168105.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5470]
>[168105.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5470] width 1920 pitch 7680 (/4 1920)
>[168105.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339aa0]
>[168105.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339aa0] width 1920 pitch 7680 (/4 1920)
>[168249.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f6c0]
>[168249.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f6c0] width 1920 pitch 7680 (/4 1920)
>[168249.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168249.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168249.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f6c0]
>[168249.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f6c0] width 1920 pitch 7680 (/4 1920)
>[168249.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168249.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168249.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f6c0]
>[168249.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f6c0] width 1920 pitch 7680 (/4 1920)
>[168249.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168249.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168249.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f6c0]
>[168249.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f6c0] width 1920 pitch 7680 (/4 1920)
>[168249.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168249.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168249.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f6c0]
>[168249.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f6c0] width 1920 pitch 7680 (/4 1920)
>[168249.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f710]
>[168249.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f710] width 1920 pitch 7680 (/4 1920)
>[168249.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0bae0]
>[168249.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0bae0] width 1920 pitch 7680 (/4 1920)
>[168249.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6af40]
>[168249.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6af40] width 1920 pitch 7680 (/4 1920)
>[168253.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0bae0]
>[168253.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0bae0] width 1920 pitch 7680 (/4 1920)
>[168253.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168253.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168253.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168253.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168253.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168253.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168253.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168253.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168253.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168253.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168253.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168253.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168253.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168253.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168253.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168254.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168254.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168254.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168254.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168254.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168254.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168254.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168254.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168254.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168255.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae60]
>[168255.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae60] width 1920 pitch 7680 (/4 1920)
>[168255.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce2f30]
>[168255.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce2f30] width 1920 pitch 7680 (/4 1920)
>[168380.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b140]
>[168380.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b140] width 1920 pitch 7680 (/4 1920)
>[168380.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068e30]
>[168380.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068e30] width 1920 pitch 7680 (/4 1920)
>[168380.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eaab40]
>[168380.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eaab40] width 1920 pitch 7680 (/4 1920)
>[168380.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168380.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168380.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9f240]
>[168380.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9f240] width 1920 pitch 7680 (/4 1920)
>[168380.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168380.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168380.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168380.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168381.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168381.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168381.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168381.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168381.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168381.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168381.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168381.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168382.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168382.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168382.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168382.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168382.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168382.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168382.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168382.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168383.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168383.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168383.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168383.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168383.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168383.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168383.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168383.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168384.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168384.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168384.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[168384.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[168385.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168385.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168385.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168385.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168385.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168385.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168385.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168385.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[168385.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[168385.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e980]
>[168385.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e980] width 1920 pitch 7680 (/4 1920)
>[168433.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168433.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168433.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168433.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168433.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168433.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168433.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168433.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168433.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168433.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168433.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168433.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168433.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168433.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168433.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168433.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168434.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168434.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168434.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168434.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168434.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168434.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168434.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168434.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168435.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168435.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168435.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168435.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168435.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168435.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168435.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168435.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168435.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168435.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168435.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168435.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168435.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168436.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168436.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168436.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168442.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62e40]
>[168442.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62e40] width 1920 pitch 7680 (/4 1920)
>[168453.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168454.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168454.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168454.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168454.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168454.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168454.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168454.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168454.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168454.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168454.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168454.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168454.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168454.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168454.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168454.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168454.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168454.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168454.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168454.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168455.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168455.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168455.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168455.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168455.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62e40]
>[168455.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62e40] width 1920 pitch 7680 (/4 1920)
>[168456.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168456.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168457.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62e40]
>[168457.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62e40] width 1920 pitch 7680 (/4 1920)
>[168457.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c9ec50]
>[168457.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c9ec50] width 1920 pitch 7680 (/4 1920)
>[168457.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62360]
>[168457.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62360] width 1920 pitch 7680 (/4 1920)
>[168457.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62360]
>[168457.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62360] width 1920 pitch 7680 (/4 1920)
>[168457.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62360]
>[168457.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62360] width 1920 pitch 7680 (/4 1920)
>[168457.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62b00]
>[168457.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62b00] width 1920 pitch 7680 (/4 1920)
>[168461.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168461.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168461.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55136d0]
>[168461.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55136d0] width 1920 pitch 7680 (/4 1920)
>[168461.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168461.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168461.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55136d0]
>[168461.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55136d0] width 1920 pitch 7680 (/4 1920)
>[168461.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168461.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168461.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55136d0]
>[168461.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55136d0] width 1920 pitch 7680 (/4 1920)
>[168462.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168462.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168462.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55136d0]
>[168462.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55136d0] width 1920 pitch 7680 (/4 1920)
>[168462.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168462.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168462.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55136d0]
>[168462.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55136d0] width 1920 pitch 7680 (/4 1920)
>[168462.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168462.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168462.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168462.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168462.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168462.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168462.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168462.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168462.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168462.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168462.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50efa50]
>[168462.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50efa50] width 1920 pitch 7680 (/4 1920)
>[168463.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513e30]
>[168463.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513e30] width 1920 pitch 7680 (/4 1920)
>[168484.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32777b0]
>[168484.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32777b0] width 1920 pitch 7680 (/4 1920)
>[168487.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55154a0]
>[168487.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55154a0] width 1920 pitch 7680 (/4 1920)
>[168487.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[168487.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[168487.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[168487.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[168487.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8780]
>[168487.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8780] width 1920 pitch 7680 (/4 1920)
>[168491.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2b9a0]
>[168491.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2b9a0] width 1920 pitch 7680 (/4 1920)
>[168491.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168491.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168491.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168491.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168491.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50679f0]
>[168491.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50679f0] width 1920 pitch 7680 (/4 1920)
>[168492.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168492.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168492.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168492.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168492.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168492.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168492.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168492.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168492.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168492.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168492.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168492.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168492.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168492.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168492.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168492.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168492.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168492.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168492.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168492.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168493.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168493.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168493.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168493.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168493.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168493.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168493.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168493.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168493.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168493.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168494.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168494.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168494.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168494.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168494.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168494.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168494.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168494.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168494.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168494.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168494.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168494.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168494.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168494.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168494.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168494.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168494.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168494.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168532.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168532.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168532.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168532.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168532.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168532.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168532.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168532.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168532.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168532.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168532.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168532.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168532.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168532.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168532.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168532.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168532.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168532.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168532.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168532.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168533.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168533.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168533.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168533.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168533.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168533.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168533.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168533.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168533.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168533.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168534.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168534.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168534.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168534.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168534.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168534.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168534.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168534.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168534.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168534.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168534.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168534.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168534.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3be0]
>[168534.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3be0] width 1920 pitch 7680 (/4 1920)
>[168534.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168534.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168535.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51970]
>[168535.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51970] width 1920 pitch 7680 (/4 1920)
>[168543.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd3710]
>[168543.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd3710] width 1920 pitch 7680 (/4 1920)
>[168581.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32671b0]
>[168581.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32671b0] width 1920 pitch 7680 (/4 1920)
>[168586.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe280]
>[168586.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe280] width 1920 pitch 7680 (/4 1920)
>[168586.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168586.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168586.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266050]
>[168586.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266050] width 1920 pitch 7680 (/4 1920)
>[168586.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168586.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168586.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266050]
>[168586.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266050] width 1920 pitch 7680 (/4 1920)
>[168586.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa840]
>[168586.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa840] width 1920 pitch 7680 (/4 1920)
>[168586.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd34d0]
>[168586.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd34d0] width 1920 pitch 7680 (/4 1920)
>[168586.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcb460]
>[168586.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcb460] width 1920 pitch 7680 (/4 1920)
>[168586.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd3f50]
>[168586.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd3f50] width 1920 pitch 7680 (/4 1920)
>[168586.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5516ad0]
>[168586.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5516ad0] width 1920 pitch 7680 (/4 1920)
>[168586.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd3f50]
>[168586.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd3f50] width 1920 pitch 7680 (/4 1920)
>[168586.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd3f50]
>[168586.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd3f50] width 1920 pitch 7680 (/4 1920)
>[168586.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45aa840]
>[168586.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45aa840] width 1920 pitch 7680 (/4 1920)
>[168586.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da4480]
>[168586.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da4480] width 1920 pitch 7680 (/4 1920)
>[168590.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51970]
>[168590.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51970] width 1920 pitch 7680 (/4 1920)
>[168590.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe220]
>[168590.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe220] width 1920 pitch 7680 (/4 1920)
>[168590.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c1b0]
>[168590.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c1b0] width 1920 pitch 7680 (/4 1920)
>[168590.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168590.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168590.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3305710]
>[168590.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3305710] width 1920 pitch 7680 (/4 1920)
>[168590.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ba5190]
>[168590.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ba5190] width 1920 pitch 7680 (/4 1920)
>[168590.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30530]
>[168590.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30530] width 1920 pitch 7680 (/4 1920)
>[168590.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd8d0]
>[168590.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd8d0] width 1920 pitch 7680 (/4 1920)
>[168590.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c1b0]
>[168590.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c1b0] width 1920 pitch 7680 (/4 1920)
>[168590.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2eb20]
>[168590.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2eb20] width 1920 pitch 7680 (/4 1920)
>[168590.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5513ad0]
>[168590.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5513ad0] width 1920 pitch 7680 (/4 1920)
>[168590.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3265c20]
>[168590.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3265c20] width 1920 pitch 7680 (/4 1920)
>[168593.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c410a0]
>[168593.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c410a0] width 1920 pitch 7680 (/4 1920)
>[168593.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d63710]
>[168593.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d63710] width 1920 pitch 7680 (/4 1920)
>[168593.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168593.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168593.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168593.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168593.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168593.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168593.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168593.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168593.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168593.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168594.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168594.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168594.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168594.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168594.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168594.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168594.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168594.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168594.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168594.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168594.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168594.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168594.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3287030]
>[168594.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3287030] width 1920 pitch 7680 (/4 1920)
>[168594.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168594.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168595.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eaef30]
>[168595.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eaef30] width 1920 pitch 7680 (/4 1920)
>[168595.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51970]
>[168595.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51970] width 1920 pitch 7680 (/4 1920)
>[168595.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3346210]
>[168595.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3346210] width 1920 pitch 7680 (/4 1920)
>[168634.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da28b0]
>[168634.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da28b0] width 1920 pitch 7680 (/4 1920)
>[168639.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084b30]
>[168639.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084b30] width 1920 pitch 7680 (/4 1920)
>[168639.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c750]
>[168639.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c750] width 1920 pitch 7680 (/4 1920)
>[168639.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084b30]
>[168639.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084b30] width 1920 pitch 7680 (/4 1920)
>[168639.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3342bc0]
>[168639.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3342bc0] width 1920 pitch 7680 (/4 1920)
>[168667.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550ee90]
>[168667.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550ee90] width 1920 pitch 7680 (/4 1920)
>[168712.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168712.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168712.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168712.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168712.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168713.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168713.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168713.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b1b0]
>[168713.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b1b0] width 1920 pitch 7680 (/4 1920)
>[168713.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168713.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168713.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168713.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168713.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168713.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168713.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168713.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168713.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168713.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168714.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168714.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168714.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168714.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168714.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168714.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168714.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168714.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168714.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168714.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168714.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47639f0]
>[168714.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47639f0] width 1920 pitch 7680 (/4 1920)
>[168714.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168714.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168714.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168714.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168714.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507b8d0]
>[168714.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507b8d0] width 1920 pitch 7680 (/4 1920)
>[168714.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50c80]
>[168714.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50c80] width 1920 pitch 7680 (/4 1920)
>[168723.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b0c0]
>[168723.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b0c0] width 1920 pitch 7680 (/4 1920)
>[168742.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f96b0]
>[168742.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f96b0] width 1920 pitch 7680 (/4 1920)
>[168742.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168742.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168742.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168742.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168742.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168743.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168743.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168743.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168743.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168743.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168743.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168743.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168743.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168743.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168743.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168743.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168743.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168743.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168743.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168743.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168744.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168744.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168744.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168744.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168744.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[168744.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[168745.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc830]
>[168745.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc830] width 1920 pitch 7680 (/4 1920)
>[168745.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47639f0]
>[168745.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47639f0] width 1920 pitch 7680 (/4 1920)
>[168745.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47639f0]
>[168745.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47639f0] width 1920 pitch 7680 (/4 1920)
>[168745.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322b0b0]
>[168745.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322b0b0] width 1920 pitch 7680 (/4 1920)
>[168745.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47639f0]
>[168745.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47639f0] width 1920 pitch 7680 (/4 1920)
>[168772.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168772.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168772.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168772.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168772.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168772.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168772.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168773.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168773.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168773.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168773.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168773.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168773.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168773.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168773.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168773.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168773.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168773.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168773.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168773.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168773.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168773.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d4a0]
>[168773.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d4a0] width 1920 pitch 7680 (/4 1920)
>[168774.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef8d10]
>[168774.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef8d10] width 1920 pitch 7680 (/4 1920)
>[168774.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168774.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168774.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168774.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168775.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168775.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168775.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168775.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168775.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168775.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168775.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168775.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168775.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168776.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168776.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168776.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168776.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168776.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168776.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168777.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168777.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168778.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168778.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168779.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168779.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168780.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168780.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168781.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105680]
>[168781.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105680] width 1920 pitch 7680 (/4 1920)
>[168782.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f250]
>[168782.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f250] width 1920 pitch 7680 (/4 1920)
>[168782.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168782.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168782.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45b8030]
>[168782.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45b8030] width 1920 pitch 7680 (/4 1920)
>[168782.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49fd0]
>[168782.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49fd0] width 1920 pitch 7680 (/4 1920)
>[168782.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5d270]
>[168782.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5d270] width 1920 pitch 7680 (/4 1920)
>[168782.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168782.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168782.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168782.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168798.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168798.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168798.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168798.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168798.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168798.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168798.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168798.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168798.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168798.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168798.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168798.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168799.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168799.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168799.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168799.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168799.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168799.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168799.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168799.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168800.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168800.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168800.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168800.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168800.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168800.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168801.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168801.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168801.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168801.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168802.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168802.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168802.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d53690]
>[168802.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d53690] width 1920 pitch 7680 (/4 1920)
>[168802.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168802.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168802.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168802.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168802.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168802.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168802.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168802.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168802.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168802.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168802.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168802.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168804.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168804.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168804.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168804.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168804.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168804.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168804.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168804.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168804.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168804.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168804.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168804.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168804.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168804.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168804.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168804.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168805.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168805.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168805.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168805.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168805.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168805.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168805.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168805.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168806.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168806.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168806.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168806.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168806.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168806.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168806.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168806.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168807.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168807.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168807.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168807.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168816.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168816.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168818.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168819.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168820.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c824b0]
>[168820.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c824b0] width 1920 pitch 7680 (/4 1920)
>[168820.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d48f20]
>[168820.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d48f20] width 1920 pitch 7680 (/4 1920)
>[168820.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168820.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168820.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb8bc0]
>[168820.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb8bc0] width 1920 pitch 7680 (/4 1920)
>[168820.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb37e0]
>[168820.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb37e0] width 1920 pitch 7680 (/4 1920)
>[168820.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb8bc0]
>[168820.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb8bc0] width 1920 pitch 7680 (/4 1920)
>[168820.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e4c0]
>[168820.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e4c0] width 1920 pitch 7680 (/4 1920)
>[168820.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54ecea0]
>[168820.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54ecea0] width 1920 pitch 7680 (/4 1920)
>[168820.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2f200]
>[168820.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2f200] width 1920 pitch 7680 (/4 1920)
>[168820.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2f2b0]
>[168820.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2f2b0] width 1920 pitch 7680 (/4 1920)
>[168833.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557d9f0]
>[168833.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557d9f0] width 1920 pitch 7680 (/4 1920)
>[168833.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557ad90]
>[168833.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557ad90] width 1920 pitch 7680 (/4 1920)
>[168836.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67620]
>[168836.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67620] width 1920 pitch 7680 (/4 1920)
>[168836.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba7d40]
>[168836.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba7d40] width 1920 pitch 7680 (/4 1920)
>[168836.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67620]
>[168836.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67620] width 1920 pitch 7680 (/4 1920)
>[168836.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9c280]
>[168836.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9c280] width 1920 pitch 7680 (/4 1920)
>[168836.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67620]
>[168836.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67620] width 1920 pitch 7680 (/4 1920)
>[168837.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcb910]
>[168837.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcb910] width 1920 pitch 7680 (/4 1920)
>[168837.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ef80]
>[168838.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ef80] width 1920 pitch 7680 (/4 1920)
>[168891.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168891.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168891.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168891.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168891.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168891.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168891.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168891.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168891.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168891.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168891.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168891.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168891.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168891.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168891.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168892.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168892.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168892.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168892.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168892.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168892.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168892.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168892.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168892.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168892.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168893.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168893.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168893.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168893.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168893.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168893.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168893.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168893.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168893.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168893.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d500]
>[168893.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d500] width 1920 pitch 7680 (/4 1920)
>[168893.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168893.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168899.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168899.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168899.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168899.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168899.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168899.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168899.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168899.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168899.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168899.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168899.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168899.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168899.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168899.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168899.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168899.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168900.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168900.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168900.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168900.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168900.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168900.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168900.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168900.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168900.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168900.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168900.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168900.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168900.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168900.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168900.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168900.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168901.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168901.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168901.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168901.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168901.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168901.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168901.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168901.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168901.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168901.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168901.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168901.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168901.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168901.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168902.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168902.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168902.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168902.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168903.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168903.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf2c0]
>[168903.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf2c0] width 1920 pitch 7680 (/4 1920)
>[168903.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168903.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168903.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168903.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168903.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168903.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168903.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168903.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168903.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f3e0]
>[168903.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f3e0] width 1920 pitch 7680 (/4 1920)
>[168903.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168903.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168935.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba50]
>[168935.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba50] width 1920 pitch 7680 (/4 1920)
>[168935.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168935.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168935.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba50]
>[168936.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba50] width 1920 pitch 7680 (/4 1920)
>[168936.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168936.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168936.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba50]
>[168936.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba50] width 1920 pitch 7680 (/4 1920)
>[168936.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168936.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168936.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba50]
>[168936.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba50] width 1920 pitch 7680 (/4 1920)
>[168936.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168936.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168936.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba50]
>[168936.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba50] width 1920 pitch 7680 (/4 1920)
>[168936.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168936.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168937.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbae60]
>[168937.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbae60] width 1920 pitch 7680 (/4 1920)
>[168937.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e44850]
>[168937.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e44850] width 1920 pitch 7680 (/4 1920)
>[168937.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168937.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168937.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168937.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168937.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168937.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168937.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32da080]
>[168937.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32da080] width 1920 pitch 7680 (/4 1920)
>[168937.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168937.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168937.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46fc0]
>[168937.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46fc0] width 1920 pitch 7680 (/4 1920)
>[168937.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168937.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168937.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46fc0]
>[168937.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46fc0] width 1920 pitch 7680 (/4 1920)
>[168937.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168938.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168938.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46fc0]
>[168938.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46fc0] width 1920 pitch 7680 (/4 1920)
>[168938.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168938.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168938.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46fc0]
>[168938.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46fc0] width 1920 pitch 7680 (/4 1920)
>[168938.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168938.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168938.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46fc0]
>[168938.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46fc0] width 1920 pitch 7680 (/4 1920)
>[168938.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168938.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168939.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168939.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168939.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[168939.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[168939.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168939.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168939.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[168939.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[168939.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168939.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168939.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168939.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168939.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5db10]
>[168939.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5db10] width 1920 pitch 7680 (/4 1920)
>[168941.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168941.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168941.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168941.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168941.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168941.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168941.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168941.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168941.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168941.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168941.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168941.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168942.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168942.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168942.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168942.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168942.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168942.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168942.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168942.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168942.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168942.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168943.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7150]
>[168943.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7150] width 1920 pitch 7680 (/4 1920)
>[168943.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d740]
>[168943.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d740] width 1920 pitch 7680 (/4 1920)
>[168943.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168943.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168943.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168943.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168943.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168943.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168943.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168943.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168943.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168943.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168948.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168948.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168948.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168948.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168948.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168948.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168948.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168948.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168948.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168949.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168949.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168949.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168949.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168949.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168949.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168949.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168949.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c7d2a0]
>[168949.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c7d2a0] width 1920 pitch 7680 (/4 1920)
>[168949.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e43bd0]
>[168949.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e43bd0] width 1920 pitch 7680 (/4 1920)
>[168949.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed9f0]
>[168950.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed9f0] width 1920 pitch 7680 (/4 1920)
>[168950.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263100]
>[168950.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263100] width 1920 pitch 7680 (/4 1920)
>[168950.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2f280]
>[168950.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2f280] width 1920 pitch 7680 (/4 1920)
>[168950.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5230]
>[168950.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5230] width 1920 pitch 7680 (/4 1920)
>[168950.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168950.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168977.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335eb50]
>[168977.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335eb50] width 1920 pitch 7680 (/4 1920)
>[168977.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed9f0]
>[168977.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed9f0] width 1920 pitch 7680 (/4 1920)
>[168977.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d2b0]
>[168977.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d2b0] width 1920 pitch 7680 (/4 1920)
>[168977.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed9f0]
>[168977.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed9f0] width 1920 pitch 7680 (/4 1920)
>[168977.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335eb50]
>[168977.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335eb50] width 1920 pitch 7680 (/4 1920)
>[168977.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263100]
>[168977.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263100] width 1920 pitch 7680 (/4 1920)
>[168977.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcff80]
>[168977.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcff80] width 1920 pitch 7680 (/4 1920)
>[168977.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168977.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168977.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcff80]
>[168977.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcff80] width 1920 pitch 7680 (/4 1920)
>[168977.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168977.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168977.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcff80]
>[168977.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcff80] width 1920 pitch 7680 (/4 1920)
>[168977.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168977.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168978.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46e20]
>[168978.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46e20] width 1920 pitch 7680 (/4 1920)
>[168978.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e319c0]
>[168978.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e319c0] width 1920 pitch 7680 (/4 1920)
>[168978.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d760]
>[168978.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d760] width 1920 pitch 7680 (/4 1920)
>[168978.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d760]
>[168978.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d760] width 1920 pitch 7680 (/4 1920)
>[168980.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168980.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168980.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168980.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168980.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168980.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168980.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168980.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168980.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168980.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168980.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168980.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168980.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168980.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168980.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168980.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168980.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168980.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168980.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168980.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168981.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168981.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168981.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168981.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168981.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168981.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168981.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168981.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168981.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168981.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168982.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168982.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168982.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168982.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168982.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168982.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168982.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168982.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168982.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168982.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168982.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168982.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168982.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168982.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168983.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168983.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168983.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168983.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168983.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[168983.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[168983.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168983.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168983.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168983.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168983.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168983.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168983.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[168983.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[168984.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[168984.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[168984.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168984.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168984.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6130]
>[168984.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6130] width 1920 pitch 7680 (/4 1920)
>[168984.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168984.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168984.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6130]
>[168984.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6130] width 1920 pitch 7680 (/4 1920)
>[168984.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168984.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168984.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6130]
>[168984.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6130] width 1920 pitch 7680 (/4 1920)
>[168984.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[168984.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[168984.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6130]
>[168984.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6130] width 1920 pitch 7680 (/4 1920)
>[169113.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169113.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169113.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169113.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169113.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169113.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169113.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169113.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169113.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169113.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169113.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169113.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169113.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169113.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169114.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169114.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169114.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169114.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169114.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169114.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169114.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169114.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169114.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7a190]
>[169115.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7a190] width 1920 pitch 7680 (/4 1920)
>[169115.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169115.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169115.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d2b0]
>[169115.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d2b0] width 1920 pitch 7680 (/4 1920)
>[169115.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e1f0]
>[169115.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e1f0] width 1920 pitch 7680 (/4 1920)
>[169115.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e1f0]
>[169115.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e1f0] width 1920 pitch 7680 (/4 1920)
>[169115.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d2b0]
>[169115.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d2b0] width 1920 pitch 7680 (/4 1920)
>[169115.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506de80]
>[169115.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506de80] width 1920 pitch 7680 (/4 1920)
>[169115.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169115.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169119.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169119.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169119.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc2b0]
>[169119.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc2b0] width 1920 pitch 7680 (/4 1920)
>[169119.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169119.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169119.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc2b0]
>[169119.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc2b0] width 1920 pitch 7680 (/4 1920)
>[169119.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169119.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169119.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc2b0]
>[169119.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc2b0] width 1920 pitch 7680 (/4 1920)
>[169119.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169119.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169119.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc2b0]
>[169119.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc2b0] width 1920 pitch 7680 (/4 1920)
>[169119.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169119.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169119.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169119.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169120.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169120.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169120.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169120.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169120.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fe20]
>[169120.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fe20] width 1920 pitch 7680 (/4 1920)
>[169120.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169120.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169120.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e260]
>[169120.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e260] width 1920 pitch 7680 (/4 1920)
>[169120.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e260]
>[169120.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e260] width 1920 pitch 7680 (/4 1920)
>[169120.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169120.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169120.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3265520]
>[169120.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3265520] width 1920 pitch 7680 (/4 1920)
>[169120.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169120.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169182.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169182.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169182.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169182.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169182.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169182.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169182.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169182.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169182.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169183.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169183.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169183.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169183.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169183.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169183.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169183.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169183.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd35b0]
>[169183.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd35b0] width 1920 pitch 7680 (/4 1920)
>[169183.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e260]
>[169183.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e260] width 1920 pitch 7680 (/4 1920)
>[169184.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2f280]
>[169184.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2f280] width 1920 pitch 7680 (/4 1920)
>[169184.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169184.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169185.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169185.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169185.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169185.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169185.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169185.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169185.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169185.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169185.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169185.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169185.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169185.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169185.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169186.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169186.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169186.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169186.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169186.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169186.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169186.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169268.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169268.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169451.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd27e0]
>[169451.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd27e0] width 1920 pitch 7680 (/4 1920)
>[169451.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169451.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169451.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd27e0]
>[169451.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd27e0] width 1920 pitch 7680 (/4 1920)
>[169451.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169451.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169451.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd27e0]
>[169451.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd27e0] width 1920 pitch 7680 (/4 1920)
>[169451.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169451.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169451.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd27e0]
>[169451.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd27e0] width 1920 pitch 7680 (/4 1920)
>[169451.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169451.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169452.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbae60]
>[169452.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbae60] width 1920 pitch 7680 (/4 1920)
>[169452.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558d2b0]
>[169452.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558d2b0] width 1920 pitch 7680 (/4 1920)
>[169453.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169454.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169454.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169454.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169454.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169454.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169454.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x558ed80]
>[169454.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x558ed80] width 1920 pitch 7680 (/4 1920)
>[169454.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169454.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169454.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a97a0]
>[169454.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a97a0] width 1920 pitch 7680 (/4 1920)
>[169454.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169454.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169454.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a97a0]
>[169454.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a97a0] width 1920 pitch 7680 (/4 1920)
>[169461.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169461.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169461.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169461.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169461.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169461.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169461.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169461.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169461.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169461.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169461.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169461.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169461.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169461.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169461.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169461.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169461.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169461.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169461.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169462.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169462.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3276ca0]
>[169462.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3276ca0] width 1920 pitch 7680 (/4 1920)
>[169462.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7680]
>[169462.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7680] width 1920 pitch 7680 (/4 1920)
>[169462.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7680]
>[169462.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7680] width 1920 pitch 7680 (/4 1920)
>[169462.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c230]
>[169462.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c230] width 1920 pitch 7680 (/4 1920)
>[169462.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7680]
>[169462.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7680] width 1920 pitch 7680 (/4 1920)
>[169481.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a770]
>[169481.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a770] width 1920 pitch 7680 (/4 1920)
>[169501.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[169501.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[170096.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9b50]
>[170096.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9b50] width 1920 pitch 7680 (/4 1920)
>[170096.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170096.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170096.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9b50]
>[170096.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9b50] width 1920 pitch 7680 (/4 1920)
>[170096.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170097.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170097.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170097.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170097.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170097.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170097.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170097.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170097.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170097.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170097.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170097.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170097.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170097.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170097.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170097.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170098.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bbc410]
>[170098.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bbc410] width 1920 pitch 7680 (/4 1920)
>[170098.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170098.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170099.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca3420]
>[170099.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca3420] width 1920 pitch 7680 (/4 1920)
>[170099.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170099.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170099.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170099.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170099.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1b00]
>[170099.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1b00] width 1920 pitch 7680 (/4 1920)
>[170099.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170099.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170099.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170099.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170099.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170099.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170107.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170107.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170107.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170108.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170108.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170108.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170108.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170108.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170108.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170108.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170108.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170108.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170108.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170108.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170108.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170108.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170108.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170108.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170108.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170108.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170108.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170108.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170108.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170109.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170109.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170109.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170109.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170109.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170109.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170109.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170109.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170109.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170109.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170109.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170109.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170109.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170109.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ca3420]
>[170109.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ca3420] width 1920 pitch 7680 (/4 1920)
>[170109.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3224bf0]
>[170109.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3224bf0] width 1920 pitch 7680 (/4 1920)
>[170109.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55120f0]
>[170109.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55120f0] width 1920 pitch 7680 (/4 1920)
>[170235.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170235.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170235.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170235.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170235.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170235.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170235.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170235.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170235.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170235.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170235.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170235.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170235.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170235.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170235.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170235.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170235.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170236.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db9920]
>[170236.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db9920] width 1920 pitch 7680 (/4 1920)
>[170236.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50710]
>[170236.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50710] width 1920 pitch 7680 (/4 1920)
>[170236.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bba0]
>[170236.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bba0] width 1920 pitch 7680 (/4 1920)
>[170236.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9ca00]
>[170236.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9ca00] width 1920 pitch 7680 (/4 1920)
>[170236.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bba0]
>[170236.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bba0] width 1920 pitch 7680 (/4 1920)
>[170236.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9ca00]
>[170236.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9ca00] width 1920 pitch 7680 (/4 1920)
>[170236.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bba0]
>[170236.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bba0] width 1920 pitch 7680 (/4 1920)
>[170236.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b9ca00]
>[170236.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b9ca00] width 1920 pitch 7680 (/4 1920)
>[170236.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bba0]
>[170236.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bba0] width 1920 pitch 7680 (/4 1920)
>[170236.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f390]
>[170236.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f390] width 1920 pitch 7680 (/4 1920)
>[170252.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9b50]
>[170252.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9b50] width 1920 pitch 7680 (/4 1920)
>[170520.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bba0]
>[170520.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bba0] width 1920 pitch 7680 (/4 1920)
>[170523.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170523.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170523.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170523.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170523.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170523.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170523.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170523.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170523.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170523.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170523.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170523.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170523.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170523.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170523.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fb910]
>[170523.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fb910] width 1920 pitch 7680 (/4 1920)
>[170523.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f390]
>[170523.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f390] width 1920 pitch 7680 (/4 1920)
>[170524.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170524.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170524.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f390]
>[170524.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f390] width 1920 pitch 7680 (/4 1920)
>[170524.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170524.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170524.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f390]
>[170524.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f390] width 1920 pitch 7680 (/4 1920)
>[170524.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f390]
>[170524.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f390] width 1920 pitch 7680 (/4 1920)
>[170525.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170525.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170525.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170525.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170525.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed9420]
>[170525.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed9420] width 1920 pitch 7680 (/4 1920)
>[170525.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2b90]
>[170525.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2b90] width 1920 pitch 7680 (/4 1920)
>[170525.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3262db0]
>[170525.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3262db0] width 1920 pitch 7680 (/4 1920)
>[170530.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54dfee0]
>[170530.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54dfee0] width 1920 pitch 7680 (/4 1920)
>[170538.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170538.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170538.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170538.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170538.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170538.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170538.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170538.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170538.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170538.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170538.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170538.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170538.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170538.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170538.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170538.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170539.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170539.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170539.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170539.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170539.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170539.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170539.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170539.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170540.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170540.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170540.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54daab0]
>[170540.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54daab0] width 1920 pitch 7680 (/4 1920)
>[170540.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df210]
>[170540.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df210] width 1920 pitch 7680 (/4 1920)
>[170540.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388020]
>[170540.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388020] width 1920 pitch 7680 (/4 1920)
>[170540.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df2e0]
>[170540.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df2e0] width 1920 pitch 7680 (/4 1920)
>[170540.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df410]
>[170540.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df410] width 1920 pitch 7680 (/4 1920)
>[170540.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df2e0]
>[170540.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df2e0] width 1920 pitch 7680 (/4 1920)
>[170540.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f40e0]
>[170541.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f40e0] width 1920 pitch 7680 (/4 1920)
>[170548.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54df410]
>[170548.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54df410] width 1920 pitch 7680 (/4 1920)
>[170563.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f40e0]
>[170563.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f40e0] width 1920 pitch 7680 (/4 1920)
>[170673.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170673.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170673.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170673.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170673.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170673.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170673.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170673.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170673.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170673.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170673.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170673.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170673.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170673.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170674.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170674.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170674.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170674.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170674.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170674.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170674.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170674.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170674.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e46ff0]
>[170674.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e46ff0] width 1920 pitch 7680 (/4 1920)
>[170674.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5ef0]
>[170674.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5ef0] width 1920 pitch 7680 (/4 1920)
>[170674.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170674.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170675.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5ef0]
>[170675.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5ef0] width 1920 pitch 7680 (/4 1920)
>[170675.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170675.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170675.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5ef0]
>[170675.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5ef0] width 1920 pitch 7680 (/4 1920)
>[170675.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170675.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170675.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170675.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170675.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170675.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170675.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170675.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170675.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170676.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170676.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170676.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170676.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170676.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170676.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170676.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170676.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170676.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170676.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170676.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170677.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170677.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170677.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30780]
>[170677.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30780] width 1920 pitch 7680 (/4 1920)
>[170677.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5930]
>[170677.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5930] width 1920 pitch 7680 (/4 1920)
>[170677.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc540]
>[170677.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc540] width 1920 pitch 7680 (/4 1920)
>[170677.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5860]
>[170677.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5860] width 1920 pitch 7680 (/4 1920)
>[170677.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5860]
>[170677.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5860] width 1920 pitch 7680 (/4 1920)
>[170677.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55027e0]
>[170677.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55027e0] width 1920 pitch 7680 (/4 1920)
>[170677.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55027e0]
>[170677.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55027e0] width 1920 pitch 7680 (/4 1920)
>[171649.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323dda0]
>[171649.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323dda0] width 1920 pitch 7680 (/4 1920)
>[171649.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dec4c0]
>[171649.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dec4c0] width 1920 pitch 7680 (/4 1920)
>[172092.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f24ed0]
>[172092.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f24ed0] width 1920 pitch 7680 (/4 1920)
>[172092.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323dda0]
>[172092.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323dda0] width 1920 pitch 7680 (/4 1920)
>[172213.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[172213.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[172213.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00480]
>[172213.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00480] width 1920 pitch 7680 (/4 1920)
>[175374.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0940]
>[175374.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0940] width 1920 pitch 7680 (/4 1920)
>[175374.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175374.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175374.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175374.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175374.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175374.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175374.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175374.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175374.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175374.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175374.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175374.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175374.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175375.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175375.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175375.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175375.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175375.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175375.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175375.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175375.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db340]
>[175375.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db340] width 1920 pitch 7680 (/4 1920)
>[175375.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175375.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175379.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[175379.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[175379.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dae10]
>[175379.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dae10] width 1920 pitch 7680 (/4 1920)
>[175827.263] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[175827.263] (II) RADEON(0): Using hsync ranges from config file
>[175827.263] (II) RADEON(0): Using vrefresh ranges from config file
>[175827.263] (II) RADEON(0): Printing DDC gathered Modelines:
>[175827.263] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[175827.263] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[175827.263] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[175827.263] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[175827.263] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[175827.263] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[175827.263] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[175917.920] (II) RADEON(0): RADEONSaveScreen(2)
>[175917.921] (II) RADEON(0): RADEONSaveScreen(0)
>[196165.069] (II) RADEON(0): RADEONSaveScreen(1)
>[196188.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5062cf0]
>[196188.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5062cf0] width 1920 pitch 7680 (/4 1920)
>[196188.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33056a0]
>[196188.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33056a0] width 1920 pitch 7680 (/4 1920)
>[196188.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f634f0]
>[196188.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f634f0] width 1920 pitch 7680 (/4 1920)
>[196188.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fc80]
>[196188.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fc80] width 1920 pitch 7680 (/4 1920)
>[196188.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9e770]
>[196188.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9e770] width 1920 pitch 7680 (/4 1920)
>[196188.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196188.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196188.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9e770]
>[196188.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9e770] width 1920 pitch 7680 (/4 1920)
>[196188.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196188.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196188.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9e770]
>[196188.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9e770] width 1920 pitch 7680 (/4 1920)
>[196188.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196188.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196188.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9e770]
>[196188.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9e770] width 1920 pitch 7680 (/4 1920)
>[196188.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196188.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196188.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9e770]
>[196188.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9e770] width 1920 pitch 7680 (/4 1920)
>[196196.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5062cf0]
>[196196.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5062cf0] width 1920 pitch 7680 (/4 1920)
>[196196.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc0390]
>[196196.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc0390] width 1920 pitch 7680 (/4 1920)
>[196196.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196196.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196196.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc0390]
>[196196.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc0390] width 1920 pitch 7680 (/4 1920)
>[196201.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5062cf0]
>[196201.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5062cf0] width 1920 pitch 7680 (/4 1920)
>[196201.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5062cf0]
>[196202.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5062cf0] width 1920 pitch 7680 (/4 1920)
>[196202.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196202.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196202.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196202.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196202.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196202.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196202.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196202.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196202.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196202.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196202.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196202.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196202.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196202.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196202.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196202.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196203.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196203.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196203.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196203.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196203.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196203.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196203.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196203.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196203.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196203.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196203.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196203.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196203.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196203.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196203.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196203.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196204.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196204.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4670ef0]
>[196204.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4670ef0] width 1920 pitch 7680 (/4 1920)
>[196204.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d1c20]
>[196204.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d1c20] width 1920 pitch 7680 (/4 1920)
>[196356.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f8bb50]
>[196356.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f8bb50] width 1920 pitch 7680 (/4 1920)
>[198253.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb7f40]
>[198253.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb7f40] width 1920 pitch 7680 (/4 1920)
>[198637.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebc090]
>[198637.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebc090] width 1920 pitch 7680 (/4 1920)
>[198638.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebc090]
>[198638.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebc090] width 1920 pitch 7680 (/4 1920)
>[198802.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31398f0]
>[198802.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31398f0] width 1920 pitch 7680 (/4 1920)
>[198802.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fe4db0]
>[198802.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fe4db0] width 1920 pitch 7680 (/4 1920)
>[198904.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece4f0]
>[198904.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece4f0] width 1920 pitch 7680 (/4 1920)
>[198904.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece4f0]
>[198904.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece4f0] width 1920 pitch 7680 (/4 1920)
>[199046.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece4f0]
>[199046.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece4f0] width 1920 pitch 7680 (/4 1920)
>[199046.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313de50]
>[199046.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313de50] width 1920 pitch 7680 (/4 1920)
>[199065.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edce30]
>[199065.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edce30] width 1920 pitch 7680 (/4 1920)
>[199065.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebab70]
>[199065.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebab70] width 1920 pitch 7680 (/4 1920)
>[200565.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ff2db0]
>[200565.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ff2db0] width 1920 pitch 7680 (/4 1920)
>[200565.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ff2db0]
>[200565.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ff2db0] width 1920 pitch 7680 (/4 1920)
>[201180.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201180.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201180.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f157a0]
>[201180.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f157a0] width 1920 pitch 7680 (/4 1920)
>[201180.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201180.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201180.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f157a0]
>[201180.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f157a0] width 1920 pitch 7680 (/4 1920)
>[201180.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201180.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201180.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f157a0]
>[201180.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f157a0] width 1920 pitch 7680 (/4 1920)
>[201180.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201180.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201180.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f157a0]
>[201180.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f157a0] width 1920 pitch 7680 (/4 1920)
>[201181.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201181.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201181.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f157a0]
>[201181.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f157a0] width 1920 pitch 7680 (/4 1920)
>[201181.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201181.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201181.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d2410]
>[201181.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d2410] width 1920 pitch 7680 (/4 1920)
>[201181.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201181.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201181.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d2410]
>[201182.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d2410] width 1920 pitch 7680 (/4 1920)
>[201182.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201182.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201182.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d2410]
>[201182.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d2410] width 1920 pitch 7680 (/4 1920)
>[201183.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201183.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201183.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d2410]
>[201183.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d2410] width 1920 pitch 7680 (/4 1920)
>[201183.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31b7d70]
>[201183.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31b7d70] width 1920 pitch 7680 (/4 1920)
>[201183.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49fd0]
>[201183.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49fd0] width 1920 pitch 7680 (/4 1920)
>[201183.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc3470]
>[201183.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc3470] width 1920 pitch 7680 (/4 1920)
>[201183.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49fd0]
>[201183.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49fd0] width 1920 pitch 7680 (/4 1920)
>[201183.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc3470]
>[201184.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc3470] width 1920 pitch 7680 (/4 1920)
>[201184.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53590]
>[201184.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53590] width 1920 pitch 7680 (/4 1920)
>[201185.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f53590]
>[201185.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f53590] width 1920 pitch 7680 (/4 1920)
>[201201.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16a10]
>[201201.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16a10] width 1920 pitch 7680 (/4 1920)
>[201201.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201201.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201201.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac510]
>[201201.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac510] width 1920 pitch 7680 (/4 1920)
>[201201.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201201.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201201.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac510]
>[201201.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac510] width 1920 pitch 7680 (/4 1920)
>[201201.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac510]
>[201201.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac510] width 1920 pitch 7680 (/4 1920)
>[201201.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201201.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201201.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac510]
>[201201.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac510] width 1920 pitch 7680 (/4 1920)
>[201202.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201202.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201202.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201202.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201202.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c6a0]
>[201202.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c6a0] width 1920 pitch 7680 (/4 1920)
>[201202.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201202.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201202.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c6a0]
>[201202.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c6a0] width 1920 pitch 7680 (/4 1920)
>[201203.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201203.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201203.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c6a0]
>[201203.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c6a0] width 1920 pitch 7680 (/4 1920)
>[201203.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201203.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201204.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201204.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201204.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2d0]
>[201204.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2d0] width 1920 pitch 7680 (/4 1920)
>[201204.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2d0]
>[201205.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2d0] width 1920 pitch 7680 (/4 1920)
>[201205.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ac510]
>[201205.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ac510] width 1920 pitch 7680 (/4 1920)
>[201205.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5590540]
>[201205.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5590540] width 1920 pitch 7680 (/4 1920)
>[201205.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201205.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201205.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5590540]
>[201205.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5590540] width 1920 pitch 7680 (/4 1920)
>[201205.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201205.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201205.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5590540]
>[201205.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5590540] width 1920 pitch 7680 (/4 1920)
>[201205.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084de0]
>[201205.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084de0] width 1920 pitch 7680 (/4 1920)
>[201249.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201249.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201249.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201249.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201249.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201249.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201249.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201249.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201249.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201249.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201249.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201249.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201249.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201249.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201249.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201249.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201249.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201249.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201250.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201250.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201250.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201250.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201250.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201250.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201250.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6190]
>[201250.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6190] width 1920 pitch 7680 (/4 1920)
>[201250.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201250.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201250.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dda70]
>[201250.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dda70] width 1920 pitch 7680 (/4 1920)
>[201250.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6260]
>[201250.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6260] width 1920 pitch 7680 (/4 1920)
>[201250.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dda70]
>[201250.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dda70] width 1920 pitch 7680 (/4 1920)
>[201250.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e6260]
>[201250.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e6260] width 1920 pitch 7680 (/4 1920)
>[201251.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557afb0]
>[201251.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557afb0] width 1920 pitch 7680 (/4 1920)
>[201266.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a09a0]
>[201266.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a09a0] width 1920 pitch 7680 (/4 1920)
>[201271.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16a10]
>[201271.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16a10] width 1920 pitch 7680 (/4 1920)
>[201273.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201273.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201273.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201273.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201273.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201273.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201273.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201273.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201273.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201273.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201273.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201273.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201273.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201273.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201273.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201273.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201273.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201274.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201274.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201274.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201274.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201274.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201274.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201275.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201275.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201275.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201275.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201275.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201275.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201276.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201276.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201276.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55719e0]
>[201276.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55719e0] width 1920 pitch 7680 (/4 1920)
>[201277.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16a10]
>[201277.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16a10] width 1920 pitch 7680 (/4 1920)
>[201277.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d9690]
>[201277.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d9690] width 1920 pitch 7680 (/4 1920)
>[201277.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16a10]
>[201277.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16a10] width 1920 pitch 7680 (/4 1920)
>[201277.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4e490]
>[201277.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4e490] width 1920 pitch 7680 (/4 1920)
>[201277.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201277.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201277.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e2cb0]
>[201277.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e2cb0] width 1920 pitch 7680 (/4 1920)
>[201277.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee2f0]
>[201277.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee2f0] width 1920 pitch 7680 (/4 1920)
>[201303.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776a50]
>[201303.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776a50] width 1920 pitch 7680 (/4 1920)
>[201304.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f85b0]
>[201304.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f85b0] width 1920 pitch 7680 (/4 1920)
>[201304.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b05970]
>[201304.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b05970] width 1920 pitch 7680 (/4 1920)
>[201483.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddced0]
>[201483.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddced0] width 1920 pitch 7680 (/4 1920)
>[201483.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddced0]
>[201483.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddced0] width 1920 pitch 7680 (/4 1920)
>[201583.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e5840]
>[201583.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e5840] width 1920 pitch 7680 (/4 1920)
>[201583.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e5840]
>[201583.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e5840] width 1920 pitch 7680 (/4 1920)
>[201583.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e5840]
>[201583.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e5840] width 1920 pitch 7680 (/4 1920)
>[201583.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e5840]
>[201583.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e5840] width 1920 pitch 7680 (/4 1920)
>[201583.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30dfd00]
>[201583.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30dfd00] width 1920 pitch 7680 (/4 1920)
>[201583.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e5840]
>[201583.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e5840] width 1920 pitch 7680 (/4 1920)
>[201588.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f0d90]
>[201588.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f0d90] width 1920 pitch 7680 (/4 1920)
>[201588.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201670]
>[201588.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201670] width 1920 pitch 7680 (/4 1920)
>[201588.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277570]
>[201588.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277570] width 1920 pitch 7680 (/4 1920)
>[201588.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201670]
>[201588.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201670] width 1920 pitch 7680 (/4 1920)
>[201588.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557aff0]
>[201588.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557aff0] width 1920 pitch 7680 (/4 1920)
>[201588.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201670]
>[201588.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201670] width 1920 pitch 7680 (/4 1920)
>[201588.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557aff0]
>[201588.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557aff0] width 1920 pitch 7680 (/4 1920)
>[201588.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201670]
>[201588.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201670] width 1920 pitch 7680 (/4 1920)
>[201589.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557aff0]
>[201589.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557aff0] width 1920 pitch 7680 (/4 1920)
>[201589.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201670]
>[201589.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201670] width 1920 pitch 7680 (/4 1920)
>[201589.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557aff0]
>[201589.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557aff0] width 1920 pitch 7680 (/4 1920)
>[201675.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47772e0]
>[201675.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47772e0] width 1920 pitch 7680 (/4 1920)
>[201675.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3201250]
>[201675.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3201250] width 1920 pitch 7680 (/4 1920)
>[201726.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1d530]
>[201726.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1d530] width 1920 pitch 7680 (/4 1920)
>[201727.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[201727.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[201814.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201814.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201814.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201814.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201814.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9bd0]
>[201814.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9bd0] width 1920 pitch 7680 (/4 1920)
>[201814.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201814.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201814.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9bd0]
>[201814.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9bd0] width 1920 pitch 7680 (/4 1920)
>[201814.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201814.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201814.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201814.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201814.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201814.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201814.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201814.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201819.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201819.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201819.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201819.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201819.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201819.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201819.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201819.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201819.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201819.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201819.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201819.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201823.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201823.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201823.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201823.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201823.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201823.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201823.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201823.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b079a0]
>[201823.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b079a0] width 1920 pitch 7680 (/4 1920)
>[201823.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[201823.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20740]
>[201823.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20740] width 1920 pitch 7680 (/4 1920)
>[201823.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef17c0]
>[201823.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef17c0] width 1920 pitch 7680 (/4 1920)
>[202046.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9b90]
>[202046.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9b90] width 1920 pitch 7680 (/4 1920)
>[202046.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277510]
>[202046.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277510] width 1920 pitch 7680 (/4 1920)
>[202046.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9b90]
>[202046.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9b90] width 1920 pitch 7680 (/4 1920)
>[202046.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277510]
>[202046.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277510] width 1920 pitch 7680 (/4 1920)
>[202046.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fbc60]
>[202046.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fbc60] width 1920 pitch 7680 (/4 1920)
>[202046.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277510]
>[202046.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277510] width 1920 pitch 7680 (/4 1920)
>[202046.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084dc0]
>[202046.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084dc0] width 1920 pitch 7680 (/4 1920)
>[202046.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31beb90]
>[202046.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31beb90] width 1920 pitch 7680 (/4 1920)
>[202046.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31beb90]
>[202046.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31beb90] width 1920 pitch 7680 (/4 1920)
>[202046.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20900]
>[202046.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20900] width 1920 pitch 7680 (/4 1920)
>[202046.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47210]
>[202046.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47210] width 1920 pitch 7680 (/4 1920)
>[202050.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202050.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cbe0]
>[202050.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cbe0] width 1920 pitch 7680 (/4 1920)
>[202050.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5510f10]
>[202050.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5510f10] width 1920 pitch 7680 (/4 1920)
>[202117.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47180]
>[202117.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47180] width 1920 pitch 7680 (/4 1920)
>[202117.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47180]
>[202117.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47180] width 1920 pitch 7680 (/4 1920)
>[202134.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202134.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202134.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202134.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202134.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202134.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202134.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202134.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202134.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202134.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202134.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202134.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202134.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202134.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202135.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202135.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202135.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202135.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202135.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202135.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202135.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202135.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202135.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202135.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202136.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202136.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202136.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202136.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202137.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202137.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202137.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202137.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202138.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202138.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202138.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202138.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202138.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202138.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202138.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202138.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202138.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fc1770]
>[202138.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fc1770] width 1920 pitch 7680 (/4 1920)
>[202138.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202138.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202138.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202138.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202142.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5591e00]
>[202142.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5591e00] width 1920 pitch 7680 (/4 1920)
>[202142.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315f880]
>[202142.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315f880] width 1920 pitch 7680 (/4 1920)
>[202142.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202142.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202142.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202142.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202142.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202142.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202142.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202142.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202142.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202142.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202142.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202142.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202142.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202142.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202142.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202142.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202143.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202143.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202143.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202143.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202143.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4dc0]
>[202143.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4dc0] width 1920 pitch 7680 (/4 1920)
>[202143.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3e990]
>[202143.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3e990] width 1920 pitch 7680 (/4 1920)
>[202143.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9a50]
>[202143.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9a50] width 1920 pitch 7680 (/4 1920)
>[202143.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b17d0]
>[202143.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b17d0] width 1920 pitch 7680 (/4 1920)
>[202143.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9a50]
>[202143.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9a50] width 1920 pitch 7680 (/4 1920)
>[202143.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b17d0]
>[202143.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b17d0] width 1920 pitch 7680 (/4 1920)
>[202143.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9a50]
>[202143.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9a50] width 1920 pitch 7680 (/4 1920)
>[202144.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e63d0]
>[202144.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e63d0] width 1920 pitch 7680 (/4 1920)
>[202144.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30e63d0]
>[202144.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30e63d0] width 1920 pitch 7680 (/4 1920)
>[202181.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5591e00]
>[202181.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5591e00] width 1920 pitch 7680 (/4 1920)
>[202181.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202181.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202181.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202181.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202181.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202181.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202181.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202181.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202181.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202181.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202181.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202181.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202181.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202181.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202181.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202181.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202181.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202182.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202182.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202182.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202182.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202182.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202182.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f000]
>[202182.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f000] width 1920 pitch 7680 (/4 1920)
>[202182.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f15e00]
>[202182.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f15e00] width 1920 pitch 7680 (/4 1920)
>[202182.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5591e00]
>[202182.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5591e00] width 1920 pitch 7680 (/4 1920)
>[202182.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5591e00]
>[202182.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5591e00] width 1920 pitch 7680 (/4 1920)
>[202182.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315f880]
>[202182.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315f880] width 1920 pitch 7680 (/4 1920)
>[202183.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5591e00]
>[202183.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5591e00] width 1920 pitch 7680 (/4 1920)
>[202185.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30a57a0]
>[202185.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30a57a0] width 1920 pitch 7680 (/4 1920)
>[202304.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202304.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202304.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5529130]
>[202304.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5529130] width 1920 pitch 7680 (/4 1920)
>[202304.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202304.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202304.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bd80]
>[202304.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bd80] width 1920 pitch 7680 (/4 1920)
>[202304.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202304.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202304.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bd80]
>[202304.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bd80] width 1920 pitch 7680 (/4 1920)
>[202304.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202305.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202305.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776ff0]
>[202305.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776ff0] width 1920 pitch 7680 (/4 1920)
>[202305.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202305.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202305.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bd80]
>[202305.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bd80] width 1920 pitch 7680 (/4 1920)
>[202305.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b9b0]
>[202305.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b9b0] width 1920 pitch 7680 (/4 1920)
>[202305.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776ff0]
>[202305.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776ff0] width 1920 pitch 7680 (/4 1920)
>[202309.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202309.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202309.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202309.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3277000]
>[202309.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3277000] width 1920 pitch 7680 (/4 1920)
>[202310.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202310.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202310.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddebe0]
>[202310.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddebe0] width 1920 pitch 7680 (/4 1920)
>[202310.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202310.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202310.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddebe0]
>[202310.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddebe0] width 1920 pitch 7680 (/4 1920)
>[202310.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4776e80]
>[202310.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4776e80] width 1920 pitch 7680 (/4 1920)
>[202310.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315f760]
>[202310.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315f760] width 1920 pitch 7680 (/4 1920)
>[202310.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddebe0]
>[202310.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddebe0] width 1920 pitch 7680 (/4 1920)
>[202310.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315f760]
>[202310.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315f760] width 1920 pitch 7680 (/4 1920)
>[202310.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddebe0]
>[202310.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddebe0] width 1920 pitch 7680 (/4 1920)
>[202310.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315f760]
>[202310.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315f760] width 1920 pitch 7680 (/4 1920)
>[202310.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33743a0]
>[202310.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33743a0] width 1920 pitch 7680 (/4 1920)
>[202314.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202314.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202314.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202314.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202314.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202314.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202314.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202314.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202314.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202314.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202314.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202314.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202314.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202314.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202314.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202314.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202314.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202314.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202314.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202314.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202315.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202315.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202315.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec610]
>[202315.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec610] width 1920 pitch 7680 (/4 1920)
>[202315.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b053c0]
>[202315.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b053c0] width 1920 pitch 7680 (/4 1920)
>[202426.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47771a0]
>[202426.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47771a0] width 1920 pitch 7680 (/4 1920)
>[202426.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202426.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202426.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1f00]
>[202426.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1f00] width 1920 pitch 7680 (/4 1920)
>[202426.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ab40]
>[202426.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ab40] width 1920 pitch 7680 (/4 1920)
>[202426.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddedc0]
>[202426.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddedc0] width 1920 pitch 7680 (/4 1920)
>[202426.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ab40]
>[202426.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ab40] width 1920 pitch 7680 (/4 1920)
>[202426.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202426.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202426.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddedc0]
>[202426.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddedc0] width 1920 pitch 7680 (/4 1920)
>[202426.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0a870]
>[202426.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0a870] width 1920 pitch 7680 (/4 1920)
>[202426.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f440]
>[202426.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f440] width 1920 pitch 7680 (/4 1920)
>[202426.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0a870]
>[202426.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0a870] width 1920 pitch 7680 (/4 1920)
>[202430.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202430.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202430.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202430.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f18940]
>[202430.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f18940] width 1920 pitch 7680 (/4 1920)
>[202609.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55292e0]
>[202609.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55292e0] width 1920 pitch 7680 (/4 1920)
>[202609.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1a30]
>[202609.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1a30] width 1920 pitch 7680 (/4 1920)
>[202609.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0cc60]
>[202609.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0cc60] width 1920 pitch 7680 (/4 1920)
>[202609.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc9d00]
>[202609.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc9d00] width 1920 pitch 7680 (/4 1920)
>[202609.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b082e0]
>[202609.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b082e0] width 1920 pitch 7680 (/4 1920)
>[202609.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31beb40]
>[202609.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31beb40] width 1920 pitch 7680 (/4 1920)
>[202609.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec3b0]
>[202609.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec3b0] width 1920 pitch 7680 (/4 1920)
>[202609.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1d20]
>[202609.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1d20] width 1920 pitch 7680 (/4 1920)
>[202609.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ec3b0]
>[202609.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ec3b0] width 1920 pitch 7680 (/4 1920)
>[202609.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1d20]
>[202609.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1d20] width 1920 pitch 7680 (/4 1920)
>[202613.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202613.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202613.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202613.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202613.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202613.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202613.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202613.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202613.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202613.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202613.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202613.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202613.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202613.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202613.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202614.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202614.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202614.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202614.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202614.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202614.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202614.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202614.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202614.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202614.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32775f0]
>[202614.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32775f0] width 1920 pitch 7680 (/4 1920)
>[202614.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202614.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202718.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0ce70]
>[202718.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0ce70] width 1920 pitch 7680 (/4 1920)
>[202718.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b048b0]
>[202718.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b048b0] width 1920 pitch 7680 (/4 1920)
>[202718.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b048b0]
>[202718.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b048b0] width 1920 pitch 7680 (/4 1920)
>[202718.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f440]
>[202718.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f440] width 1920 pitch 7680 (/4 1920)
>[202718.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b048b0]
>[202718.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b048b0] width 1920 pitch 7680 (/4 1920)
>[202718.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2e950]
>[202718.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2e950] width 1920 pitch 7680 (/4 1920)
>[202718.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b048b0]
>[202718.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b048b0] width 1920 pitch 7680 (/4 1920)
>[202718.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2e950]
>[202718.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2e950] width 1920 pitch 7680 (/4 1920)
>[202718.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b048b0]
>[202719.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b048b0] width 1920 pitch 7680 (/4 1920)
>[202719.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2e950]
>[202719.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2e950] width 1920 pitch 7680 (/4 1920)
>[202719.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f440]
>[202719.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f440] width 1920 pitch 7680 (/4 1920)
>[202719.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2e950]
>[202719.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2e950] width 1920 pitch 7680 (/4 1920)
>[202723.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202723.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32016b0]
>[202723.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32016b0] width 1920 pitch 7680 (/4 1920)
>[202723.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509f020]
>[202723.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509f020] width 1920 pitch 7680 (/4 1920)
>[202737.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1660]
>[202737.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1660] width 1920 pitch 7680 (/4 1920)
>[202737.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1660]
>[202737.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1660] width 1920 pitch 7680 (/4 1920)
>[202737.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1660]
>[202737.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1660] width 1920 pitch 7680 (/4 1920)
>[202737.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202737.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202737.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202737.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202737.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202737.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202737.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202737.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202737.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[202737.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[202737.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1dc0]
>[202737.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1dc0] width 1920 pitch 7680 (/4 1920)
>[202737.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b04fa0]
>[202737.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b04fa0] width 1920 pitch 7680 (/4 1920)
>[202737.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202737.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202737.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b04fa0]
>[202737.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b04fa0] width 1920 pitch 7680 (/4 1920)
>[202737.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202737.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202737.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b04fa0]
>[202737.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b04fa0] width 1920 pitch 7680 (/4 1920)
>[202737.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202737.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202738.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1dc0]
>[202738.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1dc0] width 1920 pitch 7680 (/4 1920)
>[202738.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202738.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202738.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202738.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202738.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202738.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202738.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202738.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202739.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1dc0]
>[202739.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1dc0] width 1920 pitch 7680 (/4 1920)
>[202739.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202739.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202739.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202739.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202739.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202739.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202739.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202739.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202739.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202739.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202739.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202739.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202739.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202739.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202739.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f07b0]
>[202739.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f07b0] width 1920 pitch 7680 (/4 1920)
>[202741.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[202741.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[202741.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[202741.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bc90]
>[202741.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bc90] width 1920 pitch 7680 (/4 1920)
>[203310.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[203310.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[203310.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[203310.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[203310.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee500]
>[203310.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee500] width 1920 pitch 7680 (/4 1920)
>[203310.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddeb20]
>[203310.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddeb20] width 1920 pitch 7680 (/4 1920)
>[203310.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edda60]
>[203310.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edda60] width 1920 pitch 7680 (/4 1920)
>[203310.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee500]
>[203310.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee500] width 1920 pitch 7680 (/4 1920)
>[203310.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f02f0]
>[203310.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f02f0] width 1920 pitch 7680 (/4 1920)
>[203310.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edda60]
>[203310.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edda60] width 1920 pitch 7680 (/4 1920)
>[203310.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ee500]
>[203310.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ee500] width 1920 pitch 7680 (/4 1920)
>[203310.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddeb20]
>[203310.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddeb20] width 1920 pitch 7680 (/4 1920)
>[203310.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f02f0]
>[203310.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f02f0] width 1920 pitch 7680 (/4 1920)
>[203311.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edda60]
>[203311.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edda60] width 1920 pitch 7680 (/4 1920)
>[203311.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebde30]
>[203311.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebde30] width 1920 pitch 7680 (/4 1920)
>[203311.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e1dc0]
>[203311.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e1dc0] width 1920 pitch 7680 (/4 1920)
>[203311.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee540]
>[203311.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee540] width 1920 pitch 7680 (/4 1920)
>[203311.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[203311.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[203311.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[203311.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[203311.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49db0]
>[203311.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49db0] width 1920 pitch 7680 (/4 1920)
>[203311.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf5e90]
>[203311.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf5e90] width 1920 pitch 7680 (/4 1920)
>[203311.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[203311.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[203311.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[203311.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[203311.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102cd0]
>[203311.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102cd0] width 1920 pitch 7680 (/4 1920)
>[203315.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3cd0]
>[203315.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3cd0] width 1920 pitch 7680 (/4 1920)
>[203315.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[203315.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[203315.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3cd0]
>[203315.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3cd0] width 1920 pitch 7680 (/4 1920)
>[203315.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[203315.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[203315.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[203315.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[203315.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31090]
>[203315.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31090] width 1920 pitch 7680 (/4 1920)
>[203315.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49db0]
>[203315.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49db0] width 1920 pitch 7680 (/4 1920)
>[203315.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[203315.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[203315.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fdc0]
>[203315.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fdc0] width 1920 pitch 7680 (/4 1920)
>[203315.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdac0]
>[203315.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdac0] width 1920 pitch 7680 (/4 1920)
>[203316.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[203316.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[203316.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[203316.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[203316.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[203316.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[203316.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f49db0]
>[203316.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f49db0] width 1920 pitch 7680 (/4 1920)
>[203317.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[203317.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[203317.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[203317.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[203317.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45bbb40]
>[203317.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45bbb40] width 1920 pitch 7680 (/4 1920)
>[203317.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b7e180]
>[203317.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b7e180] width 1920 pitch 7680 (/4 1920)
>[203317.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9fdc0]
>[203317.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9fdc0] width 1920 pitch 7680 (/4 1920)
>[203317.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3cd0]
>[203317.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3cd0] width 1920 pitch 7680 (/4 1920)
>[203317.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102cd0]
>[203317.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102cd0] width 1920 pitch 7680 (/4 1920)
>[203317.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d65110]
>[203317.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d65110] width 1920 pitch 7680 (/4 1920)
>[203317.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c01230]
>[203317.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c01230] width 1920 pitch 7680 (/4 1920)
>[203317.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[203317.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[205304.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[205305.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[205305.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[205305.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[205305.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eb6d0]
>[205305.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eb6d0] width 1920 pitch 7680 (/4 1920)
>[205366.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e74540]
>[205366.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e74540] width 1920 pitch 7680 (/4 1920)
>[205451.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205451.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205451.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205451.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205451.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205451.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205451.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4773290]
>[205451.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4773290] width 1920 pitch 7680 (/4 1920)
>[205451.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205451.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205451.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5d540]
>[205451.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5d540] width 1920 pitch 7680 (/4 1920)
>[205451.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205451.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205451.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205451.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205451.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205451.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205456.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205456.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205456.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205456.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205456.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205456.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205456.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fcf0]
>[205457.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fcf0] width 1920 pitch 7680 (/4 1920)
>[205457.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e60960]
>[205458.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e60960] width 1920 pitch 7680 (/4 1920)
>[205458.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e609c0]
>[205458.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e609c0] width 1920 pitch 7680 (/4 1920)
>[205458.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205458.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205458.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5fb10]
>[205458.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5fb10] width 1920 pitch 7680 (/4 1920)
>[205458.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e5eb00]
>[205458.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e5eb00] width 1920 pitch 7680 (/4 1920)
>[205458.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e60380]
>[205458.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e60380] width 1920 pitch 7680 (/4 1920)
>[205458.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e60960]
>[205458.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e60960] width 1920 pitch 7680 (/4 1920)
>[205458.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308fe90]
>[205458.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308fe90] width 1920 pitch 7680 (/4 1920)
>[205515.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e60960]
>[205515.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e60960] width 1920 pitch 7680 (/4 1920)
>[205515.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078200]
>[205515.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078200] width 1920 pitch 7680 (/4 1920)
>[205515.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078200]
>[205515.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078200] width 1920 pitch 7680 (/4 1920)
>[205515.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e609c0]
>[205515.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e609c0] width 1920 pitch 7680 (/4 1920)
>[205516.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078980]
>[205516.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078980] width 1920 pitch 7680 (/4 1920)
>[205516.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078200]
>[205516.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078200] width 1920 pitch 7680 (/4 1920)
>[205516.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078200]
>[205516.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078200] width 1920 pitch 7680 (/4 1920)
>[205516.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205516.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205516.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205517.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205517.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3078200]
>[205517.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3078200] width 1920 pitch 7680 (/4 1920)
>[205517.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205517.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205518.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4e330]
>[205518.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4e330] width 1920 pitch 7680 (/4 1920)
>[205518.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30aa680]
>[205518.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30aa680] width 1920 pitch 7680 (/4 1920)
>[205518.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30aa680]
>[205518.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30aa680] width 1920 pitch 7680 (/4 1920)
>[205518.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30aa680]
>[205518.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30aa680] width 1920 pitch 7680 (/4 1920)
>[205518.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205518.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205518.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205518.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205518.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205518.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30aa680]
>[205518.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30aa680] width 1920 pitch 7680 (/4 1920)
>[205518.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2de40]
>[205518.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2de40] width 1920 pitch 7680 (/4 1920)
>[205518.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2de40]
>[205519.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2de40] width 1920 pitch 7680 (/4 1920)
>[205519.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205519.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205519.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2de40]
>[205519.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2de40] width 1920 pitch 7680 (/4 1920)
>[205519.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205519.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205519.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ae6b0]
>[205519.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ae6b0] width 1920 pitch 7680 (/4 1920)
>[205519.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b0d770]
>[205519.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b0d770] width 1920 pitch 7680 (/4 1920)
>[205519.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30ada30]
>[205519.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30ada30] width 1920 pitch 7680 (/4 1920)
>[205519.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309a110]
>[205519.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309a110] width 1920 pitch 7680 (/4 1920)
>[205519.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309a650]
>[205519.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309a650] width 1920 pitch 7680 (/4 1920)
>[205519.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddc0e0]
>[205519.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddc0e0] width 1920 pitch 7680 (/4 1920)
>[205556.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3071380]
>[205556.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3071380] width 1920 pitch 7680 (/4 1920)
>[205561.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5596160]
>[205561.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5596160] width 1920 pitch 7680 (/4 1920)
>[205561.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5595730]
>[205561.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5595730] width 1920 pitch 7680 (/4 1920)
>[205561.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306ffb0]
>[205561.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306ffb0] width 1920 pitch 7680 (/4 1920)
>[205561.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5595730]
>[205561.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5595730] width 1920 pitch 7680 (/4 1920)
>[205562.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3093370]
>[205562.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3093370] width 1920 pitch 7680 (/4 1920)
>[205562.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee870]
>[205562.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee870] width 1920 pitch 7680 (/4 1920)
>[205585.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30654d0]
>[205585.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30654d0] width 1920 pitch 7680 (/4 1920)
>[205614.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3061ab0]
>[205614.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3061ab0] width 1920 pitch 7680 (/4 1920)
>[205614.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c5c0]
>[205614.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c5c0] width 1920 pitch 7680 (/4 1920)
>[205614.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3061ab0]
>[205614.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3061ab0] width 1920 pitch 7680 (/4 1920)
>[205614.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306c5c0]
>[205614.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306c5c0] width 1920 pitch 7680 (/4 1920)
>[205674.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3086780]
>[205674.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3086780] width 1920 pitch 7680 (/4 1920)
>[205714.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310ace0]
>[205714.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310ace0] width 1920 pitch 7680 (/4 1920)
>[206459.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206459.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206459.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206459.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206459.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206459.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206459.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206459.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206459.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206460.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206460.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206460.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206460.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206460.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206460.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206460.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206460.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206460.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206460.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206460.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206460.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206460.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206460.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206460.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206460.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206460.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206460.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b316b0]
>[206460.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b316b0] width 1920 pitch 7680 (/4 1920)
>[206461.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3271ea0]
>[206461.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3271ea0] width 1920 pitch 7680 (/4 1920)
>[206461.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537570]
>[206461.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537570] width 1920 pitch 7680 (/4 1920)
>[206461.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3271ea0]
>[206461.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3271ea0] width 1920 pitch 7680 (/4 1920)
>[206461.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[206461.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[206461.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3271ea0]
>[206461.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3271ea0] width 1920 pitch 7680 (/4 1920)
>[206461.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d492f0]
>[206461.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d492f0] width 1920 pitch 7680 (/4 1920)
>[206461.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d492f0]
>[206461.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d492f0] width 1920 pitch 7680 (/4 1920)
>[206511.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303dd40]
>[206511.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303dd40] width 1920 pitch 7680 (/4 1920)
>[206566.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552aa70]
>[206566.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552aa70] width 1920 pitch 7680 (/4 1920)
>[206566.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5270]
>[206566.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5270] width 1920 pitch 7680 (/4 1920)
>[206566.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c340]
>[206567.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c340] width 1920 pitch 7680 (/4 1920)
>[206567.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5270]
>[206567.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5270] width 1920 pitch 7680 (/4 1920)
>[206567.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c340]
>[206567.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c340] width 1920 pitch 7680 (/4 1920)
>[206567.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552aa70]
>[206567.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552aa70] width 1920 pitch 7680 (/4 1920)
>[206567.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5270]
>[206567.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5270] width 1920 pitch 7680 (/4 1920)
>[206567.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c340]
>[206567.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c340] width 1920 pitch 7680 (/4 1920)
>[206567.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552aa70]
>[206567.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552aa70] width 1920 pitch 7680 (/4 1920)
>[206568.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5270]
>[206568.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5270] width 1920 pitch 7680 (/4 1920)
>[206568.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c340]
>[206568.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c340] width 1920 pitch 7680 (/4 1920)
>[206568.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552aa70]
>[206568.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552aa70] width 1920 pitch 7680 (/4 1920)
>[206568.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5270]
>[206568.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5270] width 1920 pitch 7680 (/4 1920)
>[206568.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310aaa0]
>[206568.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310aaa0] width 1920 pitch 7680 (/4 1920)
>[206568.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310aaa0]
>[206568.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310aaa0] width 1920 pitch 7680 (/4 1920)
>[206568.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fff70]
>[206568.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fff70] width 1920 pitch 7680 (/4 1920)
>[206568.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b510]
>[206568.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b510] width 1920 pitch 7680 (/4 1920)
>[206568.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fff70]
>[206568.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fff70] width 1920 pitch 7680 (/4 1920)
>[206568.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f64db0]
>[206568.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f64db0] width 1920 pitch 7680 (/4 1920)
>[206569.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303c7c0]
>[206569.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303c7c0] width 1920 pitch 7680 (/4 1920)
>[206569.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fff70]
>[206569.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fff70] width 1920 pitch 7680 (/4 1920)
>[206648.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b060]
>[206648.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b060] width 1920 pitch 7680 (/4 1920)
>[206648.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5537290]
>[206648.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5537290] width 1920 pitch 7680 (/4 1920)
>[206648.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206648.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206648.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206648.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206648.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206648.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206648.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206648.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206648.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206648.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206648.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206648.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206652.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206652.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206652.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206652.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206652.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206652.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206652.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206652.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206652.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206652.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206652.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206652.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206652.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206652.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206652.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206653.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206653.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206653.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206653.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206653.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206653.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206653.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206653.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206653.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206654.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206654.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206654.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206654.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206990.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c001c0]
>[206990.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c001c0] width 1920 pitch 7680 (/4 1920)
>[206990.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206990.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206990.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206990.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206990.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b060]
>[206990.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b060] width 1920 pitch 7680 (/4 1920)
>[206990.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206990.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206990.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206990.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206990.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b060]
>[206990.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b060] width 1920 pitch 7680 (/4 1920)
>[206990.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206990.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206990.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206990.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206990.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206990.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206990.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5c010]
>[206990.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5c010] width 1920 pitch 7680 (/4 1920)
>[206990.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206990.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206990.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e30]
>[206990.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e30] width 1920 pitch 7680 (/4 1920)
>[206991.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206991.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206991.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206991.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206991.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206991.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206991.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206991.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206991.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206991.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206991.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206992.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206992.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206992.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206992.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206992.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206992.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206992.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206992.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206992.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552a240]
>[206992.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552a240] width 1920 pitch 7680 (/4 1920)
>[206993.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5c050]
>[206993.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5c050] width 1920 pitch 7680 (/4 1920)
>[206993.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[206993.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[206993.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5c050]
>[206993.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5c050] width 1920 pitch 7680 (/4 1920)
>[206993.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[206993.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[206993.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b0a0]
>[206993.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b0a0] width 1920 pitch 7680 (/4 1920)
>[206993.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206994.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206994.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[206994.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[206994.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206994.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206994.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e70]
>[206994.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e70] width 1920 pitch 7680 (/4 1920)
>[206994.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55309d0]
>[206994.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55309d0] width 1920 pitch 7680 (/4 1920)
>[206994.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[206995.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[206995.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[206995.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[206995.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5c050]
>[206995.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5c050] width 1920 pitch 7680 (/4 1920)
>[206995.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3192310]
>[206995.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3192310] width 1920 pitch 7680 (/4 1920)
>[206995.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b0a0]
>[206995.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b0a0] width 1920 pitch 7680 (/4 1920)
>[206995.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[206995.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[206995.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5536e70]
>[206995.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5536e70] width 1920 pitch 7680 (/4 1920)
>[206995.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55309d0]
>[206995.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55309d0] width 1920 pitch 7680 (/4 1920)
>[206995.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcba90]
>[206995.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcba90] width 1920 pitch 7680 (/4 1920)
>[206995.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf760]
>[206995.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf760] width 1920 pitch 7680 (/4 1920)
>[207010.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55397c0]
>[207010.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55397c0] width 1920 pitch 7680 (/4 1920)
>[207120.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f20]
>[207120.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f20] width 1920 pitch 7680 (/4 1920)
>[207120.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5545190]
>[207120.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5545190] width 1920 pitch 7680 (/4 1920)
>[207180.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307c780]
>[207180.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307c780] width 1920 pitch 7680 (/4 1920)
>[207180.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207180.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207189.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207189.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207189.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207189.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207189.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207189.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207189.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207189.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207189.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207189.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207189.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207189.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207189.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207189.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207189.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207189.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207189.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207189.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207189.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207190.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207190.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207190.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207190.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207190.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207190.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207190.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207190.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207191.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207191.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207191.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207191.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3046a50]
>[207191.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3046a50] width 1920 pitch 7680 (/4 1920)
>[207191.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d458e0]
>[207191.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d458e0] width 1920 pitch 7680 (/4 1920)
>[207191.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207191.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207191.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d458e0]
>[207191.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d458e0] width 1920 pitch 7680 (/4 1920)
>[207191.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207191.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207191.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d458e0]
>[207191.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d458e0] width 1920 pitch 7680 (/4 1920)
>[207363.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ce8bb0]
>[207363.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ce8bb0] width 1920 pitch 7680 (/4 1920)
>[207625.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207625.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207625.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207625.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207625.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207625.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207625.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207625.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207625.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207625.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207625.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207625.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207625.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207625.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207626.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207626.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207626.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207626.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207626.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207626.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207626.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207627.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207627.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e6320]
>[207627.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e6320] width 1920 pitch 7680 (/4 1920)
>[207627.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207627.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207627.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b442c0]
>[207627.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b442c0] width 1920 pitch 7680 (/4 1920)
>[207627.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207627.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207627.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b442c0]
>[207627.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b442c0] width 1920 pitch 7680 (/4 1920)
>[207627.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207627.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207627.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b442c0]
>[207627.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b442c0] width 1920 pitch 7680 (/4 1920)
>[207627.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bb5370]
>[207627.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bb5370] width 1920 pitch 7680 (/4 1920)
>[207633.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x550f430]
>[207633.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x550f430] width 1920 pitch 7680 (/4 1920)
>[207844.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207844.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207844.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207844.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207844.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207844.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207844.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207844.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207844.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207844.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207844.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207845.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207845.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207845.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207845.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207845.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207845.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207845.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207845.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207845.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207845.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207845.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207846.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[207846.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[207846.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207846.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207846.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207846.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207846.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207846.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207846.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207846.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207846.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207846.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207846.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[207846.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[207853.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3091330]
>[207853.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3091330] width 1920 pitch 7680 (/4 1920)
>[207865.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207865.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207865.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207865.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207865.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207865.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207865.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207865.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207865.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207865.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207865.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207865.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207865.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207865.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207865.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207865.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207865.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207865.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207865.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207865.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207866.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30eee00]
>[207866.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30eee00] width 1920 pitch 7680 (/4 1920)
>[207866.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207866.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207866.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207866.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207867.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304dce0]
>[207867.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304dce0] width 1920 pitch 7680 (/4 1920)
>[207867.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207867.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207867.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207867.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207867.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207867.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207867.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207867.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[207867.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[207867.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[207867.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[207867.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208063.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208063.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208063.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208063.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208063.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208063.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208063.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208063.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208063.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208063.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208063.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208063.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208063.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208063.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208063.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208063.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208065.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208065.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208065.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208065.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208071.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304dce0]
>[208071.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304dce0] width 1920 pitch 7680 (/4 1920)
>[208071.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208071.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208071.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208071.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208071.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307d0e0]
>[208071.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307d0e0] width 1920 pitch 7680 (/4 1920)
>[208071.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208071.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208071.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21100]
>[208071.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21100] width 1920 pitch 7680 (/4 1920)
>[208071.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304dce0]
>[208071.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304dce0] width 1920 pitch 7680 (/4 1920)
>[208071.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208071.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208071.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208071.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208071.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304dce0]
>[208071.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304dce0] width 1920 pitch 7680 (/4 1920)
>[208071.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208071.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208101.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3090b60]
>[208101.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3090b60] width 1920 pitch 7680 (/4 1920)
>[208152.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208152.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208152.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208152.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208152.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208152.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208152.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208152.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208152.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208152.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208152.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208152.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208152.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208156.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208156.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208156.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208156.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208156.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208156.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208156.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208156.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208156.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208156.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208156.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[208156.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[208204.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208204.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208204.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208204.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208204.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208204.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208204.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208204.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208204.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208204.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208204.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208204.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208204.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208204.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208204.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208204.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208209.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208209.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208209.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208209.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208209.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208209.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208209.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208209.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208209.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208210.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208210.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208210.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208210.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208210.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208210.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208210.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208223.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208223.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208223.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208223.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208223.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208223.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208223.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208223.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208223.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[208223.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[208223.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30a40]
>[208223.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30a40] width 1920 pitch 7680 (/4 1920)
>[208224.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307d0e0]
>[208224.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307d0e0] width 1920 pitch 7680 (/4 1920)
>[208224.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5bca0]
>[208224.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5bca0] width 1920 pitch 7680 (/4 1920)
>[208227.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208227.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208227.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307d0e0]
>[208227.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307d0e0] width 1920 pitch 7680 (/4 1920)
>[208227.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5bca0]
>[208227.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5bca0] width 1920 pitch 7680 (/4 1920)
>[208227.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208227.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208227.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208227.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208227.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307d0e0]
>[208227.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307d0e0] width 1920 pitch 7680 (/4 1920)
>[208227.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5bca0]
>[208227.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5bca0] width 1920 pitch 7680 (/4 1920)
>[208227.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208227.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208227.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208227.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208227.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x307d0e0]
>[208227.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x307d0e0] width 1920 pitch 7680 (/4 1920)
>[208227.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5bca0]
>[208227.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5bca0] width 1920 pitch 7680 (/4 1920)
>[208227.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5544e90]
>[208227.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5544e90] width 1920 pitch 7680 (/4 1920)
>[208227.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d9d90]
>[208227.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d9d90] width 1920 pitch 7680 (/4 1920)
>[208250.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304df90]
>[208250.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304df90] width 1920 pitch 7680 (/4 1920)
>[208252.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5bca0]
>[208252.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5bca0] width 1920 pitch 7680 (/4 1920)
>[208252.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208252.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208252.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208252.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208252.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208252.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208252.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208252.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208252.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208253.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208253.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208253.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208253.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208253.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208253.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208253.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208253.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208253.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208253.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548dd0]
>[208253.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548dd0] width 1920 pitch 7680 (/4 1920)
>[208253.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55508c0]
>[208253.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55508c0] width 1920 pitch 7680 (/4 1920)
>[208253.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55508c0]
>[208254.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55508c0] width 1920 pitch 7680 (/4 1920)
>[208254.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55508c0]
>[208254.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55508c0] width 1920 pitch 7680 (/4 1920)
>[208254.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55508c0]
>[208254.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55508c0] width 1920 pitch 7680 (/4 1920)
>[208254.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30190]
>[208254.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30190] width 1920 pitch 7680 (/4 1920)
>[208254.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16370]
>[208254.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16370] width 1920 pitch 7680 (/4 1920)
>[208286.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208286.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208286.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208286.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208286.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208286.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208286.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208286.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208286.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208286.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208286.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208286.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208286.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208286.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208286.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208286.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208286.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208286.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208286.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208286.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208286.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208287.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208287.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3051400]
>[208287.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3051400] width 1920 pitch 7680 (/4 1920)
>[208287.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b650]
>[208287.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b650] width 1920 pitch 7680 (/4 1920)
>[208291.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e1a0]
>[208291.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e1a0] width 1920 pitch 7680 (/4 1920)
>[208291.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c6e00]
>[208291.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c6e00] width 1920 pitch 7680 (/4 1920)
>[208291.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e1a0]
>[208291.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e1a0] width 1920 pitch 7680 (/4 1920)
>[208291.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c6e00]
>[208291.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c6e00] width 1920 pitch 7680 (/4 1920)
>[208291.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e1a0]
>[208291.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e1a0] width 1920 pitch 7680 (/4 1920)
>[208291.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c6e00]
>[208291.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c6e00] width 1920 pitch 7680 (/4 1920)
>[208291.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e1a0]
>[208291.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e1a0] width 1920 pitch 7680 (/4 1920)
>[208291.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c6e00]
>[208291.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c6e00] width 1920 pitch 7680 (/4 1920)
>[208291.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e1a0]
>[208291.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e1a0] width 1920 pitch 7680 (/4 1920)
>[208310.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554b580]
>[208310.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554b580] width 1920 pitch 7680 (/4 1920)
>[208310.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e930]
>[208310.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e930] width 1920 pitch 7680 (/4 1920)
>[208335.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d430]
>[208335.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d430] width 1920 pitch 7680 (/4 1920)
>[208357.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208357.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208357.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208357.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208357.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208357.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208357.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208357.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208357.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208357.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208357.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208357.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208357.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208357.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208357.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208357.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208357.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208358.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5530500]
>[208358.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5530500] width 1920 pitch 7680 (/4 1920)
>[208358.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208358.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208358.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208358.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208358.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208358.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208358.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208358.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208358.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208358.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208358.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208358.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208358.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208358.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208361.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3054420]
>[208362.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3054420] width 1920 pitch 7680 (/4 1920)
>[208383.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32b00]
>[208383.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32b00] width 1920 pitch 7680 (/4 1920)
>[208383.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32b00]
>[208383.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32b00] width 1920 pitch 7680 (/4 1920)
>[208383.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32b00]
>[208383.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32b00] width 1920 pitch 7680 (/4 1920)
>[208383.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32b00]
>[208383.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32b00] width 1920 pitch 7680 (/4 1920)
>[208383.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f32b00]
>[208383.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f32b00] width 1920 pitch 7680 (/4 1920)
>[208383.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208383.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554aaa0]
>[208383.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554aaa0] width 1920 pitch 7680 (/4 1920)
>[208383.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208383.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208384.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5541b80]
>[208384.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5541b80] width 1920 pitch 7680 (/4 1920)
>[208384.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[208384.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[208387.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5541b80]
>[208387.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5541b80] width 1920 pitch 7680 (/4 1920)
>[208387.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[208387.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[208387.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208387.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208387.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208387.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208387.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208387.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208387.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208387.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208387.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208387.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208387.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208387.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208387.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208387.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208387.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[208387.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[208400.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f33db0]
>[208400.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f33db0] width 1920 pitch 7680 (/4 1920)
>[208404.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208404.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208404.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208404.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208404.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208404.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208404.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208404.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208404.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208404.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208404.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208404.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208404.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208404.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208404.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208404.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208405.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208405.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208405.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208405.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208405.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555c3b0]
>[208405.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555c3b0] width 1920 pitch 7680 (/4 1920)
>[208405.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208405.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208405.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208405.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208405.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208405.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208405.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208405.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208405.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208406.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208406.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208406.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208406.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208406.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208410.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208410.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208410.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208410.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208410.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208410.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208410.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208410.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208410.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208410.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208410.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208410.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208411.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208411.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208411.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208411.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208411.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208411.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208411.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208411.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208411.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208411.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208412.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208412.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208412.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208412.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208413.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208413.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208413.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208413.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208413.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208413.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208413.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208413.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208413.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208413.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208413.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208413.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208413.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208413.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208462.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208462.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208462.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565c80]
>[208462.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565c80] width 1920 pitch 7680 (/4 1920)
>[208463.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208463.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208463.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565c80]
>[208463.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565c80] width 1920 pitch 7680 (/4 1920)
>[208463.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208463.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208463.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565c80]
>[208463.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565c80] width 1920 pitch 7680 (/4 1920)
>[208463.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208463.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208463.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565c80]
>[208463.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565c80] width 1920 pitch 7680 (/4 1920)
>[208463.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208463.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208463.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565c80]
>[208463.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565c80] width 1920 pitch 7680 (/4 1920)
>[208463.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208463.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208467.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208467.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208467.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208467.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208483.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208483.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208483.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565510]
>[208483.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565510] width 1920 pitch 7680 (/4 1920)
>[208483.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d925e0]
>[208483.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d925e0] width 1920 pitch 7680 (/4 1920)
>[208483.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5e780]
>[208483.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5e780] width 1920 pitch 7680 (/4 1920)
>[208483.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bcba50]
>[208483.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bcba50] width 1920 pitch 7680 (/4 1920)
>[208483.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565b80]
>[208483.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565b80] width 1920 pitch 7680 (/4 1920)
>[208483.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e0a0]
>[208483.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e0a0] width 1920 pitch 7680 (/4 1920)
>[208483.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208483.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208483.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e0a0]
>[208483.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e0a0] width 1920 pitch 7680 (/4 1920)
>[208483.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208483.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208483.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e0a0]
>[208483.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e0a0] width 1920 pitch 7680 (/4 1920)
>[208483.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208483.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208483.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e0a0]
>[208483.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e0a0] width 1920 pitch 7680 (/4 1920)
>[208488.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208488.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208488.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208488.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208488.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208488.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208488.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208488.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208488.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208488.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208488.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208488.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208488.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208488.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208488.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208488.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208492.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208492.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208492.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208492.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208492.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208492.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208492.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208492.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208492.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208492.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208492.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208492.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208492.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208492.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208492.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208492.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208492.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208492.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208492.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208492.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208492.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208555.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208555.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208555.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208555.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208555.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208555.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208555.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208555.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208555.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208555.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208555.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208555.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208555.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208555.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208555.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208555.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208555.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208555.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208555.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208555.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208555.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208555.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208555.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208555.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208560.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208560.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208560.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208560.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208560.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208560.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208560.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208560.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208560.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208560.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208560.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208560.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208560.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208560.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208560.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208560.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208560.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208560.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208560.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208560.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208560.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208560.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208560.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208560.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208560.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208560.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208955.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208955.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208955.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208955.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208955.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[208955.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[208955.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208956.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208956.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[208956.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[208956.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[208956.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[208956.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208956.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208956.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30456f0]
>[208956.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30456f0] width 1920 pitch 7680 (/4 1920)
>[208956.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[208956.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[208956.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[208956.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[208956.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208956.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208956.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208956.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208957.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[208957.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[208957.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208957.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208957.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208957.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208957.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[208957.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[208957.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[208957.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[208957.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208957.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[208957.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30560]
>[208957.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30560] width 1920 pitch 7680 (/4 1920)
>[208997.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3050440]
>[208997.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3050440] width 1920 pitch 7680 (/4 1920)
>[209144.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209144.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209144.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303ad10]
>[209144.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303ad10] width 1920 pitch 7680 (/4 1920)
>[209144.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209144.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209144.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209144.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209144.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303ad10]
>[209144.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303ad10] width 1920 pitch 7680 (/4 1920)
>[209144.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209144.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209144.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209144.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209144.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303ad10]
>[209144.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303ad10] width 1920 pitch 7680 (/4 1920)
>[209144.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209144.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209144.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209144.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209144.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x303ad10]
>[209144.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x303ad10] width 1920 pitch 7680 (/4 1920)
>[209145.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209145.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209146.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209146.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209147.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209147.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3f330]
>[209147.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3f330] width 1920 pitch 7680 (/4 1920)
>[209147.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209147.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209147.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3f330]
>[209147.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3f330] width 1920 pitch 7680 (/4 1920)
>[209147.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209147.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209147.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209147.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209147.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209147.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209147.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209147.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209148.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209148.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209158.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209158.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209158.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209158.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209158.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209158.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209158.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209158.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209158.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209158.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209158.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209158.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209158.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209158.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209158.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209158.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209158.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209158.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209158.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209158.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209158.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209158.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209158.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209158.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209158.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209158.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209158.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209158.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209162.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209162.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209162.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209162.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209162.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209162.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209162.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209162.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209162.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209162.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209162.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209162.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209162.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209162.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209162.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209162.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209162.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209162.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209162.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209162.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209162.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209162.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209162.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209162.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209162.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209162.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209162.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209162.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209163.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209163.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209163.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209163.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209163.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209163.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209163.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209163.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209163.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209163.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209163.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209163.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209163.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209163.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209163.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209163.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209163.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209163.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209163.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209163.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209163.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209163.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209163.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209163.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209167.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209167.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209167.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209167.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209167.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209167.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209167.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209167.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209167.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209167.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209167.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209167.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209167.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d060]
>[209167.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d060] width 1920 pitch 7680 (/4 1920)
>[209167.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209167.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209167.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5548d70]
>[209167.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5548d70] width 1920 pitch 7680 (/4 1920)
>[209167.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209167.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209167.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209167.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209209.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5d3d0]
>[209209.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5d3d0] width 1920 pitch 7680 (/4 1920)
>[209209.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209209.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209209.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5559a40]
>[209209.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5559a40] width 1920 pitch 7680 (/4 1920)
>[209227.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3054da0]
>[209227.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3054da0] width 1920 pitch 7680 (/4 1920)
>[209227.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f33670]
>[209227.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f33670] width 1920 pitch 7680 (/4 1920)
>[209227.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209227.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209227.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bd60]
>[209227.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bd60] width 1920 pitch 7680 (/4 1920)
>[209227.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209227.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209227.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209227.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209227.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209227.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209227.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f33670]
>[209227.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f33670] width 1920 pitch 7680 (/4 1920)
>[209227.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209227.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209227.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3054da0]
>[209227.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3054da0] width 1920 pitch 7680 (/4 1920)
>[209227.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f33670]
>[209227.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f33670] width 1920 pitch 7680 (/4 1920)
>[209232.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209232.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209232.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209232.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209232.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209232.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209232.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209232.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209232.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209232.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209232.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209233.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209233.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209233.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209233.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209233.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209233.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209233.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209233.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209233.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209233.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d24e50]
>[209233.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d24e50] width 1920 pitch 7680 (/4 1920)
>[209233.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554a0e0]
>[209233.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554a0e0] width 1920 pitch 7680 (/4 1920)
>[209272.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3e730]
>[209272.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3e730] width 1920 pitch 7680 (/4 1920)
>[209272.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c590]
>[209272.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c590] width 1920 pitch 7680 (/4 1920)
>[209272.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f435f0]
>[209272.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f435f0] width 1920 pitch 7680 (/4 1920)
>[209272.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c590]
>[209272.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c590] width 1920 pitch 7680 (/4 1920)
>[209272.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3054be0]
>[209272.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3054be0] width 1920 pitch 7680 (/4 1920)
>[209272.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f435f0]
>[209272.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f435f0] width 1920 pitch 7680 (/4 1920)
>[209272.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209272.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209272.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f435f0]
>[209272.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f435f0] width 1920 pitch 7680 (/4 1920)
>[209272.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209272.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209272.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f435f0]
>[209272.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f435f0] width 1920 pitch 7680 (/4 1920)
>[209272.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209272.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209272.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4a8d0]
>[209272.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4a8d0] width 1920 pitch 7680 (/4 1920)
>[209277.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209277.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209277.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209277.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209277.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209277.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5568d80]
>[209277.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5568d80] width 1920 pitch 7680 (/4 1920)
>[209277.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209277.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209281.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209281.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209281.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209281.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209281.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209281.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209281.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209281.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209281.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209281.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209281.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209281.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209281.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209282.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209282.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209282.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209282.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209282.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209282.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209282.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209282.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c660]
>[209282.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c660] width 1920 pitch 7680 (/4 1920)
>[209282.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f43ca0]
>[209282.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f43ca0] width 1920 pitch 7680 (/4 1920)
>[209299.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4bf00]
>[209299.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4bf00] width 1920 pitch 7680 (/4 1920)
>[209299.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4bf00]
>[209299.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4bf00] width 1920 pitch 7680 (/4 1920)
>[209299.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4bf00]
>[209299.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4bf00] width 1920 pitch 7680 (/4 1920)
>[209299.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4c000]
>[209299.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4c000] width 1920 pitch 7680 (/4 1920)
>[209299.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4c000]
>[209299.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4c000] width 1920 pitch 7680 (/4 1920)
>[209299.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4c000]
>[209299.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4c000] width 1920 pitch 7680 (/4 1920)
>[209299.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc80d0]
>[209299.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc80d0] width 1920 pitch 7680 (/4 1920)
>[209299.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4be80]
>[209300.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4be80] width 1920 pitch 7680 (/4 1920)
>[209300.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42fb0]
>[209300.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42fb0] width 1920 pitch 7680 (/4 1920)
>[209300.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4be80]
>[209300.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4be80] width 1920 pitch 7680 (/4 1920)
>[209300.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4be80]
>[209300.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4be80] width 1920 pitch 7680 (/4 1920)
>[209300.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42fb0]
>[209300.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42fb0] width 1920 pitch 7680 (/4 1920)
>[209300.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209300.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209300.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5549c70]
>[209300.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5549c70] width 1920 pitch 7680 (/4 1920)
>[209300.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4be80]
>[209300.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4be80] width 1920 pitch 7680 (/4 1920)
>[209300.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209300.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209300.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5549c70]
>[209300.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5549c70] width 1920 pitch 7680 (/4 1920)
>[209300.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4f00]
>[209300.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4f00] width 1920 pitch 7680 (/4 1920)
>[209348.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209348.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209348.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209348.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209348.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209348.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209348.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209348.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209348.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cf30]
>[209348.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cf30] width 1920 pitch 7680 (/4 1920)
>[209348.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209348.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209348.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209348.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209349.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209349.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209349.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209349.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209349.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209349.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209350.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209350.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209351.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209351.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209351.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209351.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209351.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209351.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209351.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3adf0]
>[209351.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3adf0] width 1920 pitch 7680 (/4 1920)
>[209351.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5564650]
>[209351.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5564650] width 1920 pitch 7680 (/4 1920)
>[209351.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5fb0]
>[209352.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5fb0] width 1920 pitch 7680 (/4 1920)
>[209352.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5551100]
>[209352.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5551100] width 1920 pitch 7680 (/4 1920)
>[209352.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209352.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209352.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5564650]
>[209352.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5564650] width 1920 pitch 7680 (/4 1920)
>[209360.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209360.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209360.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40850]
>[209360.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40850] width 1920 pitch 7680 (/4 1920)
>[209360.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d020]
>[209360.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d020] width 1920 pitch 7680 (/4 1920)
>[209360.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3adf0]
>[209360.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3adf0] width 1920 pitch 7680 (/4 1920)
>[209360.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209360.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209360.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5564650]
>[209361.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5564650] width 1920 pitch 7680 (/4 1920)
>[209361.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40850]
>[209361.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40850] width 1920 pitch 7680 (/4 1920)
>[209361.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d020]
>[209361.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d020] width 1920 pitch 7680 (/4 1920)
>[209361.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3adf0]
>[209361.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3adf0] width 1920 pitch 7680 (/4 1920)
>[209361.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d90d30]
>[209361.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d90d30] width 1920 pitch 7680 (/4 1920)
>[209365.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3080830]
>[209365.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3080830] width 1920 pitch 7680 (/4 1920)
>[209365.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209365.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209365.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3080830]
>[209365.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3080830] width 1920 pitch 7680 (/4 1920)
>[209365.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209365.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209365.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209365.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209365.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209365.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209365.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209365.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209374.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209374.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209374.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209374.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209374.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209374.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209374.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209374.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209374.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209374.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209374.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209374.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209374.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209374.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209374.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209378.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209378.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209378.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209378.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209378.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209378.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209379.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209379.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209379.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209379.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209379.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209379.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209379.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209379.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209379.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209379.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209379.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209379.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209379.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209379.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209379.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209379.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209379.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55587c0]
>[209379.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55587c0] width 1920 pitch 7680 (/4 1920)
>[209379.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3266ef0]
>[209379.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3266ef0] width 1920 pitch 7680 (/4 1920)
>[209611.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb5f90]
>[209611.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb5f90] width 1920 pitch 7680 (/4 1920)
>[209649.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40830]
>[209649.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40830] width 1920 pitch 7680 (/4 1920)
>[209649.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3043020]
>[209649.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3043020] width 1920 pitch 7680 (/4 1920)
>[209649.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3043080]
>[209649.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3043080] width 1920 pitch 7680 (/4 1920)
>[209649.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5543410]
>[209649.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5543410] width 1920 pitch 7680 (/4 1920)
>[209649.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c7d0]
>[209649.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c7d0] width 1920 pitch 7680 (/4 1920)
>[209649.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40580]
>[209649.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40580] width 1920 pitch 7680 (/4 1920)
>[209649.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c830]
>[209649.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c830] width 1920 pitch 7680 (/4 1920)
>[209649.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40580]
>[209649.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40580] width 1920 pitch 7680 (/4 1920)
>[209649.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552c7d0]
>[209649.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552c7d0] width 1920 pitch 7680 (/4 1920)
>[209649.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40760]
>[209649.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40760] width 1920 pitch 7680 (/4 1920)
>[209649.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40580]
>[209649.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40580] width 1920 pitch 7680 (/4 1920)
>[209651.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40190]
>[209651.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40190] width 1920 pitch 7680 (/4 1920)
>[209651.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cae0]
>[209651.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cae0] width 1920 pitch 7680 (/4 1920)
>[209659.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4cae0]
>[209659.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4cae0] width 1920 pitch 7680 (/4 1920)
>[209659.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209659.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209659.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555ce10]
>[209659.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555ce10] width 1920 pitch 7680 (/4 1920)
>[209659.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555ce10]
>[209659.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555ce10] width 1920 pitch 7680 (/4 1920)
>[209659.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209659.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209659.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209659.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209659.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555ce10]
>[209659.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555ce10] width 1920 pitch 7680 (/4 1920)
>[209659.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555ce10]
>[209659.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555ce10] width 1920 pitch 7680 (/4 1920)
>[209659.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209659.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209659.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209659.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209712.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209712.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209712.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40ba0]
>[209712.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40ba0] width 1920 pitch 7680 (/4 1920)
>[209712.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a90]
>[209712.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a90] width 1920 pitch 7680 (/4 1920)
>[209712.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209712.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209712.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3f390]
>[209712.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3f390] width 1920 pitch 7680 (/4 1920)
>[209712.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209712.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209712.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40ba0]
>[209712.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40ba0] width 1920 pitch 7680 (/4 1920)
>[209712.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209712.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209712.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3f390]
>[209712.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3f390] width 1920 pitch 7680 (/4 1920)
>[209712.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209712.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209712.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40ba0]
>[209712.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40ba0] width 1920 pitch 7680 (/4 1920)
>[209712.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209712.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209712.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3f390]
>[209712.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3f390] width 1920 pitch 7680 (/4 1920)
>[209712.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209712.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209716.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209716.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209716.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209717.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209717.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209717.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209717.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209717.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209717.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209717.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209717.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209717.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209717.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209717.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209717.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209717.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209717.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555d300]
>[209717.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555d300] width 1920 pitch 7680 (/4 1920)
>[209717.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209717.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209717.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044b40]
>[209717.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044b40] width 1920 pitch 7680 (/4 1920)
>[209729.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209729.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209729.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209729.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209729.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209730.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209730.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209730.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209730.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209730.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209730.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209730.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209730.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209730.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209730.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209730.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209730.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209730.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209730.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209730.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209730.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209730.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209731.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3010]
>[209731.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3010] width 1920 pitch 7680 (/4 1920)
>[209731.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209731.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209731.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x55478c0]
>[209731.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x55478c0] width 1920 pitch 7680 (/4 1920)
>[209731.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209731.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209731.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209731.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209731.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209731.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209738.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50915d0]
>[209738.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50915d0] width 1920 pitch 7680 (/4 1920)
>[209738.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209738.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209738.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209738.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209738.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209738.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209738.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209748.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209748.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209748.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209748.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209748.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209748.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209748.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209748.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209748.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209748.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209748.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209748.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209748.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209748.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209748.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209748.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209748.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209748.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209748.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209748.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209748.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209748.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209748.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209748.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209750.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209750.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209750.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209750.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209750.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209750.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209750.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209750.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209750.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209750.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209750.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209750.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209762.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209762.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209762.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209762.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209762.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209762.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209762.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209762.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209762.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209762.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209762.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209762.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209762.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209762.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209762.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209762.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209763.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f42290]
>[209763.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f42290] width 1920 pitch 7680 (/4 1920)
>[209763.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209763.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209763.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209763.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209763.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209763.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209764.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209764.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209764.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209764.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209765.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209765.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209765.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209765.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209765.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209765.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209765.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209765.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209766.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209766.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209766.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209766.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209766.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209766.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209766.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209766.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209766.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209766.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209766.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209766.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209795.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209795.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209795.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209795.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209795.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209796.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209796.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209796.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209796.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209796.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209796.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209796.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209796.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209796.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209796.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209796.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209796.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209796.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209796.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209796.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209797.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555bc30]
>[209797.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555bc30] width 1920 pitch 7680 (/4 1920)
>[209797.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209797.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209808.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209808.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209809.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209809.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209809.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209809.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209809.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209809.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209809.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209809.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209809.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209809.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209809.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209809.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209809.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209809.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40fc0]
>[209809.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40fc0] width 1920 pitch 7680 (/4 1920)
>[209892.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209892.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209892.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209892.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209892.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209892.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209892.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209892.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209892.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209892.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209892.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209892.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209892.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209892.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209892.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209896.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209896.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209896.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209896.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209896.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209896.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209896.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209896.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209896.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209897.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209897.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209897.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209897.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209897.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209897.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209897.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209897.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209897.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209897.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209897.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209897.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eb3340]
>[209897.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eb3340] width 1920 pitch 7680 (/4 1920)
>[209897.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[209897.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[209932.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f40bd0]
>[209932.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f40bd0] width 1920 pitch 7680 (/4 1920)
>[209967.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209967.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209967.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209967.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209967.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209967.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209967.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505fec0]
>[209967.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505fec0] width 1920 pitch 7680 (/4 1920)
>[209967.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cdb0]
>[209967.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cdb0] width 1920 pitch 7680 (/4 1920)
>[209967.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209967.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209967.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505fec0]
>[209967.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505fec0] width 1920 pitch 7680 (/4 1920)
>[209967.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cdb0]
>[209967.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cdb0] width 1920 pitch 7680 (/4 1920)
>[209967.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209967.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209967.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505fec0]
>[209967.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505fec0] width 1920 pitch 7680 (/4 1920)
>[209967.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cdb0]
>[209967.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cdb0] width 1920 pitch 7680 (/4 1920)
>[209967.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209967.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209968.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209968.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209971.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209971.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209971.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209971.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209971.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209971.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209971.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[209971.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[209971.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209971.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209971.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209971.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209971.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209971.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209971.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[209971.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[209971.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209971.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209971.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209971.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209971.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209971.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209971.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209971.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209971.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209971.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209971.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209971.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209975.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209975.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209975.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[209976.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[209976.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209976.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209976.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209976.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209976.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[209976.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[209976.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209976.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209976.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209976.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209976.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209976.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209976.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[209976.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[209976.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101090]
>[209976.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101090] width 1920 pitch 7680 (/4 1920)
>[209976.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46580c0]
>[209976.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46580c0] width 1920 pitch 7680 (/4 1920)
>[209976.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ffa70]
>[209976.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ffa70] width 1920 pitch 7680 (/4 1920)
>[209992.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4a140]
>[209992.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4a140] width 1920 pitch 7680 (/4 1920)
>[210029.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056580]
>[210030.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056580] width 1920 pitch 7680 (/4 1920)
>[210030.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369250]
>[210030.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369250] width 1920 pitch 7680 (/4 1920)
>[210030.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056580]
>[210030.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056580] width 1920 pitch 7680 (/4 1920)
>[210030.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f46f80]
>[210030.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f46f80] width 1920 pitch 7680 (/4 1920)
>[210030.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056580]
>[210030.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056580] width 1920 pitch 7680 (/4 1920)
>[210030.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f47940]
>[210030.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f47940] width 1920 pitch 7680 (/4 1920)
>[210030.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056580]
>[210030.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056580] width 1920 pitch 7680 (/4 1920)
>[210030.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4f420]
>[210030.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4f420] width 1920 pitch 7680 (/4 1920)
>[210030.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4a5d0]
>[210030.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4a5d0] width 1920 pitch 7680 (/4 1920)
>[210030.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3056580]
>[210030.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3056580] width 1920 pitch 7680 (/4 1920)
>[210030.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4a5d0]
>[210030.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4a5d0] width 1920 pitch 7680 (/4 1920)
>[210030.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369250]
>[210030.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369250] width 1920 pitch 7680 (/4 1920)
>[210034.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f46f80]
>[210034.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f46f80] width 1920 pitch 7680 (/4 1920)
>[210034.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ba50]
>[210034.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ba50] width 1920 pitch 7680 (/4 1920)
>[210034.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cd90]
>[210034.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cd90] width 1920 pitch 7680 (/4 1920)
>[210034.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210034.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210034.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ba50]
>[210034.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ba50] width 1920 pitch 7680 (/4 1920)
>[210034.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555cd90]
>[210034.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555cd90] width 1920 pitch 7680 (/4 1920)
>[210034.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210034.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210034.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37f70]
>[210034.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37f70] width 1920 pitch 7680 (/4 1920)
>[210034.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210034.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210034.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ba50]
>[210034.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ba50] width 1920 pitch 7680 (/4 1920)
>[210034.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ba50]
>[210034.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ba50] width 1920 pitch 7680 (/4 1920)
>[210034.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320ba50]
>[210034.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320ba50] width 1920 pitch 7680 (/4 1920)
>[210073.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1c20]
>[210073.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1c20] width 1920 pitch 7680 (/4 1920)
>[210073.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035d70]
>[210073.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035d70] width 1920 pitch 7680 (/4 1920)
>[210073.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f411f0]
>[210073.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f411f0] width 1920 pitch 7680 (/4 1920)
>[210073.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f56870]
>[210073.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f56870] width 1920 pitch 7680 (/4 1920)
>[210073.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1c20]
>[210073.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1c20] width 1920 pitch 7680 (/4 1920)
>[210073.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210073.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210073.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210073.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210073.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210073.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210073.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f259a0]
>[210074.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f259a0] width 1920 pitch 7680 (/4 1920)
>[210074.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f411f0]
>[210074.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f411f0] width 1920 pitch 7680 (/4 1920)
>[210074.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210074.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210079.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210079.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210079.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210079.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210079.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f411f0]
>[210079.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f411f0] width 1920 pitch 7680 (/4 1920)
>[210079.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f56870]
>[210079.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f56870] width 1920 pitch 7680 (/4 1920)
>[210079.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f259a0]
>[210079.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f259a0] width 1920 pitch 7680 (/4 1920)
>[210079.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1c20]
>[210079.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1c20] width 1920 pitch 7680 (/4 1920)
>[210079.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035d70]
>[210079.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035d70] width 1920 pitch 7680 (/4 1920)
>[210079.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210079.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210079.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210079.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210079.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210079.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210079.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f411f0]
>[210079.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f411f0] width 1920 pitch 7680 (/4 1920)
>[210079.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f259a0]
>[210079.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f259a0] width 1920 pitch 7680 (/4 1920)
>[210079.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035d70]
>[210079.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035d70] width 1920 pitch 7680 (/4 1920)
>[210081.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210081.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210081.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f259a0]
>[210081.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f259a0] width 1920 pitch 7680 (/4 1920)
>[210081.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f56870]
>[210081.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f56870] width 1920 pitch 7680 (/4 1920)
>[210081.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1c20]
>[210081.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1c20] width 1920 pitch 7680 (/4 1920)
>[210081.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035d70]
>[210081.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035d70] width 1920 pitch 7680 (/4 1920)
>[210081.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210081.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210081.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210081.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210081.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210081.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210081.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210081.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210081.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f411f0]
>[210081.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f411f0] width 1920 pitch 7680 (/4 1920)
>[210085.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e110]
>[210085.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e110] width 1920 pitch 7680 (/4 1920)
>[210085.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542ae0]
>[210085.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542ae0] width 1920 pitch 7680 (/4 1920)
>[210085.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210085.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210085.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210085.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210085.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210085.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210085.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e110]
>[210085.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e110] width 1920 pitch 7680 (/4 1920)
>[210085.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542ae0]
>[210085.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542ae0] width 1920 pitch 7680 (/4 1920)
>[210085.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210085.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210085.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210085.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210085.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210085.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210085.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5542ae0]
>[210085.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5542ae0] width 1920 pitch 7680 (/4 1920)
>[210085.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210085.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210085.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[210085.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[210138.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6260]
>[210138.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6260] width 1920 pitch 7680 (/4 1920)
>[210138.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210138.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210138.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210138.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210138.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210138.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210138.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210138.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210138.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210138.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210138.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6260]
>[210138.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6260] width 1920 pitch 7680 (/4 1920)
>[210139.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6260]
>[210139.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6260] width 1920 pitch 7680 (/4 1920)
>[210139.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbc050]
>[210139.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbc050] width 1920 pitch 7680 (/4 1920)
>[210139.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210139.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210139.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbc050]
>[210139.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbc050] width 1920 pitch 7680 (/4 1920)
>[210139.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbc050]
>[210139.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbc050] width 1920 pitch 7680 (/4 1920)
>[210139.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210139.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210139.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f331b0]
>[210139.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f331b0] width 1920 pitch 7680 (/4 1920)
>[210139.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f565c0]
>[210139.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f565c0] width 1920 pitch 7680 (/4 1920)
>[210139.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[210139.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[210158.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b5a0]
>[210158.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b5a0] width 1920 pitch 7680 (/4 1920)
>[210162.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210162.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210162.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554adf0]
>[210162.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554adf0] width 1920 pitch 7680 (/4 1920)
>[210162.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[210162.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[210163.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5547f70]
>[210163.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5547f70] width 1920 pitch 7680 (/4 1920)
>[210163.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[210163.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[210163.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210163.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210163.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5547f70]
>[210163.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5547f70] width 1920 pitch 7680 (/4 1920)
>[210163.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210163.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210163.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210163.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210164.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[210164.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[210164.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210164.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210164.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[210164.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[210164.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f207e0]
>[210164.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f207e0] width 1920 pitch 7680 (/4 1920)
>[210164.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210164.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210164.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210164.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210164.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f337f0]
>[210164.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f337f0] width 1920 pitch 7680 (/4 1920)
>[210164.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f337f0]
>[210164.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f337f0] width 1920 pitch 7680 (/4 1920)
>[210168.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210168.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210168.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210168.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210168.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210168.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210168.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210168.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210168.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210168.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210168.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210169.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210169.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[210169.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[210169.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[210169.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[210169.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210169.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210169.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[210169.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[210169.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210169.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210169.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210169.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210326.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210326.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210326.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210326.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210326.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210326.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210326.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210326.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210326.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210326.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210326.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210326.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210326.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210326.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210326.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210327.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210327.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210327.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210327.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210327.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210327.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210327.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210327.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210327.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210331.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210331.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210331.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210332.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210332.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210332.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210332.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210332.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210332.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210332.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210332.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210332.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210332.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210332.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210332.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210332.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210332.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210332.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210332.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210332.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210332.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210332.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210332.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210332.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210428.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210428.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210428.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210428.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210428.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210428.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210428.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210428.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210428.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210428.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210428.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210428.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210428.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210428.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210428.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210428.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210428.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210428.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210428.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210428.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210428.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210428.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210432.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210432.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210432.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210432.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210432.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210432.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210432.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210432.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210432.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210432.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210432.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210432.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210432.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210432.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210432.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210432.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210432.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210432.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210432.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210432.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210432.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210432.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210432.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210432.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210432.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210432.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210462.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210462.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210462.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210462.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210462.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210462.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210462.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210462.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210462.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210462.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210462.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210462.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210462.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210462.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210462.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210462.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210462.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210462.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210462.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210462.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210462.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210462.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210466.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210466.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210466.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210466.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210466.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210467.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210467.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210467.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210467.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210467.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210467.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210467.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210467.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210467.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210467.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210467.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210467.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210467.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210467.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210467.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210467.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210467.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210467.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210467.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210840.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210840.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210840.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210840.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210840.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210840.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210840.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210840.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210840.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210840.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210840.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210840.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210840.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210840.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210840.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210840.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210840.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210840.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210840.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210840.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210840.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210840.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210844.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210844.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210844.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210844.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210844.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210844.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210844.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[210844.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[210844.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210844.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210844.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210844.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210844.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210844.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210844.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210844.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210844.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[210844.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[210844.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210844.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210844.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210844.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210844.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210844.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210844.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210845.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210847.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210847.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210847.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210847.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210847.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210847.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210847.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210847.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210847.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210847.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210847.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210847.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210847.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210847.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210847.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[210847.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[210851.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210851.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210851.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[210851.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[210851.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210851.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210851.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210851.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210851.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210851.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210851.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210851.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210851.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210851.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210851.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210851.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210851.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210851.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210851.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210851.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210851.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210851.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210851.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210851.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210941.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210941.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210941.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210941.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210941.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210941.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210941.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210941.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210941.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210941.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210941.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210941.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210941.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210941.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210941.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210941.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210941.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210941.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210941.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210941.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210941.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210941.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210941.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210941.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210945.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210945.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210945.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210945.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210945.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210945.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210945.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210945.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210945.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210945.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210945.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210945.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210945.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210945.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210945.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210945.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210945.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210945.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210945.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210945.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210945.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210945.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210945.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210945.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210964.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210964.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210964.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210964.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210964.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210964.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210964.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210964.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210964.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210964.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210964.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210964.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210964.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210964.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210964.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[210964.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[210964.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210964.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210964.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210964.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210964.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210964.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210964.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210965.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210968.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210969.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210969.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210969.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210969.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210969.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210969.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba150]
>[210969.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba150] width 1920 pitch 7680 (/4 1920)
>[210969.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9460]
>[210969.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9460] width 1920 pitch 7680 (/4 1920)
>[210969.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[210969.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[210969.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[210969.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[210969.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb82a0]
>[210969.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb82a0] width 1920 pitch 7680 (/4 1920)
>[210969.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[210969.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[210969.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[210969.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[210969.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[210969.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[210969.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f208f0]
>[210969.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f208f0] width 1920 pitch 7680 (/4 1920)
>[210969.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[210969.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[210969.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bf9460]
>[210969.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bf9460] width 1920 pitch 7680 (/4 1920)
>[211736.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304feb0]
>[211736.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304feb0] width 1920 pitch 7680 (/4 1920)
>[211736.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211736.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211736.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb80d0]
>[211736.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb80d0] width 1920 pitch 7680 (/4 1920)
>[211736.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb82a0]
>[211736.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb82a0] width 1920 pitch 7680 (/4 1920)
>[211736.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5f40]
>[211736.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5f40] width 1920 pitch 7680 (/4 1920)
>[211736.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc26d0]
>[211736.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc26d0] width 1920 pitch 7680 (/4 1920)
>[211736.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe7ec0]
>[211737.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe7ec0] width 1920 pitch 7680 (/4 1920)
>[211737.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59654c0]
>[211737.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59654c0] width 1920 pitch 7680 (/4 1920)
>[211737.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[211737.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[211737.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595f9d0]
>[211737.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595f9d0] width 1920 pitch 7680 (/4 1920)
>[211737.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[211737.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[211737.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe83a0]
>[211737.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe83a0] width 1920 pitch 7680 (/4 1920)
>[211737.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5965860]
>[211737.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5965860] width 1920 pitch 7680 (/4 1920)
>[211741.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fba150]
>[211741.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fba150] width 1920 pitch 7680 (/4 1920)
>[211741.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211741.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211741.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3b640]
>[211741.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3b640] width 1920 pitch 7680 (/4 1920)
>[211741.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb80d0]
>[211741.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb80d0] width 1920 pitch 7680 (/4 1920)
>[211741.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59668c0]
>[211741.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59668c0] width 1920 pitch 7680 (/4 1920)
>[211741.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211741.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211741.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59654c0]
>[211741.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59654c0] width 1920 pitch 7680 (/4 1920)
>[211741.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5f40]
>[211741.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5f40] width 1920 pitch 7680 (/4 1920)
>[211741.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595f9d0]
>[211741.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595f9d0] width 1920 pitch 7680 (/4 1920)
>[211741.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5d40]
>[211741.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5d40] width 1920 pitch 7680 (/4 1920)
>[211741.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5967680]
>[211741.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5967680] width 1920 pitch 7680 (/4 1920)
>[211741.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211741.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211741.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb0a10]
>[211741.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb0a10] width 1920 pitch 7680 (/4 1920)
>[211749.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59654c0]
>[211749.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59654c0] width 1920 pitch 7680 (/4 1920)
>[211808.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5f40]
>[211808.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5f40] width 1920 pitch 7680 (/4 1920)
>[211808.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211808.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211808.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211808.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211808.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211808.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211808.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211808.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211808.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5f40]
>[211808.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5f40] width 1920 pitch 7680 (/4 1920)
>[211808.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb3fe0]
>[211808.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb3fe0] width 1920 pitch 7680 (/4 1920)
>[211809.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211809.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211809.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb3fe0]
>[211809.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb3fe0] width 1920 pitch 7680 (/4 1920)
>[211809.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211809.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211809.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211809.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211809.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211809.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211809.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211809.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211809.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211809.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211809.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb5f40]
>[211810.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb5f40] width 1920 pitch 7680 (/4 1920)
>[211810.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211810.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211810.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211810.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211810.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb3fe0]
>[211810.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb3fe0] width 1920 pitch 7680 (/4 1920)
>[211847.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211847.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211851.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211851.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211851.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211851.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211851.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211851.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211851.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211851.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211851.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211851.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211851.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211851.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211851.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211851.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211851.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211851.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211851.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211851.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211852.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[211852.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[211852.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211852.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211852.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211852.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211852.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211852.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211852.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211852.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211852.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211852.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211852.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211852.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211852.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211852.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211852.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb7e30]
>[211852.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb7e30] width 1920 pitch 7680 (/4 1920)
>[211853.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211853.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211853.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211853.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211853.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211853.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211853.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211853.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211853.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211853.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211853.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211853.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211853.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211853.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211854.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211854.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211854.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211854.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211854.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211854.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211854.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211854.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211854.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211854.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211854.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211854.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211854.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211854.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211854.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211854.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211854.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211855.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211855.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211855.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211855.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211855.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211855.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211855.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211855.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211855.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211855.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211855.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211855.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211855.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211855.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211855.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211855.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211855.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211855.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211855.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211855.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[211855.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[211928.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211928.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211928.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211928.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211928.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211928.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211928.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211928.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211930.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211930.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211934.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211934.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211934.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211934.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211934.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211934.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211934.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[211934.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[211934.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211934.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211934.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[211934.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[211934.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211934.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211934.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211935.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211935.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211935.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211935.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211935.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211935.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211935.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211935.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211935.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211935.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[211935.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[211935.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211936.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211936.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211936.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211936.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211936.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211936.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211936.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211936.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211936.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211936.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211936.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211936.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[211936.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[211936.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[211936.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[211936.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211936.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211936.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[211936.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[211936.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211936.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[211940.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[211940.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212328.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212328.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212333.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212333.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212333.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212333.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212333.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212333.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212333.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212333.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212333.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212333.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212333.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212333.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212333.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212333.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212333.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212333.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212333.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212333.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212333.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212333.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212336.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212336.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212336.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212336.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212336.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212336.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212336.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212336.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212336.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212336.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212336.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212336.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212336.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212336.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212337.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212337.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212337.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212337.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212337.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212337.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212337.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212337.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212337.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212337.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212338.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212338.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212338.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212338.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212338.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212338.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212338.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212338.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212338.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212338.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212338.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212338.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212338.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212338.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212338.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212338.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212339.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212339.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212339.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212339.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212339.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212374.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212374.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212374.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212374.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212374.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212374.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212374.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212374.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212374.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212374.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212374.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212374.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212374.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212374.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212374.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212374.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212374.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212374.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212374.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212374.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212378.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212378.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212378.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212378.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212378.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212378.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212378.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212378.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212378.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212378.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212378.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212378.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212378.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212378.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212378.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212378.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212378.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212378.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212378.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212378.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212378.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212378.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212378.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212378.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212378.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ace690]
>[212378.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ace690] width 1920 pitch 7680 (/4 1920)
>[212913.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212913.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212913.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212913.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212913.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212914.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212914.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212914.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212914.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212914.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212914.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212914.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212914.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb12d0]
>[212914.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb12d0] width 1920 pitch 7680 (/4 1920)
>[212914.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212914.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212914.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212914.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212914.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212914.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212915.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f49720]
>[212915.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f49720] width 1920 pitch 7680 (/4 1920)
>[212915.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212915.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212917.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212917.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212917.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2b50]
>[212917.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2b50] width 1920 pitch 7680 (/4 1920)
>[212917.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2b50]
>[212917.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2b50] width 1920 pitch 7680 (/4 1920)
>[212917.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2b50]
>[212917.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2b50] width 1920 pitch 7680 (/4 1920)
>[212917.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212917.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f8f0]
>[212917.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f8f0] width 1920 pitch 7680 (/4 1920)
>[212917.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554cfb0]
>[212917.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554cfb0] width 1920 pitch 7680 (/4 1920)
>[212919.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212919.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212981.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212981.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212981.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212981.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212981.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212981.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212981.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212981.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212981.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212981.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212981.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212981.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212981.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212981.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212981.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212981.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212981.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1640]
>[212981.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1640] width 1920 pitch 7680 (/4 1920)
>[212981.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212981.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212985.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212985.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212985.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212985.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5968660]
>[212985.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5968660] width 1920 pitch 7680 (/4 1920)
>[212989.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f492e0]
>[212989.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f492e0] width 1920 pitch 7680 (/4 1920)
>[212989.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc620]
>[212989.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc620] width 1920 pitch 7680 (/4 1920)
>[212989.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f492e0]
>[212989.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f492e0] width 1920 pitch 7680 (/4 1920)
>[212989.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc620]
>[212989.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc620] width 1920 pitch 7680 (/4 1920)
>[212989.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f492e0]
>[212989.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f492e0] width 1920 pitch 7680 (/4 1920)
>[212989.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc620]
>[212989.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc620] width 1920 pitch 7680 (/4 1920)
>[212989.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f492e0]
>[212989.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f492e0] width 1920 pitch 7680 (/4 1920)
>[212989.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59660c0]
>[212989.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59660c0] width 1920 pitch 7680 (/4 1920)
>[212989.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212989.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212989.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596a9e0]
>[212989.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596a9e0] width 1920 pitch 7680 (/4 1920)
>[212989.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59722d0]
>[212989.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59722d0] width 1920 pitch 7680 (/4 1920)
>[212989.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fce190]
>[212989.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fce190] width 1920 pitch 7680 (/4 1920)
>[212993.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212993.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212993.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212993.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[212993.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212993.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212993.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212993.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[212993.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212993.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212993.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212993.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[212993.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212993.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212993.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212993.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[212993.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212993.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212993.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212993.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[212994.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbe20]
>[212994.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbe20] width 1920 pitch 7680 (/4 1920)
>[212994.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5acefb0]
>[212994.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5acefb0] width 1920 pitch 7680 (/4 1920)
>[213413.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213413.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213413.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213413.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213413.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213413.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213413.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213413.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213413.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213413.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213413.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213413.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213413.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213413.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213414.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213414.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213414.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213414.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213414.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213414.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213414.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213414.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213414.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213414.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213414.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213414.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213414.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213414.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213415.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2f20]
>[213415.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2f20] width 1920 pitch 7680 (/4 1920)
>[213415.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213415.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213415.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213415.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213457.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213457.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213457.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213458.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213458.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213458.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213458.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213458.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213458.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213458.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213458.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213458.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213458.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213458.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213458.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213458.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213459.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213459.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213460.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213460.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213460.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213460.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213460.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213460.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213460.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213460.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213460.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213460.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213460.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213460.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213460.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213460.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213460.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213460.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[213460.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59972b0]
>[213460.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59972b0] width 1920 pitch 7680 (/4 1920)
>[213460.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afaa50]
>[213460.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afaa50] width 1920 pitch 7680 (/4 1920)
>[213460.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3044a00]
>[213461.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3044a00] width 1920 pitch 7680 (/4 1920)
>[213461.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca730]
>[213461.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca730] width 1920 pitch 7680 (/4 1920)
>[214180.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214180.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214180.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214180.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214180.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214180.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214180.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214180.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214180.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214180.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214180.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214180.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214180.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214180.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214180.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214180.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214180.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214180.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214181.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214181.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214181.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214181.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214181.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214181.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214181.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdbf60]
>[214181.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdbf60] width 1920 pitch 7680 (/4 1920)
>[214181.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214181.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214181.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdbf60]
>[214181.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdbf60] width 1920 pitch 7680 (/4 1920)
>[214181.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a10]
>[214181.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a10] width 1920 pitch 7680 (/4 1920)
>[214181.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdbf60]
>[214181.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdbf60] width 1920 pitch 7680 (/4 1920)
>[214181.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2faf390]
>[214181.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2faf390] width 1920 pitch 7680 (/4 1920)
>[214185.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d550]
>[214185.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d550] width 1920 pitch 7680 (/4 1920)
>[214221.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d000]
>[214221.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d000] width 1920 pitch 7680 (/4 1920)
>[214221.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024d80]
>[214221.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024d80] width 1920 pitch 7680 (/4 1920)
>[214221.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d000]
>[214222.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d000] width 1920 pitch 7680 (/4 1920)
>[214222.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024d80]
>[214222.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024d80] width 1920 pitch 7680 (/4 1920)
>[214222.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d000]
>[214222.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d000] width 1920 pitch 7680 (/4 1920)
>[214222.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024d80]
>[214222.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024d80] width 1920 pitch 7680 (/4 1920)
>[214222.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d000]
>[214222.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d000] width 1920 pitch 7680 (/4 1920)
>[214222.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024d80]
>[214222.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024d80] width 1920 pitch 7680 (/4 1920)
>[214222.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d470]
>[214222.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d470] width 1920 pitch 7680 (/4 1920)
>[214222.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982930]
>[214222.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982930] width 1920 pitch 7680 (/4 1920)
>[214223.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024d80]
>[214223.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024d80] width 1920 pitch 7680 (/4 1920)
>[214223.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d470]
>[214223.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d470] width 1920 pitch 7680 (/4 1920)
>[214223.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d470]
>[214223.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d470] width 1920 pitch 7680 (/4 1920)
>[214223.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d470]
>[214223.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d470] width 1920 pitch 7680 (/4 1920)
>[214223.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d470]
>[214223.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d470] width 1920 pitch 7680 (/4 1920)
>[214223.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50915d0]
>[214223.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50915d0] width 1920 pitch 7680 (/4 1920)
>[214223.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bbc50]
>[214223.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bbc50] width 1920 pitch 7680 (/4 1920)
>[214223.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f51b40]
>[214223.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f51b40] width 1920 pitch 7680 (/4 1920)
>[214228.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbe4d0]
>[214228.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbe4d0] width 1920 pitch 7680 (/4 1920)
>[214235.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ad2e60]
>[214235.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ad2e60] width 1920 pitch 7680 (/4 1920)
>[214235.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbe4d0]
>[214235.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbe4d0] width 1920 pitch 7680 (/4 1920)
>[214256.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214256.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214256.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214256.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214256.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214256.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214256.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214257.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214257.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214257.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214257.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214257.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214257.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214257.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214257.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30268c0]
>[214257.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30268c0] width 1920 pitch 7680 (/4 1920)
>[214257.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1b4a0]
>[214257.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1b4a0] width 1920 pitch 7680 (/4 1920)
>[214257.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f507d0]
>[214257.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f507d0] width 1920 pitch 7680 (/4 1920)
>[214261.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214261.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214261.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214261.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214261.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214261.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214261.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214261.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214261.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214261.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214261.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214261.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214261.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214261.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214261.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff6f0]
>[214261.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff6f0] width 1920 pitch 7680 (/4 1920)
>[214261.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369230]
>[214261.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369230] width 1920 pitch 7680 (/4 1920)
>[214261.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598cc70]
>[214261.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598cc70] width 1920 pitch 7680 (/4 1920)
>[214261.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30244f0]
>[214261.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30244f0] width 1920 pitch 7680 (/4 1920)
>[214261.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214261.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214261.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afa3f0]
>[214261.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afa3f0] width 1920 pitch 7680 (/4 1920)
>[214265.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214265.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214265.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5981920]
>[214265.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5981920] width 1920 pitch 7680 (/4 1920)
>[214265.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30244f0]
>[214265.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30244f0] width 1920 pitch 7680 (/4 1920)
>[214265.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214265.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214265.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214265.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214265.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214265.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214265.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214265.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214265.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214265.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214265.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214265.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214265.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1e120]
>[214265.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1e120] width 1920 pitch 7680 (/4 1920)
>[214265.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a5b0]
>[214265.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a5b0] width 1920 pitch 7680 (/4 1920)
>[214265.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30244f0]
>[214265.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30244f0] width 1920 pitch 7680 (/4 1920)
>[214265.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024620]
>[214265.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024620] width 1920 pitch 7680 (/4 1920)
>[214305.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214305.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214305.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028da0]
>[214305.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028da0] width 1920 pitch 7680 (/4 1920)
>[214305.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214305.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214305.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214305.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214305.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028da0]
>[214305.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028da0] width 1920 pitch 7680 (/4 1920)
>[214305.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214305.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214305.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214305.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214305.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214305.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214305.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214305.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214306.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214306.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214306.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214306.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214306.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214306.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214307.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214307.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214307.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214307.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214308.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214308.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214308.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214308.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214308.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214308.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214308.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598a6f0]
>[214308.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598a6f0] width 1920 pitch 7680 (/4 1920)
>[214308.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028da0]
>[214308.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028da0] width 1920 pitch 7680 (/4 1920)
>[214308.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028da0]
>[214308.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028da0] width 1920 pitch 7680 (/4 1920)
>[214316.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5620]
>[214316.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5620] width 1920 pitch 7680 (/4 1920)
>[214316.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214316.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214316.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214316.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214316.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214316.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214316.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214316.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214316.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214316.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214316.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[214316.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[214316.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214316.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214316.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f5620]
>[214316.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f5620] width 1920 pitch 7680 (/4 1920)
>[214317.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214317.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214317.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214317.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214317.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308c5e0]
>[214317.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308c5e0] width 1920 pitch 7680 (/4 1920)
>[214317.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edd60]
>[214317.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edd60] width 1920 pitch 7680 (/4 1920)
>[214317.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c3d8c0]
>[214317.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c3d8c0] width 1920 pitch 7680 (/4 1920)
>[214317.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febf80]
>[214317.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febf80] width 1920 pitch 7680 (/4 1920)
>[214317.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2febf80]
>[214317.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2febf80] width 1920 pitch 7680 (/4 1920)
>[214317.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214317.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214317.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214317.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214345.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214345.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214345.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214345.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214345.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214345.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214345.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214345.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214346.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214346.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214346.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214346.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214346.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214346.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214346.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214346.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214346.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214346.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214346.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214346.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214346.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214346.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214347.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214347.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214347.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214347.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214347.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b06750]
>[214347.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b06750] width 1920 pitch 7680 (/4 1920)
>[214347.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214347.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214347.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214347.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214347.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214347.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214347.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553b4f0]
>[214347.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553b4f0] width 1920 pitch 7680 (/4 1920)
>[214347.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598ac00]
>[214347.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598ac00] width 1920 pitch 7680 (/4 1920)
>[214399.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0a80]
>[214399.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0a80] width 1920 pitch 7680 (/4 1920)
>[214399.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214399.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214399.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214399.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214399.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214399.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214399.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214400.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0a80]
>[214400.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0a80] width 1920 pitch 7680 (/4 1920)
>[214400.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0a80]
>[214400.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0a80] width 1920 pitch 7680 (/4 1920)
>[214400.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d0f0]
>[214400.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d0f0] width 1920 pitch 7680 (/4 1920)
>[214400.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0a80]
>[214400.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0a80] width 1920 pitch 7680 (/4 1920)
>[214400.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214400.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214401.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0a80]
>[214401.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0a80] width 1920 pitch 7680 (/4 1920)
>[214401.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f45780]
>[214401.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f45780] width 1920 pitch 7680 (/4 1920)
>[214401.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d080]
>[214401.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d080] width 1920 pitch 7680 (/4 1920)
>[214401.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f5c0]
>[214401.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f5c0] width 1920 pitch 7680 (/4 1920)
>[214401.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6c80]
>[214401.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6c80] width 1920 pitch 7680 (/4 1920)
>[214401.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597d080]
>[214401.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597d080] width 1920 pitch 7680 (/4 1920)
>[214451.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214451.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214452.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553cd70]
>[214452.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553cd70] width 1920 pitch 7680 (/4 1920)
>[214452.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6aa0]
>[214452.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6aa0] width 1920 pitch 7680 (/4 1920)
>[214452.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214452.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214452.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6aa0]
>[214452.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6aa0] width 1920 pitch 7680 (/4 1920)
>[214452.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214452.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214452.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6aa0]
>[214452.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6aa0] width 1920 pitch 7680 (/4 1920)
>[214452.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214452.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214452.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6aa0]
>[214452.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6aa0] width 1920 pitch 7680 (/4 1920)
>[214452.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214452.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214452.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b6aa0]
>[214452.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b6aa0] width 1920 pitch 7680 (/4 1920)
>[214452.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214452.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214453.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214453.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214453.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214453.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214453.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214453.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214453.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214453.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214453.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214453.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214453.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214453.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214454.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214454.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214454.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214454.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214454.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214454.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214454.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aff1e0]
>[214454.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aff1e0] width 1920 pitch 7680 (/4 1920)
>[214454.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b69e0]
>[214454.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b69e0] width 1920 pitch 7680 (/4 1920)
>[214573.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015be0]
>[214573.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015be0] width 1920 pitch 7680 (/4 1920)
>[214573.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214573.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214573.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6bb0]
>[214573.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6bb0] width 1920 pitch 7680 (/4 1920)
>[214573.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b061a0]
>[214573.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b061a0] width 1920 pitch 7680 (/4 1920)
>[214573.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a50f0]
>[214573.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a50f0] width 1920 pitch 7680 (/4 1920)
>[214573.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4f20]
>[214573.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4f20] width 1920 pitch 7680 (/4 1920)
>[214573.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214573.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214573.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4f20]
>[214573.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4f20] width 1920 pitch 7680 (/4 1920)
>[214574.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a50f0]
>[214574.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a50f0] width 1920 pitch 7680 (/4 1920)
>[214574.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3041f50]
>[214574.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3041f50] width 1920 pitch 7680 (/4 1920)
>[214574.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6bb0]
>[214574.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6bb0] width 1920 pitch 7680 (/4 1920)
>[214574.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214574.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214575.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4f20]
>[214575.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4f20] width 1920 pitch 7680 (/4 1920)
>[214575.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6bb0]
>[214575.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6bb0] width 1920 pitch 7680 (/4 1920)
>[214575.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214575.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214576.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de2e0]
>[214576.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de2e0] width 1920 pitch 7680 (/4 1920)
>[214576.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4f20]
>[214576.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4f20] width 1920 pitch 7680 (/4 1920)
>[214576.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4f20]
>[214576.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4f20] width 1920 pitch 7680 (/4 1920)
>[214577.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54de2e0]
>[214577.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54de2e0] width 1920 pitch 7680 (/4 1920)
>[214577.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b061a0]
>[214577.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b061a0] width 1920 pitch 7680 (/4 1920)
>[214577.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6bb0]
>[214577.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6bb0] width 1920 pitch 7680 (/4 1920)
>[214577.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214577.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214577.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214577.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214577.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214577.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214599.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214599.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214599.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a50f0]
>[214599.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a50f0] width 1920 pitch 7680 (/4 1920)
>[214599.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a50f0]
>[214599.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a50f0] width 1920 pitch 7680 (/4 1920)
>[214599.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214599.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214601.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32020c0]
>[214601.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32020c0] width 1920 pitch 7680 (/4 1920)
>[214605.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b061a0]
>[214605.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b061a0] width 1920 pitch 7680 (/4 1920)
>[214605.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ad2d30]
>[214605.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ad2d30] width 1920 pitch 7680 (/4 1920)
>[214605.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b061a0]
>[214605.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b061a0] width 1920 pitch 7680 (/4 1920)
>[214605.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8b80]
>[214605.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8b80] width 1920 pitch 7680 (/4 1920)
>[214605.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214605.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214605.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8b80]
>[214605.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8b80] width 1920 pitch 7680 (/4 1920)
>[214605.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214605.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214605.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8b80]
>[214605.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8b80] width 1920 pitch 7680 (/4 1920)
>[214605.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214605.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214605.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8b80]
>[214605.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8b80] width 1920 pitch 7680 (/4 1920)
>[214605.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214605.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214605.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8b80]
>[214605.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8b80] width 1920 pitch 7680 (/4 1920)
>[214606.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214606.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214606.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b061a0]
>[214606.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b061a0] width 1920 pitch 7680 (/4 1920)
>[214609.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214609.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214609.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214609.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214609.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214609.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214609.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214609.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214609.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214609.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214610.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214610.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214610.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214610.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214610.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214610.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214610.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214610.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214610.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214610.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214610.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214610.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214610.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214610.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214610.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214610.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214612.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214612.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214628.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214628.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214736.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214736.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214736.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214736.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214736.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214736.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50deed0]
>[214736.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50deed0] width 1920 pitch 7680 (/4 1920)
>[214736.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5982030]
>[214736.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5982030] width 1920 pitch 7680 (/4 1920)
>[214738.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f47d40]
>[214738.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f47d40] width 1920 pitch 7680 (/4 1920)
>[214739.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3040540]
>[214739.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3040540] width 1920 pitch 7680 (/4 1920)
>[214741.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1ca30]
>[214741.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1ca30] width 1920 pitch 7680 (/4 1920)
>[214741.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214741.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214741.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ac4e0]
>[214741.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ac4e0] width 1920 pitch 7680 (/4 1920)
>[214741.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214741.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214741.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ac4e0]
>[214741.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ac4e0] width 1920 pitch 7680 (/4 1920)
>[214741.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214741.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214741.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ac4e0]
>[214741.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ac4e0] width 1920 pitch 7680 (/4 1920)
>[214741.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214741.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214741.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214741.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214741.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e80]
>[214741.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e80] width 1920 pitch 7680 (/4 1920)
>[214742.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214742.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214742.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e80]
>[214742.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e80] width 1920 pitch 7680 (/4 1920)
>[214742.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214742.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214804.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214804.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214804.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214804.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214804.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214804.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214804.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214804.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214804.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214805.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214805.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214805.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214805.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214805.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214805.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214805.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214805.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214805.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214805.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214805.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214805.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afae50]
>[214805.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afae50] width 1920 pitch 7680 (/4 1920)
>[214805.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214805.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214806.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214806.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214806.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1ca30]
>[214806.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1ca30] width 1920 pitch 7680 (/4 1920)
>[214806.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214806.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214807.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1ca30]
>[214807.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1ca30] width 1920 pitch 7680 (/4 1920)
>[214807.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214807.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214807.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214807.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214807.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214807.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214807.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214807.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214807.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214807.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214807.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555b2d0]
>[214807.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555b2d0] width 1920 pitch 7680 (/4 1920)
>[214807.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b9cc0]
>[214807.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b9cc0] width 1920 pitch 7680 (/4 1920)
>[214836.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54d95e0]
>[214836.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54d95e0] width 1920 pitch 7680 (/4 1920)
>[214837.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e14b0]
>[214837.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e14b0] width 1920 pitch 7680 (/4 1920)
>[214837.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1560]
>[214837.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1560] width 1920 pitch 7680 (/4 1920)
>[214837.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e14b0]
>[214837.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e14b0] width 1920 pitch 7680 (/4 1920)
>[214837.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1560]
>[214837.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1560] width 1920 pitch 7680 (/4 1920)
>[214837.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e14b0]
>[214837.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e14b0] width 1920 pitch 7680 (/4 1920)
>[214837.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1560]
>[214837.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1560] width 1920 pitch 7680 (/4 1920)
>[214837.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e14b0]
>[214837.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e14b0] width 1920 pitch 7680 (/4 1920)
>[214837.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0dd20]
>[214837.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0dd20] width 1920 pitch 7680 (/4 1920)
>[214837.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e14b0]
>[214837.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e14b0] width 1920 pitch 7680 (/4 1920)
>[214837.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a3400]
>[214837.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a3400] width 1920 pitch 7680 (/4 1920)
>[214837.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0d900]
>[214837.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0d900] width 1920 pitch 7680 (/4 1920)
>[214837.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0d960]
>[214837.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0d960] width 1920 pitch 7680 (/4 1920)
>[214837.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13290]
>[214837.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13290] width 1920 pitch 7680 (/4 1920)
>[214839.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214839.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214839.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3028610]
>[214839.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3028610] width 1920 pitch 7680 (/4 1920)
>[214840.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5534dc0]
>[214840.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5534dc0] width 1920 pitch 7680 (/4 1920)
>[214840.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214840.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214840.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214840.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214840.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214840.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214840.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214840.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214840.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214840.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214840.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214840.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214840.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214840.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214840.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214840.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214840.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[214842.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[214842.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214842.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[214842.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[214842.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214842.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[214842.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[214842.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214842.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[214842.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[214842.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1440]
>[214842.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1440] width 1920 pitch 7680 (/4 1920)
>[214842.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a37b0]
>[214842.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a37b0] width 1920 pitch 7680 (/4 1920)
>[214842.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b018e0]
>[214842.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b018e0] width 1920 pitch 7680 (/4 1920)
>[214842.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214842.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b018e0]
>[214842.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b018e0] width 1920 pitch 7680 (/4 1920)
>[214842.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214842.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214842.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a37b0]
>[214843.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a37b0] width 1920 pitch 7680 (/4 1920)
>[214843.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1440]
>[214843.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1440] width 1920 pitch 7680 (/4 1920)
>[214843.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[214843.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[214843.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b14c90]
>[214843.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b14c90] width 1920 pitch 7680 (/4 1920)
>[214843.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a37b0]
>[214843.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a37b0] width 1920 pitch 7680 (/4 1920)
>[214843.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308c5e0]
>[214843.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308c5e0] width 1920 pitch 7680 (/4 1920)
>[214843.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214843.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214843.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308c5e0]
>[214843.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308c5e0] width 1920 pitch 7680 (/4 1920)
>[214843.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214843.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214844.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x308c5e0]
>[214844.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x308c5e0] width 1920 pitch 7680 (/4 1920)
>[214871.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0d370]
>[214871.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0d370] width 1920 pitch 7680 (/4 1920)
>[214888.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214888.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214888.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214888.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214889.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987a90]
>[214889.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987a90] width 1920 pitch 7680 (/4 1920)
>[214889.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[214889.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[214889.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214889.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214889.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[214889.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[214889.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214889.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214889.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214889.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214890.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214890.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214890.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214890.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214890.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214890.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214890.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214890.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214890.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[214890.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[214891.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214891.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214892.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214892.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214892.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214892.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214892.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[214892.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[214892.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987a90]
>[214892.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987a90] width 1920 pitch 7680 (/4 1920)
>[214892.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987870]
>[214892.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987870] width 1920 pitch 7680 (/4 1920)
>[214892.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214892.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214908.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[214908.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[214908.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fdc50]
>[214908.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fdc50] width 1920 pitch 7680 (/4 1920)
>[214908.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214908.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214908.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[214908.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[214908.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214908.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[214908.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[214908.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[214908.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4070]
>[214908.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4070] width 1920 pitch 7680 (/4 1920)
>[214909.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[214909.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[214909.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214909.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214909.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[214909.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[214912.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[214912.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[214912.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[214912.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[214912.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[214912.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[214912.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54e1880]
>[214912.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54e1880] width 1920 pitch 7680 (/4 1920)
>[214912.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987a90]
>[214912.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987a90] width 1920 pitch 7680 (/4 1920)
>[214912.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[214913.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[214913.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fdc50]
>[214913.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fdc50] width 1920 pitch 7680 (/4 1920)
>[214913.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5986f80]
>[214913.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5986f80] width 1920 pitch 7680 (/4 1920)
>[215014.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[215014.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[215014.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[215014.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[215022.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[215022.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[215029.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[215029.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[215608.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[215608.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[215636.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[215636.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[215682.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4070]
>[215682.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4070] width 1920 pitch 7680 (/4 1920)
>[215769.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fae320]
>[215769.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fae320] width 1920 pitch 7680 (/4 1920)
>[217391.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4070]
>[217391.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4070] width 1920 pitch 7680 (/4 1920)
>[217391.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[217391.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[217391.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54fdc50]
>[217391.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54fdc50] width 1920 pitch 7680 (/4 1920)
>[217391.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d2840]
>[217391.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d2840] width 1920 pitch 7680 (/4 1920)
>[217391.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59cec10]
>[217391.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59cec10] width 1920 pitch 7680 (/4 1920)
>[217391.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37700]
>[217391.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37700] width 1920 pitch 7680 (/4 1920)
>[217391.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300ddb0]
>[217391.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300ddb0] width 1920 pitch 7680 (/4 1920)
>[217391.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3040590]
>[217391.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3040590] width 1920 pitch 7680 (/4 1920)
>[217392.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59cf3e0]
>[217392.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59cf3e0] width 1920 pitch 7680 (/4 1920)
>[217392.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217392.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217392.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[217392.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[217392.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a39730]
>[217392.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a39730] width 1920 pitch 7680 (/4 1920)
>[217392.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[217392.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[217392.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a33210]
>[217392.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a33210] width 1920 pitch 7680 (/4 1920)
>[217393.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c050]
>[217393.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c050] width 1920 pitch 7680 (/4 1920)
>[217443.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217443.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217443.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217443.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217443.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217444.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217444.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217444.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217444.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217444.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217444.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217444.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217444.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217444.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217444.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217444.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217444.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217444.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217444.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217444.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217444.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217444.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217445.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[217445.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[217445.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a39730]
>[217445.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a39730] width 1920 pitch 7680 (/4 1920)
>[217445.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217445.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217445.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59cec10]
>[217445.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59cec10] width 1920 pitch 7680 (/4 1920)
>[217445.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217445.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217445.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217445.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217456.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217456.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217456.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[217456.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[217456.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217456.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217456.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217456.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217456.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217456.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217456.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217456.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217456.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5988e20]
>[217456.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5988e20] width 1920 pitch 7680 (/4 1920)
>[217457.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217457.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217457.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217457.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217457.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217457.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217457.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[217457.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[217457.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4f3c0]
>[217457.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4f3c0] width 1920 pitch 7680 (/4 1920)
>[217457.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[217457.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[217457.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4f3c0]
>[217457.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4f3c0] width 1920 pitch 7680 (/4 1920)
>[217457.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[217457.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[217458.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4f3c0]
>[217458.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4f3c0] width 1920 pitch 7680 (/4 1920)
>[217458.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[217458.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[217458.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a33e70]
>[217458.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a33e70] width 1920 pitch 7680 (/4 1920)
>[217458.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[217458.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[217458.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a432e0]
>[217458.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a432e0] width 1920 pitch 7680 (/4 1920)
>[217458.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[217458.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[217458.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a432e0]
>[217458.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a432e0] width 1920 pitch 7680 (/4 1920)
>[217458.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[217458.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[217458.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217459.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217459.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[217459.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[217459.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217459.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217459.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[217459.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[217459.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217459.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217459.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[217459.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[217459.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b1d410]
>[217459.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b1d410] width 1920 pitch 7680 (/4 1920)
>[217459.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[217459.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[217459.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b066b0]
>[217459.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b066b0] width 1920 pitch 7680 (/4 1920)
>[217459.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c910]
>[217459.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c910] width 1920 pitch 7680 (/4 1920)
>[217459.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217459.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217460.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3027e70]
>[217460.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3027e70] width 1920 pitch 7680 (/4 1920)
>[217460.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217460.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217460.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217460.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217460.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217460.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217460.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a417f0]
>[217460.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a417f0] width 1920 pitch 7680 (/4 1920)
>[217460.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[217460.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[217460.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4f3c0]
>[217460.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4f3c0] width 1920 pitch 7680 (/4 1920)
>[217476.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5547260]
>[217476.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5547260] width 1920 pitch 7680 (/4 1920)
>[217681.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565e40]
>[217681.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565e40] width 1920 pitch 7680 (/4 1920)
>[217687.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217687.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970b10]
>[217687.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970b10] width 1920 pitch 7680 (/4 1920)
>[217687.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217687.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970b10]
>[217687.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970b10] width 1920 pitch 7680 (/4 1920)
>[217687.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217687.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a56cf0]
>[217687.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a56cf0] width 1920 pitch 7680 (/4 1920)
>[217687.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217687.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970b10]
>[217687.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970b10] width 1920 pitch 7680 (/4 1920)
>[217687.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a56b90]
>[217687.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a56b90] width 1920 pitch 7680 (/4 1920)
>[217687.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970b10]
>[217687.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970b10] width 1920 pitch 7680 (/4 1920)
>[217687.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217687.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970b10]
>[217687.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970b10] width 1920 pitch 7680 (/4 1920)
>[217687.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da2c40]
>[217687.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da2c40] width 1920 pitch 7680 (/4 1920)
>[217696.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217696.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217696.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217696.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217696.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217696.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217696.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217696.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217696.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217696.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217696.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217696.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217696.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217696.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217696.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217696.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217696.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217697.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217697.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217697.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217697.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217697.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217697.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b13f50]
>[217697.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b13f50] width 1920 pitch 7680 (/4 1920)
>[217697.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5555e60]
>[217697.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5555e60] width 1920 pitch 7680 (/4 1920)
>[217781.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5bf20]
>[217781.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5bf20] width 1920 pitch 7680 (/4 1920)
>[217781.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a55540]
>[217781.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a55540] width 1920 pitch 7680 (/4 1920)
>[217781.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a32d90]
>[217781.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a32d90] width 1920 pitch 7680 (/4 1920)
>[217781.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c110]
>[217781.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c110] width 1920 pitch 7680 (/4 1920)
>[217781.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c110]
>[217781.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c110] width 1920 pitch 7680 (/4 1920)
>[217781.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a32d90]
>[217781.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a32d90] width 1920 pitch 7680 (/4 1920)
>[217781.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c110]
>[217781.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c110] width 1920 pitch 7680 (/4 1920)
>[217781.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5d920]
>[217781.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5d920] width 1920 pitch 7680 (/4 1920)
>[217781.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c110]
>[217781.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c110] width 1920 pitch 7680 (/4 1920)
>[217781.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a32d90]
>[217781.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a32d90] width 1920 pitch 7680 (/4 1920)
>[217781.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5d920]
>[217781.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5d920] width 1920 pitch 7680 (/4 1920)
>[217781.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c110]
>[217781.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c110] width 1920 pitch 7680 (/4 1920)
>[217784.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5556600]
>[217784.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5556600] width 1920 pitch 7680 (/4 1920)
>[217784.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc5a0]
>[217784.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc5a0] width 1920 pitch 7680 (/4 1920)
>[217785.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5c510]
>[217785.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5c510] width 1920 pitch 7680 (/4 1920)
>[217785.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217785.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217785.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217785.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217785.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217785.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217785.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217785.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217785.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217785.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217785.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217785.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217787.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217787.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217788.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217788.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217788.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217788.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217788.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217788.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217788.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217788.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217788.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217788.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217789.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217789.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217789.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217789.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217789.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217789.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a653f0]
>[217789.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a653f0] width 1920 pitch 7680 (/4 1920)
>[217789.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217789.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217789.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217789.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217789.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217789.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217789.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217789.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217825.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217825.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217825.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217825.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217858.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217858.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217858.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217858.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217858.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217858.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217858.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217859.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217859.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217859.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217859.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217859.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217859.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217859.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217859.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217859.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217859.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217859.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217859.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217859.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217859.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217859.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217859.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217859.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217859.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217859.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217863.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217863.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217863.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217863.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217863.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217863.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217863.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217863.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217867.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[217867.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[217867.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cc460]
>[217867.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cc460] width 1920 pitch 7680 (/4 1920)
>[217942.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5565d50]
>[217942.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5565d50] width 1920 pitch 7680 (/4 1920)
>[218152.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00340]
>[218152.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00340] width 1920 pitch 7680 (/4 1920)
>[218152.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f265b0]
>[218152.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f265b0] width 1920 pitch 7680 (/4 1920)
>[218153.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a29250]
>[218153.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a29250] width 1920 pitch 7680 (/4 1920)
>[218156.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fa7b0]
>[218156.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fa7b0] width 1920 pitch 7680 (/4 1920)
>[218157.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a93fe0]
>[218157.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a93fe0] width 1920 pitch 7680 (/4 1920)
>[218157.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218157.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218157.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218157.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218158.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218158.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218158.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218158.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218158.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218158.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218158.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218158.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218158.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218158.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218158.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218158.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218158.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218158.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218158.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218158.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218159.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218159.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218159.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218159.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218159.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218159.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218159.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218159.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218159.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218159.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218159.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218159.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218159.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218160.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218160.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17a80]
>[218160.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17a80] width 1920 pitch 7680 (/4 1920)
>[218160.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12f60]
>[218160.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12f60] width 1920 pitch 7680 (/4 1920)
>[218160.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffc620]
>[218160.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffc620] width 1920 pitch 7680 (/4 1920)
>[218161.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aad6f0]
>[218161.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aad6f0] width 1920 pitch 7680 (/4 1920)
>[218161.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a12d70]
>[218161.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a12d70] width 1920 pitch 7680 (/4 1920)
>[218161.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfdc40]
>[218161.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfdc40] width 1920 pitch 7680 (/4 1920)
>[218161.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a93040]
>[218161.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a93040] width 1920 pitch 7680 (/4 1920)
>[218161.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e96b0]
>[218161.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e96b0] width 1920 pitch 7680 (/4 1920)
>[218161.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58990]
>[218161.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58990] width 1920 pitch 7680 (/4 1920)
>[218161.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03740]
>[218161.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03740] width 1920 pitch 7680 (/4 1920)
>[218161.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218162.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218162.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218162.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218162.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218162.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218162.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218162.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218162.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218162.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218162.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218162.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218162.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218163.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218163.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218163.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218163.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218163.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218163.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218163.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218163.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218163.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218164.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218164.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218164.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b03660]
>[218164.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b03660] width 1920 pitch 7680 (/4 1920)
>[218165.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a07b80]
>[218165.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a07b80] width 1920 pitch 7680 (/4 1920)
>[218165.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58990]
>[218165.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58990] width 1920 pitch 7680 (/4 1920)
>[218165.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326ba70]
>[218165.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326ba70] width 1920 pitch 7680 (/4 1920)
>[218165.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a18580]
>[218165.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a18580] width 1920 pitch 7680 (/4 1920)
>[218165.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306fdf0]
>[218165.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306fdf0] width 1920 pitch 7680 (/4 1920)
>[218165.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a93040]
>[218165.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a93040] width 1920 pitch 7680 (/4 1920)
>[218172.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a06240]
>[218172.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a06240] width 1920 pitch 7680 (/4 1920)
>[218172.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x306f440]
>[218172.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x306f440] width 1920 pitch 7680 (/4 1920)
>[218177.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a08500]
>[218177.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a08500] width 1920 pitch 7680 (/4 1920)
>[218179.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abba40]
>[218179.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abba40] width 1920 pitch 7680 (/4 1920)
>[218179.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab3bb0]
>[218179.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab3bb0] width 1920 pitch 7680 (/4 1920)
>[218181.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abfb90]
>[218181.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abfb90] width 1920 pitch 7680 (/4 1920)
>[218181.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x596ff70]
>[218181.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x596ff70] width 1920 pitch 7680 (/4 1920)
>[218181.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac9840]
>[218181.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac9840] width 1920 pitch 7680 (/4 1920)
>[218181.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abfb90]
>[218181.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abfb90] width 1920 pitch 7680 (/4 1920)
>[218181.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abb770]
>[218181.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abb770] width 1920 pitch 7680 (/4 1920)
>[218182.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218182.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218183.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00340]
>[218183.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00340] width 1920 pitch 7680 (/4 1920)
>[218183.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab57e0]
>[218183.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab57e0] width 1920 pitch 7680 (/4 1920)
>[218183.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab57e0]
>[218183.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab57e0] width 1920 pitch 7680 (/4 1920)
>[218183.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac0010]
>[218184.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac0010] width 1920 pitch 7680 (/4 1920)
>[218184.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab57e0]
>[218184.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab57e0] width 1920 pitch 7680 (/4 1920)
>[218184.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac0010]
>[218184.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac0010] width 1920 pitch 7680 (/4 1920)
>[218184.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5530]
>[218184.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5530] width 1920 pitch 7680 (/4 1920)
>[218184.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8a60]
>[218184.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8a60] width 1920 pitch 7680 (/4 1920)
>[218184.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5530]
>[218184.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5530] width 1920 pitch 7680 (/4 1920)
>[218184.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab5530]
>[218184.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab5530] width 1920 pitch 7680 (/4 1920)
>[218184.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab57e0]
>[218184.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab57e0] width 1920 pitch 7680 (/4 1920)
>[218184.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab57e0]
>[218184.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab57e0] width 1920 pitch 7680 (/4 1920)
>[218184.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8ce0]
>[218184.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8ce0] width 1920 pitch 7680 (/4 1920)
>[218192.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218192.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218214.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa8d0]
>[218214.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa8d0] width 1920 pitch 7680 (/4 1920)
>[218228.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218228.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218228.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e9470]
>[218228.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e9470] width 1920 pitch 7680 (/4 1920)
>[218228.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218228.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218228.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59efa50]
>[218228.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59efa50] width 1920 pitch 7680 (/4 1920)
>[218228.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e9470]
>[218228.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e9470] width 1920 pitch 7680 (/4 1920)
>[218228.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5d240]
>[218228.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5d240] width 1920 pitch 7680 (/4 1920)
>[218228.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5d240]
>[218229.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5d240] width 1920 pitch 7680 (/4 1920)
>[218229.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa8d0]
>[218229.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa8d0] width 1920 pitch 7680 (/4 1920)
>[218229.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa8d0]
>[218229.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa8d0] width 1920 pitch 7680 (/4 1920)
>[218229.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e9470]
>[218229.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e9470] width 1920 pitch 7680 (/4 1920)
>[218229.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218229.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218230.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e9470]
>[218230.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e9470] width 1920 pitch 7680 (/4 1920)
>[218231.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e9470]
>[218231.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e9470] width 1920 pitch 7680 (/4 1920)
>[218232.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fdcb0]
>[218232.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fdcb0] width 1920 pitch 7680 (/4 1920)
>[218232.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218232.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218232.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218232.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218232.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218232.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218232.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218232.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218232.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218232.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218264.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218264.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218264.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218264.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218264.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218264.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218264.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218264.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218264.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218264.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218264.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218264.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218264.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218264.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218264.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218264.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218264.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218264.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218264.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218264.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218264.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218264.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218264.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218264.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218264.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218264.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218264.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218264.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218268.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218268.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218268.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218268.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218268.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218268.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218268.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218268.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218268.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218268.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218268.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218268.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218268.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218268.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218268.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218268.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218268.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218268.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218268.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218268.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218268.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218268.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218268.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218268.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218268.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218268.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218270.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218270.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218270.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218270.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218270.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218271.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218271.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218271.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218271.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218271.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218271.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218271.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218271.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218271.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218271.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218271.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218271.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218271.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218272.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218272.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218272.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b80]
>[218272.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b80] width 1920 pitch 7680 (/4 1920)
>[218272.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[218272.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[218272.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05590]
>[218272.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05590] width 1920 pitch 7680 (/4 1920)
>[218272.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218272.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218272.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218272.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218272.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218272.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218272.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a0ab70]
>[218272.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a0ab70] width 1920 pitch 7680 (/4 1920)
>[218273.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218273.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218273.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05590]
>[218273.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05590] width 1920 pitch 7680 (/4 1920)
>[218273.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218273.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218273.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a0ab70]
>[218273.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a0ab70] width 1920 pitch 7680 (/4 1920)
>[218273.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05590]
>[218273.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05590] width 1920 pitch 7680 (/4 1920)
>[218273.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8160]
>[218273.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8160] width 1920 pitch 7680 (/4 1920)
>[218274.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a0ab70]
>[218274.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a0ab70] width 1920 pitch 7680 (/4 1920)
>[218274.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05590]
>[218274.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05590] width 1920 pitch 7680 (/4 1920)
>[218274.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a0ab70]
>[218274.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a0ab70] width 1920 pitch 7680 (/4 1920)
>[218274.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218274.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218274.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[218274.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[218274.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218274.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218274.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218274.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218274.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218274.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218274.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218274.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218274.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218274.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218274.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218274.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218274.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218274.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218282.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218282.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218282.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218282.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218282.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218282.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218282.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218282.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218282.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218283.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218283.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[218283.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[218283.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218283.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218283.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218283.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218283.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218283.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218283.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[218283.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[218283.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218283.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218283.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218283.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218284.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[218284.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[218285.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[218285.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[218286.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[218286.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[218287.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[218287.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[218287.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[218287.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[218287.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052590]
>[218288.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052590] width 1920 pitch 7680 (/4 1920)
>[218288.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[218288.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[218288.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a4f3c0]
>[218288.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a4f3c0] width 1920 pitch 7680 (/4 1920)
>[218288.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a37700]
>[218288.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a37700] width 1920 pitch 7680 (/4 1920)
>[218288.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3027e70]
>[218288.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3027e70] width 1920 pitch 7680 (/4 1920)
>[218295.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[218295.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[218297.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f92710]
>[218297.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f92710] width 1920 pitch 7680 (/4 1920)
>[218300.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa8fb0]
>[218300.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa8fb0] width 1920 pitch 7680 (/4 1920)
>[218365.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1d220]
>[218365.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1d220] width 1920 pitch 7680 (/4 1920)
>[218365.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab3d80]
>[218365.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab3d80] width 1920 pitch 7680 (/4 1920)
>[218365.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218365.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218365.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab3d80]
>[218365.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab3d80] width 1920 pitch 7680 (/4 1920)
>[218365.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218365.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218365.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab3d80]
>[218365.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab3d80] width 1920 pitch 7680 (/4 1920)
>[218369.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554f0a0]
>[218369.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554f0a0] width 1920 pitch 7680 (/4 1920)
>[218373.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554f0a0]
>[218373.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554f0a0] width 1920 pitch 7680 (/4 1920)
>[218373.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f92e60]
>[218373.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f92e60] width 1920 pitch 7680 (/4 1920)
>[218373.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaaba0]
>[218373.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaaba0] width 1920 pitch 7680 (/4 1920)
>[218373.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f92e60]
>[218373.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f92e60] width 1920 pitch 7680 (/4 1920)
>[218373.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553dc60]
>[218373.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553dc60] width 1920 pitch 7680 (/4 1920)
>[218373.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554f0a0]
>[218373.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554f0a0] width 1920 pitch 7680 (/4 1920)
>[218373.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff92c0]
>[218374.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff92c0] width 1920 pitch 7680 (/4 1920)
>[218374.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f92e60]
>[218374.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f92e60] width 1920 pitch 7680 (/4 1920)
>[218442.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a085e0]
>[218442.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a085e0] width 1920 pitch 7680 (/4 1920)
>[218442.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a085e0]
>[218442.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a085e0] width 1920 pitch 7680 (/4 1920)
>[218442.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a085e0]
>[218443.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a085e0] width 1920 pitch 7680 (/4 1920)
>[218443.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218443.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218443.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a085e0]
>[218443.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a085e0] width 1920 pitch 7680 (/4 1920)
>[218443.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553dc60]
>[218443.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553dc60] width 1920 pitch 7680 (/4 1920)
>[218443.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553dc60]
>[218443.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553dc60] width 1920 pitch 7680 (/4 1920)
>[218447.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218447.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218447.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553dc60]
>[218447.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553dc60] width 1920 pitch 7680 (/4 1920)
>[218447.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218447.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218447.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553dc60]
>[218447.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553dc60] width 1920 pitch 7680 (/4 1920)
>[218447.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218447.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218447.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[218447.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[218447.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87440]
>[218447.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87440] width 1920 pitch 7680 (/4 1920)
>[218447.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87440]
>[218447.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87440] width 1920 pitch 7680 (/4 1920)
>[218447.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87440]
>[218447.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87440] width 1920 pitch 7680 (/4 1920)
>[218779.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab3a30]
>[218779.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab3a30] width 1920 pitch 7680 (/4 1920)
>[218779.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f4840]
>[218779.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f4840] width 1920 pitch 7680 (/4 1920)
>[218810.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58e30]
>[218810.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58e30] width 1920 pitch 7680 (/4 1920)
>[218812.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a24ca0]
>[218812.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a24ca0] width 1920 pitch 7680 (/4 1920)
>[218866.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218866.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218866.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218867.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218867.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218867.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218867.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218867.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218867.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218867.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218867.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218868.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218868.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218868.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c75e00]
>[218868.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c75e00] width 1920 pitch 7680 (/4 1920)
>[218868.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fdcb0]
>[218868.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fdcb0] width 1920 pitch 7680 (/4 1920)
>[218868.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a973a0]
>[218868.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a973a0] width 1920 pitch 7680 (/4 1920)
>[218868.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fdcb0]
>[218868.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fdcb0] width 1920 pitch 7680 (/4 1920)
>[218868.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a973a0]
>[218868.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a973a0] width 1920 pitch 7680 (/4 1920)
>[218868.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fdcb0]
>[218868.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fdcb0] width 1920 pitch 7680 (/4 1920)
>[218869.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f77810]
>[218869.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f77810] width 1920 pitch 7680 (/4 1920)
>[219050.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219050.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219051.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219051.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219051.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219051.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219051.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219051.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219051.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219051.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219051.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219051.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219051.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219051.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219052.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219052.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219052.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219052.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219052.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219052.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219053.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219053.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219054.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219054.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219056.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219056.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219056.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219056.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219056.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5add8b0]
>[219056.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5add8b0] width 1920 pitch 7680 (/4 1920)
>[219056.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61d70]
>[219056.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61d70] width 1920 pitch 7680 (/4 1920)
>[219056.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5710]
>[219056.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5710] width 1920 pitch 7680 (/4 1920)
>[219056.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5710]
>[219056.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5710] width 1920 pitch 7680 (/4 1920)
>[219324.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54f4120]
>[219324.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54f4120] width 1920 pitch 7680 (/4 1920)
>[219324.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b0cae0]
>[219324.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b0cae0] width 1920 pitch 7680 (/4 1920)
>[219376.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219376.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219376.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219376.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219376.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219376.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219376.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219376.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219376.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219376.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219376.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219376.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219377.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219377.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219377.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219377.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219377.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219377.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219377.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219377.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219377.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219377.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219378.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219378.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219378.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219378.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219378.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219378.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219378.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219378.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219378.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219378.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219378.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219378.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219379.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219379.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219379.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219379.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219379.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219379.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219380.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219380.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219380.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219380.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219380.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219380.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219381.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219381.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219382.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219382.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219382.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219382.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219382.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219382.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219382.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219382.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219382.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5aaa750]
>[219382.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5aaa750] width 1920 pitch 7680 (/4 1920)
>[219382.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf8860]
>[219382.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf8860] width 1920 pitch 7680 (/4 1920)
>[219382.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd6e80]
>[219382.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd6e80] width 1920 pitch 7680 (/4 1920)
>[219382.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219382.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219382.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd5380]
>[219383.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd5380] width 1920 pitch 7680 (/4 1920)
>[219383.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf8860]
>[219383.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf8860] width 1920 pitch 7680 (/4 1920)
>[219383.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd6e80]
>[219383.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd6e80] width 1920 pitch 7680 (/4 1920)
>[219383.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219383.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219383.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf8860]
>[219383.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf8860] width 1920 pitch 7680 (/4 1920)
>[219383.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff5f90]
>[219383.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff5f90] width 1920 pitch 7680 (/4 1920)
>[219383.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd28b0]
>[219383.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd28b0] width 1920 pitch 7680 (/4 1920)
>[219475.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219475.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219475.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219475.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219475.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219475.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219475.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219475.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219475.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219475.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219475.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219475.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219475.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219475.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219475.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219475.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219479.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219479.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219479.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219479.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219479.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219480.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219480.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219480.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219480.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219480.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219480.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219480.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219480.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219480.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219480.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219480.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219550.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219550.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219550.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219550.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219550.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219550.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219550.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219550.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219550.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219550.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219550.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219550.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219550.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219550.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219554.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219554.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219554.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219554.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219554.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219555.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219555.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219555.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219555.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7430]
>[219555.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7430] width 1920 pitch 7680 (/4 1920)
>[219555.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219555.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219555.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219555.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[219555.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5580a80]
>[219555.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5580a80] width 1920 pitch 7680 (/4 1920)
>[221008.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[221008.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[221008.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[221008.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[221008.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[221008.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[221008.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[221008.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[221008.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[221008.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[221008.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[221008.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[221009.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[221009.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[221009.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[221009.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[221009.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[221009.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[221009.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[221009.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[221009.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[221009.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[221010.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[221010.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[221010.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[221010.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[221010.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[221010.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[222069.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222069.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222070.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222070.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222070.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222070.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222070.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555a4a0]
>[222070.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555a4a0] width 1920 pitch 7680 (/4 1920)
>[222070.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222070.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222070.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222070.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222070.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555a4a0]
>[222070.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555a4a0] width 1920 pitch 7680 (/4 1920)
>[222070.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222070.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222071.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x555a4a0]
>[222071.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x555a4a0] width 1920 pitch 7680 (/4 1920)
>[222071.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222071.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222071.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[222071.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[222071.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222071.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222071.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222071.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222071.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[222071.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[222071.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222072.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222072.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[222072.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[222072.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70190]
>[222072.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70190] width 1920 pitch 7680 (/4 1920)
>[222072.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222072.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222072.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[222072.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[222072.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc9da0]
>[222072.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc9da0] width 1920 pitch 7680 (/4 1920)
>[222072.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222072.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222073.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70190]
>[222073.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70190] width 1920 pitch 7680 (/4 1920)
>[222073.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222073.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222073.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222073.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222073.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[222073.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[222073.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70190]
>[222073.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70190] width 1920 pitch 7680 (/4 1920)
>[222074.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2fa30]
>[222074.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2fa30] width 1920 pitch 7680 (/4 1920)
>[222074.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[222074.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[222075.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70190]
>[222075.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70190] width 1920 pitch 7680 (/4 1920)
>[222075.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222075.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222075.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222075.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222075.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222075.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222075.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222075.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222075.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x557f920]
>[222075.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x557f920] width 1920 pitch 7680 (/4 1920)
>[222075.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4f200]
>[222075.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4f200] width 1920 pitch 7680 (/4 1920)
>[223863.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223863.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223863.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223863.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223863.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223863.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223863.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223863.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223863.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223863.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223863.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223863.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223864.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223864.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223864.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223864.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223864.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223864.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223868.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223868.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223868.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223868.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223868.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223868.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223868.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223868.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223868.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223868.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223868.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223868.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223868.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3a0]
>[223868.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3a0] width 1920 pitch 7680 (/4 1920)
>[223868.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223868.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223868.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223868.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223993.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223993.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223993.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223993.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223993.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223993.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223993.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223993.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223993.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223993.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223993.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223993.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223993.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223993.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223994.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223994.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223994.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223994.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223995.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223995.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223995.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a990]
>[223995.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a990] width 1920 pitch 7680 (/4 1920)
>[223995.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223995.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223995.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223995.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223995.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223995.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223995.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223995.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223995.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223995.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223995.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223996.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223996.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223996.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223996.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223996.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223997.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223997.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223997.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ed70]
>[223997.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ed70] width 1920 pitch 7680 (/4 1920)
>[223998.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30062b0]
>[223998.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30062b0] width 1920 pitch 7680 (/4 1920)
>[223998.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a250]
>[223998.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a250] width 1920 pitch 7680 (/4 1920)
>[223999.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3e0]
>[223999.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3e0] width 1920 pitch 7680 (/4 1920)
>[223999.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50746f0]
>[223999.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50746f0] width 1920 pitch 7680 (/4 1920)
>[223999.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb580]
>[223999.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb580] width 1920 pitch 7680 (/4 1920)
>[223999.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x320f330]
>[224000.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x320f330] width 1920 pitch 7680 (/4 1920)
>[224000.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7a3e0]
>[224000.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7a3e0] width 1920 pitch 7680 (/4 1920)
>[224000.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3291990]
>[224000.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3291990] width 1920 pitch 7680 (/4 1920)
>[224169.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224169.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224169.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224169.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224169.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224169.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224169.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224169.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224169.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224169.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224169.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224173.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224173.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224173.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72780]
>[224173.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72780] width 1920 pitch 7680 (/4 1920)
>[224173.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224173.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224173.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72780]
>[224173.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72780] width 1920 pitch 7680 (/4 1920)
>[224173.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224173.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224173.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224174.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224174.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224174.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224174.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72780]
>[224174.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72780] width 1920 pitch 7680 (/4 1920)
>[224283.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224283.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224283.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72780]
>[224283.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72780] width 1920 pitch 7680 (/4 1920)
>[224283.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224283.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224283.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224283.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224283.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d72780]
>[224283.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d72780] width 1920 pitch 7680 (/4 1920)
>[224283.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224283.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224283.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224283.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224287.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224287.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224287.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554df60]
>[224287.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554df60] width 1920 pitch 7680 (/4 1920)
>[224287.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224287.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224287.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224287.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224287.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554df60]
>[224287.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554df60] width 1920 pitch 7680 (/4 1920)
>[224287.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224287.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224287.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554e000]
>[224287.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554e000] width 1920 pitch 7680 (/4 1920)
>[224287.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x554df60]
>[224287.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x554df60] width 1920 pitch 7680 (/4 1920)
>[224943.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224943.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224943.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224943.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224943.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e060]
>[224943.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e060] width 1920 pitch 7680 (/4 1920)
>[224943.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224943.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224943.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224943.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224943.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e060]
>[224943.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e060] width 1920 pitch 7680 (/4 1920)
>[224943.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224943.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224943.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224943.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224944.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e060]
>[224944.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e060] width 1920 pitch 7680 (/4 1920)
>[224944.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224944.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224944.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224944.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224944.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224944.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224945.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224945.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224945.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50618a0]
>[224945.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50618a0] width 1920 pitch 7680 (/4 1920)
>[224946.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224946.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224946.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224946.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224946.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224946.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8d6b0]
>[224946.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8d6b0] width 1920 pitch 7680 (/4 1920)
>[224946.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8de30]
>[224946.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8de30] width 1920 pitch 7680 (/4 1920)
>[224957.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8d6b0]
>[224957.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8d6b0] width 1920 pitch 7680 (/4 1920)
>[225457.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c2a0]
>[225457.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c2a0] width 1920 pitch 7680 (/4 1920)
>[225457.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225457.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c2a0]
>[225457.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c2a0] width 1920 pitch 7680 (/4 1920)
>[225457.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[225457.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[225457.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225457.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225457.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225457.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225457.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225457.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225457.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225457.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225457.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225457.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225457.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225457.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225457.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225457.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225461.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225461.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225461.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225461.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225462.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225462.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225462.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225462.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225462.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225462.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225462.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225462.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225462.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225462.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225462.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225462.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225462.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225462.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225462.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225778.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225778.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225778.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8dc00]
>[225778.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8dc00] width 1920 pitch 7680 (/4 1920)
>[225778.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225778.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225778.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225778.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225778.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225778.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225778.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225779.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225779.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225779.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225779.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225779.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225779.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225779.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225779.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225779.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225779.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225779.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225783.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225783.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225783.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225783.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[225783.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[225783.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[225783.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[225783.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226148.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226148.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226148.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226148.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226152.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226152.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226152.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226152.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226152.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226152.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226152.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226152.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226152.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226152.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226152.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226153.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226153.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226153.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226153.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226153.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226153.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226153.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226153.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226153.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226153.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226153.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226153.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226153.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226153.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226153.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226154.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226154.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226154.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226154.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226154.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226154.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226154.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226154.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226154.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7d4f0]
>[226154.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7d4f0] width 1920 pitch 7680 (/4 1920)
>[226154.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006280]
>[226154.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006280] width 1920 pitch 7680 (/4 1920)
>[226434.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226434.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226434.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226434.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226434.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226434.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226434.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226434.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226434.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226434.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226434.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226435.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226435.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226435.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226435.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226435.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226435.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226435.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226439.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226439.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226439.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226439.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[226439.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[226439.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[226439.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[226439.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227063.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227063.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227063.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227063.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227067.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227067.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227067.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227067.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227067.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227067.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227067.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227067.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227067.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227067.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227067.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227067.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227067.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227067.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227067.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227068.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227068.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227068.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227068.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227068.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227068.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227068.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227557.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227557.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227557.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227557.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227557.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227557.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227557.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227557.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227557.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227557.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227557.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227557.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227557.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227557.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227558.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227558.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227559.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227559.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227559.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227559.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227559.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227559.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227559.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227559.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227559.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227559.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227559.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227559.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227559.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227559.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227559.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227559.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227559.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227559.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227559.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227559.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227559.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227559.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227559.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227559.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227559.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227559.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227560.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227560.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227560.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227560.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227560.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227560.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227560.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227560.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227560.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227560.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227560.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227560.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227560.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227560.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227560.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227560.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227560.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227560.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227561.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227561.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227562.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc8200]
>[227562.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc8200] width 1920 pitch 7680 (/4 1920)
>[227563.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227563.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227563.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227563.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227563.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227563.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227563.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227563.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227563.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227563.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227563.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227563.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227563.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227563.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227563.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227563.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227564.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227564.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227564.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227564.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227564.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227564.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227564.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227564.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227565.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227565.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227565.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227565.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227565.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227565.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227565.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227565.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227566.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227566.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227566.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227566.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227566.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227566.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227566.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227566.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227567.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227567.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227567.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227567.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227567.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227567.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227567.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227567.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227567.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227567.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227567.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227567.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227567.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227567.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227567.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227567.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227568.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227568.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227568.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227568.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227568.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227568.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227569.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227569.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227570.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227570.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227571.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227571.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227571.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227571.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227571.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227571.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227571.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227571.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227571.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227571.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227571.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227571.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227571.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227571.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227571.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227571.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227571.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227571.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227571.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227571.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227571.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227571.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227571.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227571.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227572.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227572.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227572.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227572.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227572.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227572.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227572.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227572.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227587.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227587.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227644.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227644.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227666.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227666.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227666.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227666.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227666.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227666.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227666.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227666.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227666.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227666.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227666.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227666.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227666.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227666.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227666.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227666.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227666.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227666.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227666.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227666.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227666.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227666.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227666.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227666.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227666.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227666.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227666.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227666.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227666.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227666.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227673.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227673.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227673.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227673.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227673.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227673.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227673.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227673.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227673.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f262c0]
>[227673.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f262c0] width 1920 pitch 7680 (/4 1920)
>[227673.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227673.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227673.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227673.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227707.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304e740]
>[227707.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304e740] width 1920 pitch 7680 (/4 1920)
>[227713.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227713.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227713.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227713.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227714.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227714.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227718.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227718.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227718.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227718.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227718.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c804c0]
>[227718.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c804c0] width 1920 pitch 7680 (/4 1920)
>[227718.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227718.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227718.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c804c0]
>[227718.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c804c0] width 1920 pitch 7680 (/4 1920)
>[227718.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c804c0]
>[227718.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c804c0] width 1920 pitch 7680 (/4 1920)
>[227719.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227719.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227719.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227719.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227719.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227719.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227719.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227719.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227719.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227719.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227719.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227719.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227719.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227719.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227719.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227719.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227734.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227734.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227734.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227734.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227754.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c803e0]
>[227754.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c803e0] width 1920 pitch 7680 (/4 1920)
>[227754.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227754.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227755.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c803e0]
>[227755.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c803e0] width 1920 pitch 7680 (/4 1920)
>[227755.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7e60]
>[227755.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7e60] width 1920 pitch 7680 (/4 1920)
>[227764.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c803e0]
>[227764.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c803e0] width 1920 pitch 7680 (/4 1920)
>[227765.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227765.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227766.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227766.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227766.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227766.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227767.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227767.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227767.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227767.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227767.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227767.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227767.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227767.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227768.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3103660]
>[227768.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3103660] width 1920 pitch 7680 (/4 1920)
>[227768.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dce2d0]
>[227768.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dce2d0] width 1920 pitch 7680 (/4 1920)
>[227768.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ed680]
>[227768.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ed680] width 1920 pitch 7680 (/4 1920)
>[227768.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227768.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227768.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ed680]
>[227768.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ed680] width 1920 pitch 7680 (/4 1920)
>[227768.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227768.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227768.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227768.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227768.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227768.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227771.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227771.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227771.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227771.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227771.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227771.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227771.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227771.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227794.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebd50]
>[227794.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebd50] width 1920 pitch 7680 (/4 1920)
>[227794.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231610]
>[227794.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231610] width 1920 pitch 7680 (/4 1920)
>[227876.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227876.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227876.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227876.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227876.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227876.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227876.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227876.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227876.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227876.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227876.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227876.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227876.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227876.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227877.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227877.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227877.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227877.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227877.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227877.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227877.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227877.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227878.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227878.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227878.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227878.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227879.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227879.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227880.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227880.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227881.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227881.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227881.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227881.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227881.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227881.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227882.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227882.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227882.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227882.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227882.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc4e70]
>[227882.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc4e70] width 1920 pitch 7680 (/4 1920)
>[227882.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc4e70]
>[227882.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc4e70] width 1920 pitch 7680 (/4 1920)
>[227882.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f310]
>[227882.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f310] width 1920 pitch 7680 (/4 1920)
>[227882.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227882.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227882.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84290]
>[227882.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84290] width 1920 pitch 7680 (/4 1920)
>[227884.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e870]
>[227884.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e870] width 1920 pitch 7680 (/4 1920)
>[227885.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f840f0]
>[227885.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f840f0] width 1920 pitch 7680 (/4 1920)
>[227885.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83f30]
>[227885.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83f30] width 1920 pitch 7680 (/4 1920)
>[227885.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83fc0]
>[227885.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83fc0] width 1920 pitch 7680 (/4 1920)
>[227885.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f840f0]
>[227885.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f840f0] width 1920 pitch 7680 (/4 1920)
>[227885.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83f30]
>[227885.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83f30] width 1920 pitch 7680 (/4 1920)
>[227885.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83fc0]
>[227885.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83fc0] width 1920 pitch 7680 (/4 1920)
>[227885.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f840f0]
>[227885.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f840f0] width 1920 pitch 7680 (/4 1920)
>[227885.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83f30]
>[227885.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83f30] width 1920 pitch 7680 (/4 1920)
>[227885.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83f30]
>[227885.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83f30] width 1920 pitch 7680 (/4 1920)
>[227885.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f83f30]
>[227885.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f83f30] width 1920 pitch 7680 (/4 1920)
>[227890.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227890.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227890.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84370]
>[227890.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84370] width 1920 pitch 7680 (/4 1920)
>[227890.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227890.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227890.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84370]
>[227890.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84370] width 1920 pitch 7680 (/4 1920)
>[227890.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227890.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227890.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f160]
>[227890.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f160] width 1920 pitch 7680 (/4 1920)
>[227890.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c76b70]
>[227890.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c76b70] width 1920 pitch 7680 (/4 1920)
>[227890.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f160]
>[227890.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f160] width 1920 pitch 7680 (/4 1920)
>[227890.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227890.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227890.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f160]
>[227890.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f160] width 1920 pitch 7680 (/4 1920)
>[227890.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c76b70]
>[227890.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c76b70] width 1920 pitch 7680 (/4 1920)
>[227890.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f160]
>[227890.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f160] width 1920 pitch 7680 (/4 1920)
>[227890.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96280]
>[227890.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96280] width 1920 pitch 7680 (/4 1920)
>[227890.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5f160]
>[227890.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5f160] width 1920 pitch 7680 (/4 1920)
>[227894.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc4e70]
>[227894.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc4e70] width 1920 pitch 7680 (/4 1920)
>[227894.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227894.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca9060]
>[227897.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca9060] width 1920 pitch 7680 (/4 1920)
>[227897.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227897.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227897.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227897.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227897.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227901.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227901.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227901.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227901.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227901.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227901.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227901.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227901.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227901.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227901.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227901.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227901.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227902.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227902.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227902.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227902.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227902.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227902.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227902.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227902.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227902.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227902.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227902.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227902.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227902.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227902.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227902.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89250]
>[227902.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89250] width 1920 pitch 7680 (/4 1920)
>[227902.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227902.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227907.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89220]
>[227907.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89220] width 1920 pitch 7680 (/4 1920)
>[227907.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227907.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227907.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89220]
>[227907.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89220] width 1920 pitch 7680 (/4 1920)
>[227907.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227907.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227907.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89220]
>[227907.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89220] width 1920 pitch 7680 (/4 1920)
>[227907.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227907.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227907.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89220]
>[227907.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89220] width 1920 pitch 7680 (/4 1920)
>[227907.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a316d0]
>[227907.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a316d0] width 1920 pitch 7680 (/4 1920)
>[227907.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c89220]
>[227907.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c89220] width 1920 pitch 7680 (/4 1920)
>[227907.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f84020]
>[227907.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f84020] width 1920 pitch 7680 (/4 1920)
>[227907.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca7700]
>[227907.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca7700] width 1920 pitch 7680 (/4 1920)
>[227915.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227915.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227915.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227915.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227915.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227915.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227916.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227916.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227916.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227916.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227916.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227916.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227916.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227916.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227916.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227916.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227916.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abca90]
>[227917.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abca90] width 1920 pitch 7680 (/4 1920)
>[227917.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227917.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227917.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227917.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[227917.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c082c0]
>[227917.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c082c0] width 1920 pitch 7680 (/4 1920)
>[227917.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227917.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227917.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa5c70]
>[227917.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa5c70] width 1920 pitch 7680 (/4 1920)
>[227917.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a4780]
>[227917.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a4780] width 1920 pitch 7680 (/4 1920)
>[227919.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8e40]
>[227919.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8e40] width 1920 pitch 7680 (/4 1920)
>[227961.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227961.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[227961.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227961.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[227961.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227961.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227961.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227961.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[227961.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227961.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227961.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227961.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227962.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227962.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227962.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227962.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227962.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227962.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227962.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227963.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227963.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227963.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227963.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a5c60]
>[227963.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a5c60] width 1920 pitch 7680 (/4 1920)
>[227963.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227963.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[227963.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227963.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227963.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227963.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227963.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227963.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227963.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4f360]
>[227963.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4f360] width 1920 pitch 7680 (/4 1920)
>[227963.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcccd0]
>[227963.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcccd0] width 1920 pitch 7680 (/4 1920)
>[227964.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2e6f0]
>[227964.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2e6f0] width 1920 pitch 7680 (/4 1920)
>[227964.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227964.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227964.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcccd0]
>[227964.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcccd0] width 1920 pitch 7680 (/4 1920)
>[227964.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227964.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227964.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227965.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227965.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227965.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227965.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227965.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227965.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227966.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3066330]
>[227966.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3066330] width 1920 pitch 7680 (/4 1920)
>[227966.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227966.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227966.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e260]
>[227966.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e260] width 1920 pitch 7680 (/4 1920)
>[227966.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e260]
>[227966.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e260] width 1920 pitch 7680 (/4 1920)
>[227966.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e260]
>[227966.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e260] width 1920 pitch 7680 (/4 1920)
>[227966.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e260]
>[227966.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e260] width 1920 pitch 7680 (/4 1920)
>[227966.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e260]
>[227966.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e260] width 1920 pitch 7680 (/4 1920)
>[227967.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5ee60]
>[227967.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5ee60] width 1920 pitch 7680 (/4 1920)
>[227997.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdc060]
>[227997.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdc060] width 1920 pitch 7680 (/4 1920)
>[228007.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3084b10]
>[228007.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3084b10] width 1920 pitch 7680 (/4 1920)
>[228024.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c21620]
>[228024.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c21620] width 1920 pitch 7680 (/4 1920)
>[228027.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ceead0]
>[228027.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ceead0] width 1920 pitch 7680 (/4 1920)
>[228027.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228027.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228027.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228027.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228027.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228028.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228028.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228028.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228028.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228028.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228028.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228029.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228029.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228029.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[228029.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[228031.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228031.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228031.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228031.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228032.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228032.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228032.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228032.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228032.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[228032.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[228032.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228032.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228032.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[228032.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[228034.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228034.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228034.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[228034.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[228034.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228034.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228034.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[228034.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[228034.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228035.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228035.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[228035.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[228035.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[228035.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[228035.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228035.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228035.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[228035.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[228035.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228035.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228035.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[228035.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[228036.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228036.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228036.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ed680]
>[228036.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ed680] width 1920 pitch 7680 (/4 1920)
>[228036.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ef80]
>[228036.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ef80] width 1920 pitch 7680 (/4 1920)
>[228036.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6550]
>[228036.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6550] width 1920 pitch 7680 (/4 1920)
>[228036.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bab8c0]
>[228036.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bab8c0] width 1920 pitch 7680 (/4 1920)
>[228036.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228036.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228036.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e3e0]
>[228036.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e3e0] width 1920 pitch 7680 (/4 1920)
>[228037.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e3e0]
>[228037.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e3e0] width 1920 pitch 7680 (/4 1920)
>[228037.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a6550]
>[228037.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a6550] width 1920 pitch 7680 (/4 1920)
>[228037.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8e3e0]
>[228037.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8e3e0] width 1920 pitch 7680 (/4 1920)
>[228037.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bab8c0]
>[228037.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bab8c0] width 1920 pitch 7680 (/4 1920)
>[228037.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ed680]
>[228037.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ed680] width 1920 pitch 7680 (/4 1920)
>[228037.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a36b30]
>[228037.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a36b30] width 1920 pitch 7680 (/4 1920)
>[228038.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4ef80]
>[228038.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4ef80] width 1920 pitch 7680 (/4 1920)
>[228038.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b8d30]
>[228038.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b8d30] width 1920 pitch 7680 (/4 1920)
>[228038.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228038.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228038.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bab8c0]
>[228038.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bab8c0] width 1920 pitch 7680 (/4 1920)
>[228038.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8820]
>[228038.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8820] width 1920 pitch 7680 (/4 1920)
>[228038.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ed680]
>[228038.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ed680] width 1920 pitch 7680 (/4 1920)
>[228038.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a36b30]
>[228038.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a36b30] width 1920 pitch 7680 (/4 1920)
>[228039.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5470]
>[228039.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5470] width 1920 pitch 7680 (/4 1920)
>[228040.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b8d30]
>[228040.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b8d30] width 1920 pitch 7680 (/4 1920)
>[228041.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bab8c0]
>[228041.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bab8c0] width 1920 pitch 7680 (/4 1920)
>[228042.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a36b30]
>[228042.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a36b30] width 1920 pitch 7680 (/4 1920)
>[228042.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da5470]
>[228042.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da5470] width 1920 pitch 7680 (/4 1920)
>[228043.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ffea0]
>[228043.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ffea0] width 1920 pitch 7680 (/4 1920)
>[228043.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b16430]
>[228043.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b16430] width 1920 pitch 7680 (/4 1920)
>[228043.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5104f20]
>[228044.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5104f20] width 1920 pitch 7680 (/4 1920)
>[228044.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4ea40]
>[228044.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4ea40] width 1920 pitch 7680 (/4 1920)
>[228044.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf78a0]
>[228044.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf78a0] width 1920 pitch 7680 (/4 1920)
>[228044.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4ea40]
>[228044.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4ea40] width 1920 pitch 7680 (/4 1920)
>[228058.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cafab0]
>[228058.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cafab0] width 1920 pitch 7680 (/4 1920)
>[228059.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228059.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228059.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccfb0]
>[228059.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccfb0] width 1920 pitch 7680 (/4 1920)
>[228059.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228059.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228059.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228059.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228059.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dccf40]
>[228059.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dccf40] width 1920 pitch 7680 (/4 1920)
>[228059.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50feac0]
>[228059.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50feac0] width 1920 pitch 7680 (/4 1920)
>[228060.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5981ac0]
>[228060.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5981ac0] width 1920 pitch 7680 (/4 1920)
>[228060.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228060.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228066.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228066.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228066.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228066.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228066.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228066.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228066.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228067.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228067.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228067.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228067.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228067.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228067.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228067.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228067.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228067.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228067.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228067.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228067.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228067.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228068.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228068.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228068.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228068.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228070.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228070.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228073.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228073.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228074.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228074.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228074.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228074.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228074.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228074.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228074.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228074.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228074.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228074.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228077.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228077.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228077.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228077.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228077.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228077.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228077.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228077.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228077.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228077.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228077.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228077.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228078.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228078.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228078.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228078.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228078.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228078.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228078.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228078.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228079.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228079.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228080.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228080.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228080.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228080.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228080.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a36b30]
>[228080.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a36b30] width 1920 pitch 7680 (/4 1920)
>[228080.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab200]
>[228080.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab200] width 1920 pitch 7680 (/4 1920)
>[228080.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7900]
>[228080.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7900] width 1920 pitch 7680 (/4 1920)
>[228081.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006180]
>[228081.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006180] width 1920 pitch 7680 (/4 1920)
>[228199.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf2080]
>[228199.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf2080] width 1920 pitch 7680 (/4 1920)
>[228199.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf2080]
>[228199.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf2080] width 1920 pitch 7680 (/4 1920)
>[228222.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228222.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228222.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f94a10]
>[228222.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f94a10] width 1920 pitch 7680 (/4 1920)
>[228560.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7ff90]
>[228560.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7ff90] width 1920 pitch 7680 (/4 1920)
>[228654.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c765a0]
>[228654.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c765a0] width 1920 pitch 7680 (/4 1920)
>[228654.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e9c0]
>[228654.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e9c0] width 1920 pitch 7680 (/4 1920)
>[228654.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7ffd0]
>[228654.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7ffd0] width 1920 pitch 7680 (/4 1920)
>[228654.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c765a0]
>[228654.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c765a0] width 1920 pitch 7680 (/4 1920)
>[228654.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc2930]
>[228654.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc2930] width 1920 pitch 7680 (/4 1920)
>[228654.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105130]
>[228654.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105130] width 1920 pitch 7680 (/4 1920)
>[228654.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c765a0]
>[228654.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c765a0] width 1920 pitch 7680 (/4 1920)
>[228654.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105130]
>[228654.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105130] width 1920 pitch 7680 (/4 1920)
>[228654.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c765a0]
>[228654.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c765a0] width 1920 pitch 7680 (/4 1920)
>[228654.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105130]
>[228654.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105130] width 1920 pitch 7680 (/4 1920)
>[228654.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7ffd0]
>[228654.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7ffd0] width 1920 pitch 7680 (/4 1920)
>[228654.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105130]
>[228654.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105130] width 1920 pitch 7680 (/4 1920)
>[228656.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7b8f0]
>[228656.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7b8f0] width 1920 pitch 7680 (/4 1920)
>[228656.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b22780]
>[228656.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b22780] width 1920 pitch 7680 (/4 1920)
>[228657.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d7b8f0]
>[228657.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d7b8f0] width 1920 pitch 7680 (/4 1920)
>[228657.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228657.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228657.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228657.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228657.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228657.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228657.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228657.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228657.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228657.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228657.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228672.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228672.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228672.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228672.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228672.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228672.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228672.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228672.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228672.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228672.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228672.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228672.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228672.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228672.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228672.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228673.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228673.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228673.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228673.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228673.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228673.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228673.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228673.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228673.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228673.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228673.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228674.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228674.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228674.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228675.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228675.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228675.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228675.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70040]
>[228675.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70040] width 1920 pitch 7680 (/4 1920)
>[228675.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228675.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228675.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca72c0]
>[228675.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca72c0] width 1920 pitch 7680 (/4 1920)
>[228718.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0bdb0]
>[228718.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0bdb0] width 1920 pitch 7680 (/4 1920)
>[228737.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[228737.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[228740.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3dd60]
>[228740.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3dd60] width 1920 pitch 7680 (/4 1920)
>[228798.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[228798.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[228798.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228798.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228798.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7150]
>[228798.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7150] width 1920 pitch 7680 (/4 1920)
>[228798.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abe9d0]
>[228798.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abe9d0] width 1920 pitch 7680 (/4 1920)
>[228798.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c822f0]
>[228798.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c822f0] width 1920 pitch 7680 (/4 1920)
>[228798.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c18ee0]
>[228798.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c18ee0] width 1920 pitch 7680 (/4 1920)
>[228798.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c27c30]
>[228798.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c27c30] width 1920 pitch 7680 (/4 1920)
>[228798.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abe9d0]
>[228798.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abe9d0] width 1920 pitch 7680 (/4 1920)
>[228799.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[228799.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[228799.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228799.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228799.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[228799.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[228799.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a31510]
>[228799.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a31510] width 1920 pitch 7680 (/4 1920)
>[228799.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[228799.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[228799.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c27c30]
>[228800.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c27c30] width 1920 pitch 7680 (/4 1920)
>[228800.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c12b90]
>[228800.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c12b90] width 1920 pitch 7680 (/4 1920)
>[228800.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[228800.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[228801.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228801.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228801.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228801.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228801.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c27c30]
>[228801.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c27c30] width 1920 pitch 7680 (/4 1920)
>[228801.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05590]
>[228801.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05590] width 1920 pitch 7680 (/4 1920)
>[228801.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05180]
>[228801.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05180] width 1920 pitch 7680 (/4 1920)
>[228802.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[228802.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[228802.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228802.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228802.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c822f0]
>[228802.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c822f0] width 1920 pitch 7680 (/4 1920)
>[228802.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228802.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228802.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f8db0]
>[228802.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f8db0] width 1920 pitch 7680 (/4 1920)
>[228802.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a31510]
>[228802.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a31510] width 1920 pitch 7680 (/4 1920)
>[228802.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[228802.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[228802.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ffd40]
>[228802.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ffd40] width 1920 pitch 7680 (/4 1920)
>[228802.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a39730]
>[228802.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a39730] width 1920 pitch 7680 (/4 1920)
>[228802.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05180]
>[228802.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05180] width 1920 pitch 7680 (/4 1920)
>[228802.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59efa50]
>[228803.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59efa50] width 1920 pitch 7680 (/4 1920)
>[228803.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[228803.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[228803.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3039bf0]
>[228803.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3039bf0] width 1920 pitch 7680 (/4 1920)
>[228803.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f2310]
>[228803.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f2310] width 1920 pitch 7680 (/4 1920)
>[228803.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7150]
>[228803.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7150] width 1920 pitch 7680 (/4 1920)
>[228803.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c822f0]
>[228803.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c822f0] width 1920 pitch 7680 (/4 1920)
>[228803.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[228803.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[228803.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cc7280]
>[228803.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cc7280] width 1920 pitch 7680 (/4 1920)
>[228804.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab54d0]
>[228804.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab54d0] width 1920 pitch 7680 (/4 1920)
>[228804.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[228804.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[228804.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[228804.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[228804.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f8db0]
>[228804.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f8db0] width 1920 pitch 7680 (/4 1920)
>[228804.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c822f0]
>[228804.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c822f0] width 1920 pitch 7680 (/4 1920)
>[228805.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[228805.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[228805.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[228805.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[228805.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[228805.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[228805.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f307f0]
>[228805.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f307f0] width 1920 pitch 7680 (/4 1920)
>[228805.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a08580]
>[228805.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a08580] width 1920 pitch 7680 (/4 1920)
>[228805.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a58fa0]
>[228805.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a58fa0] width 1920 pitch 7680 (/4 1920)
>[228805.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f8db0]
>[228805.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f8db0] width 1920 pitch 7680 (/4 1920)
>[228806.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[228806.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[228806.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[228806.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[228806.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228806.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228806.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228806.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228806.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ffb9e0]
>[228806.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ffb9e0] width 1920 pitch 7680 (/4 1920)
>[228807.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a08580]
>[228807.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a08580] width 1920 pitch 7680 (/4 1920)
>[228807.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[228808.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[228808.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfefa0]
>[228808.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfefa0] width 1920 pitch 7680 (/4 1920)
>[228808.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[228808.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[228808.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[228808.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[228808.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f8db0]
>[228808.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f8db0] width 1920 pitch 7680 (/4 1920)
>[228808.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c18ee0]
>[228808.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c18ee0] width 1920 pitch 7680 (/4 1920)
>[228808.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ffd40]
>[228808.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ffd40] width 1920 pitch 7680 (/4 1920)
>[228814.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4c220]
>[228814.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4c220] width 1920 pitch 7680 (/4 1920)
>[228843.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595e810]
>[228843.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595e810] width 1920 pitch 7680 (/4 1920)
>[228843.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8780]
>[228843.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8780] width 1920 pitch 7680 (/4 1920)
>[228846.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c224c0]
>[228846.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c224c0] width 1920 pitch 7680 (/4 1920)
>[228847.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f6d0]
>[228847.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f6d0] width 1920 pitch 7680 (/4 1920)
>[228847.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7f550]
>[228847.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7f550] width 1920 pitch 7680 (/4 1920)
>[228847.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c7cde0]
>[228847.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c7cde0] width 1920 pitch 7680 (/4 1920)
>[228847.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x304f6d0]
>[228847.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x304f6d0] width 1920 pitch 7680 (/4 1920)
>[228860.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[228860.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[228860.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0bc20]
>[228860.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0bc20] width 1920 pitch 7680 (/4 1920)
>[228860.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598b8e0]
>[228860.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598b8e0] width 1920 pitch 7680 (/4 1920)
>[228860.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfb400]
>[228860.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfb400] width 1920 pitch 7680 (/4 1920)
>[228860.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96ab0]
>[228860.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96ab0] width 1920 pitch 7680 (/4 1920)
>[228860.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc200]
>[228860.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc200] width 1920 pitch 7680 (/4 1920)
>[228860.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b048f0]
>[228860.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b048f0] width 1920 pitch 7680 (/4 1920)
>[228860.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf9c80]
>[228860.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf9c80] width 1920 pitch 7680 (/4 1920)
>[228860.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0bc20]
>[228860.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0bc20] width 1920 pitch 7680 (/4 1920)
>[228860.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[228860.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[228860.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00ff0]
>[228860.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00ff0] width 1920 pitch 7680 (/4 1920)
>[228860.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598b8e0]
>[228860.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598b8e0] width 1920 pitch 7680 (/4 1920)
>[228860.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfb400]
>[228860.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfb400] width 1920 pitch 7680 (/4 1920)
>[228860.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96ab0]
>[228860.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96ab0] width 1920 pitch 7680 (/4 1920)
>[228860.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc200]
>[228860.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc200] width 1920 pitch 7680 (/4 1920)
>[228860.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b048f0]
>[228860.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b048f0] width 1920 pitch 7680 (/4 1920)
>[228860.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf9c80]
>[228860.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf9c80] width 1920 pitch 7680 (/4 1920)
>[228860.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0bc20]
>[228860.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0bc20] width 1920 pitch 7680 (/4 1920)
>[228860.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[228860.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[228860.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598b8e0]
>[228860.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598b8e0] width 1920 pitch 7680 (/4 1920)
>[228860.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfb400]
>[228860.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfb400] width 1920 pitch 7680 (/4 1920)
>[228860.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc200]
>[228860.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc200] width 1920 pitch 7680 (/4 1920)
>[228860.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf9c80]
>[228860.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf9c80] width 1920 pitch 7680 (/4 1920)
>[228860.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc3460]
>[228860.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc3460] width 1920 pitch 7680 (/4 1920)
>[228861.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00ff0]
>[228861.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00ff0] width 1920 pitch 7680 (/4 1920)
>[228861.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c0bc20]
>[228861.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c0bc20] width 1920 pitch 7680 (/4 1920)
>[228862.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x598b8e0]
>[228862.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x598b8e0] width 1920 pitch 7680 (/4 1920)
>[228863.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00ff0]
>[228863.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00ff0] width 1920 pitch 7680 (/4 1920)
>[228869.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a08580]
>[228869.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a08580] width 1920 pitch 7680 (/4 1920)
>[228869.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987a90]
>[228869.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987a90] width 1920 pitch 7680 (/4 1920)
>[228869.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a3a820]
>[228869.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a3a820] width 1920 pitch 7680 (/4 1920)
>[228869.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05180]
>[228869.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05180] width 1920 pitch 7680 (/4 1920)
>[228870.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228870.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228870.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abe9d0]
>[228870.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abe9d0] width 1920 pitch 7680 (/4 1920)
>[228870.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[228870.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[228870.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[228870.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[228870.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228870.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228870.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[228870.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[228870.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[228870.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[228871.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c18ee0]
>[228871.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c18ee0] width 1920 pitch 7680 (/4 1920)
>[228871.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2bb50]
>[228871.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2bb50] width 1920 pitch 7680 (/4 1920)
>[228871.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e50250]
>[228871.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e50250] width 1920 pitch 7680 (/4 1920)
>[228871.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[228871.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[228871.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a6ad20]
>[228871.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a6ad20] width 1920 pitch 7680 (/4 1920)
>[228871.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90180]
>[228871.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90180] width 1920 pitch 7680 (/4 1920)
>[228872.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1cf80]
>[228872.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1cf80] width 1920 pitch 7680 (/4 1920)
>[228872.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228872.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228872.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac0780]
>[228872.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac0780] width 1920 pitch 7680 (/4 1920)
>[228872.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[228872.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[228873.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b048f0]
>[228873.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b048f0] width 1920 pitch 7680 (/4 1920)
>[228873.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05410]
>[228873.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05410] width 1920 pitch 7680 (/4 1920)
>[228873.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[228873.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[228873.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7fb0]
>[228873.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7fb0] width 1920 pitch 7680 (/4 1920)
>[228873.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5595d80]
>[228873.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5595d80] width 1920 pitch 7680 (/4 1920)
>[228873.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[228873.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[228873.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac0780]
>[228873.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac0780] width 1920 pitch 7680 (/4 1920)
>[228873.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a18590]
>[228873.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a18590] width 1920 pitch 7680 (/4 1920)
>[228873.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96ab0]
>[228873.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96ab0] width 1920 pitch 7680 (/4 1920)
>[228874.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5abe9d0]
>[228874.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5abe9d0] width 1920 pitch 7680 (/4 1920)
>[228874.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5987a90]
>[228874.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5987a90] width 1920 pitch 7680 (/4 1920)
>[228874.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[228874.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[228874.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f307f0]
>[228874.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f307f0] width 1920 pitch 7680 (/4 1920)
>[228874.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a61fb0]
>[228874.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a61fb0] width 1920 pitch 7680 (/4 1920)
>[228875.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b048f0]
>[228875.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b048f0] width 1920 pitch 7680 (/4 1920)
>[228875.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2ba90]
>[228875.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2ba90] width 1920 pitch 7680 (/4 1920)
>[228876.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e67440]
>[228876.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e67440] width 1920 pitch 7680 (/4 1920)
>[228876.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[228876.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[228876.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[228876.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[228876.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[228876.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[228876.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[228876.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[228876.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fb2a60]
>[228876.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fb2a60] width 1920 pitch 7680 (/4 1920)
>[228876.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5595d80]
>[228876.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5595d80] width 1920 pitch 7680 (/4 1920)
>[228877.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a08580]
>[228877.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a08580] width 1920 pitch 7680 (/4 1920)
>[228877.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ac0780]
>[228877.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ac0780] width 1920 pitch 7680 (/4 1920)
>[228877.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[228877.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[228877.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96ab0]
>[228877.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96ab0] width 1920 pitch 7680 (/4 1920)
>[228877.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30bee30]
>[228877.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30bee30] width 1920 pitch 7680 (/4 1920)
>[228878.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a63460]
>[228878.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a63460] width 1920 pitch 7680 (/4 1920)
>[228878.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8a370]
>[228878.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8a370] width 1920 pitch 7680 (/4 1920)
>[228912.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f52830]
>[228912.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f52830] width 1920 pitch 7680 (/4 1920)
>[230800.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b7f30]
>[230800.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b7f30] width 1920 pitch 7680 (/4 1920)
>[231787.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05180]
>[231787.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05180] width 1920 pitch 7680 (/4 1920)
>[235389.578] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[235389.578] (II) RADEON(0): Using hsync ranges from config file
>[235389.578] (II) RADEON(0): Using vrefresh ranges from config file
>[235389.578] (II) RADEON(0): Printing DDC gathered Modelines:
>[235389.578] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[235389.578] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[235389.578] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[235389.578] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[235389.578] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[235389.578] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[235389.578] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[235479.919] (II) RADEON(0): RADEONSaveScreen(2)
>[235479.919] (II) RADEON(0): RADEONSaveScreen(0)
>[240166.853] (II) RADEON(0): RADEONSaveScreen(1)
>[240174.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240174.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240174.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240174.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240174.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240179.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240179.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240179.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240179.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240179.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240180.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240180.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240180.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240180.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240180.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240180.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240180.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240180.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240180.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240180.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240180.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240180.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240180.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240180.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240180.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240180.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240181.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240181.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240181.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240181.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240236.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240236.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240236.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240236.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240236.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240236.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240236.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240236.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240236.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240236.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240236.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240236.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240236.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240236.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240237.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240237.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240237.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240237.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240237.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240237.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240237.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240237.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240237.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240237.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240237.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240237.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240237.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240237.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240237.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240237.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca6df0]
>[240237.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca6df0] width 1920 pitch 7680 (/4 1920)
>[240249.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240249.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240249.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240249.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240249.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240249.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240249.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240249.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240249.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240249.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240249.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240249.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240249.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240249.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240249.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240249.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240249.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240249.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240250.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240250.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240250.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240250.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240250.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30087e0]
>[240250.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30087e0] width 1920 pitch 7680 (/4 1920)
>[240250.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4fec0]
>[240250.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4fec0] width 1920 pitch 7680 (/4 1920)
>[240250.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f307f0]
>[240251.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f307f0] width 1920 pitch 7680 (/4 1920)
>[240251.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973430]
>[240251.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973430] width 1920 pitch 7680 (/4 1920)
>[240251.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab7f10]
>[240251.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab7f10] width 1920 pitch 7680 (/4 1920)
>[240251.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90180]
>[240251.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90180] width 1920 pitch 7680 (/4 1920)
>[240252.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05410]
>[240252.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05410] width 1920 pitch 7680 (/4 1920)
>[240252.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a05410]
>[240252.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a05410] width 1920 pitch 7680 (/4 1920)
>[240252.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240253.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240253.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240253.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240253.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240254.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240254.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240254.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240254.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240254.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240254.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240254.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x552b6a0]
>[240254.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x552b6a0] width 1920 pitch 7680 (/4 1920)
>[240254.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d40f0]
>[240254.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d40f0] width 1920 pitch 7680 (/4 1920)
>[240254.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a18590]
>[240254.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a18590] width 1920 pitch 7680 (/4 1920)
>[240254.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240254.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240255.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00be0]
>[240255.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00be0] width 1920 pitch 7680 (/4 1920)
>[240255.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82ca0]
>[240255.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82ca0] width 1920 pitch 7680 (/4 1920)
>[240255.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cae030]
>[240255.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cae030] width 1920 pitch 7680 (/4 1920)
>[240255.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc200]
>[240255.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc200] width 1920 pitch 7680 (/4 1920)
>[240273.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[240273.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[240309.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240309.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240309.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240309.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240309.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240309.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240309.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240309.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240309.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240309.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240309.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240309.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240309.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240309.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240309.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240309.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240309.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240309.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240310.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240310.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240310.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240310.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240310.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240310.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240310.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a5b350]
>[240310.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a5b350] width 1920 pitch 7680 (/4 1920)
>[240310.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a00f50]
>[240310.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a00f50] width 1920 pitch 7680 (/4 1920)
>[240310.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a39730]
>[240310.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a39730] width 1920 pitch 7680 (/4 1920)
>[240311.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240311.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240311.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab8b20]
>[240311.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab8b20] width 1920 pitch 7680 (/4 1920)
>[240311.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240311.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240311.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[240311.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[240446.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240446.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240446.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c82f10]
>[240446.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c82f10] width 1920 pitch 7680 (/4 1920)
>[240448.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[240448.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[240448.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3105540]
>[240448.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3105540] width 1920 pitch 7680 (/4 1920)
>[240448.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240448.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240448.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[240448.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[240448.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240448.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240448.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90180]
>[240448.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90180] width 1920 pitch 7680 (/4 1920)
>[240448.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fe0b0]
>[240448.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fe0b0] width 1920 pitch 7680 (/4 1920)
>[240448.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[240448.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[240449.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240449.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240449.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[240449.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[240449.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb090]
>[240449.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb090] width 1920 pitch 7680 (/4 1920)
>[240449.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90180]
>[240449.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90180] width 1920 pitch 7680 (/4 1920)
>[240449.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c11720]
>[240449.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c11720] width 1920 pitch 7680 (/4 1920)
>[240449.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[240449.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[240449.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59fe0b0]
>[240449.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59fe0b0] width 1920 pitch 7680 (/4 1920)
>[240449.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240449.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240449.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240449.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240449.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240449.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240449.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240449.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240449.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2cf60]
>[240449.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2cf60] width 1920 pitch 7680 (/4 1920)
>[240449.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3052530]
>[240449.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3052530] width 1920 pitch 7680 (/4 1920)
>[240449.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1d150]
>[240449.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1d150] width 1920 pitch 7680 (/4 1920)
>[240449.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x326b760]
>[240449.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x326b760] width 1920 pitch 7680 (/4 1920)
>[240449.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a90180]
>[240449.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a90180] width 1920 pitch 7680 (/4 1920)
>[240451.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5535050]
>[240451.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5535050] width 1920 pitch 7680 (/4 1920)
>[240451.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b2d680]
>[240451.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b2d680] width 1920 pitch 7680 (/4 1920)
>[240596.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a181a0]
>[240596.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a181a0] width 1920 pitch 7680 (/4 1920)
>[240596.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b89e0]
>[240596.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b89e0] width 1920 pitch 7680 (/4 1920)
>[240596.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab9d0]
>[240596.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab9d0] width 1920 pitch 7680 (/4 1920)
>[240596.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fe2200]
>[240596.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fe2200] width 1920 pitch 7680 (/4 1920)
>[240596.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b89e0]
>[240596.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b89e0] width 1920 pitch 7680 (/4 1920)
>[240596.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eedb0]
>[240596.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eedb0] width 1920 pitch 7680 (/4 1920)
>[240596.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30c7e70]
>[240596.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30c7e70] width 1920 pitch 7680 (/4 1920)
>[240596.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b89e0]
>[240597.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b89e0] width 1920 pitch 7680 (/4 1920)
>[240597.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b89e0]
>[240597.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b89e0] width 1920 pitch 7680 (/4 1920)
>[240597.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab9d0]
>[240597.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab9d0] width 1920 pitch 7680 (/4 1920)
>[240598.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab9d0]
>[240598.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab9d0] width 1920 pitch 7680 (/4 1920)
>[240598.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b89e0]
>[240598.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b89e0] width 1920 pitch 7680 (/4 1920)
>[240598.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab9d0]
>[240598.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab9d0] width 1920 pitch 7680 (/4 1920)
>[240598.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a181a0]
>[240598.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a181a0] width 1920 pitch 7680 (/4 1920)
>[240598.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54b12a0]
>[240598.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54b12a0] width 1920 pitch 7680 (/4 1920)
>[240598.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fab9d0]
>[240598.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fab9d0] width 1920 pitch 7680 (/4 1920)
>[240598.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fe2200]
>[240598.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fe2200] width 1920 pitch 7680 (/4 1920)
>[241622.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241622.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241622.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a020d0]
>[241622.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a020d0] width 1920 pitch 7680 (/4 1920)
>[241622.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241622.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241622.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a020d0]
>[241622.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a020d0] width 1920 pitch 7680 (/4 1920)
>[241622.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241622.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241622.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a020d0]
>[241622.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a020d0] width 1920 pitch 7680 (/4 1920)
>[241622.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241622.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241623.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a020d0]
>[241623.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a020d0] width 1920 pitch 7680 (/4 1920)
>[241623.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241623.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241624.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a020d0]
>[241624.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a020d0] width 1920 pitch 7680 (/4 1920)
>[241624.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32705a0]
>[241624.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32705a0] width 1920 pitch 7680 (/4 1920)
>[241624.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce3830]
>[241624.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce3830] width 1920 pitch 7680 (/4 1920)
>[241624.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3006180]
>[241624.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3006180] width 1920 pitch 7680 (/4 1920)
>[241657.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241657.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241657.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241657.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241657.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54acbe0]
>[241657.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54acbe0] width 1920 pitch 7680 (/4 1920)
>[241657.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241657.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241657.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54acbe0]
>[241657.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54acbe0] width 1920 pitch 7680 (/4 1920)
>[241657.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241657.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241657.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54acbe0]
>[241658.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54acbe0] width 1920 pitch 7680 (/4 1920)
>[241658.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241658.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241658.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241658.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241658.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241658.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241658.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241658.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241658.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241658.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241658.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241658.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241658.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241658.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241659.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241659.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241659.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241659.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241659.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241659.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241659.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54acbe0]
>[241659.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54acbe0] width 1920 pitch 7680 (/4 1920)
>[241659.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241659.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241659.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54acbe0]
>[241659.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54acbe0] width 1920 pitch 7680 (/4 1920)
>[241659.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241659.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241664.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241664.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241670.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241670.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241670.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241670.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241670.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241670.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241670.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241670.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241670.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241670.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241670.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241670.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241670.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241670.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241671.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241671.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241671.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241671.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241671.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1a250]
>[241671.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1a250] width 1920 pitch 7680 (/4 1920)
>[241671.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309b620]
>[241671.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309b620] width 1920 pitch 7680 (/4 1920)
>[241671.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1a250]
>[241671.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1a250] width 1920 pitch 7680 (/4 1920)
>[241671.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241671.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241671.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1a250]
>[241671.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1a250] width 1920 pitch 7680 (/4 1920)
>[241671.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d13b0]
>[241671.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d13b0] width 1920 pitch 7680 (/4 1920)
>[241671.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1a250]
>[241671.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1a250] width 1920 pitch 7680 (/4 1920)
>[241871.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a95340]
>[241871.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a95340] width 1920 pitch 7680 (/4 1920)
>[242241.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242241.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242241.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242241.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242241.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242241.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242241.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242241.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242241.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242241.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242241.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242241.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242241.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242241.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242242.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242242.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242242.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242242.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242242.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242242.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242242.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242242.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242243.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242243.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242243.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242243.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242243.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a92d60]
>[242243.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a92d60] width 1920 pitch 7680 (/4 1920)
>[242243.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfcab0]
>[242243.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfcab0] width 1920 pitch 7680 (/4 1920)
>[242243.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f0e80]
>[242243.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f0e80] width 1920 pitch 7680 (/4 1920)
>[242243.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004ad0]
>[242243.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004ad0] width 1920 pitch 7680 (/4 1920)
>[242243.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef880]
>[242243.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef880] width 1920 pitch 7680 (/4 1920)
>[242243.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004ad0]
>[242243.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004ad0] width 1920 pitch 7680 (/4 1920)
>[245869.256] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[245869.256] (II) RADEON(0): Using hsync ranges from config file
>[245869.256] (II) RADEON(0): Using vrefresh ranges from config file
>[245869.256] (II) RADEON(0): Printing DDC gathered Modelines:
>[245869.256] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[245869.256] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[245869.256] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[245869.256] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[245869.256] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[245869.256] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[245869.256] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[245869.257] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[245959.938] (II) RADEON(0): RADEONSaveScreen(2)
>[245959.938] (II) RADEON(0): RADEONSaveScreen(0)
>[246707.782] (II) RADEON(0): RADEONSaveScreen(1)
>[246709.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2a370]
>[246709.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2a370] width 1920 pitch 7680 (/4 1920)
>[246716.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a15310]
>[246716.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a15310] width 1920 pitch 7680 (/4 1920)
>[246721.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e657d0]
>[246721.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e657d0] width 1920 pitch 7680 (/4 1920)
>[246721.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246721.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246721.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246721.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246721.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246721.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246721.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246721.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246721.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246721.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246722.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246722.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246722.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246722.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246722.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee900]
>[246722.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee900] width 1920 pitch 7680 (/4 1920)
>[246722.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee900]
>[246722.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee900] width 1920 pitch 7680 (/4 1920)
>[246722.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee900]
>[246722.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee900] width 1920 pitch 7680 (/4 1920)
>[246723.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246723.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246723.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e657d0]
>[246723.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e657d0] width 1920 pitch 7680 (/4 1920)
>[246724.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ff00]
>[246724.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ff00] width 1920 pitch 7680 (/4 1920)
>[246724.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e657d0]
>[246724.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e657d0] width 1920 pitch 7680 (/4 1920)
>[246724.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e657d0]
>[246724.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e657d0] width 1920 pitch 7680 (/4 1920)
>[246724.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6ffe0]
>[246724.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6ffe0] width 1920 pitch 7680 (/4 1920)
>[246724.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f71080]
>[246724.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f71080] width 1920 pitch 7680 (/4 1920)
>[246724.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25780]
>[246724.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25780] width 1920 pitch 7680 (/4 1920)
>[246724.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3035b80]
>[246724.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3035b80] width 1920 pitch 7680 (/4 1920)
>[246724.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b25780]
>[246724.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b25780] width 1920 pitch 7680 (/4 1920)
>[246735.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b8c0]
>[246735.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b8c0] width 1920 pitch 7680 (/4 1920)
>[246795.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f10b0]
>[246795.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f10b0] width 1920 pitch 7680 (/4 1920)
>[246796.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eec860]
>[246796.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eec860] width 1920 pitch 7680 (/4 1920)
>[247299.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f28190]
>[247299.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f28190] width 1920 pitch 7680 (/4 1920)
>[247326.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e557e0]
>[247326.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e557e0] width 1920 pitch 7680 (/4 1920)
>[247603.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a79400]
>[247603.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a79400] width 1920 pitch 7680 (/4 1920)
>[247613.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c9c650]
>[247613.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c9c650] width 1920 pitch 7680 (/4 1920)
>[247613.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e54d80]
>[247613.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e54d80] width 1920 pitch 7680 (/4 1920)
>[247848.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b47f40]
>[247848.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b47f40] width 1920 pitch 7680 (/4 1920)
>[247949.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a79400]
>[247949.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a79400] width 1920 pitch 7680 (/4 1920)
>[248109.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c97a30]
>[248109.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c97a30] width 1920 pitch 7680 (/4 1920)
>[248334.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b60a80]
>[248334.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b60a80] width 1920 pitch 7680 (/4 1920)
>[248436.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e70bd0]
>[248436.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e70bd0] width 1920 pitch 7680 (/4 1920)
>[248484.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b62110]
>[248484.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b62110] width 1920 pitch 7680 (/4 1920)
>[248859.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c9bbd0]
>[248859.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c9bbd0] width 1920 pitch 7680 (/4 1920)
>[249075.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a88050]
>[249075.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a88050] width 1920 pitch 7680 (/4 1920)
>[249215.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b30040]
>[249215.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b30040] width 1920 pitch 7680 (/4 1920)
>[249476.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca27e0]
>[249476.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca27e0] width 1920 pitch 7680 (/4 1920)
>[249476.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c4cb70]
>[249476.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c4cb70] width 1920 pitch 7680 (/4 1920)
>[249736.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b47f40]
>[249736.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b47f40] width 1920 pitch 7680 (/4 1920)
>[249736.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c4aa00]
>[249736.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c4aa00] width 1920 pitch 7680 (/4 1920)
>[249739.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b51b20]
>[249739.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b51b20] width 1920 pitch 7680 (/4 1920)
>[249740.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[249740.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[249916.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61b90]
>[249916.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61b90] width 1920 pitch 7680 (/4 1920)
>[249916.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a862a0]
>[249916.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a862a0] width 1920 pitch 7680 (/4 1920)
>[249916.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c3f720]
>[249916.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c3f720] width 1920 pitch 7680 (/4 1920)
>[249916.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab04a0]
>[249916.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab04a0] width 1920 pitch 7680 (/4 1920)
>[249916.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249916.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249916.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab04a0]
>[249917.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab04a0] width 1920 pitch 7680 (/4 1920)
>[249917.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249917.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249917.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab04a0]
>[249917.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab04a0] width 1920 pitch 7680 (/4 1920)
>[249917.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249917.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249917.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab04a0]
>[249917.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab04a0] width 1920 pitch 7680 (/4 1920)
>[249917.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249917.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249917.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab04a0]
>[249917.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab04a0] width 1920 pitch 7680 (/4 1920)
>[249917.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249917.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249917.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ca27e0]
>[249917.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ca27e0] width 1920 pitch 7680 (/4 1920)
>[249918.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bf9dd0]
>[249918.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bf9dd0] width 1920 pitch 7680 (/4 1920)
>[249918.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dd7330]
>[249918.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dd7330] width 1920 pitch 7680 (/4 1920)
>[249918.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b51b20]
>[249918.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b51b20] width 1920 pitch 7680 (/4 1920)
>[249935.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c96cb0]
>[249935.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c96cb0] width 1920 pitch 7680 (/4 1920)
>[249935.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bca400]
>[249935.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bca400] width 1920 pitch 7680 (/4 1920)
>[249936.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249936.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249936.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249937.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249937.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249937.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249937.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249937.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249937.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249937.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249937.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249937.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249937.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249937.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249937.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249937.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249937.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249937.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249937.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249938.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249938.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249938.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249938.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcdfd0]
>[249938.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcdfd0] width 1920 pitch 7680 (/4 1920)
>[249938.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249938.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249938.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a88140]
>[249938.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a88140] width 1920 pitch 7680 (/4 1920)
>[249938.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c92fb0]
>[249938.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c92fb0] width 1920 pitch 7680 (/4 1920)
>[249939.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[249939.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[249982.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc5ad0]
>[249982.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc5ad0] width 1920 pitch 7680 (/4 1920)
>[249982.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[249982.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[249982.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249982.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249982.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e95630]
>[249982.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e95630] width 1920 pitch 7680 (/4 1920)
>[249982.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249983.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249983.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e95630]
>[249983.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e95630] width 1920 pitch 7680 (/4 1920)
>[249983.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249983.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249983.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e95630]
>[249983.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e95630] width 1920 pitch 7680 (/4 1920)
>[249983.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249983.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249983.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e95630]
>[249983.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e95630] width 1920 pitch 7680 (/4 1920)
>[249983.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249983.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249984.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e95630]
>[249984.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e95630] width 1920 pitch 7680 (/4 1920)
>[249984.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249984.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249985.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a88230]
>[249985.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a88230] width 1920 pitch 7680 (/4 1920)
>[249985.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5be4320]
>[249985.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5be4320] width 1920 pitch 7680 (/4 1920)
>[249985.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc5ad0]
>[249985.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc5ad0] width 1920 pitch 7680 (/4 1920)
>[249985.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bba9f0]
>[249985.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bba9f0] width 1920 pitch 7680 (/4 1920)
>[249985.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c96cb0]
>[249985.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c96cb0] width 1920 pitch 7680 (/4 1920)
>[250014.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250014.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250014.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250014.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250014.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250014.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250014.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250014.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250014.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250014.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250015.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250015.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250015.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250015.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250015.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250015.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250015.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250015.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250015.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250015.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250016.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250016.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250016.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250016.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250016.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250016.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250016.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250016.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250016.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250016.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250017.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250017.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250017.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5de3ca0]
>[250017.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5de3ca0] width 1920 pitch 7680 (/4 1920)
>[250017.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c494d0]
>[250017.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c494d0] width 1920 pitch 7680 (/4 1920)
>[250017.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c92fb0]
>[250017.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c92fb0] width 1920 pitch 7680 (/4 1920)
>[250017.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e89e50]
>[250017.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e89e50] width 1920 pitch 7680 (/4 1920)
>[250017.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e88a90]
>[250017.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e88a90] width 1920 pitch 7680 (/4 1920)
>[250017.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c47180]
>[250017.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c47180] width 1920 pitch 7680 (/4 1920)
>[250017.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300fcf0]
>[250017.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300fcf0] width 1920 pitch 7680 (/4 1920)
>[250018.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c47180]
>[250018.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c47180] width 1920 pitch 7680 (/4 1920)
>[250111.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5940]
>[250111.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5940] width 1920 pitch 7680 (/4 1920)
>[250111.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250111.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250111.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250111.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250111.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250111.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250111.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250111.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250111.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250111.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250112.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250112.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250112.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250112.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250112.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250112.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250112.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250112.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250112.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250113.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250113.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250113.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250113.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bc62b0]
>[250113.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bc62b0] width 1920 pitch 7680 (/4 1920)
>[250113.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8a790]
>[250113.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8a790] width 1920 pitch 7680 (/4 1920)
>[250113.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96990]
>[250113.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96990] width 1920 pitch 7680 (/4 1920)
>[250113.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bd5080]
>[250113.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bd5080] width 1920 pitch 7680 (/4 1920)
>[250113.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5bfe310]
>[250113.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5bfe310] width 1920 pitch 7680 (/4 1920)
>[250113.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f2e070]
>[250113.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f2e070] width 1920 pitch 7680 (/4 1920)
>[250126.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a88230]
>[250126.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a88230] width 1920 pitch 7680 (/4 1920)
>[250126.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b61b90]
>[250126.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b61b90] width 1920 pitch 7680 (/4 1920)
>[250126.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a96990]
>[250126.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a96990] width 1920 pitch 7680 (/4 1920)
>[250126.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab1af0]
>[250126.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab1af0] width 1920 pitch 7680 (/4 1920)
>[250126.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c41de0]
>[250126.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c41de0] width 1920 pitch 7680 (/4 1920)
>[250126.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8efb0]
>[250126.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8efb0] width 1920 pitch 7680 (/4 1920)
>[250126.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[250126.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[250127.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a84dc0]
>[250127.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a84dc0] width 1920 pitch 7680 (/4 1920)
>[250127.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[250127.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[250127.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a84dc0]
>[250127.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a84dc0] width 1920 pitch 7680 (/4 1920)
>[250127.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[250127.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[250127.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a84dc0]
>[250127.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a84dc0] width 1920 pitch 7680 (/4 1920)
>[250128.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[250128.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[250128.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b47f40]
>[250128.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b47f40] width 1920 pitch 7680 (/4 1920)
>[250128.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cfc0b0]
>[250128.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cfc0b0] width 1920 pitch 7680 (/4 1920)
>[250128.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8de0]
>[250128.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8de0] width 1920 pitch 7680 (/4 1920)
>[250128.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c40550]
>[250128.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c40550] width 1920 pitch 7680 (/4 1920)
>[250128.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8efb0]
>[250128.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8efb0] width 1920 pitch 7680 (/4 1920)
>[250140.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b47f40]
>[250140.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b47f40] width 1920 pitch 7680 (/4 1920)
>[250140.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b65df0]
>[250140.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b65df0] width 1920 pitch 7680 (/4 1920)
>[250161.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c86a90]
>[250161.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c86a90] width 1920 pitch 7680 (/4 1920)
>[250161.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d9b120]
>[250161.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d9b120] width 1920 pitch 7680 (/4 1920)
>[250161.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d9b120]
>[250161.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d9b120] width 1920 pitch 7680 (/4 1920)
>[250161.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c86a90]
>[250161.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c86a90] width 1920 pitch 7680 (/4 1920)
>[250161.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5d98ee0]
>[250161.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5d98ee0] width 1920 pitch 7680 (/4 1920)
>[250171.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5db4b60]
>[250171.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5db4b60] width 1920 pitch 7680 (/4 1920)
>[250171.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dfacc0]
>[250171.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dfacc0] width 1920 pitch 7680 (/4 1920)
>[250272.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0770]
>[250272.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0770] width 1920 pitch 7680 (/4 1920)
>[250272.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fe20]
>[250272.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fe20] width 1920 pitch 7680 (/4 1920)
>[250272.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f2f0]
>[250272.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f2f0] width 1920 pitch 7680 (/4 1920)
>[250272.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fe20]
>[250272.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fe20] width 1920 pitch 7680 (/4 1920)
>[250272.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f2f0]
>[250272.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f2f0] width 1920 pitch 7680 (/4 1920)
>[250272.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f2f0]
>[250272.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f2f0] width 1920 pitch 7680 (/4 1920)
>[250272.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fe20]
>[250272.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fe20] width 1920 pitch 7680 (/4 1920)
>[250272.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f2f0]
>[250272.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f2f0] width 1920 pitch 7680 (/4 1920)
>[250272.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992500]
>[250272.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992500] width 1920 pitch 7680 (/4 1920)
>[250272.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992500]
>[250272.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992500] width 1920 pitch 7680 (/4 1920)
>[250272.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f650]
>[250272.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f650] width 1920 pitch 7680 (/4 1920)
>[250272.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f650]
>[250272.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f650] width 1920 pitch 7680 (/4 1920)
>[250272.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992500]
>[250272.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992500] width 1920 pitch 7680 (/4 1920)
>[250272.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992500]
>[250272.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992500] width 1920 pitch 7680 (/4 1920)
>[250272.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f650]
>[250272.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f650] width 1920 pitch 7680 (/4 1920)
>[250272.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0b20]
>[250272.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0b20] width 1920 pitch 7680 (/4 1920)
>[250272.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f650]
>[250272.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f650] width 1920 pitch 7680 (/4 1920)
>[250304.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250304.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250304.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250304.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250304.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250304.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250304.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250304.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250304.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250304.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250305.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250305.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250305.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250305.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250305.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250305.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250305.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250305.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250305.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250305.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250305.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250306.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250306.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250306.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250306.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250306.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250306.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250306.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250306.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250307.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250307.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250307.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250307.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250307.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250307.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250307.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250307.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250307.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250307.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fa60]
>[250307.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fa60] width 1920 pitch 7680 (/4 1920)
>[250307.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6999b60]
>[250307.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6999b60] width 1920 pitch 7680 (/4 1920)
>[250477.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250477.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250477.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db8d00]
>[250477.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db8d00] width 1920 pitch 7680 (/4 1920)
>[250477.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df8f20]
>[250477.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df8f20] width 1920 pitch 7680 (/4 1920)
>[250477.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db8d00]
>[250477.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db8d00] width 1920 pitch 7680 (/4 1920)
>[250477.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df8f20]
>[250477.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df8f20] width 1920 pitch 7680 (/4 1920)
>[250477.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db8d00]
>[250478.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db8d00] width 1920 pitch 7680 (/4 1920)
>[250478.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df8f20]
>[250478.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df8f20] width 1920 pitch 7680 (/4 1920)
>[250478.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250478.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250478.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250478.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250478.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db8d00]
>[250478.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db8d00] width 1920 pitch 7680 (/4 1920)
>[250478.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250478.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250479.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250479.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250479.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250479.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250480.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250480.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250480.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250480.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250481.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250481.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250481.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250481.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250481.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250481.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250481.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250481.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250481.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250481.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250481.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250482.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250482.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250482.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250482.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250482.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250483.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250483.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250483.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250483.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250483.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250483.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250484.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[250484.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[250484.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6599690]
>[250484.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6599690] width 1920 pitch 7680 (/4 1920)
>[250484.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df24a0]
>[250484.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df24a0] width 1920 pitch 7680 (/4 1920)
>[250484.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250484.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250484.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250484.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250484.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250484.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250484.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250484.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250495.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250495.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5062ba0]
>[250496.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5062ba0] width 1920 pitch 7680 (/4 1920)
>[250496.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250496.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250496.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x659eff0]
>[250496.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x659eff0] width 1920 pitch 7680 (/4 1920)
>[250497.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250497.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250497.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250497.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250497.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d320]
>[250497.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d320] width 1920 pitch 7680 (/4 1920)
>[250498.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292c0]
>[250498.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292c0] width 1920 pitch 7680 (/4 1920)
>[250504.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54db3c0]
>[250504.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54db3c0] width 1920 pitch 7680 (/4 1920)
>[250504.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e12c50]
>[250504.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e12c50] width 1920 pitch 7680 (/4 1920)
>[250504.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54db3c0]
>[250504.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54db3c0] width 1920 pitch 7680 (/4 1920)
>[250504.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e12c50]
>[250504.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e12c50] width 1920 pitch 7680 (/4 1920)
>[250504.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54db3c0]
>[250504.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54db3c0] width 1920 pitch 7680 (/4 1920)
>[250504.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5e12c50]
>[250504.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5e12c50] width 1920 pitch 7680 (/4 1920)
>[250504.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cf1270]
>[250504.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cf1270] width 1920 pitch 7680 (/4 1920)
>[250505.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c428c0]
>[250505.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c428c0] width 1920 pitch 7680 (/4 1920)
>[250505.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x54db3c0]
>[250505.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x54db3c0] width 1920 pitch 7680 (/4 1920)
>[250505.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c800]
>[250505.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c800] width 1920 pitch 7680 (/4 1920)
>[250505.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c800]
>[250505.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c800] width 1920 pitch 7680 (/4 1920)
>[250506.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df3ed0]
>[250506.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df3ed0] width 1920 pitch 7680 (/4 1920)
>[250506.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250506.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250506.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[250506.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[250506.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250506.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250506.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250506.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250506.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250506.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250510.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[250510.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[250510.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250510.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250510.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[250510.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[250510.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[250510.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[250510.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250510.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250510.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[250510.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[250510.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[250510.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[250511.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[250511.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[250511.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250511.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250511.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250511.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250511.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250511.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250511.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250512.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250512.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250512.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250512.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250512.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250512.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250512.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250512.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5afef60]
>[250512.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5afef60] width 1920 pitch 7680 (/4 1920)
>[250512.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250512.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250512.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250512.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250521.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250521.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250521.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250521.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250521.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250522.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250522.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250522.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250522.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250522.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250522.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250522.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250522.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250522.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250522.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250522.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250522.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250523.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250523.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c7c0]
>[250523.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c7c0] width 1920 pitch 7680 (/4 1920)
>[250523.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcccd0]
>[250523.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcccd0] width 1920 pitch 7680 (/4 1920)
>[250523.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250523.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250523.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250523.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250523.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30b7670]
>[250523.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30b7670] width 1920 pitch 7680 (/4 1920)
>[250523.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250523.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250523.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699e350]
>[250523.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699e350] width 1920 pitch 7680 (/4 1920)
>[250523.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250523.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250543.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0730]
>[250543.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0730] width 1920 pitch 7680 (/4 1920)
>[250543.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250543.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250545.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250545.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250545.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250545.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250546.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250546.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250546.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250546.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250546.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250546.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250546.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250546.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250546.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250546.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250546.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250546.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250546.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250546.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250546.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250546.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250546.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250546.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250547.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250547.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250547.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250547.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250547.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250547.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250547.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250547.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250547.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250547.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250547.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250547.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250547.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250548.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250548.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250548.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250548.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250548.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250548.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df27e0]
>[250548.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df27e0] width 1920 pitch 7680 (/4 1920)
>[250548.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c078c0]
>[250548.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c078c0] width 1920 pitch 7680 (/4 1920)
>[250571.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5556930]
>[250571.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5556930] width 1920 pitch 7680 (/4 1920)
>[250571.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5556930]
>[250571.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5556930] width 1920 pitch 7680 (/4 1920)
>[250764.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab0270]
>[250765.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab0270] width 1920 pitch 7680 (/4 1920)
>[250765.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ab0270]
>[250765.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ab0270] width 1920 pitch 7680 (/4 1920)
>[250796.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250796.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250796.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250797.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250797.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67dadf0]
>[250797.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67dadf0] width 1920 pitch 7680 (/4 1920)
>[250797.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250797.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250797.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67dadf0]
>[250797.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67dadf0] width 1920 pitch 7680 (/4 1920)
>[250797.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250797.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250797.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250797.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250797.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250797.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250797.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67dadf0]
>[250797.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67dadf0] width 1920 pitch 7680 (/4 1920)
>[250797.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250797.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250797.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67dadf0]
>[250797.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67dadf0] width 1920 pitch 7680 (/4 1920)
>[250798.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250798.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250799.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250799.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250799.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250799.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250799.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250799.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250800.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250800.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250800.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250800.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250800.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250800.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250800.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250800.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250800.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250800.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250800.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250800.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250800.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250800.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250800.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67dadf0]
>[250800.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67dadf0] width 1920 pitch 7680 (/4 1920)
>[250800.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250800.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250800.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e62e0]
>[250800.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e62e0] width 1920 pitch 7680 (/4 1920)
>[250800.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a576b0]
>[250800.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a576b0] width 1920 pitch 7680 (/4 1920)
>[250842.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0dc0]
>[250842.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0dc0] width 1920 pitch 7680 (/4 1920)
>[250843.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0dc0]
>[250843.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0dc0] width 1920 pitch 7680 (/4 1920)
>[251012.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67efb40]
>[251012.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67efb40] width 1920 pitch 7680 (/4 1920)
>[251012.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ef050]
>[251012.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ef050] width 1920 pitch 7680 (/4 1920)
>[251733.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f3870]
>[251733.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f3870] width 1920 pitch 7680 (/4 1920)
>[251733.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f7d00]
>[251733.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f7d00] width 1920 pitch 7680 (/4 1920)
>[251733.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f3810]
>[251733.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f3810] width 1920 pitch 7680 (/4 1920)
>[251733.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f7d00]
>[251733.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f7d00] width 1920 pitch 7680 (/4 1920)
>[251733.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f3810]
>[251733.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f3810] width 1920 pitch 7680 (/4 1920)
>[251733.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f7d00]
>[251733.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f7d00] width 1920 pitch 7680 (/4 1920)
>[251733.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67f3810]
>[251733.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67f3810] width 1920 pitch 7680 (/4 1920)
>[251736.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309f3d0]
>[251736.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309f3d0] width 1920 pitch 7680 (/4 1920)
>[251736.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309f3d0]
>[251736.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309f3d0] width 1920 pitch 7680 (/4 1920)
>[251737.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x309f3d0]
>[251737.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x309f3d0] width 1920 pitch 7680 (/4 1920)
>[251737.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a7f0]
>[251737.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a7f0] width 1920 pitch 7680 (/4 1920)
>[251737.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc180]
>[251737.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc180] width 1920 pitch 7680 (/4 1920)
>[251737.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a7f0]
>[251737.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a7f0] width 1920 pitch 7680 (/4 1920)
>[251737.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc180]
>[251737.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc180] width 1920 pitch 7680 (/4 1920)
>[251737.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a7f0]
>[251737.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a7f0] width 1920 pitch 7680 (/4 1920)
>[251737.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc180]
>[251737.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc180] width 1920 pitch 7680 (/4 1920)
>[251737.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a7f0]
>[251737.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a7f0] width 1920 pitch 7680 (/4 1920)
>[251737.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc180]
>[251737.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc180] width 1920 pitch 7680 (/4 1920)
>[251737.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a7f0]
>[251737.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a7f0] width 1920 pitch 7680 (/4 1920)
>[251737.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5adc180]
>[251737.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5adc180] width 1920 pitch 7680 (/4 1920)
>[253641.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8dd40]
>[253641.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8dd40] width 1920 pitch 7680 (/4 1920)
>[253641.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x680acb0]
>[253641.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x680acb0] width 1920 pitch 7680 (/4 1920)
>[253664.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da8e0]
>[253664.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da8e0] width 1920 pitch 7680 (/4 1920)
>[253664.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253664.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253665.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253665.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253665.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253665.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253665.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253665.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253665.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253665.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253665.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253665.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253665.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253665.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253665.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da8e0]
>[253665.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da8e0] width 1920 pitch 7680 (/4 1920)
>[253666.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da8e0]
>[253666.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da8e0] width 1920 pitch 7680 (/4 1920)
>[253666.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253666.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253667.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253667.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253668.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253668.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253668.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253668.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253668.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253668.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253668.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253668.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253668.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253668.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253668.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6808140]
>[253668.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6808140] width 1920 pitch 7680 (/4 1920)
>[253668.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6800cb0]
>[253668.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6800cb0] width 1920 pitch 7680 (/4 1920)
>[253668.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681fb20]
>[253668.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681fb20] width 1920 pitch 7680 (/4 1920)
>[253669.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a8dd40]
>[253669.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a8dd40] width 1920 pitch 7680 (/4 1920)
>[253669.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681fb20]
>[253669.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681fb20] width 1920 pitch 7680 (/4 1920)
>[257268.750] (II) RADEON(0): EDID vendor "ACR", prod id 515
>[257268.750] (II) RADEON(0): Using hsync ranges from config file
>[257268.750] (II) RADEON(0): Using vrefresh ranges from config file
>[257268.750] (II) RADEON(0): Printing DDC gathered Modelines:
>[257268.750] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[257268.750] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[257268.750] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[257268.750] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[257268.750] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[257268.750] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[257268.750] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[257268.750] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[257268.750] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[257268.750] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[257268.750] (II) RADEON(0): Modeline "1440x900"x0.0   88.75  1440 1488 1520 1600  900 903 909 926 +hsync -vsync (55.5 kHz e)
>[257268.751] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 +hsync -vsync (49.3 kHz e)
>[257268.751] (II) RADEON(0): Modeline "1920x1080"x60.0  172.80  1920 2040 2248 2576  1080 1081 1084 1118 -hsync +vsync (67.1 kHz e)
>[257358.926] (II) RADEON(0): RADEONSaveScreen(2)
>[257358.926] (II) RADEON(0): RADEONSaveScreen(0)
>[284661.153] (II) RADEON(0): RADEONSaveScreen(1)
>[284695.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68181b0]
>[284695.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68181b0] width 1920 pitch 7680 (/4 1920)
>[284837.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284837.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284837.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284837.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284837.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284837.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284837.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284837.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284837.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284837.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284837.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284837.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284837.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284837.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284838.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284838.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284838.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284838.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284838.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284838.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284838.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284838.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284838.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284838.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284838.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284838.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284838.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284839.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284839.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284839.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284839.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284839.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284839.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830610]
>[284839.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830610] width 1920 pitch 7680 (/4 1920)
>[284839.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682e490]
>[284839.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682e490] width 1920 pitch 7680 (/4 1920)
>[284839.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830520]
>[284839.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830520] width 1920 pitch 7680 (/4 1920)
>[285019.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681f4e0]
>[285019.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681f4e0] width 1920 pitch 7680 (/4 1920)
>[285019.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820900]
>[285019.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820900] width 1920 pitch 7680 (/4 1920)
>[285020.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9580]
>[285020.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9580] width 1920 pitch 7680 (/4 1920)
>[285020.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681f4e0]
>[285020.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681f4e0] width 1920 pitch 7680 (/4 1920)
>[285020.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9580]
>[285020.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9580] width 1920 pitch 7680 (/4 1920)
>[285020.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[285020.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[285020.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820900]
>[285020.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820900] width 1920 pitch 7680 (/4 1920)
>[285020.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[285020.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[285020.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681f4e0]
>[285020.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681f4e0] width 1920 pitch 7680 (/4 1920)
>[285020.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9580]
>[285021.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9580] width 1920 pitch 7680 (/4 1920)
>[285021.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681f4e0]
>[285021.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681f4e0] width 1920 pitch 7680 (/4 1920)
>[285021.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9580]
>[285021.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9580] width 1920 pitch 7680 (/4 1920)
>[285021.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[285021.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[285021.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e9580]
>[285021.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e9580] width 1920 pitch 7680 (/4 1920)
>[285021.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820900]
>[285021.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820900] width 1920 pitch 7680 (/4 1920)
>[285021.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[285021.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[285021.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820900]
>[285021.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820900] width 1920 pitch 7680 (/4 1920)
>[285032.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a750]
>[285032.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a750] width 1920 pitch 7680 (/4 1920)
>[285066.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[285066.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[285067.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6597bb0]
>[285067.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6597bb0] width 1920 pitch 7680 (/4 1920)
>[285067.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285067.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285067.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[285067.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[285067.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285067.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285067.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[285067.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[285067.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285067.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285067.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[285068.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[285068.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285068.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285068.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[285068.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[285068.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285068.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285069.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[285069.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[285069.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68380f0]
>[285069.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68380f0] width 1920 pitch 7680 (/4 1920)
>[285069.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6831c70]
>[285069.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6831c70] width 1920 pitch 7680 (/4 1920)
>[285069.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4dd70]
>[285069.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4dd70] width 1920 pitch 7680 (/4 1920)
>[285069.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6831c70]
>[285069.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6831c70] width 1920 pitch 7680 (/4 1920)
>[285069.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4dbd0]
>[285069.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4dbd0] width 1920 pitch 7680 (/4 1920)
>[285069.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6831c70]
>[285069.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6831c70] width 1920 pitch 7680 (/4 1920)
>[285069.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4dbd0]
>[285069.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4dbd0] width 1920 pitch 7680 (/4 1920)
>[285069.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6831c70]
>[285069.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6831c70] width 1920 pitch 7680 (/4 1920)
>[285069.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e4dbd0]
>[285069.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e4dbd0] width 1920 pitch 7680 (/4 1920)
>[285069.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6831c70]
>[285069.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6831c70] width 1920 pitch 7680 (/4 1920)
>[285083.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825630]
>[285083.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825630] width 1920 pitch 7680 (/4 1920)
>[285083.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825760]
>[285083.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825760] width 1920 pitch 7680 (/4 1920)
>[285083.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67176f0]
>[285083.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67176f0] width 1920 pitch 7680 (/4 1920)
>[285083.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825630]
>[285083.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825630] width 1920 pitch 7680 (/4 1920)
>[285083.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4588da0]
>[285083.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4588da0] width 1920 pitch 7680 (/4 1920)
>[285083.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46565d0]
>[285083.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46565d0] width 1920 pitch 7680 (/4 1920)
>[285083.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da3f0]
>[285083.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da3f0] width 1920 pitch 7680 (/4 1920)
>[285083.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46565d0]
>[285083.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46565d0] width 1920 pitch 7680 (/4 1920)
>[285083.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da3f0]
>[285083.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da3f0] width 1920 pitch 7680 (/4 1920)
>[285084.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46565d0]
>[285084.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46565d0] width 1920 pitch 7680 (/4 1920)
>[285084.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67da3f0]
>[285084.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67da3f0] width 1920 pitch 7680 (/4 1920)
>[285084.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x46565d0]
>[285084.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x46565d0] width 1920 pitch 7680 (/4 1920)
>[285085.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825760]
>[285085.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825760] width 1920 pitch 7680 (/4 1920)
>[285085.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825760]
>[285085.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825760] width 1920 pitch 7680 (/4 1920)
>[285085.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96930]
>[285085.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96930] width 1920 pitch 7680 (/4 1920)
>[285085.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6825630]
>[285085.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6825630] width 1920 pitch 7680 (/4 1920)
>[285085.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e96930]
>[285085.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e96930] width 1920 pitch 7680 (/4 1920)
>[285112.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5df04d0]
>[285112.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5df04d0] width 1920 pitch 7680 (/4 1920)
>[285125.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cbc40]
>[285125.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cbc40] width 1920 pitch 7680 (/4 1920)
>[285126.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00750]
>[285126.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00750] width 1920 pitch 7680 (/4 1920)
>[285126.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00750]
>[285126.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00750] width 1920 pitch 7680 (/4 1920)
>[285126.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee34a0]
>[285126.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee34a0] width 1920 pitch 7680 (/4 1920)
>[285126.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d0270]
>[285126.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d0270] width 1920 pitch 7680 (/4 1920)
>[286275.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286275.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286275.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286275.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286275.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286275.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286275.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830b80]
>[286275.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830b80] width 1920 pitch 7680 (/4 1920)
>[286275.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286275.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286275.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286276.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286276.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286276.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286276.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286276.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286276.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286276.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286277.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286277.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286277.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830b80]
>[286277.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830b80] width 1920 pitch 7680 (/4 1920)
>[286277.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dcb560]
>[286277.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dcb560] width 1920 pitch 7680 (/4 1920)
>[286278.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d1480]
>[286278.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d1480] width 1920 pitch 7680 (/4 1920)
>[286278.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe8b20]
>[286278.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe8b20] width 1920 pitch 7680 (/4 1920)
>[286278.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d1480]
>[286278.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d1480] width 1920 pitch 7680 (/4 1920)
>[286278.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d1480]
>[286278.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d1480] width 1920 pitch 7680 (/4 1920)
>[286278.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c1bcd0]
>[286278.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c1bcd0] width 1920 pitch 7680 (/4 1920)
>[286278.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d1480]
>[286278.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d1480] width 1920 pitch 7680 (/4 1920)
>[286497.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe8920]
>[286497.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe8920] width 1920 pitch 7680 (/4 1920)
>[286497.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe8920]
>[286497.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe8920] width 1920 pitch 7680 (/4 1920)
>[286508.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286508.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286508.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286508.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286508.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e6730]
>[286508.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e6730] width 1920 pitch 7680 (/4 1920)
>[286508.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286509.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286509.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286509.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286509.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286509.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286509.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286509.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286509.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286509.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286509.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e6730]
>[286509.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e6730] width 1920 pitch 7680 (/4 1920)
>[286510.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286510.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286510.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e6730]
>[286510.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e6730] width 1920 pitch 7680 (/4 1920)
>[286510.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286510.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286510.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e6730]
>[286510.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e6730] width 1920 pitch 7680 (/4 1920)
>[286510.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286510.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286510.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682bb20]
>[286510.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682bb20] width 1920 pitch 7680 (/4 1920)
>[286510.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67e6730]
>[286510.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67e6730] width 1920 pitch 7680 (/4 1920)
>[286510.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6716a70]
>[286510.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6716a70] width 1920 pitch 7680 (/4 1920)
>[286521.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286521.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286521.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286521.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286521.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286521.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286521.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286521.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286521.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286521.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286521.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286521.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286522.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286522.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286522.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286522.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286522.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286522.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286522.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286522.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286522.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67cb590]
>[286522.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67cb590] width 1920 pitch 7680 (/4 1920)
>[286522.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286522.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286523.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286523.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286523.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286523.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286523.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286523.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286523.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286523.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286523.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286523.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286524.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286524.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286524.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286524.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286524.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286524.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286524.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286524.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286524.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286524.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286524.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286524.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286524.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286524.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286524.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286524.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286524.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286525.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286525.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286525.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286525.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286525.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286525.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286525.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286525.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286525.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286525.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286525.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286525.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286525.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286525.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286525.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286525.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286525.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286526.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286526.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286526.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286526.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286527.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286527.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286527.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286527.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286527.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286527.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286527.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286527.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286527.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286527.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286527.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286527.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286527.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286528.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[286528.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[286528.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286528.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x553c9e0]
>[286528.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x553c9e0] width 1920 pitch 7680 (/4 1920)
>[286528.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286528.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286528.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286528.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f820]
>[286528.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f820] width 1920 pitch 7680 (/4 1920)
>[286549.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee34a0]
>[286549.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee34a0] width 1920 pitch 7680 (/4 1920)
>[288457.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288457.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cef560]
>[288457.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cef560] width 1920 pitch 7680 (/4 1920)
>[288457.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288457.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[288461.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e6ff10]
>[288461.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e6ff10] width 1920 pitch 7680 (/4 1920)
>[288461.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[288461.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289153.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289153.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289153.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289153.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289153.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289153.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289153.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289153.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289153.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289153.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289153.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289157.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682f8c0]
>[289157.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682f8c0] width 1920 pitch 7680 (/4 1920)
>[289157.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c190]
>[289157.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c190] width 1920 pitch 7680 (/4 1920)
>[289157.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6714bf0]
>[289157.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6714bf0] width 1920 pitch 7680 (/4 1920)
>[289157.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6714bf0]
>[289157.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6714bf0] width 1920 pitch 7680 (/4 1920)
>[289157.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5caede0]
>[289157.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5caede0] width 1920 pitch 7680 (/4 1920)
>[289157.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5caede0]
>[289157.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5caede0] width 1920 pitch 7680 (/4 1920)
>[289157.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5caede0]
>[289157.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5caede0] width 1920 pitch 7680 (/4 1920)
>[289157.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6801710]
>[289157.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6801710] width 1920 pitch 7680 (/4 1920)
>[289157.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5caede0]
>[289157.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5caede0] width 1920 pitch 7680 (/4 1920)
>[290190.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738860]
>[290190.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738860] width 1920 pitch 7680 (/4 1920)
>[290190.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671e810]
>[290190.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671e810] width 1920 pitch 7680 (/4 1920)
>[290190.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673e9d0]
>[290190.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673e9d0] width 1920 pitch 7680 (/4 1920)
>[290190.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738860]
>[290190.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738860] width 1920 pitch 7680 (/4 1920)
>[290190.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673f410]
>[290190.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673f410] width 1920 pitch 7680 (/4 1920)
>[290190.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6720870]
>[290190.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6720870] width 1920 pitch 7680 (/4 1920)
>[290190.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290190.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290191.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6720870]
>[290191.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6720870] width 1920 pitch 7680 (/4 1920)
>[290191.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290191.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290191.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6720870]
>[290191.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6720870] width 1920 pitch 7680 (/4 1920)
>[290191.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290191.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290191.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6720870]
>[290191.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6720870] width 1920 pitch 7680 (/4 1920)
>[290191.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290191.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290191.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290192.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290192.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[290192.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[290192.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290192.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290192.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e710]
>[290192.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e710] width 1920 pitch 7680 (/4 1920)
>[290192.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290192.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290341.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5dc8780]
>[290341.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5dc8780] width 1920 pitch 7680 (/4 1920)
>[290349.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290349.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290349.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290349.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290349.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290349.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290349.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290349.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290349.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290349.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290349.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290349.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290349.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290349.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290349.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290349.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290349.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290354.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290354.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290354.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290354.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290355.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67396f0]
>[290355.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67396f0] width 1920 pitch 7680 (/4 1920)
>[290355.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681e810]
>[290355.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681e810] width 1920 pitch 7680 (/4 1920)
>[290359.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290359.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290359.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290359.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290359.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290360.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290360.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290360.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290360.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290361.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290361.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290361.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290361.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290361.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290361.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290361.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6744c00]
>[290361.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6744c00] width 1920 pitch 7680 (/4 1920)
>[290361.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290361.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290362.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290362.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729510]
>[290362.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729510] width 1920 pitch 7680 (/4 1920)
>[290362.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729510]
>[290362.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729510] width 1920 pitch 7680 (/4 1920)
>[290362.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290362.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290362.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290362.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290362.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290362.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290362.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290362.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290362.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290362.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290362.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290362.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290362.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290363.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290363.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290363.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290363.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290364.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290364.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290364.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290364.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290365.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdad80]
>[290365.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdad80] width 1920 pitch 7680 (/4 1920)
>[290365.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6729510]
>[290365.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6729510] width 1920 pitch 7680 (/4 1920)
>[290366.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290366.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290369.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290369.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290369.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290369.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290369.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290369.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290369.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290369.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290369.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290369.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290369.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290369.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290369.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290369.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290369.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290369.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290369.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290369.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290369.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290369.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290369.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290369.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290370.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290370.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290370.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290370.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290370.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290370.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290370.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290370.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290370.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290370.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290370.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290370.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290370.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290370.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290370.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290370.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290370.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290370.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290370.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290370.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290370.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6811dd0]
>[290371.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6811dd0] width 1920 pitch 7680 (/4 1920)
>[290371.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290371.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290371.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290371.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290371.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6725080]
>[290371.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6725080] width 1920 pitch 7680 (/4 1920)
>[290372.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6816680]
>[290372.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6816680] width 1920 pitch 7680 (/4 1920)
>[290375.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c68b0]
>[290375.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c68b0] width 1920 pitch 7680 (/4 1920)
>[290392.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290392.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290392.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290392.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290392.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290392.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290392.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671f510]
>[290392.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671f510] width 1920 pitch 7680 (/4 1920)
>[290392.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290392.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290392.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290392.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290392.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290392.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290393.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290393.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290393.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290393.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290393.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290393.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290393.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290393.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290393.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290393.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290393.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290393.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290393.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290393.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fcc90]
>[290394.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fcc90] width 1920 pitch 7680 (/4 1920)
>[290394.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c320]
>[290394.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c320] width 1920 pitch 7680 (/4 1920)
>[290606.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290606.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290607.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290607.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290607.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290607.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290607.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290607.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290607.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290607.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290607.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290607.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290607.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290607.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290607.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290607.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290608.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290608.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290608.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290608.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290608.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290608.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290608.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290608.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290609.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69391d0]
>[290609.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69391d0] width 1920 pitch 7680 (/4 1920)
>[290609.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x692cc50]
>[290609.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x692cc50] width 1920 pitch 7680 (/4 1920)
>[290609.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[290609.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[290609.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[290609.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[290609.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[290609.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[290609.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5e810]
>[290609.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5e810] width 1920 pitch 7680 (/4 1920)
>[290609.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5581260]
>[290609.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5581260] width 1920 pitch 7680 (/4 1920)
>[290615.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f70190]
>[290616.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f70190] width 1920 pitch 7680 (/4 1920)
>[291028.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730530]
>[291028.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730530] width 1920 pitch 7680 (/4 1920)
>[291028.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a150]
>[291028.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a150] width 1920 pitch 7680 (/4 1920)
>[291028.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a73300]
>[291028.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a73300] width 1920 pitch 7680 (/4 1920)
>[291028.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a73300]
>[291028.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a73300] width 1920 pitch 7680 (/4 1920)
>[291028.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291028.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291028.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730530]
>[291028.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730530] width 1920 pitch 7680 (/4 1920)
>[291028.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730530]
>[291028.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730530] width 1920 pitch 7680 (/4 1920)
>[291029.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a73300]
>[291029.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a73300] width 1920 pitch 7680 (/4 1920)
>[291029.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a150]
>[291029.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a150] width 1920 pitch 7680 (/4 1920)
>[291029.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291029.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291041.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291041.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291041.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693cdc0]
>[291041.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693cdc0] width 1920 pitch 7680 (/4 1920)
>[291041.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291041.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291041.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693cdc0]
>[291041.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693cdc0] width 1920 pitch 7680 (/4 1920)
>[291042.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291042.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291042.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693cdc0]
>[291042.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693cdc0] width 1920 pitch 7680 (/4 1920)
>[291042.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731fe0]
>[291042.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731fe0] width 1920 pitch 7680 (/4 1920)
>[291042.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730530]
>[291042.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730530] width 1920 pitch 7680 (/4 1920)
>[291884.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6941a20]
>[291884.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6941a20] width 1920 pitch 7680 (/4 1920)
>[291884.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291884.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291884.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291884.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291884.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291884.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291884.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291884.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291884.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291884.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291884.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291884.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291884.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291884.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291885.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291885.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291885.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291885.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291885.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291885.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291885.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291885.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291886.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291886.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291886.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291886.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291886.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291886.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291886.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291886.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291886.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940e80]
>[291886.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940e80] width 1920 pitch 7680 (/4 1920)
>[291886.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940880]
>[291886.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940880] width 1920 pitch 7680 (/4 1920)
>[291889.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291889.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291889.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291889.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291889.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6941b80]
>[291889.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6941b80] width 1920 pitch 7680 (/4 1920)
>[291889.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291889.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291889.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291890.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291890.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291890.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291890.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c410]
>[291890.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c410] width 1920 pitch 7680 (/4 1920)
>[291890.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682c410]
>[291890.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682c410] width 1920 pitch 7680 (/4 1920)
>[291890.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300fb70]
>[291890.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300fb70] width 1920 pitch 7680 (/4 1920)
>[291890.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300fb70]
>[291890.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300fb70] width 1920 pitch 7680 (/4 1920)
>[291890.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940c60]
>[291890.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940c60] width 1920 pitch 7680 (/4 1920)
>[291891.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6940c60]
>[291891.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6940c60] width 1920 pitch 7680 (/4 1920)
>[291912.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6946990]
>[291912.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6946990] width 1920 pitch 7680 (/4 1920)
>[291912.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291912.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291912.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6946990]
>[291912.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6946990] width 1920 pitch 7680 (/4 1920)
>[291912.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291912.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291912.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6946990]
>[291912.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6946990] width 1920 pitch 7680 (/4 1920)
>[291912.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291912.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291912.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6946990]
>[291912.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6946990] width 1920 pitch 7680 (/4 1920)
>[291912.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291912.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291994.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291994.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291994.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291994.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291995.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[291995.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[291995.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291995.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291995.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694c900]
>[291995.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694c900] width 1920 pitch 7680 (/4 1920)
>[291995.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291995.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291995.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694c900]
>[291995.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694c900] width 1920 pitch 7680 (/4 1920)
>[291995.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693f2f0]
>[291995.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693f2f0] width 1920 pitch 7680 (/4 1920)
>[291995.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693f2f0]
>[291995.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693f2f0] width 1920 pitch 7680 (/4 1920)
>[291996.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693f2f0]
>[291996.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693f2f0] width 1920 pitch 7680 (/4 1920)
>[291996.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291996.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291996.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291996.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291996.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693f2f0]
>[291996.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693f2f0] width 1920 pitch 7680 (/4 1920)
>[291996.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[291996.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[291997.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[291997.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[291997.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[291997.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[291997.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68256a0]
>[291997.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68256a0] width 1920 pitch 7680 (/4 1920)
>[291997.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694c900]
>[291997.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694c900] width 1920 pitch 7680 (/4 1920)
>[291997.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[291997.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[291997.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x694c900]
>[291997.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x694c900] width 1920 pitch 7680 (/4 1920)
>[292114.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32a1510]
>[292114.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32a1510] width 1920 pitch 7680 (/4 1920)
>[292136.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292136.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292136.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292136.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292138.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292138.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292139.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292139.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292139.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292139.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292139.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292139.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292139.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292139.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292139.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292139.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292139.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292139.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292139.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292139.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292139.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292139.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292140.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292140.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292140.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292140.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292140.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292140.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292140.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292140.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292140.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292140.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292141.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292141.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292141.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292141.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292141.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292141.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292141.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292141.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292141.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67fbe10]
>[292141.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67fbe10] width 1920 pitch 7680 (/4 1920)
>[292141.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6945310]
>[292141.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6945310] width 1920 pitch 7680 (/4 1920)
>[292141.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730c10]
>[292141.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730c10] width 1920 pitch 7680 (/4 1920)
>[292273.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6961920]
>[292273.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6961920] width 1920 pitch 7680 (/4 1920)
>[292273.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69618d0]
>[292273.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69618d0] width 1920 pitch 7680 (/4 1920)
>[292273.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292273.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292273.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292273.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292273.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292274.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292274.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292274.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292274.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292274.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292274.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292274.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292274.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292274.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292274.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292274.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292274.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292274.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292274.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292274.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292275.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292275.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292275.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x679fa60]
>[292275.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x679fa60] width 1920 pitch 7680 (/4 1920)
>[292275.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292275.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292275.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6961550]
>[292275.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6961550] width 1920 pitch 7680 (/4 1920)
>[292275.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292275.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292275.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6961550]
>[292275.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6961550] width 1920 pitch 7680 (/4 1920)
>[292275.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[292275.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[292275.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[292275.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[292284.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2550]
>[292284.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2550] width 1920 pitch 7680 (/4 1920)
>[292383.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7240]
>[292383.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7240] width 1920 pitch 7680 (/4 1920)
>[292383.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292383.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292383.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3af0]
>[292383.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3af0] width 1920 pitch 7680 (/4 1920)
>[292383.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292383.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292383.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3af0]
>[292383.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3af0] width 1920 pitch 7680 (/4 1920)
>[292383.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292383.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292383.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3af0]
>[292383.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3af0] width 1920 pitch 7680 (/4 1920)
>[292383.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3d50]
>[292383.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3d50] width 1920 pitch 7680 (/4 1920)
>[292384.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292384.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292384.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3d50]
>[292384.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3d50] width 1920 pitch 7680 (/4 1920)
>[292384.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292384.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292384.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3d50]
>[292384.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3d50] width 1920 pitch 7680 (/4 1920)
>[292384.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292384.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292384.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a6fc0]
>[292384.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a6fc0] width 1920 pitch 7680 (/4 1920)
>[292384.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292384.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292384.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a6fc0]
>[292384.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a6fc0] width 1920 pitch 7680 (/4 1920)
>[292384.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292384.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292384.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a6fc0]
>[292384.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a6fc0] width 1920 pitch 7680 (/4 1920)
>[292388.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a63f0]
>[292388.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a63f0] width 1920 pitch 7680 (/4 1920)
>[292410.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292410.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292410.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292410.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292410.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292410.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292410.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292410.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292410.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292410.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292410.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292410.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292410.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292410.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292410.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292410.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292410.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292410.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292411.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292411.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292411.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292411.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292411.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292411.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292411.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292411.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292411.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292411.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292412.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292412.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292412.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292412.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292413.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfe50]
>[292413.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfe50] width 1920 pitch 7680 (/4 1920)
>[292413.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292413.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292413.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292413.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292413.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292413.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292413.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292413.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292413.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292413.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292415.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292415.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292415.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292415.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292415.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292415.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292415.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292415.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292415.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292415.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292415.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292415.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292416.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292416.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292416.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292416.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292416.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bfce0]
>[292416.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bfce0] width 1920 pitch 7680 (/4 1920)
>[292416.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4a50]
>[292416.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4a50] width 1920 pitch 7680 (/4 1920)
>[292491.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292491.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292491.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5150]
>[292491.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5150] width 1920 pitch 7680 (/4 1920)
>[292491.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292491.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292491.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5150]
>[292491.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5150] width 1920 pitch 7680 (/4 1920)
>[292491.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292491.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292492.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5150]
>[292492.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5150] width 1920 pitch 7680 (/4 1920)
>[292492.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292492.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292492.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5150]
>[292492.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5150] width 1920 pitch 7680 (/4 1920)
>[292492.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292492.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292492.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5150]
>[292492.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5150] width 1920 pitch 7680 (/4 1920)
>[292493.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292493.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292493.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a4fb0]
>[292493.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a4fb0] width 1920 pitch 7680 (/4 1920)
>[292493.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bac00]
>[292493.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bac00] width 1920 pitch 7680 (/4 1920)
>[292493.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292493.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292493.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bac00]
>[292493.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bac00] width 1920 pitch 7680 (/4 1920)
>[292493.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6954e50]
>[292493.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6954e50] width 1920 pitch 7680 (/4 1920)
>[292493.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67bac00]
>[292493.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67bac00] width 1920 pitch 7680 (/4 1920)
>[292499.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59a09e0]
>[292499.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59a09e0] width 1920 pitch 7680 (/4 1920)
>[292675.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a8980]
>[292675.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a8980] width 1920 pitch 7680 (/4 1920)
>[292675.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a8980]
>[292675.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a8980] width 1920 pitch 7680 (/4 1920)
>[292699.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292699.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292699.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952280]
>[292699.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952280] width 1920 pitch 7680 (/4 1920)
>[292699.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292699.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292699.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952280]
>[292699.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952280] width 1920 pitch 7680 (/4 1920)
>[292699.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292699.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292699.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952280]
>[292699.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952280] width 1920 pitch 7680 (/4 1920)
>[292699.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292699.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292699.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952280]
>[292699.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952280] width 1920 pitch 7680 (/4 1920)
>[292699.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292699.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292700.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952280]
>[292700.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952280] width 1920 pitch 7680 (/4 1920)
>[292700.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a7f70]
>[292700.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a7f70] width 1920 pitch 7680 (/4 1920)
>[292700.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292700.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292700.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d8d0]
>[292700.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d8d0] width 1920 pitch 7680 (/4 1920)
>[292700.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292700.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292700.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d8d0]
>[292700.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d8d0] width 1920 pitch 7680 (/4 1920)
>[292700.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a580d0]
>[292700.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a580d0] width 1920 pitch 7680 (/4 1920)
>[292710.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6990360]
>[292710.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6990360] width 1920 pitch 7680 (/4 1920)
>[292737.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6971d10]
>[292737.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6971d10] width 1920 pitch 7680 (/4 1920)
>[292759.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a8980]
>[292759.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a8980] width 1920 pitch 7680 (/4 1920)
>[292816.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67afb30]
>[292816.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67afb30] width 1920 pitch 7680 (/4 1920)
>[292816.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67afb30]
>[292816.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67afb30] width 1920 pitch 7680 (/4 1920)
>[292816.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292816.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292816.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292816.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292816.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x696a3e0]
>[292816.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x696a3e0] width 1920 pitch 7680 (/4 1920)
>[292816.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x696a3e0]
>[292816.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x696a3e0] width 1920 pitch 7680 (/4 1920)
>[292816.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292816.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x696a3e0]
>[292816.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x696a3e0] width 1920 pitch 7680 (/4 1920)
>[292816.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6952750]
>[292816.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6952750] width 1920 pitch 7680 (/4 1920)
>[292820.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292820.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292820.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292821.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292821.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292821.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c2a0]
>[292821.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c2a0] width 1920 pitch 7680 (/4 1920)
>[292821.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292821.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c2a0]
>[292821.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c2a0] width 1920 pitch 7680 (/4 1920)
>[292821.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292821.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c2a0]
>[292821.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c2a0] width 1920 pitch 7680 (/4 1920)
>[292821.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292821.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c2a0]
>[292821.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c2a0] width 1920 pitch 7680 (/4 1920)
>[292821.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292821.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c2a0]
>[292821.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c2a0] width 1920 pitch 7680 (/4 1920)
>[292821.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292821.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292885.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292885.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292885.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292885.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292885.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292885.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292885.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292885.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292885.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292885.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292885.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292885.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292885.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292885.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292885.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292885.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292885.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292885.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292886.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292886.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292886.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292886.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292886.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292886.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292886.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292886.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292886.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292886.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292886.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292886.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292886.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292886.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292887.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6969c10]
>[292887.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6969c10] width 1920 pitch 7680 (/4 1920)
>[292887.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292887.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292887.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c3350]
>[292887.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c3350] width 1920 pitch 7680 (/4 1920)
>[292887.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6971d10]
>[292887.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6971d10] width 1920 pitch 7680 (/4 1920)
>[292887.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c3350]
>[292887.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c3350] width 1920 pitch 7680 (/4 1920)
>[292887.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292887.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292887.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6962800]
>[292887.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6962800] width 1920 pitch 7680 (/4 1920)
>[292887.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6971d10]
>[292887.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6971d10] width 1920 pitch 7680 (/4 1920)
>[292887.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6962800]
>[292887.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6962800] width 1920 pitch 7680 (/4 1920)
>[292946.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67c3350]
>[292946.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67c3350] width 1920 pitch 7680 (/4 1920)
>[292946.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f87050]
>[292946.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f87050] width 1920 pitch 7680 (/4 1920)
>[292948.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x696a290]
>[292948.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x696a290] width 1920 pitch 7680 (/4 1920)
>[292954.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3600]
>[292954.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3600] width 1920 pitch 7680 (/4 1920)
>[292955.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a3600]
>[292955.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a3600] width 1920 pitch 7680 (/4 1920)
>[293071.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293071.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293071.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293071.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293071.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293071.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695a680]
>[293071.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695a680] width 1920 pitch 7680 (/4 1920)
>[293071.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293071.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293075.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579d0]
>[293075.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579d0] width 1920 pitch 7680 (/4 1920)
>[293075.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293075.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579c0]
>[293080.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579c0] width 1920 pitch 7680 (/4 1920)
>[293080.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293080.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293080.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293080.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293080.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293080.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293080.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293080.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293080.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293080.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293080.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293080.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293080.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293084.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69579c0]
>[293084.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69579c0] width 1920 pitch 7680 (/4 1920)
>[293084.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293084.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293084.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293084.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293084.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293084.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293084.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293084.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293084.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293084.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293084.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293084.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293084.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43450]
>[293085.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43450] width 1920 pitch 7680 (/4 1920)
>[293085.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293085.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293085.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293085.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293085.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695aa00]
>[293085.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695aa00] width 1920 pitch 7680 (/4 1920)
>[293085.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293085.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293085.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293085.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293085.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293085.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293085.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293085.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293085.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293085.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293085.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293085.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293085.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293085.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293085.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293085.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293085.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6932130]
>[293085.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6932130] width 1920 pitch 7680 (/4 1920)
>[293085.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293085.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293088.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293088.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293088.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293088.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293088.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293088.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293088.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293088.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293088.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293088.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293088.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293088.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293088.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293088.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293088.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293088.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293088.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293088.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293088.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293088.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293089.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293089.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293089.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293089.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293090.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293090.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293090.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293090.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293090.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293090.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293090.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293090.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ac10]
>[293090.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ac10] width 1920 pitch 7680 (/4 1920)
>[293090.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a2cd0]
>[293090.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a2cd0] width 1920 pitch 7680 (/4 1920)
>[293156.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6984c60]
>[293156.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6984c60] width 1920 pitch 7680 (/4 1920)
>[293156.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6985290]
>[293156.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6985290] width 1920 pitch 7680 (/4 1920)
>[293157.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6961120]
>[293157.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6961120] width 1920 pitch 7680 (/4 1920)
>[293157.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293157.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293157.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293157.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293157.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293157.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293157.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293157.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293157.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293157.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293157.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293157.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293157.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293157.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293158.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293158.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293158.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293158.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293158.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293158.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293158.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293158.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293158.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695c040]
>[293158.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695c040] width 1920 pitch 7680 (/4 1920)
>[293159.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293159.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293159.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f170]
>[293159.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f170] width 1920 pitch 7680 (/4 1920)
>[293159.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f170]
>[293159.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f170] width 1920 pitch 7680 (/4 1920)
>[293159.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43ea0]
>[293159.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43ea0] width 1920 pitch 7680 (/4 1920)
>[293159.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f170]
>[293159.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f170] width 1920 pitch 7680 (/4 1920)
>[293159.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6960cf0]
>[293159.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6960cf0] width 1920 pitch 7680 (/4 1920)
>[293159.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695f170]
>[293159.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695f170] width 1920 pitch 7680 (/4 1920)
>[293159.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698eb70]
>[293159.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698eb70] width 1920 pitch 7680 (/4 1920)
>[293268.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c43ea0]
>[293268.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c43ea0] width 1920 pitch 7680 (/4 1920)
>[293642.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ac150]
>[293642.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ac150] width 1920 pitch 7680 (/4 1920)
>[293642.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x675e130]
>[293642.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x675e130] width 1920 pitch 7680 (/4 1920)
>[293642.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x697fc30]
>[293642.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x697fc30] width 1920 pitch 7680 (/4 1920)
>[293642.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ac150]
>[293643.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ac150] width 1920 pitch 7680 (/4 1920)
>[293643.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69810b0]
>[293643.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69810b0] width 1920 pitch 7680 (/4 1920)
>[293643.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293643.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293643.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69810b0]
>[293643.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69810b0] width 1920 pitch 7680 (/4 1920)
>[293643.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293643.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293643.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69810b0]
>[293643.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69810b0] width 1920 pitch 7680 (/4 1920)
>[293643.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293643.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293643.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69810b0]
>[293643.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69810b0] width 1920 pitch 7680 (/4 1920)
>[293643.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293643.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293644.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69810b0]
>[293644.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69810b0] width 1920 pitch 7680 (/4 1920)
>[293644.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293644.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293644.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x697fc30]
>[293644.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x697fc30] width 1920 pitch 7680 (/4 1920)
>[293644.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67ac150]
>[293644.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67ac150] width 1920 pitch 7680 (/4 1920)
>[293644.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989110]
>[293644.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989110] width 1920 pitch 7680 (/4 1920)
>[293644.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6960f30]
>[293644.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6960f30] width 1920 pitch 7680 (/4 1920)
>[293644.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6981d60]
>[293644.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6981d60] width 1920 pitch 7680 (/4 1920)
>[293671.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989100]
>[293671.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989100] width 1920 pitch 7680 (/4 1920)
>[293713.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698e860]
>[293713.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698e860] width 1920 pitch 7680 (/4 1920)
>[293713.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293713.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293713.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293713.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293713.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293713.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293713.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293713.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293713.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293713.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293713.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293713.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293714.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293714.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293714.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293714.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293714.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293714.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293714.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293714.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293714.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293714.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293715.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293715.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293715.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293715.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293716.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293716.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293716.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293716.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293716.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293716.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293716.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293716.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293716.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6974b90]
>[293716.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6974b90] width 1920 pitch 7680 (/4 1920)
>[293716.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293716.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293787.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293787.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293787.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293787.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293787.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293787.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293787.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293787.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293787.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293787.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293787.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293787.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293788.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293788.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293788.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293788.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293788.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293788.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293788.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293788.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293788.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293788.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293788.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293788.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293788.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293789.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293789.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a43f0]
>[293789.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a43f0] width 1920 pitch 7680 (/4 1920)
>[293789.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6930bf0]
>[293789.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6930bf0] width 1920 pitch 7680 (/4 1920)
>[293855.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6746200]
>[293855.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6746200] width 1920 pitch 7680 (/4 1920)
>[293855.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67472e0]
>[293855.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67472e0] width 1920 pitch 7680 (/4 1920)
>[293855.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6961120]
>[293855.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6961120] width 1920 pitch 7680 (/4 1920)
>[293855.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[293855.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[293855.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925d40]
>[293855.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925d40] width 1920 pitch 7680 (/4 1920)
>[293855.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69288f0]
>[293855.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69288f0] width 1920 pitch 7680 (/4 1920)
>[293856.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925d40]
>[293856.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925d40] width 1920 pitch 7680 (/4 1920)
>[293856.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b7e60]
>[293856.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b7e60] width 1920 pitch 7680 (/4 1920)
>[293856.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d0e0]
>[293856.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d0e0] width 1920 pitch 7680 (/4 1920)
>[293856.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6973460]
>[293856.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6973460] width 1920 pitch 7680 (/4 1920)
>[293856.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d0e0]
>[293856.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d0e0] width 1920 pitch 7680 (/4 1920)
>[293856.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925d40]
>[293856.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925d40] width 1920 pitch 7680 (/4 1920)
>[293856.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6925d40]
>[293856.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6925d40] width 1920 pitch 7680 (/4 1920)
>[293955.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749390]
>[293955.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749390] width 1920 pitch 7680 (/4 1920)
>[294030.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x693cae0]
>[294030.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x693cae0] width 1920 pitch 7680 (/4 1920)
>[294030.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6782ca0]
>[294030.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6782ca0] width 1920 pitch 7680 (/4 1920)
>[294030.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677e120]
>[294030.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677e120] width 1920 pitch 7680 (/4 1920)
>[294030.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x671bc80]
>[294030.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x671bc80] width 1920 pitch 7680 (/4 1920)
>[294030.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67476b0]
>[294030.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67476b0] width 1920 pitch 7680 (/4 1920)
>[294030.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5ac0]
>[294030.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5ac0] width 1920 pitch 7680 (/4 1920)
>[294030.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x677e120]
>[294030.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x677e120] width 1920 pitch 7680 (/4 1920)
>[294030.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6782ca0]
>[294030.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6782ca0] width 1920 pitch 7680 (/4 1920)
>[294031.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67a5ac0]
>[294031.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67a5ac0] width 1920 pitch 7680 (/4 1920)
>[294031.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6782ca0]
>[294031.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6782ca0] width 1920 pitch 7680 (/4 1920)
>[294031.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2180]
>[294031.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2180] width 1920 pitch 7680 (/4 1920)
>[294031.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4280]
>[294031.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4280] width 1920 pitch 7680 (/4 1920)
>[294031.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69268b0]
>[294031.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69268b0] width 1920 pitch 7680 (/4 1920)
>[294031.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2180]
>[294031.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2180] width 1920 pitch 7680 (/4 1920)
>[294031.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2180]
>[294031.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2180] width 1920 pitch 7680 (/4 1920)
>[294031.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d2180]
>[294031.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d2180] width 1920 pitch 7680 (/4 1920)
>[294044.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d5f0]
>[294044.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d5f0] width 1920 pitch 7680 (/4 1920)
>[294044.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d5f0]
>[294044.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d5f0] width 1920 pitch 7680 (/4 1920)
>[294044.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69268b0]
>[294044.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69268b0] width 1920 pitch 7680 (/4 1920)
>[294044.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ef40]
>[294044.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ef40] width 1920 pitch 7680 (/4 1920)
>[294044.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69268b0]
>[294044.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69268b0] width 1920 pitch 7680 (/4 1920)
>[294044.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ef40]
>[294044.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ef40] width 1920 pitch 7680 (/4 1920)
>[294045.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d5f0]
>[294045.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d5f0] width 1920 pitch 7680 (/4 1920)
>[294045.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ef40]
>[294045.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ef40] width 1920 pitch 7680 (/4 1920)
>[294045.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x695ef40]
>[294045.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x695ef40] width 1920 pitch 7680 (/4 1920)
>[294045.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d5f0]
>[294045.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d5f0] width 1920 pitch 7680 (/4 1920)
>[294045.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698d5f0]
>[294045.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698d5f0] width 1920 pitch 7680 (/4 1920)
>[294046.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69268b0]
>[294046.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69268b0] width 1920 pitch 7680 (/4 1920)
>[294046.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294046.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294046.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294046.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294046.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294046.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294046.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294046.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294046.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294046.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294046.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294046.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294047.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294047.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294047.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294047.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294047.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294047.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294047.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294047.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294047.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294047.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294048.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294048.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294048.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294048.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294048.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294048.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294048.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294048.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294048.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5b292b0]
>[294048.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5b292b0] width 1920 pitch 7680 (/4 1920)
>[294048.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294048.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294048.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294048.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294049.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294049.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294049.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd2fd0]
>[294049.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd2fd0] width 1920 pitch 7680 (/4 1920)
>[294049.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5c20320]
>[294049.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5c20320] width 1920 pitch 7680 (/4 1920)
>[294049.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ceead0]
>[294049.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ceead0] width 1920 pitch 7680 (/4 1920)
>[294049.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cd2fd0]
>[294049.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cd2fd0] width 1920 pitch 7680 (/4 1920)
>[294057.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294057.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294057.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbc10]
>[294057.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbc10] width 1920 pitch 7680 (/4 1920)
>[294057.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbc10]
>[294057.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbc10] width 1920 pitch 7680 (/4 1920)
>[294057.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294057.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294057.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbc10]
>[294057.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbc10] width 1920 pitch 7680 (/4 1920)
>[294057.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294057.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294057.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbc10]
>[294057.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbc10] width 1920 pitch 7680 (/4 1920)
>[294057.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67b5a60]
>[294057.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67b5a60] width 1920 pitch 7680 (/4 1920)
>[294057.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294057.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294057.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294057.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294059.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cae460]
>[294059.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cae460] width 1920 pitch 7680 (/4 1920)
>[294059.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5cae460]
>[294059.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5cae460] width 1920 pitch 7680 (/4 1920)
>[294059.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294059.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294060.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294060.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294061.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294061.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294061.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294061.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294061.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294061.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294061.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294061.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294061.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbb30]
>[294061.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbb30] width 1920 pitch 7680 (/4 1920)
>[294061.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294061.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f4e6a0]
>[294061.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f4e6a0] width 1920 pitch 7680 (/4 1920)
>[294061.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294061.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294061.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294061.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294061.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbb30]
>[294061.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbb30] width 1920 pitch 7680 (/4 1920)
>[294061.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294061.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294061.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294061.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294148.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294148.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294151.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294151.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294151.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2e840]
>[294151.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2e840] width 1920 pitch 7680 (/4 1920)
>[294151.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294151.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294159.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69882a0]
>[294159.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69882a0] width 1920 pitch 7680 (/4 1920)
>[294159.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2e840]
>[294159.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2e840] width 1920 pitch 7680 (/4 1920)
>[294159.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ce8d80]
>[294159.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ce8d80] width 1920 pitch 7680 (/4 1920)
>[294159.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbb30]
>[294159.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbb30] width 1920 pitch 7680 (/4 1920)
>[294159.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a2e840]
>[294159.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a2e840] width 1920 pitch 7680 (/4 1920)
>[294159.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ccbb30]
>[294159.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ccbb30] width 1920 pitch 7680 (/4 1920)
>[294175.047] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[294175.108] 
>[294175.108] Backtrace:
>[294177.102] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[294177.102] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x5514db]
>[294177.102] 2: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[294177.102] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f19fe77d000+0x60e4) [0x7f19fe7830e4]
>[294177.102] 4: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[294177.102] 5: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[294177.102] 6: /lib64/libpthread.so.0 (0x36f6400000+0xefe0) [0x36f640efe0]
>[294177.102] 7: /usr/bin/Xorg (0x400000+0x6aba0) [0x46aba0]
>[294177.102] 8: /lib64/libpthread.so.0 (0x36f6400000+0xefe0) [0x36f640efe0]
>[294177.102] 9: /lib64/libc.so.6 (_IO_vfprintf+0xde) [0x36f604679e]
>[294177.102] 10: /lib64/libc.so.6 (0x36f6000000+0x4b51f) [0x36f604b51f]
>[294177.102] 11: /lib64/libc.so.6 (_IO_vfprintf+0x1f6) [0x36f60468b6]
>[294177.102] 12: /lib64/libc.so.6 (__fprintf_chk+0xee) [0x36f610706e]
>[294177.102] 13: /usr/bin/Xorg (0x400000+0x69269) [0x469269]
>[294177.102] 14: /usr/bin/Xorg (LogVMessageVerb+0x92) [0x469682]
>[294177.102] 15: /usr/bin/Xorg (ErrorF+0x8c) [0x46901c]
>[294177.102] 16: /usr/bin/Xorg (mieqProcessInputEvents+0x1d2) [0x551b02]
>[294177.102] 17: /usr/bin/Xorg (ProcessInputEvents+0x9) [0x480839]
>[294177.102] 18: /usr/bin/Xorg (0x400000+0x341ec) [0x4341ec]
>[294177.102] 19: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[294177.102] 20: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x36f6021735]
>[294177.102] 21: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[294177.102] 
>[294177.102] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[294177.102] [mi] mieq is *NOT* the cause.  It is a victim.
>[294174.924] [mi] Increasing EQ size to 512 to prevent dropped events.
>[294177.123] [mi] EQ processing has resumed after 29 dropped events.
>[294177.123] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.

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Attachments on bug 864704: 624324 | 624325 | 624326