Attachment 632789 Details for Bug 869652 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 292.14 KB, created by linelux on 2012-10-24 13:41:18 UTC

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Creator: linelux

Created: 2012-10-24 13:41:18 UTC

Size: 292.14 KB

patch

obsolete

>[    27.010] 
>X.Org X Server 1.12.3
>Release Date: 2012-07-09
>[    27.010] X Protocol Version 11, Revision 0
>[    27.010] Build Operating System:  2.6.32-220.17.1.el6.x86_64 
>[    27.010] Current Operating System: Linux marknotebook 3.6.1-1.fc17.x86_64 #1 SMP Wed Oct 10 12:13:05 UTC 2012 x86_64
>[    27.010] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.1-1.fc17.x86_64 root=/dev/mapper/vg_marknotebook-lv_root ro rd.lvm.lv=vg_marknotebook/lv_swap rd.md=0 rd.dm=0 SYSFONT=True KEYTABLE=de rd.luks=0 LANG=en_US.UTF-8 rd.lvm.lv=vg_marknotebook/lv_root rhgb quiet
>[    27.010] Build Date: 20 September 2012  07:51:23AM
>[    27.010] Build ID: xorg-x11-server 1.12.3-2.fc17 
>[    27.010] Current version of pixman: 0.24.4
>[    27.010] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    27.010] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    27.011] (==) Log file: "/var/log/Xorg.0.log", Time: Wed Oct 24 15:18:54 2012
>[    27.021] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    27.021] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    27.021] (==) No Layout section.  Using the first Screen section.
>[    27.021] (==) No screen section available. Using defaults.
>[    27.021] (**) |-->Screen "Default Screen Section" (0)
>[    27.021] (**) |   |-->Monitor "<default monitor>"
>[    27.021] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    27.021] (==) Automatically adding devices
>[    27.021] (==) Automatically enabling devices
>[    27.021] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    27.021] (==) ModulePath set to "/usr/lib64/xorg/modules"
>[    27.021] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    27.021] (II) Loader magic: 0x7c6ac0
>[    27.021] (II) Module ABI versions:
>[    27.021] 	X.Org ANSI C Emulation: 0.4
>[    27.021] 	X.Org Video Driver: 12.0
>[    27.021] 	X.Org XInput driver : 16.0
>[    27.021] 	X.Org Server Extension : 6.0
>[    27.023] (--) PCI:*(0:1:0:0) 1002:94c9:1043:15b2 rev 0, Mem @ 0xe0000000/268435456, 0xfdef0000/65536, I/O @ 0x0000a000/256, BIOS @ 0x????????/131072
>[    27.023] (II) LoadModule: "extmod"
>[    27.100] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so
>[    27.101] (II) Module extmod: vendor="X.Org Foundation"
>[    27.101] 	compiled for 1.12.3, module version = 1.0.0
>[    27.101] 	Module class: X.Org Server Extension
>[    27.101] 	ABI class: X.Org Server Extension, version 6.0
>[    27.101] (II) Loading extension SELinux
>[    27.101] (II) Loading extension MIT-SCREEN-SAVER
>[    27.101] (II) Loading extension XFree86-VidModeExtension
>[    27.101] (II) Loading extension XFree86-DGA
>[    27.101] (II) Loading extension DPMS
>[    27.101] (II) Loading extension XVideo
>[    27.101] (II) Loading extension XVideo-MotionCompensation
>[    27.101] (II) Loading extension X-Resource
>[    27.101] (II) LoadModule: "dbe"
>[    27.101] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so
>[    27.101] (II) Module dbe: vendor="X.Org Foundation"
>[    27.101] 	compiled for 1.12.3, module version = 1.0.0
>[    27.101] 	Module class: X.Org Server Extension
>[    27.101] 	ABI class: X.Org Server Extension, version 6.0
>[    27.101] (II) Loading extension DOUBLE-BUFFER
>[    27.101] (II) LoadModule: "glx"
>[    27.101] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
>[    27.101] (II) Module glx: vendor="X.Org Foundation"
>[    27.101] 	compiled for 1.12.3, module version = 1.0.0
>[    27.101] 	ABI class: X.Org Server Extension, version 6.0
>[    27.101] (==) AIGLX enabled
>[    27.101] (II) Loading extension GLX
>[    27.101] (II) LoadModule: "record"
>[    27.102] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so
>[    27.102] (II) Module record: vendor="X.Org Foundation"
>[    27.102] 	compiled for 1.12.3, module version = 1.13.0
>[    27.102] 	Module class: X.Org Server Extension
>[    27.102] 	ABI class: X.Org Server Extension, version 6.0
>[    27.102] (II) Loading extension RECORD
>[    27.102] (II) LoadModule: "dri"
>[    27.102] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so
>[    27.102] (II) Module dri: vendor="X.Org Foundation"
>[    27.102] 	compiled for 1.12.3, module version = 1.0.0
>[    27.102] 	ABI class: X.Org Server Extension, version 6.0
>[    27.102] (II) Loading extension XFree86-DRI
>[    27.102] (II) LoadModule: "dri2"
>[    27.102] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so
>[    27.103] (II) Module dri2: vendor="X.Org Foundation"
>[    27.103] 	compiled for 1.12.3, module version = 1.2.0
>[    27.103] 	ABI class: X.Org Server Extension, version 6.0
>[    27.103] (II) Loading extension DRI2
>[    27.103] (==) Matched ati as autoconfigured driver 0
>[    27.103] (==) Matched vesa as autoconfigured driver 1
>[    27.103] (==) Matched modesetting as autoconfigured driver 2
>[    27.103] (==) Matched fbdev as autoconfigured driver 3
>[    27.103] (==) Assigned the driver to the xf86ConfigLayout
>[    27.103] (II) LoadModule: "ati"
>[    27.103] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so
>[    27.103] (II) Module ati: vendor="X.Org Foundation"
>[    27.103] 	compiled for 1.12.0, module version = 6.14.99
>[    27.103] 	Module class: X.Org Video Driver
>[    27.103] 	ABI class: X.Org Video Driver, version 12.0
>[    27.103] (II) LoadModule: "radeon"
>[    27.103] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so
>[    27.103] (II) Module radeon: vendor="X.Org Foundation"
>[    27.103] 	compiled for 1.12.0, module version = 6.14.99
>[    27.103] 	Module class: X.Org Video Driver
>[    27.103] 	ABI class: X.Org Video Driver, version 12.0
>[    27.103] (II) LoadModule: "vesa"
>[    27.103] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so
>[    27.104] (II) Module vesa: vendor="X.Org Foundation"
>[    27.104] 	compiled for 1.12.0, module version = 2.3.1
>[    27.104] 	Module class: X.Org Video Driver
>[    27.104] 	ABI class: X.Org Video Driver, version 12.0
>[    27.104] (II) LoadModule: "modesetting"
>[    27.104] (WW) Warning, couldn't open module modesetting
>[    27.104] (II) UnloadModule: "modesetting"
>[    27.104] (II) Unloading modesetting
>[    27.104] (EE) Failed to load module "modesetting" (module does not exist, 0)
>[    27.104] (II) LoadModule: "fbdev"
>[    27.104] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so
>[    27.104] (II) Module fbdev: vendor="X.Org Foundation"
>[    27.104] 	compiled for 1.11.99.901, module version = 0.4.2
>[    27.104] 	ABI class: X.Org Video Driver, version 12.0
>[    27.104] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    27.108] (II) VESA: driver for VESA chipsets: vesa
>[    27.108] (II) FBDEV: driver for framebuffer: fbdev
>[    27.108] (++) using VT number 1
>
>[    27.109] (II) [KMS] Kernel modesetting enabled.
>[    27.109] (WW) Falling back to old probe method for vesa
>[    27.109] (WW) Falling back to old probe method for fbdev
>[    27.109] (II) Loading sub module "fbdevhw"
>[    27.109] (II) LoadModule: "fbdevhw"
>[    27.110] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so
>[    27.110] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    27.110] 	compiled for 1.12.3, module version = 0.0.2
>[    27.110] 	ABI class: X.Org Video Driver, version 12.0
>[    27.110] (II) RADEON(0): RADEONPreInit_KMS
>[    27.110] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    27.110] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    27.110] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    27.110] (==) RADEON(0): Default visual is TrueColor
>[    27.110] (==) RADEON(0): RGB weight 888
>[    27.110] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    27.110] (--) RADEON(0): Chipset: "ATI Mobility Radeon HD 2400" (ChipID = 0x94c9)
>[    27.110] (II) RADEON(0): PCIE card detected
>[    27.110] drmOpenDevice: node name is /dev/dri/card0
>[    27.110] drmOpenDevice: open result is 8, (OK)
>[    27.110] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    27.110] drmOpenDevice: node name is /dev/dri/card0
>[    27.110] drmOpenDevice: open result is 8, (OK)
>[    27.110] drmOpenByBusid: drmOpenMinor returns 8
>[    27.110] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    27.110] (II) Loading sub module "exa"
>[    27.110] (II) LoadModule: "exa"
>[    27.110] (II) Loading /usr/lib64/xorg/modules/libexa.so
>[    27.110] (II) Module exa: vendor="X.Org Foundation"
>[    27.110] 	compiled for 1.12.3, module version = 2.5.0
>[    27.110] 	ABI class: X.Org Video Driver, version 12.0
>[    27.110] (II) RADEON(0): KMS Color Tiling: enabled
>[    27.110] (II) RADEON(0): KMS Pageflipping: enabled
>[    27.110] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    27.125] (II) RADEON(0): Output VGA-0 has no monitor section
>[    27.125] (II) RADEON(0): Output LVDS has no monitor section
>[    27.137] (II) RADEON(0): Output DIN has no monitor section
>[    27.140] (II) RADEON(0): Output DVI-0 has no monitor section
>[    27.154] (II) RADEON(0): EDID for output VGA-0
>[    27.154] (II) RADEON(0): EDID for output LVDS
>[    27.154] (II) RADEON(0): Manufacturer: CMO  Model: 1526  Serial#: 0
>[    27.154] (II) RADEON(0): Year: 2006  Week: 9
>[    27.154] (II) RADEON(0): EDID Version: 1.3
>[    27.154] (II) RADEON(0): Digital Display Input
>[    27.154] (II) RADEON(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>[    27.154] (II) RADEON(0): Gamma: 2.20
>[    27.154] (II) RADEON(0): No DPMS capabilities specified
>[    27.154] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>[    27.154] (II) RADEON(0): First detailed timing is preferred mode
>[    27.155] (II) RADEON(0): redX: 0.604 redY: 0.340   greenX: 0.306 greenY: 0.521
>[    27.155] (II) RADEON(0): blueX: 0.150 blueY: 0.119   whiteX: 0.314 whiteY: 0.321
>[    27.155] (II) RADEON(0): Manufacturer's mask: 0
>[    27.155] (II) RADEON(0): Supported detailed timing:
>[    27.155] (II) RADEON(0): clock: 71.0 MHz   Image Size:  331 x 207 mm
>[    27.155] (II) RADEON(0): h_active: 1280  h_sync: 1328  h_sync_end 1360 h_blank_end 1440 h_border: 0
>[    27.155] (II) RADEON(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 823 v_border: 0
>[    27.155] (II) RADEON(0):  N154I2-L02
>[    27.155] (II) RADEON(0):  CMO
>[    27.155] (II) RADEON(0):  N154I2-L02
>[    27.155] (II) RADEON(0): EDID (in hex):
>[    27.155] (II) RADEON(0): 	00ffffffffffff000daf261500000000
>[    27.155] (II) RADEON(0): 	09100103802115780ac6a99a574e8526
>[    27.155] (II) RADEON(0): 	1e505200000001010101010101010101
>[    27.155] (II) RADEON(0): 	010101010101bc1b00a0502017303020
>[    27.155] (II) RADEON(0): 	36004bcf10000018000000fe004e3135
>[    27.155] (II) RADEON(0): 	3449322d4c30320a2020000000fe0043
>[    27.155] (II) RADEON(0): 	4d4f0a202020202020202020000000fe
>[    27.155] (II) RADEON(0): 	004e31353449322d4c30320a20200088
>[    27.155] (II) RADEON(0): Printing probed modes for output LVDS
>[    27.155] (II) RADEON(0): Modeline "1280x800"x59.9   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    27.155] (II) RADEON(0): Modeline "1280x720"x59.9   74.50  1280 1344 1472 1664  720 723 728 748 -hsync +vsync (44.8 kHz)
>[    27.155] (II) RADEON(0): Modeline "1152x768"x59.8   71.75  1152 1216 1328 1504  768 771 781 798 -hsync +vsync (47.7 kHz)
>[    27.155] (II) RADEON(0): Modeline "1024x768"x120.1  133.47  1024 1100 1212 1400  768 768 770 794 doublescan -hsync +vsync (95.3 kHz d)
>[    27.155] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz d)
>[    27.156] (II) RADEON(0): Modeline "1024x768"x59.9   63.50  1024 1072 1176 1328  768 771 775 798 -hsync +vsync (47.8 kHz)
>[    27.156] (II) RADEON(0): Modeline "960x720"x120.0  117.00  960 1024 1128 1300  720 720 722 750 doublescan -hsync +vsync (90.0 kHz d)
>[    27.156] (II) RADEON(0): Modeline "928x696"x120.1  109.15  928 976 1088 1264  696 696 698 719 doublescan -hsync +vsync (86.4 kHz d)
>[    27.156] (II) RADEON(0): Modeline "896x672"x120.0  102.40  896 960 1060 1224  672 672 674 697 doublescan -hsync +vsync (83.7 kHz d)
>[    27.156] (II) RADEON(0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
>[    27.156] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
>[    27.156] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    27.156] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
>[    27.156] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    27.156] (II) RADEON(0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
>[    27.156] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    27.156] (II) RADEON(0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
>[    27.156] (II) RADEON(0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
>[    27.156] (II) RADEON(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
>[    27.156] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    27.156] (II) RADEON(0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
>[    27.156] (II) RADEON(0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
>[    27.156] (II) RADEON(0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
>[    27.156] (II) RADEON(0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
>[    27.168] (II) RADEON(0): EDID for output DIN
>[    27.170] (II) RADEON(0): EDID for output DVI-0
>[    27.170] (II) RADEON(0): Output VGA-0 disconnected
>[    27.170] (II) RADEON(0): Output LVDS connected
>[    27.170] (II) RADEON(0): Output DIN disconnected
>[    27.170] (II) RADEON(0): Output DVI-0 disconnected
>[    27.171] (II) RADEON(0): Using exact sizes for initial modes
>[    27.171] (II) RADEON(0): Output LVDS using initial mode 1280x800 +0+0
>[    27.171] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    27.171] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:8000000 visible:fbd8000
>[    27.171] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    27.171] (==) RADEON(0): DPI set to (96, 96)
>[    27.171] (II) Loading sub module "fb"
>[    27.171] (II) LoadModule: "fb"
>[    27.171] (II) Loading /usr/lib64/xorg/modules/libfb.so
>[    27.172] (II) Module fb: vendor="X.Org Foundation"
>[    27.172] 	compiled for 1.12.3, module version = 1.0.0
>[    27.172] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    27.172] (II) Loading sub module "ramdac"
>[    27.172] (II) LoadModule: "ramdac"
>[    27.172] (II) Module "ramdac" already built-in
>[    27.172] (II) UnloadModule: "vesa"
>[    27.172] (II) Unloading vesa
>[    27.172] (II) UnloadModule: "fbdev"
>[    27.172] (II) Unloading fbdev
>[    27.172] (II) UnloadSubModule: "fbdevhw"
>[    27.172] (II) Unloading fbdevhw
>[    27.172] (--) Depth 24 pixmap format is 32 bpp
>[    27.172] (II) RADEON(0): [DRI2] Setup complete
>[    27.172] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    27.172] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    27.173] (II) RADEON(0): Front buffer size: 4000K
>[    27.173] (II) RADEON(0): VRAM usage limit set to 228499K
>[    27.173] (II) RADEON(0): Initializing backing store
>[    27.173] (==) RADEON(0): Backing store disabled
>[    27.173] (II) RADEON(0): Direct rendering enabled
>[    27.173] (II) RADEON(0): Initializing Acceleration
>[    27.173] (II) RADEON(0): Setting EXA maxPitchBytes
>[    27.173] (II) EXA(0): Driver allocated offscreen pixmaps
>[    27.173] (II) EXA(0): Driver registered support for the following operations:
>[    27.173] (II)         Solid
>[    27.173] (II)         Copy
>[    27.173] (II)         Composite (RENDER acceleration)
>[    27.173] (II)         UploadToScreen
>[    27.173] (II)         DownloadFromScreen
>[    27.173] (II) RADEON(0): Acceleration enabled
>[    27.173] (II) RADEON(0): Initializing DPMS
>[    27.173] (==) RADEON(0): DPMS enabled
>[    27.173] (II) RADEON(0): Initializing Cursor
>[    27.173] (==) RADEON(0): Silken mouse enabled
>[    27.173] (II) RADEON(0): Initializing Xv
>[    27.173] (II) RADEON(0): Set up textured video
>[    27.173] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    27.173] (II) RADEON(0): [XvMC] Extension initialized.
>[    27.173] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    27.173] (II) RADEON(0): Initializing kms color map
>[    27.173] (II) RADEON(0): RADEONScreenInit finished
>[    27.174] (--) RandR disabled
>[    27.174] (II) Initializing built-in extension Generic Event Extension
>[    27.174] (II) Initializing built-in extension SHAPE
>[    27.174] (II) Initializing built-in extension MIT-SHM
>[    27.174] (II) Initializing built-in extension XInputExtension
>[    27.174] (II) Initializing built-in extension XTEST
>[    27.174] (II) Initializing built-in extension BIG-REQUESTS
>[    27.174] (II) Initializing built-in extension SYNC
>[    27.174] (II) Initializing built-in extension XKEYBOARD
>[    27.174] (II) Initializing built-in extension XC-MISC
>[    27.174] (II) Initializing built-in extension XINERAMA
>[    27.174] (II) Initializing built-in extension XFIXES
>[    27.174] (II) Initializing built-in extension RENDER
>[    27.174] (II) Initializing built-in extension RANDR
>[    27.174] (II) Initializing built-in extension COMPOSITE
>[    27.174] (II) Initializing built-in extension DAMAGE
>[    27.175] (II) SELinux: Disabled by boolean
>[    27.750] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    27.750] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    27.750] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    27.750] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    27.751] (II) AIGLX: Loaded and initialized r600
>[    27.751] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    27.754] (II) RADEON(0): Setting screen physical size to 338 x 211
>[    27.807] (II) XKB: Reusing cached keymap
>[    27.809] (II) config/udev: Adding input device Power Button (/dev/input/event2)
>[    27.809] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    27.809] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    27.809] (II) LoadModule: "evdev"
>[    27.810] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so
>[    27.810] (II) Module evdev: vendor="X.Org Foundation"
>[    27.810] 	compiled for 1.12.0, module version = 2.7.0
>[    27.810] 	Module class: X.Org XInput Driver
>[    27.810] 	ABI class: X.Org XInput driver, version 16.0
>[    27.810] (II) Using input driver 'evdev' for 'Power Button'
>[    27.810] 	Option "XkbRules" "evdev"
>[    27.810] 	Option "XkbModel" "pc105"
>[    27.810] 	Option "XkbLayout" "de"
>[    27.810] 	Option "_source" "server/udev"
>[    27.810] 	Option "name" "Power Button"
>[    27.810] 	Option "path" "/dev/input/event2"
>[    27.810] 	Option "device" "/dev/input/event2"
>[    27.810] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    27.810] 	Option "driver" "evdev"
>[    27.810] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.810] (**) Power Button: always reports core events
>[    27.810] (**) evdev: Power Button: Device: "/dev/input/event2"
>[    27.810] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    27.810] (--) evdev: Power Button: Found keys
>[    27.810] (II) evdev: Power Button: Configuring as keyboard
>[    27.810] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    27.810] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    27.810] (**) Option "xkb_rules" "evdev"
>[    27.810] (**) Option "xkb_model" "pc105"
>[    27.810] (**) Option "xkb_layout" "de"
>[    27.810] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.837] (II) config/udev: Adding input device Video Bus (/dev/input/event5)
>[    27.837] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    27.837] (**) Video Bus: Applying InputClass "system-setup-keyboard"
>[    27.837] (II) Using input driver 'evdev' for 'Video Bus'
>[    27.837] 	Option "XkbRules" "evdev"
>[    27.837] 	Option "XkbModel" "pc105"
>[    27.837] 	Option "XkbLayout" "de"
>[    27.837] 	Option "_source" "server/udev"
>[    27.837] 	Option "name" "Video Bus"
>[    27.837] 	Option "path" "/dev/input/event5"
>[    27.837] 	Option "device" "/dev/input/event5"
>[    27.837] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:1b/LNXVIDEO:00/input/input5/event5"
>[    27.837] 	Option "driver" "evdev"
>[    27.837] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.837] (**) Video Bus: always reports core events
>[    27.837] (**) evdev: Video Bus: Device: "/dev/input/event5"
>[    27.837] (--) evdev: Video Bus: Vendor 0 Product 0x6
>[    27.837] (--) evdev: Video Bus: Found keys
>[    27.837] (II) evdev: Video Bus: Configuring as keyboard
>[    27.837] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:1b/LNXVIDEO:00/input/input5/event5"
>[    27.837] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7)
>[    27.837] (**) Option "xkb_rules" "evdev"
>[    27.837] (**) Option "xkb_model" "pc105"
>[    27.837] (**) Option "xkb_layout" "de"
>[    27.837] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.837] (II) XKB: Reusing cached keymap
>[    27.838] (II) config/udev: Adding input device Lid Switch (/dev/input/event1)
>[    27.838] (II) No input driver specified, ignoring this device.
>[    27.838] (II) This device may have been added with another device file.
>[    27.838] (II) config/udev: Adding input device Sleep Button (/dev/input/event0)
>[    27.838] (**) Sleep Button: Applying InputClass "evdev keyboard catchall"
>[    27.838] (**) Sleep Button: Applying InputClass "system-setup-keyboard"
>[    27.838] (II) Using input driver 'evdev' for 'Sleep Button'
>[    27.838] 	Option "XkbRules" "evdev"
>[    27.838] 	Option "XkbModel" "pc105"
>[    27.838] 	Option "XkbLayout" "de"
>[    27.838] 	Option "_source" "server/udev"
>[    27.838] 	Option "name" "Sleep Button"
>[    27.838] 	Option "path" "/dev/input/event0"
>[    27.838] 	Option "device" "/dev/input/event0"
>[    27.838] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    27.838] 	Option "driver" "evdev"
>[    27.838] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.838] (**) Sleep Button: always reports core events
>[    27.838] (**) evdev: Sleep Button: Device: "/dev/input/event0"
>[    27.838] (--) evdev: Sleep Button: Vendor 0 Product 0x3
>[    27.838] (--) evdev: Sleep Button: Found keys
>[    27.838] (II) evdev: Sleep Button: Configuring as keyboard
>[    27.838] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    27.838] (II) XINPUT: Adding extended input device "Sleep Button" (type: KEYBOARD, id 8)
>[    27.838] (**) Option "xkb_rules" "evdev"
>[    27.838] (**) Option "xkb_model" "pc105"
>[    27.838] (**) Option "xkb_layout" "de"
>[    27.838] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.838] (II) XKB: Reusing cached keymap
>[    27.839] (II) config/udev: Adding input device USB2.0 1.3M UVC WebCam  (/dev/input/event7)
>[    27.839] (**) USB2.0 1.3M UVC WebCam : Applying InputClass "evdev keyboard catchall"
>[    27.839] (**) USB2.0 1.3M UVC WebCam : Applying InputClass "system-setup-keyboard"
>[    27.839] (II) Using input driver 'evdev' for 'USB2.0 1.3M UVC WebCam '
>[    27.839] 	Option "XkbRules" "evdev"
>[    27.839] 	Option "XkbModel" "pc105"
>[    27.839] 	Option "XkbLayout" "de"
>[    27.839] 	Option "_source" "server/udev"
>[    27.839] 	Option "name" "USB2.0 1.3M UVC WebCam "
>[    27.839] 	Option "path" "/dev/input/event7"
>[    27.839] 	Option "device" "/dev/input/event7"
>[    27.839] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.7/usb1/1-2/1-2:1.0/input/input7/event7"
>[    27.839] 	Option "driver" "evdev"
>[    27.839] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.839] (**) USB2.0 1.3M UVC WebCam : always reports core events
>[    27.839] (**) evdev: USB2.0 1.3M UVC WebCam : Device: "/dev/input/event7"
>[    27.839] (--) evdev: USB2.0 1.3M UVC WebCam : Vendor 0x4f2 Product 0xb012
>[    27.839] (--) evdev: USB2.0 1.3M UVC WebCam : Found keys
>[    27.839] (II) evdev: USB2.0 1.3M UVC WebCam : Configuring as keyboard
>[    27.839] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.7/usb1/1-2/1-2:1.0/input/input7/event7"
>[    27.839] (II) XINPUT: Adding extended input device "USB2.0 1.3M UVC WebCam " (type: KEYBOARD, id 9)
>[    27.839] (**) Option "xkb_rules" "evdev"
>[    27.839] (**) Option "xkb_model" "pc105"
>[    27.839] (**) Option "xkb_layout" "de"
>[    27.839] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.839] (II) XKB: Reusing cached keymap
>[    27.840] (II) config/udev: Adding input device HDA Intel Mic (/dev/input/event8)
>[    27.840] (II) No input driver specified, ignoring this device.
>[    27.840] (II) This device may have been added with another device file.
>[    27.840] (II) config/udev: Adding input device HDA Intel Headphone (/dev/input/event9)
>[    27.840] (II) No input driver specified, ignoring this device.
>[    27.840] (II) This device may have been added with another device file.
>[    27.840] (II) config/udev: Adding input device Asus Laptop extra buttons (/dev/input/event6)
>[    27.840] (**) Asus Laptop extra buttons: Applying InputClass "evdev keyboard catchall"
>[    27.840] (**) Asus Laptop extra buttons: Applying InputClass "system-setup-keyboard"
>[    27.840] (II) Using input driver 'evdev' for 'Asus Laptop extra buttons'
>[    27.840] 	Option "XkbRules" "evdev"
>[    27.840] 	Option "XkbModel" "pc105"
>[    27.840] 	Option "XkbLayout" "de"
>[    27.840] 	Option "_source" "server/udev"
>[    27.840] 	Option "name" "Asus Laptop extra buttons"
>[    27.840] 	Option "path" "/dev/input/event6"
>[    27.840] 	Option "device" "/dev/input/event6"
>[    27.840] 	Option "config_info" "udev:/sys/devices/platform/asus_laptop/input/input6/event6"
>[    27.840] 	Option "driver" "evdev"
>[    27.840] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.840] (**) Asus Laptop extra buttons: always reports core events
>[    27.840] (**) evdev: Asus Laptop extra buttons: Device: "/dev/input/event6"
>[    27.840] (--) evdev: Asus Laptop extra buttons: Vendor 0 Product 0
>[    27.840] (--) evdev: Asus Laptop extra buttons: Found keys
>[    27.840] (II) evdev: Asus Laptop extra buttons: Configuring as keyboard
>[    27.840] (**) Option "config_info" "udev:/sys/devices/platform/asus_laptop/input/input6/event6"
>[    27.840] (II) XINPUT: Adding extended input device "Asus Laptop extra buttons" (type: KEYBOARD, id 10)
>[    27.840] (**) Option "xkb_rules" "evdev"
>[    27.840] (**) Option "xkb_model" "pc105"
>[    27.840] (**) Option "xkb_layout" "de"
>[    27.840] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.840] (II) XKB: Reusing cached keymap
>[    27.841] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event3)
>[    27.841] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    27.841] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard"
>[    27.841] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    27.841] 	Option "XkbRules" "evdev"
>[    27.841] 	Option "XkbModel" "pc105"
>[    27.841] 	Option "XkbLayout" "de"
>[    27.841] 	Option "_source" "server/udev"
>[    27.841] 	Option "name" "AT Translated Set 2 keyboard"
>[    27.841] 	Option "path" "/dev/input/event3"
>[    27.841] 	Option "device" "/dev/input/event3"
>[    27.841] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    27.841] 	Option "driver" "evdev"
>[    27.841] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    27.841] (**) AT Translated Set 2 keyboard: always reports core events
>[    27.841] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event3"
>[    27.841] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    27.841] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    27.841] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    27.841] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    27.841] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 11)
>[    27.841] (**) Option "xkb_rules" "evdev"
>[    27.841] (**) Option "xkb_model" "pc105"
>[    27.841] (**) Option "xkb_layout" "de"
>[    27.841] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    27.841] (II) XKB: Reusing cached keymap
>[    27.842] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event4)
>[    27.842] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    27.842] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    27.842] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons"
>[    27.842] (II) LoadModule: "synaptics"
>[    27.842] (II) Loading /usr/lib64/xorg/modules/input/synaptics_drv.so
>[    27.842] (II) Module synaptics: vendor="X.Org Foundation"
>[    27.842] 	compiled for 1.12.0, module version = 1.6.2
>[    27.842] 	Module class: X.Org XInput Driver
>[    27.842] 	ABI class: X.Org XInput driver, version 16.0
>[    27.842] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    27.842] 	Option "_source" "server/udev"
>[    27.842] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    27.842] 	Option "path" "/dev/input/event4"
>[    27.842] 	Option "device" "/dev/input/event4"
>[    27.842] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4"
>[    27.842] 	Option "driver" "synaptics"
>[    27.842] 	Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0"
>[    27.842] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    27.842] (**) Option "Device" "/dev/input/event4"
>[    27.867] (**) Option "Device" "/dev/input/event4"
>[    27.867] port opened successfully
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5472
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4448
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right double triple
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7
>[    27.867] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    27.867] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    27.887] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input4/event4"
>[    27.887] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 12)
>[    27.887] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    27.887] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    27.887] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.040
>[    27.888] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    27.888] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    27.888] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    27.888] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    27.888] (**) Option "Device" "/dev/input/event4"
>[    27.888] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    27.889] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0)
>[    27.889] (II) No input driver specified, ignoring this device.
>[    27.889] (II) This device may have been added with another device file.
>[    27.902] (II) RADEON(0): RADEONSaveScreen(2)
>[    27.922] (II) RADEON(0): EDID vendor "CMO", prod id 5414
>[    27.922] (II) RADEON(0): Printing DDC gathered Modelines:
>[    27.922] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    29.164] (II) RADEON(0): EDID vendor "CMO", prod id 5414
>[    29.164] (II) RADEON(0): Printing DDC gathered Modelines:
>[    29.164] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    31.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e1a0]
>[    31.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e1a0] width 1280 pitch 5120 (/4 1280)
>[    31.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e1a0]
>[    31.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e1a0] width 1280 pitch 5120 (/4 1280)
>[    31.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e1a0]
>[    31.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e1a0] width 1280 pitch 5120 (/4 1280)
>[    31.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e1a0]
>[    31.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e1a0] width 1280 pitch 5120 (/4 1280)
>[    31.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e1a0]
>[    31.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e1a0] width 1280 pitch 5120 (/4 1280)
>[    31.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e320]
>[    31.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e320] width 1280 pitch 5120 (/4 1280)
>[    31.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3d260]
>[    31.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3d260] width 1280 pitch 5120 (/4 1280)
>[    31.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d3e320]
>[    31.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d3e320] width 1280 pitch 5120 (/4 1280)
>[    31.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    31.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    31.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    31.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    31.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40030]
>[    32.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40030] width 1280 pitch 5120 (/4 1280)
>[    32.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40090]
>[    32.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40090] width 1280 pitch 5120 (/4 1280)
>[    32.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    32.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    32.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    32.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    32.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    33.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    33.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    33.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    33.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    33.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    33.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    33.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    33.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f240]
>[    33.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f240] width 1280 pitch 5120 (/4 1280)
>[    33.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d0f1e0]
>[    33.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d0f1e0] width 1280 pitch 5120 (/4 1280)
>[    33.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    33.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    33.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    33.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    33.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    33.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    34.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    34.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    34.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    34.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    34.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    34.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    34.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    34.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    34.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    34.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    34.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    34.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    34.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    34.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    35.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    35.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    35.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    35.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    35.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    35.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    35.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    35.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    35.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    35.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    36.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d40150]
>[    36.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d40150] width 1280 pitch 5120 (/4 1280)
>[    36.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d400f0]
>[    36.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d400f0] width 1280 pitch 5120 (/4 1280)
>[    38.737] (II) RADEON(0): EDID vendor "CMO", prod id 5414
>[    38.737] (II) RADEON(0): Printing DDC gathered Modelines:
>[    38.737] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    40.672] (II) RADEON(0): EDID vendor "CMO", prod id 5414
>[    40.672] (II) RADEON(0): Printing DDC gathered Modelines:
>[    40.672] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    41.014] (II) RADEON(0): EDID vendor "CMO", prod id 5414
>[    41.014] (II) RADEON(0): Printing DDC gathered Modelines:
>[    41.014] (II) RADEON(0): Modeline "1280x800"x0.0   71.00  1280 1328 1360 1440  800 803 809 823 -hsync -vsync (49.3 kHz eP)
>[    56.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351dee0]
>[    56.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351dee0] width 1280 pitch 5120 (/4 1280)
>[    56.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d6e260]
>[    56.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d6e260] width 1280 pitch 5120 (/4 1280)
>[    56.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351dee0]
>[    56.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351dee0] width 1280 pitch 5120 (/4 1280)
>[    56.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d6e260]
>[    56.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d6e260] width 1280 pitch 5120 (/4 1280)
>[    56.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351dee0]
>[    56.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351dee0] width 1280 pitch 5120 (/4 1280)
>[    56.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d6e260]
>[    56.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d6e260] width 1280 pitch 5120 (/4 1280)
>[    56.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351dee0]
>[    56.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351dee0] width 1280 pitch 5120 (/4 1280)
>[    56.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d6e260]
>[    56.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d6e260] width 1280 pitch 5120 (/4 1280)
>[    56.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351dee0]
>[    56.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351dee0] width 1280 pitch 5120 (/4 1280)
>[    56.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d736e0]
>[    56.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d736e0] width 1280 pitch 5120 (/4 1280)
>[    56.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d7cdd0]
>[    56.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d7cdd0] width 1280 pitch 5120 (/4 1280)
>[    57.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d736e0]
>[    57.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d736e0] width 1280 pitch 5120 (/4 1280)
>[    57.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d7cdd0]
>[    57.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d7cdd0] width 1280 pitch 5120 (/4 1280)
>[    57.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d736e0]
>[    57.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d736e0] width 1280 pitch 5120 (/4 1280)
>[    57.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d88520]
>[    57.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d88520] width 1280 pitch 5120 (/4 1280)
>[    58.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d88470]
>[    58.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d88470] width 1280 pitch 5120 (/4 1280)
>[    58.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d88520]
>[    58.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d88520] width 1280 pitch 5120 (/4 1280)
>[    58.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d62f60]
>[    58.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d62f60] width 1280 pitch 5120 (/4 1280)
>[    58.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d62f00]
>[    58.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d62f00] width 1280 pitch 5120 (/4 1280)
>[    58.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d62f60]
>[    58.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d62f60] width 1280 pitch 5120 (/4 1280)
>[    60.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b4b0]
>[    61.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b4b0] width 1280 pitch 5120 (/4 1280)
>[    63.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d62f00]
>[    63.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d62f00] width 1280 pitch 5120 (/4 1280)
>[    63.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d62f00]
>[    63.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d62f00] width 1280 pitch 5120 (/4 1280)
>[    63.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    63.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    63.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    63.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    63.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    63.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    63.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    63.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    63.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    63.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    63.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    63.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    64.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    64.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    64.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    64.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    64.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    64.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b0d0]
>[    64.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b0d0] width 1280 pitch 5120 (/4 1280)
>[    64.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353bbe0]
>[    64.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353bbe0] width 1280 pitch 5120 (/4 1280)
>[    64.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353bbe0]
>[    64.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353bbe0] width 1280 pitch 5120 (/4 1280)
>[    64.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353bbe0]
>[    64.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353bbe0] width 1280 pitch 5120 (/4 1280)
>[    64.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353bbe0]
>[    64.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353bbe0] width 1280 pitch 5120 (/4 1280)
>[    64.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    64.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353bbe0]
>[    64.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353bbe0] width 1280 pitch 5120 (/4 1280)
>[    64.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    64.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    65.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d930]
>[    65.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d930] width 1280 pitch 5120 (/4 1280)
>[    65.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    65.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    65.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    65.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    65.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    65.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    65.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    65.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    65.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    65.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    65.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    65.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    65.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    65.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    65.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    65.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    65.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    65.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353afe0]
>[    65.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353afe0] width 1280 pitch 5120 (/4 1280)
>[    65.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    65.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    66.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d930]
>[    66.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d930] width 1280 pitch 5120 (/4 1280)
>[    66.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    66.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    66.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    66.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    66.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    66.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    66.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    66.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    66.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d65540]
>[    66.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d65540] width 1280 pitch 5120 (/4 1280)
>[    66.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351cf30]
>[    66.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351cf30] width 1280 pitch 5120 (/4 1280)
>[    66.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d930]
>[    66.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d930] width 1280 pitch 5120 (/4 1280)
>[    66.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    66.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    66.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    66.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    66.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d930]
>[    66.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d930] width 1280 pitch 5120 (/4 1280)
>[    66.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351cf30]
>[    66.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351cf30] width 1280 pitch 5120 (/4 1280)
>[    66.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d65540]
>[    66.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d65540] width 1280 pitch 5120 (/4 1280)
>[    66.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    66.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    66.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b3a0]
>[    66.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b3a0] width 1280 pitch 5120 (/4 1280)
>[    66.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d65540]
>[    66.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d65540] width 1280 pitch 5120 (/4 1280)
>[    66.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351cf30]
>[    66.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351cf30] width 1280 pitch 5120 (/4 1280)
>[    67.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x351d9f0]
>[    67.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x351d9f0] width 1280 pitch 5120 (/4 1280)
>[    68.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da0130]
>[    68.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da0130] width 1280 pitch 5120 (/4 1280)
>[    68.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9ffe0]
>[    68.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9ffe0] width 1280 pitch 5120 (/4 1280)
>[    70.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da70e0]
>[    70.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da70e0] width 1280 pitch 5120 (/4 1280)
>[    70.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7140]
>[    70.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7140] width 1280 pitch 5120 (/4 1280)
>[    70.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7090]
>[    70.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7090] width 1280 pitch 5120 (/4 1280)
>[    70.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7190]
>[    70.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7190] width 1280 pitch 5120 (/4 1280)
>[    70.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7290]
>[    70.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7290] width 1280 pitch 5120 (/4 1280)
>[    70.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7190]
>[    70.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7190] width 1280 pitch 5120 (/4 1280)
>[    70.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7040]
>[    71.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7040] width 1280 pitch 5120 (/4 1280)
>[    71.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da70f0]
>[    71.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da70f0] width 1280 pitch 5120 (/4 1280)
>[    71.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7040]
>[    71.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7040] width 1280 pitch 5120 (/4 1280)
>[    71.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6f90]
>[    71.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6f90] width 1280 pitch 5120 (/4 1280)
>[    71.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7040]
>[    71.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7040] width 1280 pitch 5120 (/4 1280)
>[    71.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6f90]
>[    71.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6f90] width 1280 pitch 5120 (/4 1280)
>[    71.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7040]
>[    71.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7040] width 1280 pitch 5120 (/4 1280)
>[    71.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6f90]
>[    71.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6f90] width 1280 pitch 5120 (/4 1280)
>[    71.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7040]
>[    71.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7040] width 1280 pitch 5120 (/4 1280)
>[    71.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6f90]
>[    71.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6f90] width 1280 pitch 5120 (/4 1280)
>[    72.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa260]
>[    72.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa260] width 1280 pitch 5120 (/4 1280)
>[    72.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    72.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    72.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    72.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    72.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    72.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    72.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    72.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    72.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa260]
>[    72.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa260] width 1280 pitch 5120 (/4 1280)
>[    72.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    72.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa260]
>[    72.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa260] width 1280 pitch 5120 (/4 1280)
>[    72.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    72.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    72.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    72.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    72.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    72.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    72.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    72.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    73.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    73.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    73.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    73.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    73.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    73.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    73.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    73.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    73.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa2a0]
>[    73.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa2a0] width 1280 pitch 5120 (/4 1280)
>[    73.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa2a0]
>[    73.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa2a0] width 1280 pitch 5120 (/4 1280)
>[    73.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da6fe0]
>[    73.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da6fe0] width 1280 pitch 5120 (/4 1280)
>[    73.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa120]
>[    73.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa120] width 1280 pitch 5120 (/4 1280)
>[    74.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da71c0]
>[    74.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da71c0] width 1280 pitch 5120 (/4 1280)
>[    74.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da87e0]
>[    74.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da87e0] width 1280 pitch 5120 (/4 1280)
>[    74.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa960]
>[    74.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa960] width 1280 pitch 5120 (/4 1280)
>[    74.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da87e0]
>[    74.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da87e0] width 1280 pitch 5120 (/4 1280)
>[    74.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa960]
>[    74.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa960] width 1280 pitch 5120 (/4 1280)
>[    74.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da7ef0]
>[    74.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da7ef0] width 1280 pitch 5120 (/4 1280)
>[    74.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2daa960]
>[    74.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2daa960] width 1280 pitch 5120 (/4 1280)
>[    75.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab670]
>[    75.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab670] width 1280 pitch 5120 (/4 1280)
>[    75.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab610]
>[    75.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab610] width 1280 pitch 5120 (/4 1280)
>[    75.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab670]
>[    75.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab670] width 1280 pitch 5120 (/4 1280)
>[    75.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacd00]
>[    75.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacd00] width 1280 pitch 5120 (/4 1280)
>[    75.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab670]
>[    75.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab670] width 1280 pitch 5120 (/4 1280)
>[    75.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacd00]
>[    75.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacd00] width 1280 pitch 5120 (/4 1280)
>[    75.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab670]
>[    75.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab670] width 1280 pitch 5120 (/4 1280)
>[    75.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dacd00]
>[    75.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dacd00] width 1280 pitch 5120 (/4 1280)
>[    75.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2dab670]
>[    75.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2dab670] width 1280 pitch 5120 (/4 1280)
>[    76.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a10]
>[    76.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a10] width 1280 pitch 5120 (/4 1280)
>[    76.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec19b0]
>[    76.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec19b0] width 1280 pitch 5120 (/4 1280)
>[    76.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a10]
>[    76.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a10] width 1280 pitch 5120 (/4 1280)
>[    76.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a70]
>[    76.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a70] width 1280 pitch 5120 (/4 1280)
>[    76.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a10]
>[    76.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a10] width 1280 pitch 5120 (/4 1280)
>[    76.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a70]
>[    76.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a70] width 1280 pitch 5120 (/4 1280)
>[    76.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3c30]
>[    76.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3c30] width 1280 pitch 5120 (/4 1280)
>[    76.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec1a70]
>[    76.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec1a70] width 1280 pitch 5120 (/4 1280)
>[    76.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3c30]
>[    76.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3c30] width 1280 pitch 5120 (/4 1280)
>[    76.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3bd0]
>[    76.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3bd0] width 1280 pitch 5120 (/4 1280)
>[    76.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3c30]
>[    76.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3c30] width 1280 pitch 5120 (/4 1280)
>[    76.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3bd0]
>[    76.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3bd0] width 1280 pitch 5120 (/4 1280)
>[    76.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3c30]
>[    76.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3c30] width 1280 pitch 5120 (/4 1280)
>[    76.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3bd0]
>[    76.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3bd0] width 1280 pitch 5120 (/4 1280)
>[    76.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3c30]
>[    76.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3c30] width 1280 pitch 5120 (/4 1280)
>[    76.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e36b30]
>[    77.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e36b30] width 1280 pitch 5120 (/4 1280)
>[    77.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e36b30]
>[    77.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e36b30] width 1280 pitch 5120 (/4 1280)
>[    77.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecafa0]
>[    77.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecafa0] width 1280 pitch 5120 (/4 1280)
>[    77.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30f7bb0]
>[    77.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30f7bb0] width 1280 pitch 5120 (/4 1280)
>[    77.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed76d0]
>[    77.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed76d0] width 1280 pitch 5120 (/4 1280)
>[    77.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2da1210]
>[    77.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2da1210] width 1280 pitch 5120 (/4 1280)
>[    78.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f141e0]
>[    78.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f141e0] width 1280 pitch 5120 (/4 1280)
>[    78.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0f580]
>[    78.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0f580] width 1280 pitch 5120 (/4 1280)
>[    81.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b320]
>[    81.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b320] width 1280 pitch 5120 (/4 1280)
>[    81.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37806f0]
>[    81.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37806f0] width 1280 pitch 5120 (/4 1280)
>[    81.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b5c0]
>[    81.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b5c0] width 1280 pitch 5120 (/4 1280)
>[    81.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3776d90]
>[    81.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3776d90] width 1280 pitch 5120 (/4 1280)
>[    81.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b5c0]
>[    81.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b5c0] width 1280 pitch 5120 (/4 1280)
>[    81.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3776d90]
>[    81.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3776d90] width 1280 pitch 5120 (/4 1280)
>[    81.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b5c0]
>[    81.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b5c0] width 1280 pitch 5120 (/4 1280)
>[    81.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3776d90]
>[    82.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3776d90] width 1280 pitch 5120 (/4 1280)
>[    82.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353b320]
>[    82.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353b320] width 1280 pitch 5120 (/4 1280)
>[    82.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3776d90]
>[    82.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3776d90] width 1280 pitch 5120 (/4 1280)
>[    82.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d91000]
>[    82.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d91000] width 1280 pitch 5120 (/4 1280)
>[    82.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3776d90]
>[    82.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3776d90] width 1280 pitch 5120 (/4 1280)
>[    83.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f7e0]
>[    83.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f7e0] width 1280 pitch 5120 (/4 1280)
>[    86.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f3af90]
>[    86.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f3af90] width 1280 pitch 5120 (/4 1280)
>[    87.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc63a0]
>[    87.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc63a0] width 1280 pitch 5120 (/4 1280)
>[    87.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ba290]
>[    87.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ba290] width 1280 pitch 5120 (/4 1280)
>[    87.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353f190]
>[    87.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353f190] width 1280 pitch 5120 (/4 1280)
>[    87.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    87.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    87.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    87.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    87.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    87.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    87.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37c3b60]
>[    87.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37c3b60] width 1280 pitch 5120 (/4 1280)
>[    87.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bb0b0]
>[    87.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bb0b0] width 1280 pitch 5120 (/4 1280)
>[    87.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37c3b60]
>[    87.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37c3b60] width 1280 pitch 5120 (/4 1280)
>[    87.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    87.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    87.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bb0b0]
>[    87.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bb0b0] width 1280 pitch 5120 (/4 1280)
>[    87.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bb0b0]
>[    87.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bb0b0] width 1280 pitch 5120 (/4 1280)
>[    87.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bb0b0]
>[    87.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bb0b0] width 1280 pitch 5120 (/4 1280)
>[    87.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    87.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    88.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f7e0]
>[    88.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f7e0] width 1280 pitch 5120 (/4 1280)
>[    88.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b2290]
>[    88.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b2290] width 1280 pitch 5120 (/4 1280)
>[    88.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    88.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    88.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cf680]
>[    88.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cf680] width 1280 pitch 5120 (/4 1280)
>[    88.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    88.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    88.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cf680]
>[    89.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cf680] width 1280 pitch 5120 (/4 1280)
>[    89.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f5a0]
>[    89.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f5a0] width 1280 pitch 5120 (/4 1280)
>[    89.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    89.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    89.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f5a0]
>[    89.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f5a0] width 1280 pitch 5120 (/4 1280)
>[    89.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    89.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    89.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f5a0]
>[    89.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f5a0] width 1280 pitch 5120 (/4 1280)
>[    89.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    89.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    89.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cf680]
>[    89.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cf680] width 1280 pitch 5120 (/4 1280)
>[    89.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d3d90]
>[    89.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d3d90] width 1280 pitch 5120 (/4 1280)
>[    91.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bf130]
>[    91.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bf130] width 1280 pitch 5120 (/4 1280)
>[    91.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3854bd0]
>[    91.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3854bd0] width 1280 pitch 5120 (/4 1280)
>[    91.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    91.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    91.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3854bd0]
>[    91.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3854bd0] width 1280 pitch 5120 (/4 1280)
>[    91.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3854bd0]
>[    91.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3854bd0] width 1280 pitch 5120 (/4 1280)
>[    91.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    91.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    92.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    92.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    92.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f0b0]
>[    92.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f0b0] width 1280 pitch 5120 (/4 1280)
>[    92.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1cb20]
>[    92.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1cb20] width 1280 pitch 5120 (/4 1280)
>[    92.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3854bd0]
>[    92.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3854bd0] width 1280 pitch 5120 (/4 1280)
>[    92.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377f0b0]
>[    92.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377f0b0] width 1280 pitch 5120 (/4 1280)
>[    92.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3854bd0]
>[    92.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3854bd0] width 1280 pitch 5120 (/4 1280)
>[    92.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cf680]
>[    92.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cf680] width 1280 pitch 5120 (/4 1280)
>[    94.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cca30]
>[    94.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cca30] width 1280 pitch 5120 (/4 1280)
>[    94.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dc80]
>[    94.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dc80] width 1280 pitch 5120 (/4 1280)
>[    94.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dff0]
>[    94.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dff0] width 1280 pitch 5120 (/4 1280)
>[    94.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37c8de0]
>[    94.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37c8de0] width 1280 pitch 5120 (/4 1280)
>[    94.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dff0]
>[    94.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dff0] width 1280 pitch 5120 (/4 1280)
>[    94.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385d9f0]
>[    94.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385d9f0] width 1280 pitch 5120 (/4 1280)
>[    94.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dff0]
>[    94.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dff0] width 1280 pitch 5120 (/4 1280)
>[    94.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385d9f0]
>[    94.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385d9f0] width 1280 pitch 5120 (/4 1280)
>[    94.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dff0]
>[    94.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dff0] width 1280 pitch 5120 (/4 1280)
>[    94.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385d9f0]
>[    94.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385d9f0] width 1280 pitch 5120 (/4 1280)
>[    94.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385dff0]
>[    94.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385dff0] width 1280 pitch 5120 (/4 1280)
>[    94.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37cca30]
>[    94.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37cca30] width 1280 pitch 5120 (/4 1280)
>[    94.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37afb40]
>[    94.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37afb40] width 1280 pitch 5120 (/4 1280)
>[    94.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d39b0]
>[    94.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d39b0] width 1280 pitch 5120 (/4 1280)
>[    98.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385d070]
>[    98.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385d070] width 1280 pitch 5120 (/4 1280)
>[    98.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385d070]
>[    98.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385d070] width 1280 pitch 5120 (/4 1280)
>[    98.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bba90]
>[    98.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bba90] width 1280 pitch 5120 (/4 1280)
>[    98.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bba90]
>[    98.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bba90] width 1280 pitch 5120 (/4 1280)
>[    98.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bba90]
>[    98.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bba90] width 1280 pitch 5120 (/4 1280)
>[    98.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bba90]
>[    98.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bba90] width 1280 pitch 5120 (/4 1280)
>[    98.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bbaf0]
>[    98.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bbaf0] width 1280 pitch 5120 (/4 1280)
>[    98.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bba90]
>[    98.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bba90] width 1280 pitch 5120 (/4 1280)
>[    99.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[    99.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[    99.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[    99.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[    99.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[    99.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[    99.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[    99.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[    99.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[    99.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[    99.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[    99.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[    99.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[   100.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[   100.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[   100.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[   100.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[   100.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[   100.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[   100.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[   100.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[   100.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[   100.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[   100.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[   100.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3787690]
>[   100.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3787690] width 1280 pitch 5120 (/4 1280)
>[   100.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3786020]
>[   100.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3786020] width 1280 pitch 5120 (/4 1280)
>[   121.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   121.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   121.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   121.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   121.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   121.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   121.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   121.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   121.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   121.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   121.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   121.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   121.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   121.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   121.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   121.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   121.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   121.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   122.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   122.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   122.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   122.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   122.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   122.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   122.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   122.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   122.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   122.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   122.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   122.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   122.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   122.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   122.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   122.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   122.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386a6a0]
>[   122.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386a6a0] width 1280 pitch 5120 (/4 1280)
>[   122.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2d9c350]
>[   122.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2d9c350] width 1280 pitch 5120 (/4 1280)
>[   160.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   160.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   160.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   160.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   160.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   160.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   160.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   160.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   160.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   160.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   160.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   160.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   160.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   160.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   160.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   160.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   160.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   160.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   161.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   161.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   161.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   161.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   161.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   161.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   161.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   161.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   161.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   161.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   161.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   161.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   162.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   162.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   162.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   162.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   162.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   162.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   162.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   162.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   162.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   162.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   162.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   162.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   162.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   162.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   162.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcb9e0]
>[   162.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcb9e0] width 1280 pitch 5120 (/4 1280)
>[   162.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc88a0]
>[   162.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc88a0] width 1280 pitch 5120 (/4 1280)
>[   167.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efe6c0]
>[   167.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efe6c0] width 1280 pitch 5120 (/4 1280)
>[   187.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d81f0]
>[   187.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d81f0] width 1280 pitch 5120 (/4 1280)
>[   190.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9d00]
>[   190.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9d00] width 1280 pitch 5120 (/4 1280)
>[   191.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6d0]
>[   191.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6d0] width 1280 pitch 5120 (/4 1280)
>[   191.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[   191.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[   197.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   198.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   198.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   198.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   198.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   198.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   198.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   198.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   198.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   198.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   198.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   198.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   198.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   198.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   198.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   198.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   199.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   199.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   199.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   199.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   199.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e90040]
>[   199.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e90040] width 1280 pitch 5120 (/4 1280)
>[   200.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37728c0]
>[   200.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37728c0] width 1280 pitch 5120 (/4 1280)
>[   200.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f00f20]
>[   200.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f00f20] width 1280 pitch 5120 (/4 1280)
>[   200.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9770]
>[   200.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9770] width 1280 pitch 5120 (/4 1280)
>[   200.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f01d70]
>[   200.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f01d70] width 1280 pitch 5120 (/4 1280)
>[   200.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9770]
>[   200.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9770] width 1280 pitch 5120 (/4 1280)
>[   200.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f01d70]
>[   200.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f01d70] width 1280 pitch 5120 (/4 1280)
>[   200.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9770]
>[   200.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9770] width 1280 pitch 5120 (/4 1280)
>[   211.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f03390]
>[   211.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f03390] width 1280 pitch 5120 (/4 1280)
>[   211.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6db30]
>[   211.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6db30] width 1280 pitch 5120 (/4 1280)
>[   211.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6f790]
>[   211.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6f790] width 1280 pitch 5120 (/4 1280)
>[   211.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6db30]
>[   212.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6db30] width 1280 pitch 5120 (/4 1280)
>[   212.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6f790]
>[   212.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6f790] width 1280 pitch 5120 (/4 1280)
>[   212.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6db30]
>[   212.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6db30] width 1280 pitch 5120 (/4 1280)
>[   212.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772750]
>[   212.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772750] width 1280 pitch 5120 (/4 1280)
>[   212.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc23a0]
>[   212.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc23a0] width 1280 pitch 5120 (/4 1280)
>[   212.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc23a0]
>[   212.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc23a0] width 1280 pitch 5120 (/4 1280)
>[   212.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6dc50]
>[   212.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6dc50] width 1280 pitch 5120 (/4 1280)
>[   212.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc23a0]
>[   212.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc23a0] width 1280 pitch 5120 (/4 1280)
>[   212.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6dc50]
>[   212.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6dc50] width 1280 pitch 5120 (/4 1280)
>[   212.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc23a0]
>[   212.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc23a0] width 1280 pitch 5120 (/4 1280)
>[   212.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353f240]
>[   212.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353f240] width 1280 pitch 5120 (/4 1280)
>[   213.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc23a0]
>[   213.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc23a0] width 1280 pitch 5120 (/4 1280)
>[   237.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f799f0]
>[   237.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f799f0] width 1280 pitch 5120 (/4 1280)
>[   238.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6d440]
>[   238.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6d440] width 1280 pitch 5120 (/4 1280)
>[   238.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea350]
>[   238.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea350] width 1280 pitch 5120 (/4 1280)
>[   238.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   238.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   238.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   238.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   238.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   238.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   238.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   238.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   239.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   239.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   239.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   239.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   239.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   239.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   239.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   239.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   239.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   239.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   239.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   239.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   240.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   240.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   240.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   240.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   240.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   240.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   240.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   240.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   240.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   240.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   241.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   241.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   241.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79710]
>[   241.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79710] width 1280 pitch 5120 (/4 1280)
>[   241.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   241.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   241.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7e50]
>[   241.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7e50] width 1280 pitch 5120 (/4 1280)
>[   241.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7300]
>[   241.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7300] width 1280 pitch 5120 (/4 1280)
>[   241.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ef70]
>[   241.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ef70] width 1280 pitch 5120 (/4 1280)
>[   241.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982d60]
>[   241.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982d60] width 1280 pitch 5120 (/4 1280)
>[   241.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38148a0]
>[   241.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38148a0] width 1280 pitch 5120 (/4 1280)
>[   242.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7e50]
>[   242.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7e50] width 1280 pitch 5120 (/4 1280)
>[   242.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38148a0]
>[   242.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38148a0] width 1280 pitch 5120 (/4 1280)
>[   242.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7e50]
>[   242.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7e50] width 1280 pitch 5120 (/4 1280)
>[   242.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38148a0]
>[   242.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38148a0] width 1280 pitch 5120 (/4 1280)
>[   242.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7e50]
>[   242.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7e50] width 1280 pitch 5120 (/4 1280)
>[   242.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38148a0]
>[   242.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38148a0] width 1280 pitch 5120 (/4 1280)
>[   242.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7e50]
>[   242.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7e50] width 1280 pitch 5120 (/4 1280)
>[   259.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa97b0]
>[   259.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa97b0] width 1280 pitch 5120 (/4 1280)
>[   278.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37b9770]
>[   278.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37b9770] width 1280 pitch 5120 (/4 1280)
>[   300.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   300.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   300.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   300.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   300.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   300.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   300.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   300.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   300.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   300.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   300.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x382ce40]
>[   301.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x382ce40] width 1280 pitch 5120 (/4 1280)
>[   301.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f48a50]
>[   301.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f48a50] width 1280 pitch 5120 (/4 1280)
>[   301.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3836df0]
>[   302.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3836df0] width 1280 pitch 5120 (/4 1280)
>[   302.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3836df0]
>[   302.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3836df0] width 1280 pitch 5120 (/4 1280)
>[   588.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   588.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   589.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97580]
>[   589.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97580] width 1280 pitch 5120 (/4 1280)
>[   589.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   589.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   589.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97580]
>[   589.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97580] width 1280 pitch 5120 (/4 1280)
>[   589.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fea60]
>[   589.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fea60] width 1280 pitch 5120 (/4 1280)
>[   590.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   590.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   591.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4620]
>[   591.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4620] width 1280 pitch 5120 (/4 1280)
>[   591.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392bca0]
>[   591.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392bca0] width 1280 pitch 5120 (/4 1280)
>[   592.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3974f00]
>[   592.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3974f00] width 1280 pitch 5120 (/4 1280)
>[   594.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   594.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   594.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939570]
>[   594.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939570] width 1280 pitch 5120 (/4 1280)
>[   594.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   594.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   594.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b340]
>[   594.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b340] width 1280 pitch 5120 (/4 1280)
>[   595.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939570]
>[   595.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939570] width 1280 pitch 5120 (/4 1280)
>[   595.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   595.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   595.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939570]
>[   595.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939570] width 1280 pitch 5120 (/4 1280)
>[   595.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   595.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   595.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2630]
>[   595.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2630] width 1280 pitch 5120 (/4 1280)
>[   595.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb030]
>[   595.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb030] width 1280 pitch 5120 (/4 1280)
>[   595.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2630]
>[   595.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2630] width 1280 pitch 5120 (/4 1280)
>[   595.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb030]
>[   595.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb030] width 1280 pitch 5120 (/4 1280)
>[   595.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2630]
>[   595.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2630] width 1280 pitch 5120 (/4 1280)
>[   596.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb030]
>[   596.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb030] width 1280 pitch 5120 (/4 1280)
>[   596.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2630]
>[   596.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2630] width 1280 pitch 5120 (/4 1280)
>[   596.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bb030]
>[   596.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bb030] width 1280 pitch 5120 (/4 1280)
>[   596.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2630]
>[   596.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2630] width 1280 pitch 5120 (/4 1280)
>[   596.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   596.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   596.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39109d0]
>[   596.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39109d0] width 1280 pitch 5120 (/4 1280)
>[   596.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   596.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   596.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39109d0]
>[   596.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39109d0] width 1280 pitch 5120 (/4 1280)
>[   596.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   596.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   596.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39109d0]
>[   596.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39109d0] width 1280 pitch 5120 (/4 1280)
>[   596.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   596.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   599.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   599.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   600.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed610]
>[   600.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed610] width 1280 pitch 5120 (/4 1280)
>[   618.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353cae0]
>[   618.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353cae0] width 1280 pitch 5120 (/4 1280)
>[   619.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   619.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   619.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   619.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   619.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   619.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   619.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   619.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   619.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   619.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   619.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   619.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   620.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   620.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   620.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   620.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   620.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   620.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   620.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   621.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   621.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   621.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   621.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   621.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   621.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   621.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   621.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   622.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   622.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   622.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   622.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   622.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   622.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   622.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   622.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   622.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   622.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   622.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   622.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   622.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   622.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   622.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   628.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   628.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   628.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   628.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   629.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   629.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   629.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   629.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   629.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   629.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   629.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   629.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   629.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   629.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   629.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   629.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   630.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   630.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   630.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   630.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   630.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   630.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   630.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   630.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   630.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   630.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   630.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   630.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   630.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   630.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   630.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   630.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   630.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   630.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   633.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   633.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   633.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   633.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   633.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   633.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   633.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   633.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   634.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   634.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   634.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   634.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   634.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   634.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   634.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   634.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   634.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   634.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   634.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   634.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   635.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39582c0]
>[   635.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39582c0] width 1280 pitch 5120 (/4 1280)
>[   635.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   635.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   635.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e03c0]
>[   635.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e03c0] width 1280 pitch 5120 (/4 1280)
>[   635.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   635.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   635.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e03c0]
>[   635.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e03c0] width 1280 pitch 5120 (/4 1280)
>[   635.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30be0]
>[   635.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30be0] width 1280 pitch 5120 (/4 1280)
>[   635.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e03c0]
>[   635.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e03c0] width 1280 pitch 5120 (/4 1280)
>[   665.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   665.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   676.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   676.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   677.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   677.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   677.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   677.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   677.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   677.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   677.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   677.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   677.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   677.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   677.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   677.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   677.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   678.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   678.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   678.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   678.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3955d60]
>[   678.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3955d60] width 1280 pitch 5120 (/4 1280)
>[   678.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4b80]
>[   678.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4b80] width 1280 pitch 5120 (/4 1280)
>[   678.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ff7d0]
>[   678.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ff7d0] width 1280 pitch 5120 (/4 1280)
>[   678.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8fce0]
>[   678.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8fce0] width 1280 pitch 5120 (/4 1280)
>[   678.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f8e50]
>[   678.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f8e50] width 1280 pitch 5120 (/4 1280)
>[   678.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39800b0]
>[   678.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39800b0] width 1280 pitch 5120 (/4 1280)
>[   678.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f8e50]
>[   678.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f8e50] width 1280 pitch 5120 (/4 1280)
>[   678.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ff7d0]
>[   678.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ff7d0] width 1280 pitch 5120 (/4 1280)
>[   680.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397c090]
>[   680.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397c090] width 1280 pitch 5120 (/4 1280)
>[   680.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3948110]
>[   680.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3948110] width 1280 pitch 5120 (/4 1280)
>[   680.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397c4f0]
>[   680.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397c4f0] width 1280 pitch 5120 (/4 1280)
>[   680.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f240]
>[   680.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f240] width 1280 pitch 5120 (/4 1280)
>[   680.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee9940]
>[   680.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee9940] width 1280 pitch 5120 (/4 1280)
>[   680.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f240]
>[   680.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f240] width 1280 pitch 5120 (/4 1280)
>[   680.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee76b0]
>[   680.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee76b0] width 1280 pitch 5120 (/4 1280)
>[   682.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393bdb0]
>[   682.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393bdb0] width 1280 pitch 5120 (/4 1280)
>[   682.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e300]
>[   682.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e300] width 1280 pitch 5120 (/4 1280)
>[   682.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e360]
>[   682.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e360] width 1280 pitch 5120 (/4 1280)
>[   682.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e300]
>[   682.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e300] width 1280 pitch 5120 (/4 1280)
>[   682.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e360]
>[   682.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e360] width 1280 pitch 5120 (/4 1280)
>[   682.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e300]
>[   682.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e300] width 1280 pitch 5120 (/4 1280)
>[   682.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e360]
>[   682.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e360] width 1280 pitch 5120 (/4 1280)
>[   682.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e300]
>[   682.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e300] width 1280 pitch 5120 (/4 1280)
>[   682.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e360]
>[   682.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e360] width 1280 pitch 5120 (/4 1280)
>[   682.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e300]
>[   682.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e300] width 1280 pitch 5120 (/4 1280)
>[   682.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39793f0]
>[   682.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39793f0] width 1280 pitch 5120 (/4 1280)
>[   687.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978350]
>[   687.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978350] width 1280 pitch 5120 (/4 1280)
>[   687.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397adc0]
>[   687.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397adc0] width 1280 pitch 5120 (/4 1280)
>[   690.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8c510]
>[   690.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8c510] width 1280 pitch 5120 (/4 1280)
>[   690.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee9090]
>[   690.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee9090] width 1280 pitch 5120 (/4 1280)
>[   690.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee9090]
>[   690.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee9090] width 1280 pitch 5120 (/4 1280)
>[   690.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3947f30]
>[   690.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3947f30] width 1280 pitch 5120 (/4 1280)
>[   690.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b74bc0]
>[   690.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b74bc0] width 1280 pitch 5120 (/4 1280)
>[   690.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3947f30]
>[   690.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3947f30] width 1280 pitch 5120 (/4 1280)
>[   690.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b74bc0]
>[   690.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b74bc0] width 1280 pitch 5120 (/4 1280)
>[   690.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3947f30]
>[   690.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3947f30] width 1280 pitch 5120 (/4 1280)
>[   690.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b74bc0]
>[   690.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b74bc0] width 1280 pitch 5120 (/4 1280)
>[   690.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee9090]
>[   690.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee9090] width 1280 pitch 5120 (/4 1280)
>[   690.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39777a0]
>[   690.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39777a0] width 1280 pitch 5120 (/4 1280)
>[   690.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   690.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   690.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   690.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   690.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   691.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   691.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   691.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   691.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   691.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   691.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   691.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   691.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   691.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   691.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   691.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   691.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   691.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   691.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   691.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   691.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   692.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   692.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   692.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   692.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   692.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   692.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   692.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f5b40]
>[   692.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f5b40] width 1280 pitch 5120 (/4 1280)
>[   692.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   692.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   692.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f5b40]
>[   692.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f5b40] width 1280 pitch 5120 (/4 1280)
>[   692.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   692.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   692.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d020]
>[   692.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d020] width 1280 pitch 5120 (/4 1280)
>[   692.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3973fb0]
>[   692.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3973fb0] width 1280 pitch 5120 (/4 1280)
>[   693.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b520]
>[   693.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b520] width 1280 pitch 5120 (/4 1280)
>[   694.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39659c0]
>[   694.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39659c0] width 1280 pitch 5120 (/4 1280)
>[   695.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3962120]
>[   695.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3962120] width 1280 pitch 5120 (/4 1280)
>[   695.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8bc00]
>[   695.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8bc00] width 1280 pitch 5120 (/4 1280)
>[   695.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8b990]
>[   695.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8b990] width 1280 pitch 5120 (/4 1280)
>[   695.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8baa0]
>[   695.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8baa0] width 1280 pitch 5120 (/4 1280)
>[   695.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8baa0]
>[   695.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8baa0] width 1280 pitch 5120 (/4 1280)
>[   695.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08f00]
>[   695.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08f00] width 1280 pitch 5120 (/4 1280)
>[   695.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963ef0]
>[   695.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963ef0] width 1280 pitch 5120 (/4 1280)
>[   695.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963e90]
>[   695.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963e90] width 1280 pitch 5120 (/4 1280)
>[   695.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963ef0]
>[   695.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963ef0] width 1280 pitch 5120 (/4 1280)
>[   695.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963e90]
>[   695.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963e90] width 1280 pitch 5120 (/4 1280)
>[   695.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963ef0]
>[   695.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963ef0] width 1280 pitch 5120 (/4 1280)
>[   696.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963e90]
>[   696.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963e90] width 1280 pitch 5120 (/4 1280)
>[   696.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963ef0]
>[   696.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963ef0] width 1280 pitch 5120 (/4 1280)
>[   696.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8b990]
>[   696.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8b990] width 1280 pitch 5120 (/4 1280)
>[   696.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963ef0]
>[   696.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963ef0] width 1280 pitch 5120 (/4 1280)
>[   696.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d0fb0]
>[   696.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d0fb0] width 1280 pitch 5120 (/4 1280)
>[   696.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8b990]
>[   696.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8b990] width 1280 pitch 5120 (/4 1280)
>[   696.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eed50]
>[   696.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eed50] width 1280 pitch 5120 (/4 1280)
>[   696.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8b990]
>[   696.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8b990] width 1280 pitch 5120 (/4 1280)
>[   696.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eed50]
>[   696.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eed50] width 1280 pitch 5120 (/4 1280)
>[   696.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8b990]
>[   696.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8b990] width 1280 pitch 5120 (/4 1280)
>[   696.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eed50]
>[   696.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eed50] width 1280 pitch 5120 (/4 1280)
>[   703.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d0fb0]
>[   703.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d0fb0] width 1280 pitch 5120 (/4 1280)
>[   709.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   709.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff3a0]
>[   709.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff3a0] width 1280 pitch 5120 (/4 1280)
>[   709.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff5a0]
>[   709.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff5a0] width 1280 pitch 5120 (/4 1280)
>[   710.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eb10]
>[   710.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eb10] width 1280 pitch 5120 (/4 1280)
>[   710.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eb10]
>[   710.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eb10] width 1280 pitch 5120 (/4 1280)
>[   710.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376d3e0]
>[   710.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376d3e0] width 1280 pitch 5120 (/4 1280)
>[   710.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376d3e0]
>[   710.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376d3e0] width 1280 pitch 5120 (/4 1280)
>[   710.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376d3e0]
>[   710.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376d3e0] width 1280 pitch 5120 (/4 1280)
>[   710.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376d3e0]
>[   710.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376d3e0] width 1280 pitch 5120 (/4 1280)
>[   710.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376eab0]
>[   710.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376eab0] width 1280 pitch 5120 (/4 1280)
>[   710.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376d3e0]
>[   710.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376d3e0] width 1280 pitch 5120 (/4 1280)
>[   724.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a5d0]
>[   724.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a5d0] width 1280 pitch 5120 (/4 1280)
>[   733.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   733.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   733.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   733.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   733.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   734.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   734.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   734.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   734.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376a1a0]
>[   734.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376a1a0] width 1280 pitch 5120 (/4 1280)
>[   734.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   734.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   734.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   734.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   734.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   734.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   734.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   734.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   734.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   735.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   735.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   735.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   735.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   735.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   735.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   735.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   735.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   735.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   735.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   735.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   735.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   735.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   735.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   735.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   735.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa53c0]
>[   735.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa53c0] width 1280 pitch 5120 (/4 1280)
>[   735.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385cec0]
>[   735.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385cec0] width 1280 pitch 5120 (/4 1280)
>[   742.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8ba00]
>[   742.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8ba00] width 1280 pitch 5120 (/4 1280)
>[   742.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   743.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   743.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8ba00]
>[   743.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8ba00] width 1280 pitch 5120 (/4 1280)
>[   743.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   743.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   743.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8ba00]
>[   743.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8ba00] width 1280 pitch 5120 (/4 1280)
>[   743.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   743.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   743.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f8ba00]
>[   743.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f8ba00] width 1280 pitch 5120 (/4 1280)
>[   743.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   743.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   744.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08fc0]
>[   744.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08fc0] width 1280 pitch 5120 (/4 1280)
>[   744.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   744.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   744.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   744.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   744.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   744.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   744.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   744.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   744.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   744.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   744.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   744.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   746.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   746.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   757.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x376dee0]
>[   757.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x376dee0] width 1280 pitch 5120 (/4 1280)
>[   757.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   757.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   757.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa80b0]
>[   757.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa80b0] width 1280 pitch 5120 (/4 1280)
>[   757.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fa4500]
>[   758.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fa4500] width 1280 pitch 5120 (/4 1280)
>[   758.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   758.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   758.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   758.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   758.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   872.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08fc0]
>[   872.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08fc0] width 1280 pitch 5120 (/4 1280)
>[   872.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   872.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   872.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31113c0]
>[   872.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31113c0] width 1280 pitch 5120 (/4 1280)
>[   872.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921b50]
>[   873.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921b50] width 1280 pitch 5120 (/4 1280)
>[   873.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772af0]
>[   873.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772af0] width 1280 pitch 5120 (/4 1280)
>[   873.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   873.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   873.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   898.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31180f0]
>[   898.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31180f0] width 1280 pitch 5120 (/4 1280)
>[   902.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[   902.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[   903.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   903.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   904.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   904.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   904.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   904.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   904.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   904.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   904.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   904.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   904.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   904.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   905.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   905.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   905.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   905.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   905.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   905.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   905.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   905.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   906.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   906.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   906.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   906.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   906.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   906.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   906.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   906.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   906.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39235b0]
>[   906.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39235b0] width 1280 pitch 5120 (/4 1280)
>[   906.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdced0]
>[   906.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdced0] width 1280 pitch 5120 (/4 1280)
>[   909.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f78050]
>[   909.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f78050] width 1280 pitch 5120 (/4 1280)
>[   912.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f7b310]
>[   912.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f7b310] width 1280 pitch 5120 (/4 1280)
>[   912.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   912.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   912.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f7b310]
>[   912.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f7b310] width 1280 pitch 5120 (/4 1280)
>[   912.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   912.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   912.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ef320]
>[   912.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ef320] width 1280 pitch 5120 (/4 1280)
>[   913.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   913.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   913.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ef320]
>[   913.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ef320] width 1280 pitch 5120 (/4 1280)
>[   913.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   913.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   913.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ef320]
>[   913.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ef320] width 1280 pitch 5120 (/4 1280)
>[   913.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   913.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   913.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ef320]
>[   913.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ef320] width 1280 pitch 5120 (/4 1280)
>[   913.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   913.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   913.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97770]
>[   913.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97770] width 1280 pitch 5120 (/4 1280)
>[   915.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31202a0]
>[   915.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31202a0] width 1280 pitch 5120 (/4 1280)
>[   915.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f88d90]
>[   915.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f88d90] width 1280 pitch 5120 (/4 1280)
>[   915.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce0410]
>[   915.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce0410] width 1280 pitch 5120 (/4 1280)
>[   915.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f88d90]
>[   915.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f88d90] width 1280 pitch 5120 (/4 1280)
>[   915.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ecea0]
>[   915.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ecea0] width 1280 pitch 5120 (/4 1280)
>[   915.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfc290]
>[   915.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfc290] width 1280 pitch 5120 (/4 1280)
>[   916.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   916.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   919.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   919.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   919.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   919.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90920]
>[   919.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90920] width 1280 pitch 5120 (/4 1280)
>[   920.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a4f0]
>[   920.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a4f0] width 1280 pitch 5120 (/4 1280)
>[   920.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3772110]
>[   921.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3772110] width 1280 pitch 5120 (/4 1280)
>[   921.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a4f0]
>[   921.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a4f0] width 1280 pitch 5120 (/4 1280)
>[   921.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a4f0]
>[   921.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a4f0] width 1280 pitch 5120 (/4 1280)
>[   921.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a4f0]
>[   921.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a4f0] width 1280 pitch 5120 (/4 1280)
>[   921.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a4f0]
>[   921.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a4f0] width 1280 pitch 5120 (/4 1280)
>[   921.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   921.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   921.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76420]
>[   921.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76420] width 1280 pitch 5120 (/4 1280)
>[   921.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf4d0]
>[   921.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf4d0] width 1280 pitch 5120 (/4 1280)
>[   921.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2510]
>[   921.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2510] width 1280 pitch 5120 (/4 1280)
>[   923.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3705060]
>[   923.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3705060] width 1280 pitch 5120 (/4 1280)
>[   923.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37019a0]
>[   923.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37019a0] width 1280 pitch 5120 (/4 1280)
>[   923.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf3b0]
>[   923.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf3b0] width 1280 pitch 5120 (/4 1280)
>[   927.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3702130]
>[   927.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3702130] width 1280 pitch 5120 (/4 1280)
>[   927.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f50]
>[   927.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f50] width 1280 pitch 5120 (/4 1280)
>[   927.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce05b0]
>[   927.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce05b0] width 1280 pitch 5120 (/4 1280)
>[   927.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701d10]
>[   927.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701d10] width 1280 pitch 5120 (/4 1280)
>[   927.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   927.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   927.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce04f0]
>[   927.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce04f0] width 1280 pitch 5120 (/4 1280)
>[   927.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   927.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   927.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce04f0]
>[   927.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce04f0] width 1280 pitch 5120 (/4 1280)
>[   927.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   927.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   927.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce04f0]
>[   927.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce04f0] width 1280 pitch 5120 (/4 1280)
>[   927.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   927.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   927.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ce04f0]
>[   927.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ce04f0] width 1280 pitch 5120 (/4 1280)
>[   927.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   927.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d2050]
>[   928.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d2050] width 1280 pitch 5120 (/4 1280)
>[   928.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x384fc80]
>[   928.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x384fc80] width 1280 pitch 5120 (/4 1280)
>[   928.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3702130]
>[   928.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3702130] width 1280 pitch 5120 (/4 1280)
>[   928.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   928.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   928.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   928.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   928.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   928.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   928.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   928.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   928.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   928.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   928.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   928.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   928.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   928.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   928.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3701800]
>[   928.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3701800] width 1280 pitch 5120 (/4 1280)
>[   928.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706880]
>[   929.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706880] width 1280 pitch 5120 (/4 1280)
>[   935.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d2050]
>[   935.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d2050] width 1280 pitch 5120 (/4 1280)
>[   959.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf260]
>[   959.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf260] width 1280 pitch 5120 (/4 1280)
>[   959.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf200]
>[   959.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf200] width 1280 pitch 5120 (/4 1280)
>[   959.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf260]
>[   959.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf260] width 1280 pitch 5120 (/4 1280)
>[   959.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf200]
>[   959.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf200] width 1280 pitch 5120 (/4 1280)
>[   959.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf260]
>[   959.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf260] width 1280 pitch 5120 (/4 1280)
>[   960.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf200]
>[   960.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf200] width 1280 pitch 5120 (/4 1280)
>[   960.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf260]
>[   960.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf260] width 1280 pitch 5120 (/4 1280)
>[   960.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf200]
>[   960.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf200] width 1280 pitch 5120 (/4 1280)
>[   960.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   960.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   960.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[   960.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[   960.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[   960.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[   960.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[   960.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[   960.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706c10]
>[   960.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706c10] width 1280 pitch 5120 (/4 1280)
>[   960.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3702c50]
>[   960.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3702c50] width 1280 pitch 5120 (/4 1280)
>[   974.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x384f470]
>[   974.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x384f470] width 1280 pitch 5120 (/4 1280)
>[   974.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   974.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e520]
>[   974.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e520] width 1280 pitch 5120 (/4 1280)
>[   974.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97880]
>[   974.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97880] width 1280 pitch 5120 (/4 1280)
>[   975.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   975.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[   975.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[   975.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[   975.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[   984.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bda0]
>[   984.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bda0] width 1280 pitch 5120 (/4 1280)
>[   984.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   984.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   984.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bda0]
>[   984.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bda0] width 1280 pitch 5120 (/4 1280)
>[   984.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   984.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   984.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bda0]
>[   984.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bda0] width 1280 pitch 5120 (/4 1280)
>[   984.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   984.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   984.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bda0]
>[   984.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bda0] width 1280 pitch 5120 (/4 1280)
>[   984.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   984.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   984.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bda0]
>[   984.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bda0] width 1280 pitch 5120 (/4 1280)
>[   984.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   985.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   985.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   985.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   985.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[   985.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[   985.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8e3b0]
>[   985.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8e3b0] width 1280 pitch 5120 (/4 1280)
>[   985.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[   985.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[   985.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   985.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f55bc0]
>[   985.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f55bc0] width 1280 pitch 5120 (/4 1280)
>[   985.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[   985.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[   999.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[   999.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396cd80]
>[   999.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396cd80] width 1280 pitch 5120 (/4 1280)
>[   999.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392c160]
>[   999.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392c160] width 1280 pitch 5120 (/4 1280)
>[  1000.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1000.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1000.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1000.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1000.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1015.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1015.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1019.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3110dc0]
>[  1019.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3110dc0] width 1280 pitch 5120 (/4 1280)
>[  1021.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1021.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1021.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1022.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1022.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1022.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1022.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1022.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1022.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1022.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1022.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1022.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1022.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1022.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1022.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1022.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1022.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1022.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1023.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1023.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1023.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1023.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1023.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1023.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1023.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1023.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1023.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1023.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1023.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1023.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1023.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d2c80]
>[  1023.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d2c80] width 1280 pitch 5120 (/4 1280)
>[  1023.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f767b0]
>[  1023.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f767b0] width 1280 pitch 5120 (/4 1280)
>[  1032.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5300]
>[  1032.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5300] width 1280 pitch 5120 (/4 1280)
>[  1040.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1040.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1040.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1040.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1040.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1040.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1040.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1040.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1040.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1040.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1040.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1040.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1040.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1040.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1041.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1041.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1041.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1041.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1041.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1041.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1041.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1041.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1041.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1041.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1041.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1041.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1041.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1041.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1041.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1042.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1042.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1042.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1042.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1042.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1042.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1042.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1042.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1042.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1042.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1042.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1042.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1043.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1043.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1043.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1043.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1044.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1044.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1044.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1044.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1044.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1044.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1044.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1044.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1044.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1044.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1045.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3769600]
>[  1045.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3769600] width 1280 pitch 5120 (/4 1280)
>[  1045.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1045.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1045.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1045.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1045.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[  1045.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[  1045.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1045.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1045.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef1710]
>[  1045.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef1710] width 1280 pitch 5120 (/4 1280)
>[  1045.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a750]
>[  1045.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a750] width 1280 pitch 5120 (/4 1280)
>[  1135.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3834340]
>[  1135.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3834340] width 1280 pitch 5120 (/4 1280)
>[  1135.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3984190]
>[  1135.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3984190] width 1280 pitch 5120 (/4 1280)
>[  1136.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978280]
>[  1136.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978280] width 1280 pitch 5120 (/4 1280)
>[  1136.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8d440]
>[  1136.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8d440] width 1280 pitch 5120 (/4 1280)
>[  1136.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978280]
>[  1136.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978280] width 1280 pitch 5120 (/4 1280)
>[  1136.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bd8d0]
>[  1136.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bd8d0] width 1280 pitch 5120 (/4 1280)
>[  1136.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978280]
>[  1136.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978280] width 1280 pitch 5120 (/4 1280)
>[  1136.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bd8d0]
>[  1136.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bd8d0] width 1280 pitch 5120 (/4 1280)
>[  1136.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978280]
>[  1136.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978280] width 1280 pitch 5120 (/4 1280)
>[  1136.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bd8d0]
>[  1137.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bd8d0] width 1280 pitch 5120 (/4 1280)
>[  1137.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978280]
>[  1137.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978280] width 1280 pitch 5120 (/4 1280)
>[  1137.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37bd8d0]
>[  1137.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37bd8d0] width 1280 pitch 5120 (/4 1280)
>[  1137.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f799f0]
>[  1137.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f799f0] width 1280 pitch 5120 (/4 1280)
>[  1137.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3906f10]
>[  1137.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3906f10] width 1280 pitch 5120 (/4 1280)
>[  1137.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f799f0]
>[  1137.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f799f0] width 1280 pitch 5120 (/4 1280)
>[  1137.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3906f10]
>[  1137.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3906f10] width 1280 pitch 5120 (/4 1280)
>[  1137.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39076a0]
>[  1137.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39076a0] width 1280 pitch 5120 (/4 1280)
>[  1139.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1139.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1139.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310ef20]
>[  1139.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310ef20] width 1280 pitch 5120 (/4 1280)
>[  1139.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1139.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1139.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310ef20]
>[  1139.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310ef20] width 1280 pitch 5120 (/4 1280)
>[  1139.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1139.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1139.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310ef20]
>[  1139.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310ef20] width 1280 pitch 5120 (/4 1280)
>[  1140.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1140.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1140.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310ef20]
>[  1140.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310ef20] width 1280 pitch 5120 (/4 1280)
>[  1140.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1140.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1140.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1140.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1140.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1140.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1140.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1140.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1140.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1140.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1140.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1140.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1145.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1145.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1145.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1145.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1145.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1145.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1145.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1145.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1145.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1145.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1145.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1145.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1145.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1145.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1145.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1145.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1145.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8b0]
>[  1145.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8b0] width 1280 pitch 5120 (/4 1280)
>[  1146.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cf0b0]
>[  1146.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cf0b0] width 1280 pitch 5120 (/4 1280)
>[  1146.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[  1146.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[  1146.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9d00]
>[  1146.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9d00] width 1280 pitch 5120 (/4 1280)
>[  1146.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f7a0]
>[  1146.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f7a0] width 1280 pitch 5120 (/4 1280)
>[  1146.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9d00]
>[  1146.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9d00] width 1280 pitch 5120 (/4 1280)
>[  1146.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38578e0]
>[  1146.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38578e0] width 1280 pitch 5120 (/4 1280)
>[  1171.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3907700]
>[  1171.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3907700] width 1280 pitch 5120 (/4 1280)
>[  1171.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970d50]
>[  1171.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970d50] width 1280 pitch 5120 (/4 1280)
>[  1171.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393fda0]
>[  1171.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393fda0] width 1280 pitch 5120 (/4 1280)
>[  1171.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970d50]
>[  1171.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970d50] width 1280 pitch 5120 (/4 1280)
>[  1171.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393fda0]
>[  1171.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393fda0] width 1280 pitch 5120 (/4 1280)
>[  1171.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970d50]
>[  1171.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970d50] width 1280 pitch 5120 (/4 1280)
>[  1171.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393fda0]
>[  1171.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393fda0] width 1280 pitch 5120 (/4 1280)
>[  1171.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3916010]
>[  1171.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3916010] width 1280 pitch 5120 (/4 1280)
>[  1171.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393fda0]
>[  1171.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393fda0] width 1280 pitch 5120 (/4 1280)
>[  1171.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1171.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1175.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f938b0]
>[  1175.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f938b0] width 1280 pitch 5120 (/4 1280)
>[  1175.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1175.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f938b0]
>[  1175.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f938b0] width 1280 pitch 5120 (/4 1280)
>[  1175.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1175.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f938b0]
>[  1175.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f938b0] width 1280 pitch 5120 (/4 1280)
>[  1175.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1175.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f938b0]
>[  1175.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f938b0] width 1280 pitch 5120 (/4 1280)
>[  1175.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f93470]
>[  1175.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f93470] width 1280 pitch 5120 (/4 1280)
>[  1175.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f938b0]
>[  1175.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f938b0] width 1280 pitch 5120 (/4 1280)
>[  1212.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310e1e0]
>[  1212.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310e1e0] width 1280 pitch 5120 (/4 1280)
>[  1212.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a610]
>[  1212.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a610] width 1280 pitch 5120 (/4 1280)
>[  1212.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310e1e0]
>[  1212.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310e1e0] width 1280 pitch 5120 (/4 1280)
>[  1212.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a610]
>[  1213.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a610] width 1280 pitch 5120 (/4 1280)
>[  1213.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310e1e0]
>[  1213.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310e1e0] width 1280 pitch 5120 (/4 1280)
>[  1213.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a610]
>[  1213.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a610] width 1280 pitch 5120 (/4 1280)
>[  1213.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310e1e0]
>[  1213.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310e1e0] width 1280 pitch 5120 (/4 1280)
>[  1213.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a610]
>[  1213.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a610] width 1280 pitch 5120 (/4 1280)
>[  1213.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x310e1e0]
>[  1213.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x310e1e0] width 1280 pitch 5120 (/4 1280)
>[  1213.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f5a610]
>[  1213.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f5a610] width 1280 pitch 5120 (/4 1280)
>[  1215.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[  1215.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[  1215.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08ca0]
>[  1215.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08ca0] width 1280 pitch 5120 (/4 1280)
>[  1215.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[  1215.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[  1215.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08ca0]
>[  1215.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08ca0] width 1280 pitch 5120 (/4 1280)
>[  1215.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[  1215.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[  1215.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08ca0]
>[  1215.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08ca0] width 1280 pitch 5120 (/4 1280)
>[  1215.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[  1215.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[  1216.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d08ca0]
>[  1216.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d08ca0] width 1280 pitch 5120 (/4 1280)
>[  1216.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e8f960]
>[  1216.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e8f960] width 1280 pitch 5120 (/4 1280)
>[  1216.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9d00]
>[  1216.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9d00] width 1280 pitch 5120 (/4 1280)
>[  1216.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[  1216.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[  1216.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9d00]
>[  1216.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9d00] width 1280 pitch 5120 (/4 1280)
>[  1216.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38646c0]
>[  1216.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38646c0] width 1280 pitch 5120 (/4 1280)
>[  1216.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f6c6e0]
>[  1216.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f6c6e0] width 1280 pitch 5120 (/4 1280)
>[  1227.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37003c0]
>[  1227.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37003c0] width 1280 pitch 5120 (/4 1280)
>[  1232.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1232.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1232.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1232.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1232.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1232.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1232.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1232.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1232.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1232.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1232.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1232.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1232.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1232.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1232.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1232.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1232.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1233.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1233.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1233.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1233.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a52a0]
>[  1233.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a52a0] width 1280 pitch 5120 (/4 1280)
>[  1233.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc5c0]
>[  1233.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc5c0] width 1280 pitch 5120 (/4 1280)
>[  1233.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1233.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1233.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eff8f0]
>[  1233.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eff8f0] width 1280 pitch 5120 (/4 1280)
>[  1233.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97990]
>[  1233.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97990] width 1280 pitch 5120 (/4 1280)
>[  1233.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f90c50]
>[  1233.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f90c50] width 1280 pitch 5120 (/4 1280)
>[  1233.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f97990]
>[  1233.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f97990] width 1280 pitch 5120 (/4 1280)
>[  1249.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1249.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1249.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1249.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1249.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1249.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1250.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1250.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1250.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1250.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1250.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1250.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1250.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1250.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1250.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1250.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1250.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1250.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1250.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1250.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1251.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1251.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1251.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1251.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1251.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1251.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1251.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1251.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1251.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1251.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1252.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1252.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1252.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1252.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1252.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1253.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1253.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1253.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1253.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b220]
>[  1253.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b220] width 1280 pitch 5120 (/4 1280)
>[  1253.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1253.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1253.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b220]
>[  1253.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b220] width 1280 pitch 5120 (/4 1280)
>[  1253.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1253.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1254.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b220]
>[  1254.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b220] width 1280 pitch 5120 (/4 1280)
>[  1254.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1254.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1254.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b220]
>[  1254.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b220] width 1280 pitch 5120 (/4 1280)
>[  1255.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d37f0]
>[  1255.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d37f0] width 1280 pitch 5120 (/4 1280)
>[  1255.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392b220]
>[  1255.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392b220] width 1280 pitch 5120 (/4 1280)
>[  1255.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939570]
>[  1255.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939570] width 1280 pitch 5120 (/4 1280)
>[  1255.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1255.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1255.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1255.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1255.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393e490]
>[  1255.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393e490] width 1280 pitch 5120 (/4 1280)
>[  1256.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982040]
>[  1256.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982040] width 1280 pitch 5120 (/4 1280)
>[  1256.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c25e0]
>[  1256.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c25e0] width 1280 pitch 5120 (/4 1280)
>[  1256.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e03c0]
>[  1256.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e03c0] width 1280 pitch 5120 (/4 1280)
>[  1256.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c25e0]
>[  1256.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c25e0] width 1280 pitch 5120 (/4 1280)
>[  1256.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fea60]
>[  1256.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fea60] width 1280 pitch 5120 (/4 1280)
>[  1256.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c25e0]
>[  1256.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c25e0] width 1280 pitch 5120 (/4 1280)
>[  1298.332] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[  1298.332] 
>[  1298.332] Backtrace:
>[  1298.403] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[  1298.403] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x5514db]
>[  1298.403] 2: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[  1298.403] 3: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900a0]
>[  1298.403] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x5025) [0x7f12d3951025]
>[  1298.403] 5: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x6f44) [0x7f12d3952f44]
>[  1298.403] 6: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[  1298.403] 7: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[  1298.403] 8: /lib64/libpthread.so.0 (0x31bca00000+0xefe0) [0x31bca0efe0]
>[  1298.403] 9: /lib64/libpixman-1.so.0 (0x31c5a00000+0x14b1e) [0x31c5a14b1e]
>[  1298.403] 10: /lib64/libpixman-1.so.0 (0x31c5a00000+0x144c6) [0x31c5a144c6]
>[  1298.403] 11: /lib64/libpixman-1.so.0 (0x31c5a00000+0x42177) [0x31c5a42177]
>[  1298.403] 12: /lib64/libpixman-1.so.0 (pixman_image_composite32+0x3d6) [0x31c5a09fd6]
>[  1298.403] 13: /usr/lib64/xorg/modules/libfb.so (fbComposite+0x1d8) [0x7f12d60bda88]
>[  1298.403] 14: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0x11fdd) [0x7f12d62dafdd]
>[  1298.403] 15: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0xe898) [0x7f12d62d7898]
>[  1298.403] 16: /usr/bin/Xorg (0x400000+0x102139) [0x502139]
>[  1298.403] 17: /usr/bin/Xorg (0x400000+0xfb0a4) [0x4fb0a4]
>[  1298.403] 18: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[  1298.403] 19: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[  1298.403] 20: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x31bc621735]
>[  1298.403] 21: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[  1298.403] 
>[  1298.403] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[  1298.403] [mi] mieq is *NOT* the cause.  It is a victim.
>[  1299.017] [mi] EQ overflow continuing.  100 events have been dropped.
>[  1299.017] 
>[  1299.017] Backtrace:
>[  1299.017] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[  1299.017] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[  1299.017] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900a0]
>[  1299.017] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x5025) [0x7f12d3951025]
>[  1299.017] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x6f44) [0x7f12d3952f44]
>[  1299.017] 5: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[  1299.017] 6: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[  1299.017] 7: /lib64/libpthread.so.0 (0x31bca00000+0xefe0) [0x31bca0efe0]
>[  1299.017] 8: /lib64/libpixman-1.so.0 (0x31c5a00000+0x14b1e) [0x31c5a14b1e]
>[  1299.017] 9: /lib64/libpixman-1.so.0 (0x31c5a00000+0x144c6) [0x31c5a144c6]
>[  1299.017] 10: /lib64/libpixman-1.so.0 (0x31c5a00000+0x42177) [0x31c5a42177]
>[  1299.017] 11: /lib64/libpixman-1.so.0 (pixman_image_composite32+0x3d6) [0x31c5a09fd6]
>[  1299.017] 12: /usr/lib64/xorg/modules/libfb.so (fbComposite+0x1d8) [0x7f12d60bda88]
>[  1299.017] 13: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0x11fdd) [0x7f12d62dafdd]
>[  1299.017] 14: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0xe898) [0x7f12d62d7898]
>[  1299.017] 15: /usr/bin/Xorg (0x400000+0x102139) [0x502139]
>[  1299.017] 16: /usr/bin/Xorg (0x400000+0xfb0a4) [0x4fb0a4]
>[  1299.017] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[  1299.017] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[  1299.017] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x31bc621735]
>[  1299.017] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[  1299.018] 
>[  1300.433] [mi] EQ overflow continuing.  200 events have been dropped.
>[  1300.433] 
>[  1300.433] Backtrace:
>[  1300.433] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[  1300.433] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[  1300.433] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900a0]
>[  1300.433] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x5025) [0x7f12d3951025]
>[  1300.433] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x6f44) [0x7f12d3952f44]
>[  1300.433] 5: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[  1300.433] 6: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[  1300.434] 7: /lib64/libpthread.so.0 (0x31bca00000+0xefe0) [0x31bca0efe0]
>[  1300.434] 8: /lib64/libpixman-1.so.0 (0x31c5a00000+0x14b53) [0x31c5a14b53]
>[  1300.434] 9: /lib64/libpixman-1.so.0 (0x31c5a00000+0x144c6) [0x31c5a144c6]
>[  1300.434] 10: /lib64/libpixman-1.so.0 (0x31c5a00000+0x42177) [0x31c5a42177]
>[  1300.434] 11: /lib64/libpixman-1.so.0 (pixman_image_composite32+0x3d6) [0x31c5a09fd6]
>[  1300.434] 12: /usr/lib64/xorg/modules/libfb.so (fbComposite+0x1d8) [0x7f12d60bda88]
>[  1300.434] 13: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0x11fdd) [0x7f12d62dafdd]
>[  1300.434] 14: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0xe898) [0x7f12d62d7898]
>[  1300.434] 15: /usr/bin/Xorg (0x400000+0x102139) [0x502139]
>[  1300.434] 16: /usr/bin/Xorg (0x400000+0xfb0a4) [0x4fb0a4]
>[  1300.434] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[  1300.434] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[  1300.434] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x31bc621735]
>[  1300.434] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[  1300.434] 
>[  1301.121] [mi] EQ overflow continuing.  300 events have been dropped.
>[  1301.121] 
>[  1301.121] Backtrace:
>[  1301.121] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[  1301.121] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[  1301.121] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900a0]
>[  1301.121] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x5025) [0x7f12d3951025]
>[  1301.121] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x6f44) [0x7f12d3952f44]
>[  1301.121] 5: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[  1301.121] 6: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[  1301.121] 7: /lib64/libpthread.so.0 (0x31bca00000+0xefe0) [0x31bca0efe0]
>[  1301.121] 8: /lib64/libpixman-1.so.0 (0x31c5a00000+0x14b23) [0x31c5a14b23]
>[  1301.121] 9: /lib64/libpixman-1.so.0 (0x31c5a00000+0x144c6) [0x31c5a144c6]
>[  1301.121] 10: /lib64/libpixman-1.so.0 (0x31c5a00000+0x42177) [0x31c5a42177]
>[  1301.121] 11: /lib64/libpixman-1.so.0 (pixman_image_composite32+0x3d6) [0x31c5a09fd6]
>[  1301.121] 12: /usr/lib64/xorg/modules/libfb.so (fbComposite+0x1d8) [0x7f12d60bda88]
>[  1301.121] 13: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0x11fdd) [0x7f12d62dafdd]
>[  1301.121] 14: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0xe898) [0x7f12d62d7898]
>[  1301.121] 15: /usr/bin/Xorg (0x400000+0x102139) [0x502139]
>[  1301.121] 16: /usr/bin/Xorg (0x400000+0xfb0a4) [0x4fb0a4]
>[  1301.121] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[  1301.121] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[  1301.121] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x31bc621735]
>[  1301.121] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[  1301.121] 
>[  1301.968] [mi] EQ overflow continuing.  400 events have been dropped.
>[  1301.968] 
>[  1301.968] Backtrace:
>[  1301.968] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[  1301.968] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[  1301.968] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900a0]
>[  1301.968] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x5025) [0x7f12d3951025]
>[  1301.968] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f12d394c000+0x6f44) [0x7f12d3952f44]
>[  1301.968] 5: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[  1301.968] 6: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[  1301.968] 7: /lib64/libpthread.so.0 (0x31bca00000+0xefe0) [0x31bca0efe0]
>[  1301.968] 8: /lib64/libpixman-1.so.0 (0x31c5a00000+0x14b23) [0x31c5a14b23]
>[  1301.968] 9: /lib64/libpixman-1.so.0 (0x31c5a00000+0x144c6) [0x31c5a144c6]
>[  1301.968] 10: /lib64/libpixman-1.so.0 (0x31c5a00000+0x42177) [0x31c5a42177]
>[  1301.968] 11: /lib64/libpixman-1.so.0 (pixman_image_composite32+0x3d6) [0x31c5a09fd6]
>[  1301.968] 12: /usr/lib64/xorg/modules/libfb.so (fbComposite+0x1d8) [0x7f12d60bda88]
>[  1301.968] 13: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0x11fdd) [0x7f12d62dafdd]
>[  1301.968] 14: /usr/lib64/xorg/modules/libexa.so (0x7f12d62c9000+0xe898) [0x7f12d62d7898]
>[  1301.968] 15: /usr/bin/Xorg (0x400000+0x102139) [0x502139]
>[  1301.968] 16: /usr/bin/Xorg (0x400000+0xfb0a4) [0x4fb0a4]
>[  1301.968] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[  1301.968] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[  1301.968] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x31bc621735]
>[  1301.968] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[  1301.968]

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Attachments on bug 869652: 632789 | 632790 | 632791