Attachment 633132 Details for Bug 869872 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 671.61 KB, created by Paulo Lajos on 2012-10-25 03:03:13 UTC

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Creator: Paulo Lajos

Created: 2012-10-25 03:03:13 UTC

Size: 671.61 KB

patch

obsolete

>[    30.823] 
>X.Org X Server 1.12.3
>Release Date: 2012-07-09
>[    30.823] X Protocol Version 11, Revision 0
>[    30.823] Build Operating System:  2.6.32-220.17.1.el6.x86_64 
>[    30.823] Current Operating System: Linux fedora 3.6.2-7.fc17.x86_64 #1 SMP Sat Oct 20 08:48:08 CEST 2012 x86_64
>[    30.823] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.6.2-7.fc17.x86_64 root=UUID=ea5dc2af-8981-435c-ac19-c084a6857086 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=latarcyrheb-sun16 rd.luks=0 LANG=hu_HU.UTF-8 KEYTABLE=hu rhgb quiet
>[    30.823] Build Date: 20 September 2012  07:51:23AM
>[    30.824] Build ID: xorg-x11-server 1.12.3-2.fc17 
>[    30.824] Current version of pixman: 0.24.4
>[    30.824] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    30.824] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    30.824] (==) Log file: "/var/log/Xorg.0.log", Time: Wed Oct 24 19:58:31 2012
>[    30.825] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    30.825] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    30.825] (==) No Layout section.  Using the first Screen section.
>[    30.825] (==) No screen section available. Using defaults.
>[    30.825] (**) |-->Screen "Default Screen Section" (0)
>[    30.825] (**) |   |-->Monitor "<default monitor>"
>[    30.826] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    30.826] (==) Automatically adding devices
>[    30.826] (==) Automatically enabling devices
>[    30.826] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    30.826] (==) ModulePath set to "/usr/lib64/xorg/modules"
>[    30.826] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    30.826] (II) Loader magic: 0x7c6ac0
>[    30.826] (II) Module ABI versions:
>[    30.826] 	X.Org ANSI C Emulation: 0.4
>[    30.826] 	X.Org Video Driver: 12.0
>[    30.826] 	X.Org XInput driver : 16.0
>[    30.826] 	X.Org Server Extension : 6.0
>[    30.829] (--) PCI:*(0:1:0:0) 1002:95c0:174b:e390 rev 0, Mem @ 0xd0000000/268435456, 0xfeaf0000/65536, I/O @ 0x0000e000/256, BIOS @ 0x????????/131072
>[    30.829] (--) PCI: (0:3:6:0) 4444:0016:0070:8003 rev 1, Mem @ 0xf8000000/67108864, BIOS @ 0x????????/65536
>[    30.829] (II) LoadModule: "extmod"
>[    30.830] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so
>[    30.832] (II) Module extmod: vendor="X.Org Foundation"
>[    30.832] 	compiled for 1.12.3, module version = 1.0.0
>[    30.832] 	Module class: X.Org Server Extension
>[    30.832] 	ABI class: X.Org Server Extension, version 6.0
>[    30.832] (II) Loading extension SELinux
>[    30.832] (II) Loading extension MIT-SCREEN-SAVER
>[    30.832] (II) Loading extension XFree86-VidModeExtension
>[    30.832] (II) Loading extension XFree86-DGA
>[    30.832] (II) Loading extension DPMS
>[    30.832] (II) Loading extension XVideo
>[    30.832] (II) Loading extension XVideo-MotionCompensation
>[    30.832] (II) Loading extension X-Resource
>[    30.832] (II) LoadModule: "dbe"
>[    30.832] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so
>[    30.833] (II) Module dbe: vendor="X.Org Foundation"
>[    30.833] 	compiled for 1.12.3, module version = 1.0.0
>[    30.833] 	Module class: X.Org Server Extension
>[    30.833] 	ABI class: X.Org Server Extension, version 6.0
>[    30.833] (II) Loading extension DOUBLE-BUFFER
>[    30.833] (II) LoadModule: "glx"
>[    30.833] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
>[    30.833] (II) Module glx: vendor="X.Org Foundation"
>[    30.833] 	compiled for 1.12.3, module version = 1.0.0
>[    30.834] 	ABI class: X.Org Server Extension, version 6.0
>[    30.834] (==) AIGLX enabled
>[    30.834] (II) Loading extension GLX
>[    30.834] (II) LoadModule: "record"
>[    30.834] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so
>[    30.834] (II) Module record: vendor="X.Org Foundation"
>[    30.834] 	compiled for 1.12.3, module version = 1.13.0
>[    30.834] 	Module class: X.Org Server Extension
>[    30.834] 	ABI class: X.Org Server Extension, version 6.0
>[    30.834] (II) Loading extension RECORD
>[    30.834] (II) LoadModule: "dri"
>[    30.835] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so
>[    30.835] (II) Module dri: vendor="X.Org Foundation"
>[    30.835] 	compiled for 1.12.3, module version = 1.0.0
>[    30.835] 	ABI class: X.Org Server Extension, version 6.0
>[    30.835] (II) Loading extension XFree86-DRI
>[    30.835] (II) LoadModule: "dri2"
>[    30.836] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so
>[    30.836] (II) Module dri2: vendor="X.Org Foundation"
>[    30.836] 	compiled for 1.12.3, module version = 1.2.0
>[    30.836] 	ABI class: X.Org Server Extension, version 6.0
>[    30.836] (II) Loading extension DRI2
>[    30.836] (==) Matched ati as autoconfigured driver 0
>[    30.836] (==) Matched vesa as autoconfigured driver 1
>[    30.836] (==) Matched modesetting as autoconfigured driver 2
>[    30.836] (==) Matched fbdev as autoconfigured driver 3
>[    30.836] (==) Assigned the driver to the xf86ConfigLayout
>[    30.836] (II) LoadModule: "ati"
>[    30.836] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so
>[    30.837] (II) Module ati: vendor="X.Org Foundation"
>[    30.837] 	compiled for 1.12.0, module version = 6.14.99
>[    30.837] 	Module class: X.Org Video Driver
>[    30.837] 	ABI class: X.Org Video Driver, version 12.0
>[    30.837] (II) LoadModule: "radeon"
>[    30.837] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so
>[    30.838] (II) Module radeon: vendor="X.Org Foundation"
>[    30.838] 	compiled for 1.12.0, module version = 6.14.99
>[    30.838] 	Module class: X.Org Video Driver
>[    30.838] 	ABI class: X.Org Video Driver, version 12.0
>[    30.838] (II) LoadModule: "vesa"
>[    30.838] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so
>[    30.838] (II) Module vesa: vendor="X.Org Foundation"
>[    30.838] 	compiled for 1.12.0, module version = 2.3.1
>[    30.838] 	Module class: X.Org Video Driver
>[    30.838] 	ABI class: X.Org Video Driver, version 12.0
>[    30.838] (II) LoadModule: "modesetting"
>[    30.839] (WW) Warning, couldn't open module modesetting
>[    30.839] (II) UnloadModule: "modesetting"
>[    30.839] (II) Unloading modesetting
>[    30.839] (EE) Failed to load module "modesetting" (module does not exist, 0)
>[    30.839] (II) LoadModule: "fbdev"
>[    30.839] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so
>[    30.840] (II) Module fbdev: vendor="X.Org Foundation"
>[    30.840] 	compiled for 1.11.99.901, module version = 0.4.2
>[    30.840] 	ABI class: X.Org Video Driver, version 12.0
>[    30.840] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    30.850] (II) VESA: driver for VESA chipsets: vesa
>[    30.850] (II) FBDEV: driver for framebuffer: fbdev
>[    30.850] (++) using VT number 1
>
>[    30.852] (II) [KMS] Kernel modesetting enabled.
>[    30.852] (WW) Falling back to old probe method for vesa
>[    30.852] (WW) Falling back to old probe method for fbdev
>[    30.852] (II) Loading sub module "fbdevhw"
>[    30.852] (II) LoadModule: "fbdevhw"
>[    30.853] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so
>[    30.853] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    30.853] 	compiled for 1.12.3, module version = 0.0.2
>[    30.853] 	ABI class: X.Org Video Driver, version 12.0
>[    30.854] (II) RADEON(0): RADEONPreInit_KMS
>[    30.854] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    30.854] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    30.854] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    30.854] (==) RADEON(0): Default visual is TrueColor
>[    30.854] (==) RADEON(0): RGB weight 888
>[    30.854] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    30.854] (--) RADEON(0): Chipset: "ATI Radeon HD 3470" (ChipID = 0x95c0)
>[    30.854] (II) RADEON(0): PCIE card detected
>[    30.854] drmOpenDevice: node name is /dev/dri/card0
>[    30.854] drmOpenDevice: open result is 8, (OK)
>[    30.854] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    30.854] drmOpenDevice: node name is /dev/dri/card0
>[    30.854] drmOpenDevice: open result is 8, (OK)
>[    30.854] drmOpenByBusid: drmOpenMinor returns 8
>[    30.854] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    30.854] (II) Loading sub module "exa"
>[    30.855] (II) LoadModule: "exa"
>[    30.855] (II) Loading /usr/lib64/xorg/modules/libexa.so
>[    30.855] (II) Module exa: vendor="X.Org Foundation"
>[    30.855] 	compiled for 1.12.3, module version = 2.5.0
>[    30.855] 	ABI class: X.Org Video Driver, version 12.0
>[    30.855] (II) RADEON(0): KMS Color Tiling: enabled
>[    30.855] (II) RADEON(0): KMS Pageflipping: enabled
>[    30.855] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    30.867] (II) RADEON(0): Output DIN has no monitor section
>[    30.881] (II) RADEON(0): Output DVI-0 has no monitor section
>[    30.913] (II) RADEON(0): Output DVI-1 has no monitor section
>[    30.925] (II) RADEON(0): EDID for output DIN
>[    30.939] (II) RADEON(0): EDID for output DVI-0
>[    30.971] (II) RADEON(0): EDID for output DVI-1
>[    30.971] (II) RADEON(0): Manufacturer: SAM  Model: 117  Serial#: 1279602999
>[    30.971] (II) RADEON(0): Year: 2004  Week: 28
>[    30.971] (II) RADEON(0): EDID Version: 1.3
>[    30.971] (II) RADEON(0): Analog Display Input,  Input Voltage Level: 0.700/0.700 V
>[    30.971] (II) RADEON(0): Sync:  Separate
>[    30.971] (II) RADEON(0): Max Image Size [cm]: horiz.: 31  vert.: 23
>[    30.971] (II) RADEON(0): Gamma: 2.20
>[    30.971] (II) RADEON(0): DPMS capabilities: Off; RGB/Color Display
>[    30.971] (II) RADEON(0): Default color space is primary color space
>[    30.971] (II) RADEON(0): First detailed timing is preferred mode
>[    30.971] (II) RADEON(0): redX: 0.640 redY: 0.330   greenX: 0.300 greenY: 0.600
>[    30.971] (II) RADEON(0): blueX: 0.150 blueY: 0.060   whiteX: 0.312 whiteY: 0.329
>[    30.971] (II) RADEON(0): Supported established timings:
>[    30.971] (II) RADEON(0): 720x400@70Hz
>[    30.971] (II) RADEON(0): 640x480@60Hz
>[    30.971] (II) RADEON(0): 640x480@67Hz
>[    30.971] (II) RADEON(0): 640x480@72Hz
>[    30.971] (II) RADEON(0): 640x480@75Hz
>[    30.971] (II) RADEON(0): 800x600@56Hz
>[    30.971] (II) RADEON(0): 800x600@60Hz
>[    30.971] (II) RADEON(0): 800x600@72Hz
>[    30.971] (II) RADEON(0): 800x600@75Hz
>[    30.971] (II) RADEON(0): 832x624@75Hz
>[    30.971] (II) RADEON(0): 1024x768@60Hz
>[    30.971] (II) RADEON(0): 1024x768@70Hz
>[    30.971] (II) RADEON(0): 1024x768@75Hz
>[    30.971] (II) RADEON(0): 1152x864@75Hz
>[    30.972] (II) RADEON(0): Manufacturer's mask: 0
>[    30.972] (II) RADEON(0): Supported standard timings:
>[    30.972] (II) RADEON(0): #0: hsize: 1024  vsize 768  refresh: 85  vid: 22881
>[    30.972] (II) RADEON(0): #1: hsize: 800  vsize 600  refresh: 85  vid: 22853
>[    30.972] (II) RADEON(0): #2: hsize: 640  vsize 480  refresh: 85  vid: 22833
>[    30.972] (II) RADEON(0): #3: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
>[    30.972] (II) RADEON(0): #4: hsize: 1152  vsize 864  refresh: 75  vid: 20337
>[    30.972] (II) RADEON(0): Supported detailed timing:
>[    30.972] (II) RADEON(0): clock: 94.5 MHz   Image Size:  312 x 234 mm
>[    30.972] (II) RADEON(0): h_active: 1024  h_sync: 1072  h_sync_end 1168 h_blank_end 1376 h_border: 0
>[    30.972] (II) RADEON(0): v_active: 768  v_sync: 769  v_sync_end 772 v_blanking: 808 v_border: 0
>[    30.972] (II) RADEON(0): Ranges: V min: 50 V max: 160 Hz, H min: 30 H max: 71 kHz, PixClock max 115 MHz
>[    30.972] (II) RADEON(0): Monitor name: SyncMaster
>[    30.972] (II) RADEON(0): Serial No: HMBX705383
>[    30.972] (II) RADEON(0): EDID (in hex):
>[    30.972] (II) RADEON(0): 	00ffffffffffff004c2d17013731454c
>[    30.972] (II) RADEON(0): 	1c0e0103681f17782eee91a3544c9926
>[    30.972] (II) RADEON(0): 	0f5054bfee806159455931598180714f
>[    30.972] (II) RADEON(0): 	010101010101ea240060410028303060
>[    30.972] (II) RADEON(0): 	130038ea1000001e000000fd0032a01e
>[    30.972] (II) RADEON(0): 	470b000a202020202020000000fc0053
>[    30.972] (II) RADEON(0): 	796e634d61737465720a2020000000ff
>[    30.972] (II) RADEON(0): 	00484d42583730353338330a202000fc
>[    30.972] (II) RADEON(0): Printing probed modes for output DVI-1
>[    30.972] (II) RADEON(0): Modeline "1024x768"x85.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    30.972] (II) RADEON(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1280x800"x74.9  106.50  1280 1360 1488 1696  800 803 809 838 -hsync +vsync (62.8 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1280x800"x59.8   83.50  1280 1352 1480 1680  800 803 809 831 +hsync -vsync (49.7 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1280x768"x74.9  102.25  1280 1360 1488 1696  768 771 778 805 +hsync -vsync (60.3 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1280x768"x59.9   79.50  1280 1344 1472 1664  768 771 778 798 -hsync +vsync (47.8 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1024x768"x75.1   78.80  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.1 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    30.972] (II) RADEON(0): Modeline "1024x768"x87.0   44.90  1024 1032 1208 1264  768 768 772 817 interlace +hsync +vsync (35.5 kHz e)
>[    30.973] (II) RADEON(0): Modeline "1024x576"x60.0   46.97  1024 1064 1168 1312  576 577 580 597 -hsync +vsync (35.8 kHz)
>[    30.973] (II) RADEON(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    30.973] (II) RADEON(0): Modeline "800x600"x85.1   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    30.973] (II) RADEON(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    30.973] (II) RADEON(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    30.973] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    30.973] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    30.973] (II) RADEON(0): Modeline "848x480"x60.0   33.75  848 864 976 1088  480 486 494 517 +hsync +vsync (31.0 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x480"x66.7   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    30.973] (II) RADEON(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz e)
>[    30.973] (II) RADEON(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz e)
>[    30.973] (II) RADEON(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz e)
>[    30.973] (II) RADEON(0): Output DIN disconnected
>[    30.973] (II) RADEON(0): Output DVI-0 disconnected
>[    30.973] (II) RADEON(0): Output DVI-1 connected
>[    30.973] (II) RADEON(0): Using exact sizes for initial modes
>[    30.973] (II) RADEON(0): Output DVI-1 using initial mode 1024x768 +0+0
>[    30.973] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    30.973] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fcc0000
>[    30.973] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    30.973] (==) RADEON(0): DPI set to (96, 96)
>[    30.973] (II) Loading sub module "fb"
>[    30.973] (II) LoadModule: "fb"
>[    30.974] (II) Loading /usr/lib64/xorg/modules/libfb.so
>[    30.974] (II) Module fb: vendor="X.Org Foundation"
>[    30.974] 	compiled for 1.12.3, module version = 1.0.0
>[    30.974] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    30.974] (II) Loading sub module "ramdac"
>[    30.974] (II) LoadModule: "ramdac"
>[    30.974] (II) Module "ramdac" already built-in
>[    30.974] (II) UnloadModule: "vesa"
>[    30.974] (II) Unloading vesa
>[    30.974] (II) UnloadModule: "fbdev"
>[    30.974] (II) Unloading fbdev
>[    30.974] (II) UnloadSubModule: "fbdevhw"
>[    30.974] (II) Unloading fbdevhw
>[    30.974] (--) Depth 24 pixmap format is 32 bpp
>[    30.975] (II) RADEON(0): [DRI2] Setup complete
>[    30.975] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    30.975] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    30.975] (II) RADEON(0): Front buffer size: 3072K
>[    30.975] (II) RADEON(0): VRAM usage limit set to 230169K
>[    30.975] (II) RADEON(0): Initializing backing store
>[    30.975] (==) RADEON(0): Backing store disabled
>[    30.975] (II) RADEON(0): Direct rendering enabled
>[    30.975] (II) RADEON(0): Initializing Acceleration
>[    30.975] (II) RADEON(0): Setting EXA maxPitchBytes
>[    30.976] (II) EXA(0): Driver allocated offscreen pixmaps
>[    30.976] (II) EXA(0): Driver registered support for the following operations:
>[    30.976] (II)         Solid
>[    30.976] (II)         Copy
>[    30.976] (II)         Composite (RENDER acceleration)
>[    30.976] (II)         UploadToScreen
>[    30.976] (II)         DownloadFromScreen
>[    30.976] (II) RADEON(0): Acceleration enabled
>[    30.976] (II) RADEON(0): Initializing DPMS
>[    30.976] (==) RADEON(0): DPMS enabled
>[    30.976] (II) RADEON(0): Initializing Cursor
>[    30.976] (==) RADEON(0): Silken mouse enabled
>[    30.976] (II) RADEON(0): Initializing Xv
>[    30.976] (II) RADEON(0): Set up textured video
>[    30.976] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    30.976] (II) RADEON(0): [XvMC] Extension initialized.
>[    30.976] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    31.184] (II) RADEON(0): Initializing kms color map
>[    31.184] (II) RADEON(0): RADEONScreenInit finished
>[    31.184] (--) RandR disabled
>[    31.184] (II) Initializing built-in extension Generic Event Extension
>[    31.184] (II) Initializing built-in extension SHAPE
>[    31.184] (II) Initializing built-in extension MIT-SHM
>[    31.184] (II) Initializing built-in extension XInputExtension
>[    31.184] (II) Initializing built-in extension XTEST
>[    31.184] (II) Initializing built-in extension BIG-REQUESTS
>[    31.184] (II) Initializing built-in extension SYNC
>[    31.184] (II) Initializing built-in extension XKEYBOARD
>[    31.184] (II) Initializing built-in extension XC-MISC
>[    31.184] (II) Initializing built-in extension XINERAMA
>[    31.184] (II) Initializing built-in extension XFIXES
>[    31.184] (II) Initializing built-in extension RENDER
>[    31.184] (II) Initializing built-in extension RANDR
>[    31.184] (II) Initializing built-in extension COMPOSITE
>[    31.184] (II) Initializing built-in extension DAMAGE
>[    31.188] (II) SELinux: Disabled by boolean
>[    32.086] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    32.086] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    32.086] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    32.086] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    32.087] (II) AIGLX: Loaded and initialized r600
>[    32.087] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    32.090] (II) RADEON(0): Setting screen physical size to 270 x 203
>[    32.239] (II) XKB: Reusing cached keymap
>[    32.247] (II) config/udev: Adding input device Power Button (/dev/input/event1)
>[    32.247] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    32.247] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    32.247] (II) LoadModule: "evdev"
>[    32.247] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so
>[    32.248] (II) Module evdev: vendor="X.Org Foundation"
>[    32.248] 	compiled for 1.12.0, module version = 2.7.0
>[    32.248] 	Module class: X.Org XInput Driver
>[    32.248] 	ABI class: X.Org XInput driver, version 16.0
>[    32.248] (II) Using input driver 'evdev' for 'Power Button'
>[    32.248] 	Option "XkbRules" "evdev"
>[    32.248] 	Option "XkbModel" "pc105"
>[    32.248] 	Option "XkbLayout" "hu"
>[    32.248] 	Option "_source" "server/udev"
>[    32.248] 	Option "name" "Power Button"
>[    32.248] 	Option "path" "/dev/input/event1"
>[    32.248] 	Option "device" "/dev/input/event1"
>[    32.248] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1"
>[    32.248] 	Option "driver" "evdev"
>[    32.248] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    32.248] (**) Power Button: always reports core events
>[    32.248] (**) evdev: Power Button: Device: "/dev/input/event1"
>[    32.249] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    32.249] (--) evdev: Power Button: Found keys
>[    32.249] (II) evdev: Power Button: Configuring as keyboard
>[    32.249] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1"
>[    32.249] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    32.249] (**) Option "xkb_rules" "evdev"
>[    32.249] (**) Option "xkb_model" "pc105"
>[    32.249] (**) Option "xkb_layout" "hu"
>[    32.249] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    32.319] (II) config/udev: Adding input device Power Button (/dev/input/event0)
>[    32.319] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    32.319] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    32.319] (II) Using input driver 'evdev' for 'Power Button'
>[    32.319] 	Option "XkbRules" "evdev"
>[    32.319] 	Option "XkbModel" "pc105"
>[    32.319] 	Option "XkbLayout" "hu"
>[    32.319] 	Option "_source" "server/udev"
>[    32.319] 	Option "name" "Power Button"
>[    32.319] 	Option "path" "/dev/input/event0"
>[    32.319] 	Option "device" "/dev/input/event0"
>[    32.319] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    32.319] 	Option "driver" "evdev"
>[    32.319] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    32.319] (**) Power Button: always reports core events
>[    32.319] (**) evdev: Power Button: Device: "/dev/input/event0"
>[    32.319] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    32.319] (--) evdev: Power Button: Found keys
>[    32.319] (II) evdev: Power Button: Configuring as keyboard
>[    32.319] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    32.319] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7)
>[    32.319] (**) Option "xkb_rules" "evdev"
>[    32.319] (**) Option "xkb_model" "pc105"
>[    32.319] (**) Option "xkb_layout" "hu"
>[    32.319] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    32.319] (II) XKB: Reusing cached keymap
>[    32.321] (II) config/udev: Adding input device HDA ATI HDMI HDMI/DP,pcm=3 (/dev/input/event12)
>[    32.321] (II) No input driver specified, ignoring this device.
>[    32.321] (II) This device may have been added with another device file.
>[    32.322] (II) config/udev: Adding input device MLK Trust Mouse 15399 (/dev/input/event3)
>[    32.322] (**) MLK Trust Mouse 15399: Applying InputClass "evdev pointer catchall"
>[    32.322] (**) MLK Trust Mouse 15399: Applying InputClass "evdev keyboard catchall"
>[    32.322] (**) MLK Trust Mouse 15399: Applying InputClass "system-setup-keyboard"
>[    32.322] (II) Using input driver 'evdev' for 'MLK Trust Mouse 15399'
>[    32.322] 	Option "XkbRules" "evdev"
>[    32.322] 	Option "XkbModel" "pc105"
>[    32.322] 	Option "XkbLayout" "hu"
>[    32.322] 	Option "_source" "server/udev"
>[    32.322] 	Option "name" "MLK Trust Mouse 15399"
>[    32.322] 	Option "path" "/dev/input/event3"
>[    32.322] 	Option "device" "/dev/input/event3"
>[    32.322] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb3/3-3/3-3:1.0/input/input3/event3"
>[    32.322] 	Option "driver" "evdev"
>[    32.322] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    32.322] (**) MLK Trust Mouse 15399: always reports core events
>[    32.322] (**) evdev: MLK Trust Mouse 15399: Device: "/dev/input/event3"
>[    32.322] (--) evdev: MLK Trust Mouse 15399: absolute axis 0x20 [896..0]
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Vendor 0x4fc Product 0x538
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Found 9 mouse buttons
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Found scroll wheel(s)
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Found relative axes
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Found x and y relative axes
>[    32.322] (--) evdev: MLK Trust Mouse 15399: Found absolute axes
>[    32.323] (II) evdev: MLK Trust Mouse 15399: Forcing absolute x/y axes to exist.
>[    32.323] (--) evdev: MLK Trust Mouse 15399: Found keys
>[    32.323] (II) evdev: MLK Trust Mouse 15399: Configuring as mouse
>[    32.323] (II) evdev: MLK Trust Mouse 15399: Configuring as keyboard
>[    32.323] (II) evdev: MLK Trust Mouse 15399: Adding scrollwheel support
>[    32.323] (**) evdev: MLK Trust Mouse 15399: YAxisMapping: buttons 4 and 5
>[    32.323] (**) evdev: MLK Trust Mouse 15399: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    32.323] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.0/usb3/3-3/3-3:1.0/input/input3/event3"
>[    32.323] (II) XINPUT: Adding extended input device "MLK Trust Mouse 15399" (type: KEYBOARD, id 8)
>[    32.323] (**) Option "xkb_rules" "evdev"
>[    32.323] (**) Option "xkb_model" "pc105"
>[    32.323] (**) Option "xkb_layout" "hu"
>[    32.323] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    32.323] (II) XKB: Reusing cached keymap
>[    32.324] (II) evdev: MLK Trust Mouse 15399: initialized for relative axes.
>[    32.324] (WW) evdev: MLK Trust Mouse 15399: ignoring absolute axes.
>[    32.324] (**) MLK Trust Mouse 15399: (accel) keeping acceleration scheme 1
>[    32.324] (**) MLK Trust Mouse 15399: (accel) acceleration profile 0
>[    32.324] (**) MLK Trust Mouse 15399: (accel) acceleration factor: 2.000
>[    32.324] (**) MLK Trust Mouse 15399: (accel) acceleration threshold: 4
>[    32.325] (II) config/udev: Adding input device MLK Trust Mouse 15399 (/dev/input/mouse0)
>[    32.325] (**) MLK Trust Mouse 15399: Applying InputClass "system-setup-keyboard"
>[    32.325] (II) No input driver specified, ignoring this device.
>[    32.325] (II) This device may have been added with another device file.
>[    32.326] (II) config/udev: Adding input device HDA ATI SB Line Out Surround (/dev/input/event10)
>[    32.326] (II) No input driver specified, ignoring this device.
>[    32.326] (II) This device may have been added with another device file.
>[    32.327] (II) config/udev: Adding input device HDA ATI SB Line Out Front (/dev/input/event11)
>[    32.327] (II) No input driver specified, ignoring this device.
>[    32.327] (II) This device may have been added with another device file.
>[    32.327] (II) config/udev: Adding input device HDA ATI SB Line (/dev/input/event4)
>[    32.327] (II) No input driver specified, ignoring this device.
>[    32.327] (II) This device may have been added with another device file.
>[    32.328] (II) config/udev: Adding input device HDA ATI SB Front Mic (/dev/input/event5)
>[    32.328] (II) No input driver specified, ignoring this device.
>[    32.328] (II) This device may have been added with another device file.
>[    32.329] (II) config/udev: Adding input device HDA ATI SB Rear Mic (/dev/input/event6)
>[    32.329] (II) No input driver specified, ignoring this device.
>[    32.329] (II) This device may have been added with another device file.
>[    32.329] (II) config/udev: Adding input device HDA ATI SB Front Headphone (/dev/input/event7)
>[    32.330] (II) No input driver specified, ignoring this device.
>[    32.330] (II) This device may have been added with another device file.
>[    32.330] (II) config/udev: Adding input device HDA ATI SB Line Out Side (/dev/input/event8)
>[    32.330] (II) No input driver specified, ignoring this device.
>[    32.330] (II) This device may have been added with another device file.
>[    32.331] (II) config/udev: Adding input device HDA ATI SB Line Out CLFE (/dev/input/event9)
>[    32.331] (II) No input driver specified, ignoring this device.
>[    32.331] (II) This device may have been added with another device file.
>[    32.332] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event2)
>[    32.332] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    32.332] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard"
>[    32.332] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    32.332] 	Option "XkbRules" "evdev"
>[    32.332] 	Option "XkbModel" "pc105"
>[    32.332] 	Option "XkbLayout" "hu"
>[    32.332] 	Option "_source" "server/udev"
>[    32.332] 	Option "name" "AT Translated Set 2 keyboard"
>[    32.332] 	Option "path" "/dev/input/event2"
>[    32.332] 	Option "device" "/dev/input/event2"
>[    32.332] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2"
>[    32.332] 	Option "driver" "evdev"
>[    32.332] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    32.332] (**) AT Translated Set 2 keyboard: always reports core events
>[    32.332] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event2"
>[    32.332] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    32.332] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    32.332] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    32.332] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2"
>[    32.332] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 9)
>[    32.332] (**) Option "xkb_rules" "evdev"
>[    32.332] (**) Option "xkb_model" "pc105"
>[    32.332] (**) Option "xkb_layout" "hu"
>[    32.332] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    32.333] (II) XKB: Reusing cached keymap
>[    32.348] (II) RADEON(0): RADEONSaveScreen(2)
>[    32.412] (II) RADEON(0): EDID vendor "SAM", prod id 279
>[    32.412] (II) RADEON(0): Using EDID range info for horizontal sync
>[    32.412] (II) RADEON(0): Using EDID range info for vertical refresh
>[    32.412] (II) RADEON(0): Printing DDC gathered Modelines:
>[    32.412] (II) RADEON(0): Modeline "1024x768"x0.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    32.412] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    32.412] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    32.412] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    32.412] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    32.412] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    32.412] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    32.412] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    32.412] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    32.412] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    32.412] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    32.413] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    32.413] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    32.413] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    32.413] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    32.413] (II) RADEON(0): Modeline "800x600"x0.0   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    32.413] (II) RADEON(0): Modeline "640x480"x0.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    32.413] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    33.974] (II) RADEON(0): EDID vendor "SAM", prod id 279
>[    33.974] (II) RADEON(0): Using hsync ranges from config file
>[    33.974] (II) RADEON(0): Using vrefresh ranges from config file
>[    33.974] (II) RADEON(0): Printing DDC gathered Modelines:
>[    33.974] (II) RADEON(0): Modeline "1024x768"x0.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    33.974] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    33.974] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    33.974] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    33.974] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    33.974] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    33.974] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    33.974] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    33.974] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    33.974] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    33.974] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    33.975] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    33.975] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    33.975] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    33.975] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    33.975] (II) RADEON(0): Modeline "800x600"x0.0   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    33.975] (II) RADEON(0): Modeline "640x480"x0.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    33.975] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    35.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfa20]
>[    35.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfa20] width 1024 pitch 4096 (/4 1024)
>[    35.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    35.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    35.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    35.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    35.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    36.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfaa0]
>[    36.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfaa0] width 1024 pitch 4096 (/4 1024)
>[    36.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1ddfb00]
>[    36.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1ddfb00] width 1024 pitch 4096 (/4 1024)
>[    41.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    41.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    41.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    41.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    41.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    42.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    42.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    42.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    42.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    43.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    43.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    43.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de1fa0]
>[    43.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de1fa0] width 1024 pitch 4096 (/4 1024)
>[    43.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    43.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    44.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    44.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    44.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    44.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    45.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    45.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    47.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    47.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    47.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    47.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    48.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    48.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    48.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    48.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    49.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    49.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    49.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    49.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    50.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    50.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    50.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    50.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    51.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    51.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    51.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    51.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    52.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    52.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de66c0]
>[    52.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de66c0] width 1024 pitch 4096 (/4 1024)
>[    52.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6720]
>[    52.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6720] width 1024 pitch 4096 (/4 1024)
>[    53.146] (II) RADEON(0): EDID vendor "SAM", prod id 279
>[    53.146] (II) RADEON(0): Using hsync ranges from config file
>[    53.146] (II) RADEON(0): Using vrefresh ranges from config file
>[    53.146] (II) RADEON(0): Printing DDC gathered Modelines:
>[    53.146] (II) RADEON(0): Modeline "1024x768"x0.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    53.146] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    53.146] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    53.146] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    53.146] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    53.146] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    53.146] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    53.146] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    53.146] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    53.146] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    53.146] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    53.146] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    53.146] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    53.146] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    53.146] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    53.146] (II) RADEON(0): Modeline "800x600"x0.0   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    53.146] (II) RADEON(0): Modeline "640x480"x0.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    53.146] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    54.249] (II) RADEON(0): EDID vendor "SAM", prod id 279
>[    54.249] (II) RADEON(0): Using hsync ranges from config file
>[    54.249] (II) RADEON(0): Using vrefresh ranges from config file
>[    54.249] (II) RADEON(0): Printing DDC gathered Modelines:
>[    54.249] (II) RADEON(0): Modeline "1024x768"x0.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    54.249] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    54.249] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    54.249] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    54.249] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    54.249] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    54.249] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    54.249] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    54.249] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    54.249] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    54.249] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    54.249] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    54.249] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    54.249] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    54.249] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    54.249] (II) RADEON(0): Modeline "800x600"x0.0   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    54.249] (II) RADEON(0): Modeline "640x480"x0.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    54.249] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    54.728] (II) RADEON(0): EDID vendor "SAM", prod id 279
>[    54.728] (II) RADEON(0): Using hsync ranges from config file
>[    54.728] (II) RADEON(0): Using vrefresh ranges from config file
>[    54.728] (II) RADEON(0): Printing DDC gathered Modelines:
>[    54.728] (II) RADEON(0): Modeline "1024x768"x0.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz eP)
>[    54.728] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    54.728] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    54.728] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    54.728] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    54.728] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    54.728] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    54.728] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    54.728] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    54.728] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    54.728] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    54.728] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    54.728] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    54.728] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    54.728] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    54.728] (II) RADEON(0): Modeline "800x600"x0.0   56.25  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz e)
>[    54.729] (II) RADEON(0): Modeline "640x480"x0.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz e)
>[    54.729] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    56.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    56.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    56.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    56.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    56.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244aed0]
>[    57.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244aed0] width 1024 pitch 4096 (/4 1024)
>[    57.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    57.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244eab0]
>[    57.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244eab0] width 1024 pitch 4096 (/4 1024)
>[    57.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    57.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    58.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244ec50]
>[    58.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244ec50] width 1024 pitch 4096 (/4 1024)
>[    58.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244ec50]
>[    58.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244ec50] width 1024 pitch 4096 (/4 1024)
>[    58.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244f190]
>[    58.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244f190] width 1024 pitch 4096 (/4 1024)
>[    60.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    60.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    60.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    60.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    60.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b080]
>[    60.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b080] width 1024 pitch 4096 (/4 1024)
>[    60.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    60.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    60.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b080]
>[    60.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b080] width 1024 pitch 4096 (/4 1024)
>[    60.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    60.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    60.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b080]
>[    60.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b080] width 1024 pitch 4096 (/4 1024)
>[    60.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244af30]
>[    60.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244af30] width 1024 pitch 4096 (/4 1024)
>[    60.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b080]
>[    60.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b080] width 1024 pitch 4096 (/4 1024)
>[    64.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2470f80]
>[    64.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2470f80] width 1024 pitch 4096 (/4 1024)
>[    64.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2470f80]
>[    64.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2470f80] width 1024 pitch 4096 (/4 1024)
>[    64.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244ba50]
>[    64.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244ba50] width 1024 pitch 4096 (/4 1024)
>[    64.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244ba50]
>[    64.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244ba50] width 1024 pitch 4096 (/4 1024)
>[    64.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244ba50]
>[    64.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244ba50] width 1024 pitch 4096 (/4 1024)
>[    64.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bcb0]
>[    64.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bcb0] width 1024 pitch 4096 (/4 1024)
>[    64.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bcb0]
>[    64.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bcb0] width 1024 pitch 4096 (/4 1024)
>[    64.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bcb0]
>[    64.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bcb0] width 1024 pitch 4096 (/4 1024)
>[    64.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    64.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bcb0]
>[    64.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bcb0] width 1024 pitch 4096 (/4 1024)
>[    64.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244bab0]
>[    64.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244bab0] width 1024 pitch 4096 (/4 1024)
>[    65.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244f590]
>[    65.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244f590] width 1024 pitch 4096 (/4 1024)
>[    65.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a1af0]
>[    65.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a1af0] width 1024 pitch 4096 (/4 1024)
>[    65.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a1db0]
>[    65.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a1db0] width 1024 pitch 4096 (/4 1024)
>[    65.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a1e60]
>[    65.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a1e60] width 1024 pitch 4096 (/4 1024)
>[    65.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    65.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a7110]
>[    65.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a7110] width 1024 pitch 4096 (/4 1024)
>[    65.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a70b0]
>[    65.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a70b0] width 1024 pitch 4096 (/4 1024)
>[    71.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db900]
>[    71.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db900] width 1024 pitch 4096 (/4 1024)
>[   103.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d4b30]
>[   103.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d4b30] width 1024 pitch 4096 (/4 1024)
>[  1038.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1038.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1038.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1038.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1039.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1039.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1039.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1039.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1042.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1042.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1042.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1042.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1043.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1043.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1046.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2e80]
>[  1046.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2e80] width 1024 pitch 4096 (/4 1024)
>[  1046.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1c63dc0]
>[  1046.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1c63dc0] width 1024 pitch 4096 (/4 1024)
>[  1049.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25244f0]
>[  1049.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25244f0] width 1024 pitch 4096 (/4 1024)
>[  1049.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540690]
>[  1049.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540690] width 1024 pitch 4096 (/4 1024)
>[  1052.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b4c80]
>[  1052.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b4c80] width 1024 pitch 4096 (/4 1024)
>[  1070.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  1070.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  1071.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1ee0]
>[  1071.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1ee0] width 1024 pitch 4096 (/4 1024)
>[  1071.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ef860]
>[  1071.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ef860] width 1024 pitch 4096 (/4 1024)
>[  1071.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ba410]
>[  1071.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ba410] width 1024 pitch 4096 (/4 1024)
>[  1071.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ba410]
>[  1071.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ba410] width 1024 pitch 4096 (/4 1024)
>[  1071.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1071.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1071.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2602d90]
>[  1071.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2602d90] width 1024 pitch 4096 (/4 1024)
>[  1071.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f89d0]
>[  1071.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f89d0] width 1024 pitch 4096 (/4 1024)
>[  1071.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2602d90]
>[  1071.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2602d90] width 1024 pitch 4096 (/4 1024)
>[  1071.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f89d0]
>[  1071.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f89d0] width 1024 pitch 4096 (/4 1024)
>[  1071.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2602d90]
>[  1071.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2602d90] width 1024 pitch 4096 (/4 1024)
>[  1071.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f89d0]
>[  1071.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f89d0] width 1024 pitch 4096 (/4 1024)
>[  1071.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2602d90]
>[  1071.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2602d90] width 1024 pitch 4096 (/4 1024)
>[  1071.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f89d0]
>[  1071.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f89d0] width 1024 pitch 4096 (/4 1024)
>[  1071.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2602d90]
>[  1071.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2602d90] width 1024 pitch 4096 (/4 1024)
>[  1078.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1078.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bb2a0]
>[  1078.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1078.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f1300]
>[  1078.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f1300] width 1024 pitch 4096 (/4 1024)
>[  1082.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eac70]
>[  1082.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eac70] width 1024 pitch 4096 (/4 1024)
>[  1083.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c3f80]
>[  1083.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c3f80] width 1024 pitch 4096 (/4 1024)
>[  1083.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1083.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b1fe0]
>[  1083.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b1fe0] width 1024 pitch 4096 (/4 1024)
>[  1083.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb3c0]
>[  1083.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb3c0] width 1024 pitch 4096 (/4 1024)
>[  1092.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1092.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1105.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1105.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1105.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1105.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1105.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1105.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1105.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1105.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1105.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1105.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1105.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1105.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1105.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1105.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1105.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1105.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1105.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2f0]
>[  1105.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2f0] width 1024 pitch 4096 (/4 1024)
>[  1106.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25510f0]
>[  1106.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25510f0] width 1024 pitch 4096 (/4 1024)
>[  1106.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1106.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1106.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1106.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1106.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25510f0]
>[  1106.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25510f0] width 1024 pitch 4096 (/4 1024)
>[  1106.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1106.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1107.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1107.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1107.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260eb90]
>[  1107.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260eb90] width 1024 pitch 4096 (/4 1024)
>[  1107.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e990]
>[  1107.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e990] width 1024 pitch 4096 (/4 1024)
>[  1107.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260ea20]
>[  1107.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260ea20] width 1024 pitch 4096 (/4 1024)
>[  1107.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e990]
>[  1107.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e990] width 1024 pitch 4096 (/4 1024)
>[  1107.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260ea20]
>[  1107.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260ea20] width 1024 pitch 4096 (/4 1024)
>[  1107.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e990]
>[  1107.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e990] width 1024 pitch 4096 (/4 1024)
>[  1111.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257b650]
>[  1111.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257b650] width 1024 pitch 4096 (/4 1024)
>[  1111.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257cbd0]
>[  1111.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257cbd0] width 1024 pitch 4096 (/4 1024)
>[  1111.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2644db0]
>[  1111.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2644db0] width 1024 pitch 4096 (/4 1024)
>[  1136.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1136.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1136.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1136.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1136.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1137.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1137.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1137.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1137.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1138.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1138.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1139.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e4d60]
>[  1139.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e4d60] width 1024 pitch 4096 (/4 1024)
>[  1140.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  1140.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  1140.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2697760]
>[  1140.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2697760] width 1024 pitch 4096 (/4 1024)
>[  1140.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691300]
>[  1140.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691300] width 1024 pitch 4096 (/4 1024)
>[  1140.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2697670]
>[  1140.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2697670] width 1024 pitch 4096 (/4 1024)
>[  1140.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269c940]
>[  1140.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269c940] width 1024 pitch 4096 (/4 1024)
>[  1140.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1140.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1140.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1140.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1140.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1140.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257e200]
>[  1140.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257e200] width 1024 pitch 4096 (/4 1024)
>[  1140.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26036d0]
>[  1140.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26036d0] width 1024 pitch 4096 (/4 1024)
>[  1150.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd3e0]
>[  1150.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd3e0] width 1024 pitch 4096 (/4 1024)
>[  1153.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f64d0]
>[  1153.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f64d0] width 1024 pitch 4096 (/4 1024)
>[  1181.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb2a0]
>[  1181.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb2a0] width 1024 pitch 4096 (/4 1024)
>[  1183.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbb50]
>[  1183.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbb50] width 1024 pitch 4096 (/4 1024)
>[  1184.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbb50]
>[  1184.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbb50] width 1024 pitch 4096 (/4 1024)
>[  1185.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a6510]
>[  1185.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a6510] width 1024 pitch 4096 (/4 1024)
>[  1185.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2603d40]
>[  1185.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2603d40] width 1024 pitch 4096 (/4 1024)
>[  1186.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2603d40]
>[  1186.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2603d40] width 1024 pitch 4096 (/4 1024)
>[  1186.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2690e30]
>[  1186.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2690e30] width 1024 pitch 4096 (/4 1024)
>[  1187.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2690e30]
>[  1187.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2690e30] width 1024 pitch 4096 (/4 1024)
>[  1187.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b3150]
>[  1187.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b3150] width 1024 pitch 4096 (/4 1024)
>[  1187.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b30f0]
>[  1187.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b30f0] width 1024 pitch 4096 (/4 1024)
>[  1187.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b3150]
>[  1187.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b3150] width 1024 pitch 4096 (/4 1024)
>[  1187.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b30f0]
>[  1187.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b30f0] width 1024 pitch 4096 (/4 1024)
>[  1187.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b3150]
>[  1187.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b3150] width 1024 pitch 4096 (/4 1024)
>[  1187.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b30f0]
>[  1187.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b30f0] width 1024 pitch 4096 (/4 1024)
>[  1187.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b3150]
>[  1187.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b3150] width 1024 pitch 4096 (/4 1024)
>[  1187.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b30f0]
>[  1187.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b30f0] width 1024 pitch 4096 (/4 1024)
>[  1187.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b3150]
>[  1187.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b3150] width 1024 pitch 4096 (/4 1024)
>[  1187.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b30f0]
>[  1187.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b30f0] width 1024 pitch 4096 (/4 1024)
>[  1189.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb7e0]
>[  1189.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb7e0] width 1024 pitch 4096 (/4 1024)
>[  1189.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257c2f0]
>[  1189.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257c2f0] width 1024 pitch 4096 (/4 1024)
>[  1190.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb7e0]
>[  1190.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb7e0] width 1024 pitch 4096 (/4 1024)
>[  1191.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8400]
>[  1191.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8400] width 1024 pitch 4096 (/4 1024)
>[  1192.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1192.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257f6a0]
>[  1192.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257f6a0] width 1024 pitch 4096 (/4 1024)
>[  1192.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1192.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1199.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb7e0]
>[  1199.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb7e0] width 1024 pitch 4096 (/4 1024)
>[  1200.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2648260]
>[  1200.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2648260] width 1024 pitch 4096 (/4 1024)
>[  1200.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb7e0]
>[  1200.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb7e0] width 1024 pitch 4096 (/4 1024)
>[  1200.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8210]
>[  1200.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8210] width 1024 pitch 4096 (/4 1024)
>[  1547.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  1547.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  1547.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb7e0]
>[  1547.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb7e0] width 1024 pitch 4096 (/4 1024)
>[  1547.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257d180]
>[  1547.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257d180] width 1024 pitch 4096 (/4 1024)
>[  1547.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bb6d0]
>[  1547.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bb6d0] width 1024 pitch 4096 (/4 1024)
>[  1549.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  1549.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  1550.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbb50]
>[  1550.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbb50] width 1024 pitch 4096 (/4 1024)
>[  1550.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25811d0]
>[  1550.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25811d0] width 1024 pitch 4096 (/4 1024)
>[  1550.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581dc0]
>[  1550.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581dc0] width 1024 pitch 4096 (/4 1024)
>[  1555.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586680]
>[  1555.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586680] width 1024 pitch 4096 (/4 1024)
>[  1646.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1646.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1646.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1646.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1646.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1646.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1646.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1646.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1646.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1647.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25851b0]
>[  1647.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25851b0] width 1024 pitch 4096 (/4 1024)
>[  1647.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2589550]
>[  1647.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2589550] width 1024 pitch 4096 (/4 1024)
>[  1648.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3990]
>[  1648.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3990] width 1024 pitch 4096 (/4 1024)
>[  1659.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26970e0]
>[  1659.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26970e0] width 1024 pitch 4096 (/4 1024)
>[  1659.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1659.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252a950]
>[  1659.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252a950] width 1024 pitch 4096 (/4 1024)
>[  1659.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a490]
>[  1659.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a490] width 1024 pitch 4096 (/4 1024)
>[  1682.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25532e0]
>[  1682.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25532e0] width 1024 pitch 4096 (/4 1024)
>[  1684.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258fe60]
>[  1684.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258fe60] width 1024 pitch 4096 (/4 1024)
>[  1690.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a35a0]
>[  1690.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a35a0] width 1024 pitch 4096 (/4 1024)
>[  1701.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b62c0]
>[  1701.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b62c0] width 1024 pitch 4096 (/4 1024)
>[  1701.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1701.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b36b0]
>[  1701.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b36b0] width 1024 pitch 4096 (/4 1024)
>[  1701.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1701.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1704.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1704.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  1705.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b3470]
>[  1705.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b3470] width 1024 pitch 4096 (/4 1024)
>[  1705.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ad50]
>[  1705.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ad50] width 1024 pitch 4096 (/4 1024)
>[  2069.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2069.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2069.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e9660]
>[  2069.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e9660] width 1024 pitch 4096 (/4 1024)
>[  2069.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2069.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2069.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e9660]
>[  2069.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e9660] width 1024 pitch 4096 (/4 1024)
>[  2069.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2070.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2070.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e9660]
>[  2070.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e9660] width 1024 pitch 4096 (/4 1024)
>[  2070.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2070.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2070.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e9660]
>[  2070.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e9660] width 1024 pitch 4096 (/4 1024)
>[  2070.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2070.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2070.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e9660]
>[  2070.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e9660] width 1024 pitch 4096 (/4 1024)
>[  2070.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  2070.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  2070.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8270]
>[  2070.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8270] width 1024 pitch 4096 (/4 1024)
>[  2070.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  2070.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  2070.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529900]
>[  2070.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529900] width 1024 pitch 4096 (/4 1024)
>[  2071.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  2071.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  2071.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529900]
>[  2071.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529900] width 1024 pitch 4096 (/4 1024)
>[  2071.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  2071.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  2071.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529900]
>[  2071.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529900] width 1024 pitch 4096 (/4 1024)
>[  2071.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  2071.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  2523.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d17c0]
>[  2523.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d17c0] width 1024 pitch 4096 (/4 1024)
>[  2523.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2579b90]
>[  2523.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2579b90] width 1024 pitch 4096 (/4 1024)
>[  2543.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cf670]
>[  2543.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cf670] width 1024 pitch 4096 (/4 1024)
>[  2563.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  2563.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  2563.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2694480]
>[  2563.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2694480] width 1024 pitch 4096 (/4 1024)
>[  2563.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2747ec0]
>[  2563.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2747ec0] width 1024 pitch 4096 (/4 1024)
>[  2563.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2694480]
>[  2563.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2694480] width 1024 pitch 4096 (/4 1024)
>[  2563.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2747ec0]
>[  2563.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2747ec0] width 1024 pitch 4096 (/4 1024)
>[  2563.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2694480]
>[  2563.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2694480] width 1024 pitch 4096 (/4 1024)
>[  2563.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d1870]
>[  2563.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d1870] width 1024 pitch 4096 (/4 1024)
>[  2563.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2747ec0]
>[  2563.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2747ec0] width 1024 pitch 4096 (/4 1024)
>[  2563.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d1870]
>[  2563.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d1870] width 1024 pitch 4096 (/4 1024)
>[  2563.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d35e0]
>[  2563.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d35e0] width 1024 pitch 4096 (/4 1024)
>[  2563.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257a4d0]
>[  2563.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257a4d0] width 1024 pitch 4096 (/4 1024)
>[  2563.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cee50]
>[  2563.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cee50] width 1024 pitch 4096 (/4 1024)
>[  2563.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257a4d0]
>[  2563.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257a4d0] width 1024 pitch 4096 (/4 1024)
>[  2563.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cee50]
>[  2563.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cee50] width 1024 pitch 4096 (/4 1024)
>[  2674.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a8b50]
>[  2674.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a8b50] width 1024 pitch 4096 (/4 1024)
>[  2944.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed240]
>[  2945.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed240] width 1024 pitch 4096 (/4 1024)
>[  2975.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271f170]
>[  2975.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271f170] width 1024 pitch 4096 (/4 1024)
>[  2975.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e8ae0]
>[  2975.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e8ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e91c0]
>[  2975.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e91c0] width 1024 pitch 4096 (/4 1024)
>[  2975.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e91c0]
>[  2975.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e91c0] width 1024 pitch 4096 (/4 1024)
>[  2975.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e91c0]
>[  2975.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e91c0] width 1024 pitch 4096 (/4 1024)
>[  2975.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ae0]
>[  2975.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ae0] width 1024 pitch 4096 (/4 1024)
>[  2975.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e91c0]
>[  2975.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e91c0] width 1024 pitch 4096 (/4 1024)
>[  2983.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  2983.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  2983.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  2983.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde210]
>[  2983.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde210] width 1024 pitch 4096 (/4 1024)
>[  3024.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270d060]
>[  3024.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270d060] width 1024 pitch 4096 (/4 1024)
>[  3029.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271cbb0]
>[  3029.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271cbb0] width 1024 pitch 4096 (/4 1024)
>[  3030.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2708070]
>[  3030.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2708070] width 1024 pitch 4096 (/4 1024)
>[  3032.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27495a0]
>[  3032.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27495a0] width 1024 pitch 4096 (/4 1024)
>[  3032.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7890]
>[  3032.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7890] width 1024 pitch 4096 (/4 1024)
>[  3032.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25366b0]
>[  3032.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25366b0] width 1024 pitch 4096 (/4 1024)
>[  3048.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bac90]
>[  3048.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bac90] width 1024 pitch 4096 (/4 1024)
>[  3048.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bac90]
>[  3048.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bac90] width 1024 pitch 4096 (/4 1024)
>[  3048.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bac90]
>[  3048.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bac90] width 1024 pitch 4096 (/4 1024)
>[  3048.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bac90]
>[  3048.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bac90] width 1024 pitch 4096 (/4 1024)
>[  3048.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bac90]
>[  3048.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bac90] width 1024 pitch 4096 (/4 1024)
>[  3048.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3048.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3048.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3048.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3048.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3048.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553500]
>[  3048.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553500] width 1024 pitch 4096 (/4 1024)
>[  3048.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b5b10]
>[  3048.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b5b10] width 1024 pitch 4096 (/4 1024)
>[  3050.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3050.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549140]
>[  3050.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549140] width 1024 pitch 4096 (/4 1024)
>[  3050.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25293e0]
>[  3050.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25293e0] width 1024 pitch 4096 (/4 1024)
>[  3056.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2612af0]
>[  3056.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2612af0] width 1024 pitch 4096 (/4 1024)
>[  3057.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  3057.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  3057.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b4140]
>[  3057.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b4140] width 1024 pitch 4096 (/4 1024)
>[  3057.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b0bd0]
>[  3057.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b0bd0] width 1024 pitch 4096 (/4 1024)
>[  3060.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2583f10]
>[  3060.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2583f10] width 1024 pitch 4096 (/4 1024)
>[  3072.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c1f50]
>[  3072.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c1f50] width 1024 pitch 4096 (/4 1024)
>[  3072.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c24d0]
>[  3072.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c24d0] width 1024 pitch 4096 (/4 1024)
>[  3073.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c1f50]
>[  3073.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c1f50] width 1024 pitch 4096 (/4 1024)
>[  3073.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c24d0]
>[  3073.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c24d0] width 1024 pitch 4096 (/4 1024)
>[  3079.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c4890]
>[  3079.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c4890] width 1024 pitch 4096 (/4 1024)
>[  3088.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f6790]
>[  3088.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f6790] width 1024 pitch 4096 (/4 1024)
>[  3088.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f7d00]
>[  3088.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f7d00] width 1024 pitch 4096 (/4 1024)
>[  3088.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719650]
>[  3088.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719650] width 1024 pitch 4096 (/4 1024)
>[  3088.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cde70]
>[  3088.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cde70] width 1024 pitch 4096 (/4 1024)
>[  3088.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255a6c0]
>[  3088.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255a6c0] width 1024 pitch 4096 (/4 1024)
>[  3088.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3088.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6550]
>[  3088.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6550] width 1024 pitch 4096 (/4 1024)
>[  3089.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0c00]
>[  3089.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0c00] width 1024 pitch 4096 (/4 1024)
>[  3090.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581c50]
>[  3090.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581c50] width 1024 pitch 4096 (/4 1024)
>[  3090.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2581c50]
>[  3090.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2581c50] width 1024 pitch 4096 (/4 1024)
>[  3090.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  3090.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  3090.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  3090.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  3090.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  3090.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  3090.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24a67d0]
>[  3090.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24a67d0] width 1024 pitch 4096 (/4 1024)
>[  3090.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252ac80]
>[  3090.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252ac80] width 1024 pitch 4096 (/4 1024)
>[  3090.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbb50]
>[  3090.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbb50] width 1024 pitch 4096 (/4 1024)
>[  3090.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0c00]
>[  3090.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0c00] width 1024 pitch 4096 (/4 1024)
>[  3090.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  3090.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  3090.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0c00]
>[  3090.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0c00] width 1024 pitch 4096 (/4 1024)
>[  3090.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  3090.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  3099.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2736000]
>[  3099.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2736000] width 1024 pitch 4096 (/4 1024)
>[  3100.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ad860]
>[  3100.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ad860] width 1024 pitch 4096 (/4 1024)
>[  3101.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbb50]
>[  3101.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbb50] width 1024 pitch 4096 (/4 1024)
>[  3103.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a0a60]
>[  3103.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a0a60] width 1024 pitch 4096 (/4 1024)
>[  3105.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0ac0]
>[  3105.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0ac0] width 1024 pitch 4096 (/4 1024)
>[  3105.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b81e0]
>[  3105.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b81e0] width 1024 pitch 4096 (/4 1024)
>[  3105.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b80f0]
>[  3105.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b80f0] width 1024 pitch 4096 (/4 1024)
>[  3168.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2697890]
>[  3168.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2697890] width 1024 pitch 4096 (/4 1024)
>[  3172.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cda60]
>[  3172.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cda60] width 1024 pitch 4096 (/4 1024)
>[  3172.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd0d0]
>[  3172.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd0d0] width 1024 pitch 4096 (/4 1024)
>[  3172.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd9b0]
>[  3172.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd9b0] width 1024 pitch 4096 (/4 1024)
>[  3172.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cd0d0]
>[  3172.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cd0d0] width 1024 pitch 4096 (/4 1024)
>[  3192.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1300]
>[  3192.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1300] width 1024 pitch 4096 (/4 1024)
>[  3194.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  3194.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  3196.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2737ac0]
>[  3196.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2737ac0] width 1024 pitch 4096 (/4 1024)
>[  3207.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dd580]
>[  3207.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dd580] width 1024 pitch 4096 (/4 1024)
>[  3223.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259e6b0]
>[  3223.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259e6b0] width 1024 pitch 4096 (/4 1024)
>[  3226.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3226.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  3226.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  3226.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  3226.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  3227.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  3227.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  3227.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  3227.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  3227.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251ef70]
>[  3227.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251ef70] width 1024 pitch 4096 (/4 1024)
>[  3245.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719fc0]
>[  3245.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719fc0] width 1024 pitch 4096 (/4 1024)
>[  3266.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3266.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3266.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3266.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3270.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3270.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3270.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3270.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3271.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3271.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3271.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3271.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3271.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3271.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3271.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3271.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3271.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3271.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3271.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3271.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3271.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3271.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3271.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0ab0]
>[  3271.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0ab0] width 1024 pitch 4096 (/4 1024)
>[  3271.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3271.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3272.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586970]
>[  3272.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586970] width 1024 pitch 4096 (/4 1024)
>[  3272.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0b00]
>[  3273.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0b00] width 1024 pitch 4096 (/4 1024)
>[  3273.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691750]
>[  3273.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691750] width 1024 pitch 4096 (/4 1024)
>[  3273.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb1e0]
>[  3273.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb1e0] width 1024 pitch 4096 (/4 1024)
>[  3273.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691750]
>[  3273.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691750] width 1024 pitch 4096 (/4 1024)
>[  3273.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2612af0]
>[  3273.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2612af0] width 1024 pitch 4096 (/4 1024)
>[  3273.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691750]
>[  3273.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691750] width 1024 pitch 4096 (/4 1024)
>[  3273.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2612af0]
>[  3273.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2612af0] width 1024 pitch 4096 (/4 1024)
>[  3273.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691750]
>[  3273.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691750] width 1024 pitch 4096 (/4 1024)
>[  3794.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb1e0]
>[  3794.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb1e0] width 1024 pitch 4096 (/4 1024)
>[  3795.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25790b0]
>[  3795.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25790b0] width 1024 pitch 4096 (/4 1024)
>[  3795.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  3795.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  3795.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25863e0]
>[  3795.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25863e0] width 1024 pitch 4096 (/4 1024)
>[  3795.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2720c40]
>[  3795.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2720c40] width 1024 pitch 4096 (/4 1024)
>[  3865.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3865.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3865.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3865.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3866.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3866.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3866.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3866.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3867.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f9280]
>[  3867.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f9280] width 1024 pitch 4096 (/4 1024)
>[  3867.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3867.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  3873.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3873.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3874.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3874.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3874.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3874.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3874.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3874.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3874.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3874.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3874.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3874.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3874.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3874.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3874.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3874.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3874.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3874.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3874.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3875.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3875.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3875.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3875.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3875.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3875.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3875.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3875.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  3875.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  3875.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dc560]
>[  3875.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dc560] width 1024 pitch 4096 (/4 1024)
>[  3875.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  3875.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  3875.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb1e0]
>[  3875.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb1e0] width 1024 pitch 4096 (/4 1024)
>[  3875.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  3875.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  3875.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb1e0]
>[  3875.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb1e0] width 1024 pitch 4096 (/4 1024)
>[  3875.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  3875.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  3875.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb1e0]
>[  3875.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb1e0] width 1024 pitch 4096 (/4 1024)
>[  3875.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  3876.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  3951.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25790b0]
>[  3951.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25790b0] width 1024 pitch 4096 (/4 1024)
>[  3951.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  3951.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  3951.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea540]
>[  3951.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea540] width 1024 pitch 4096 (/4 1024)
>[  3951.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719e30]
>[  3951.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719e30] width 1024 pitch 4096 (/4 1024)
>[  4036.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4036.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4036.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4036.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4036.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4037.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea7f0]
>[  4037.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea7f0] width 1024 pitch 4096 (/4 1024)
>[  4038.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  4038.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  4038.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c0b0]
>[  4038.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c0b0] width 1024 pitch 4096 (/4 1024)
>[  4038.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  4038.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  4038.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c0b0]
>[  4038.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c0b0] width 1024 pitch 4096 (/4 1024)
>[  4038.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  4038.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  4038.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c0b0]
>[  4038.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c0b0] width 1024 pitch 4096 (/4 1024)
>[  4038.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f07c0]
>[  4038.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f07c0] width 1024 pitch 4096 (/4 1024)
>[  4038.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c0b0]
>[  4038.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c0b0] width 1024 pitch 4096 (/4 1024)
>[  4038.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  4038.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  4038.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2707f50]
>[  4038.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2707f50] width 1024 pitch 4096 (/4 1024)
>[  4038.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  4038.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  4038.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2707f50]
>[  4038.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2707f50] width 1024 pitch 4096 (/4 1024)
>[  4981.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  4981.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  4982.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  4982.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  4982.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  4982.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  4982.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  4982.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  4982.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270ccf0]
>[  4982.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270ccf0] width 1024 pitch 4096 (/4 1024)
>[  5021.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5021.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5021.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5021.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5022.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5022.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5022.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5022.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5023.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ea890]
>[  5023.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ea890] width 1024 pitch 4096 (/4 1024)
>[  5024.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5024.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5025.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5025.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5025.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5025.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5025.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719f60]
>[  5025.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719f60] width 1024 pitch 4096 (/4 1024)
>[  5025.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5025.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5025.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719f60]
>[  5025.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719f60] width 1024 pitch 4096 (/4 1024)
>[  5025.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5025.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5025.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719f60]
>[  5025.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719f60] width 1024 pitch 4096 (/4 1024)
>[  5025.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5025.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5025.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719f60]
>[  5025.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719f60] width 1024 pitch 4096 (/4 1024)
>[  5025.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5025.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5032.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270cd90]
>[  5032.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270cd90] width 1024 pitch 4096 (/4 1024)
>[  5033.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ed300]
>[  5033.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ed300] width 1024 pitch 4096 (/4 1024)
>[  5033.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5033.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5033.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25aa8e0]
>[  5033.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25aa8e0] width 1024 pitch 4096 (/4 1024)
>[  5034.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25790b0]
>[  5034.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25790b0] width 1024 pitch 4096 (/4 1024)
>[  5034.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  5034.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  5034.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f80]
>[  5034.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f80] width 1024 pitch 4096 (/4 1024)
>[  5034.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270ccf0]
>[  5034.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270ccf0] width 1024 pitch 4096 (/4 1024)
>[  5035.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  5035.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  5035.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699490]
>[  5035.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699490] width 1024 pitch 4096 (/4 1024)
>[  5035.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699490]
>[  5035.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699490] width 1024 pitch 4096 (/4 1024)
>[  5043.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  5043.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  5043.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699490]
>[  5043.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699490] width 1024 pitch 4096 (/4 1024)
>[  5052.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  5052.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  5053.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2586a60]
>[  5053.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2586a60] width 1024 pitch 4096 (/4 1024)
>[  5133.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5133.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5133.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5133.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5134.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5134.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5134.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5134.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5136.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5136.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5136.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2691c80]
>[  5136.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2691c80] width 1024 pitch 4096 (/4 1024)
>[  5138.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5138.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5138.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f56b0]
>[  5138.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f56b0] width 1024 pitch 4096 (/4 1024)
>[  5138.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f5920]
>[  5138.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f5920] width 1024 pitch 4096 (/4 1024)
>[  5138.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f56b0]
>[  5138.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f56b0] width 1024 pitch 4096 (/4 1024)
>[  5138.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f5920]
>[  5138.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f5920] width 1024 pitch 4096 (/4 1024)
>[  5144.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c5140]
>[  5144.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c5140] width 1024 pitch 4096 (/4 1024)
>[  5145.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5ab0]
>[  5145.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5ab0] width 1024 pitch 4096 (/4 1024)
>[  5145.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278bc00]
>[  5145.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278bc00] width 1024 pitch 4096 (/4 1024)
>[  5146.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4e20]
>[  5146.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4e20] width 1024 pitch 4096 (/4 1024)
>[  5146.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278bc00]
>[  5146.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278bc00] width 1024 pitch 4096 (/4 1024)
>[  5146.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25790b0]
>[  5146.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25790b0] width 1024 pitch 4096 (/4 1024)
>[  5146.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258c0b0]
>[  5146.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258c0b0] width 1024 pitch 4096 (/4 1024)
>[  5146.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  5146.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  5146.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5146.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5146.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  5147.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  5147.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5147.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5147.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  5147.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  5147.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5147.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5199.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2538730]
>[  5199.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2538730] width 1024 pitch 4096 (/4 1024)
>[  5215.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5215.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5216.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f67d0]
>[  5216.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f67d0] width 1024 pitch 4096 (/4 1024)
>[  5216.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27cc400]
>[  5216.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27cc400] width 1024 pitch 4096 (/4 1024)
>[  5232.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5232.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5234.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2543920]
>[  5234.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2543920] width 1024 pitch 4096 (/4 1024)
>[  5234.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2d30]
>[  5234.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2d30] width 1024 pitch 4096 (/4 1024)
>[  5234.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2d30]
>[  5234.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2d30] width 1024 pitch 4096 (/4 1024)
>[  5316.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca0c0]
>[  5316.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca0c0] width 1024 pitch 4096 (/4 1024)
>[  5316.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca0c0]
>[  5316.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca0c0] width 1024 pitch 4096 (/4 1024)
>[  5316.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278d610]
>[  5316.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278d610] width 1024 pitch 4096 (/4 1024)
>[  5316.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278d610]
>[  5316.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278d610] width 1024 pitch 4096 (/4 1024)
>[  5316.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5316.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5316.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5316.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5316.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5316.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5316.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5316.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5316.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5319.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2744d40]
>[  5319.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2744d40] width 1024 pitch 4096 (/4 1024)
>[  5319.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5319.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5319.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a3d70]
>[  5319.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a3d70] width 1024 pitch 4096 (/4 1024)
>[  5319.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d14d0]
>[  5319.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d14d0] width 1024 pitch 4096 (/4 1024)
>[  5319.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1570]
>[  5319.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1570] width 1024 pitch 4096 (/4 1024)
>[  5319.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a3e70]
>[  5319.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a3e70] width 1024 pitch 4096 (/4 1024)
>[  5319.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2744d40]
>[  5319.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2744d40] width 1024 pitch 4096 (/4 1024)
>[  5319.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1540]
>[  5319.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1540] width 1024 pitch 4096 (/4 1024)
>[  5319.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5319.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5319.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4140]
>[  5319.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4140] width 1024 pitch 4096 (/4 1024)
>[  5319.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5319.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5319.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4e60]
>[  5319.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4e60] width 1024 pitch 4096 (/4 1024)
>[  5319.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5319.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5319.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5319.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5319.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4140]
>[  5319.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4140] width 1024 pitch 4096 (/4 1024)
>[  5319.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5319.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5335.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5335.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5335.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5335.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5335.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5335.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5335.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5335.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5335.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5335.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5335.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5335.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5335.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5335.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5335.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5335.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5336.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5336.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5336.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  5336.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  5336.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26034a0]
>[  5336.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26034a0] width 1024 pitch 4096 (/4 1024)
>[  5337.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5337.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5337.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2579cd0]
>[  5337.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2579cd0] width 1024 pitch 4096 (/4 1024)
>[  5337.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699500]
>[  5337.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699500] width 1024 pitch 4096 (/4 1024)
>[  5337.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270ccf0]
>[  5337.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270ccf0] width 1024 pitch 4096 (/4 1024)
>[  5337.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699500]
>[  5337.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699500] width 1024 pitch 4096 (/4 1024)
>[  5337.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270ccf0]
>[  5337.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270ccf0] width 1024 pitch 4096 (/4 1024)
>[  5337.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699500]
>[  5337.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699500] width 1024 pitch 4096 (/4 1024)
>[  5337.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270ccf0]
>[  5337.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270ccf0] width 1024 pitch 4096 (/4 1024)
>[  5355.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2719f60]
>[  5355.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2719f60] width 1024 pitch 4096 (/4 1024)
>[  5355.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5355.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5355.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5355.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5355.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5356.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5356.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5356.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5356.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5356.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5356.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5356.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5356.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb2b0]
>[  5356.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb2b0] width 1024 pitch 4096 (/4 1024)
>[  5357.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e4390]
>[  5357.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e4390] width 1024 pitch 4096 (/4 1024)
>[  5357.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5357.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5357.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5357.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5357.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5357.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5357.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b20f0]
>[  5357.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b20f0] width 1024 pitch 4096 (/4 1024)
>[  5357.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5357.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5357.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5357.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5357.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5357.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5357.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5357.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5357.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5357.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5357.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25510b0]
>[  5357.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25510b0] width 1024 pitch 4096 (/4 1024)
>[  5357.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f2a30]
>[  5357.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f2a30] width 1024 pitch 4096 (/4 1024)
>[  5357.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  5357.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  5357.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  5357.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  5357.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5357.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5357.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  5357.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  5357.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5357.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5357.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  5357.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  5357.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5357.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5373.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5373.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5373.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5373.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5373.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  5373.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  5373.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5373.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5373.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5373.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5373.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5373.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5373.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5373.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5373.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5373.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5373.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5373.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5374.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5374.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5375.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5375.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5376.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5376.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5376.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  5376.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  5377.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e2470]
>[  5377.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e2470] width 1024 pitch 4096 (/4 1024)
>[  5377.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ba3c0]
>[  5377.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ba3c0] width 1024 pitch 4096 (/4 1024)
>[  5377.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eef10]
>[  5377.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eef10] width 1024 pitch 4096 (/4 1024)
>[  5377.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x271cbb0]
>[  5377.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x271cbb0] width 1024 pitch 4096 (/4 1024)
>[  5377.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dbd90]
>[  5377.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dbd90] width 1024 pitch 4096 (/4 1024)
>[  5377.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ad020]
>[  5377.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ad020] width 1024 pitch 4096 (/4 1024)
>[  5377.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2583310]
>[  5377.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2583310] width 1024 pitch 4096 (/4 1024)
>[  5387.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27447d0]
>[  5387.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27447d0] width 1024 pitch 4096 (/4 1024)
>[  5393.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x252d250]
>[  5393.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x252d250] width 1024 pitch 4096 (/4 1024)
>[  5403.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253f8c0]
>[  5403.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253f8c0] width 1024 pitch 4096 (/4 1024)
>[  5403.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253e6b0]
>[  5403.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253e6b0] width 1024 pitch 4096 (/4 1024)
>[  5403.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922c0]
>[  5403.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922c0] width 1024 pitch 4096 (/4 1024)
>[  5403.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253e6b0]
>[  5403.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253e6b0] width 1024 pitch 4096 (/4 1024)
>[  5403.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922c0]
>[  5403.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922c0] width 1024 pitch 4096 (/4 1024)
>[  5403.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253e6b0]
>[  5403.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253e6b0] width 1024 pitch 4096 (/4 1024)
>[  5403.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922c0]
>[  5403.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922c0] width 1024 pitch 4096 (/4 1024)
>[  5403.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253e6b0]
>[  5404.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253e6b0] width 1024 pitch 4096 (/4 1024)
>[  5404.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922c0]
>[  5404.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922c0] width 1024 pitch 4096 (/4 1024)
>[  5404.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253e6b0]
>[  5404.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253e6b0] width 1024 pitch 4096 (/4 1024)
>[  5404.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922c0]
>[  5404.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922c0] width 1024 pitch 4096 (/4 1024)
>[  5410.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26425a0]
>[  5410.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26425a0] width 1024 pitch 4096 (/4 1024)
>[  5410.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25acf90]
>[  5410.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25acf90] width 1024 pitch 4096 (/4 1024)
>[  5410.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26421a0]
>[  5410.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26421a0] width 1024 pitch 4096 (/4 1024)
>[  5410.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26421a0]
>[  5410.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26421a0] width 1024 pitch 4096 (/4 1024)
>[  5410.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26421a0]
>[  5410.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26421a0] width 1024 pitch 4096 (/4 1024)
>[  5410.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25acf90]
>[  5410.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25acf90] width 1024 pitch 4096 (/4 1024)
>[  5410.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26425a0]
>[  5410.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26425a0] width 1024 pitch 4096 (/4 1024)
>[  5410.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922f0]
>[  5410.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922f0] width 1024 pitch 4096 (/4 1024)
>[  5410.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922f0]
>[  5410.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922f0] width 1024 pitch 4096 (/4 1024)
>[  5410.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922f0]
>[  5410.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922f0] width 1024 pitch 4096 (/4 1024)
>[  5410.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5410.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27922f0]
>[  5410.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27922f0] width 1024 pitch 4096 (/4 1024)
>[  5410.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5410.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5413.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26425a0]
>[  5413.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26425a0] width 1024 pitch 4096 (/4 1024)
>[  5413.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d98a0]
>[  5413.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d98a0] width 1024 pitch 4096 (/4 1024)
>[  5413.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e9320]
>[  5413.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e9320] width 1024 pitch 4096 (/4 1024)
>[  5414.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b2f00]
>[  5414.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b2f00] width 1024 pitch 4096 (/4 1024)
>[  5414.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c9310]
>[  5414.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c9310] width 1024 pitch 4096 (/4 1024)
>[  5414.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5414.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5414.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c9310]
>[  5414.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c9310] width 1024 pitch 4096 (/4 1024)
>[  5414.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5414.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5414.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c9310]
>[  5414.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c9310] width 1024 pitch 4096 (/4 1024)
>[  5414.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5414.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5414.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c9310]
>[  5414.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c9310] width 1024 pitch 4096 (/4 1024)
>[  5414.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2553490]
>[  5414.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2553490] width 1024 pitch 4096 (/4 1024)
>[  5415.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26421a0]
>[  5415.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26421a0] width 1024 pitch 4096 (/4 1024)
>[  5416.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e92d0]
>[  5416.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e92d0] width 1024 pitch 4096 (/4 1024)
>[  5416.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5416.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5416.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5416.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5416.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5416.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5416.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5416.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5416.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5416.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5416.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5416.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a00c0]
>[  5416.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a00c0] width 1024 pitch 4096 (/4 1024)
>[  5424.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d9580]
>[  5424.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d9580] width 1024 pitch 4096 (/4 1024)
>[  5425.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c7720]
>[  5425.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c7720] width 1024 pitch 4096 (/4 1024)
>[  5425.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550790]
>[  5425.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550790] width 1024 pitch 4096 (/4 1024)
>[  5425.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2543470]
>[  5426.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2543470] width 1024 pitch 4096 (/4 1024)
>[  5426.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c8530]
>[  5426.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c8530] width 1024 pitch 4096 (/4 1024)
>[  5427.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  5427.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  5434.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b6150]
>[  5434.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b6150] width 1024 pitch 4096 (/4 1024)
>[  5434.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26caed0]
>[  5434.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26caed0] width 1024 pitch 4096 (/4 1024)
>[  5434.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26caed0]
>[  5434.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26caed0] width 1024 pitch 4096 (/4 1024)
>[  5434.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5434.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5c00]
>[  5434.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5c00] width 1024 pitch 4096 (/4 1024)
>[  5434.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b67d0]
>[  5434.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b67d0] width 1024 pitch 4096 (/4 1024)
>[  5442.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2550570]
>[  5442.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2550570] width 1024 pitch 4096 (/4 1024)
>[  5445.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cb090]
>[  5445.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cb090] width 1024 pitch 4096 (/4 1024)
>[  5446.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cb090]
>[  5446.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cb090] width 1024 pitch 4096 (/4 1024)
>[  5446.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2645f80]
>[  5446.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2645f80] width 1024 pitch 4096 (/4 1024)
>[  5446.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27355c0]
>[  5446.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27355c0] width 1024 pitch 4096 (/4 1024)
>[  5446.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2645f80]
>[  5446.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2645f80] width 1024 pitch 4096 (/4 1024)
>[  5446.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27355c0]
>[  5446.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27355c0] width 1024 pitch 4096 (/4 1024)
>[  5446.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2645f80]
>[  5446.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2645f80] width 1024 pitch 4096 (/4 1024)
>[  5446.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27355c0]
>[  5446.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27355c0] width 1024 pitch 4096 (/4 1024)
>[  5447.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cdd50]
>[  5447.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cdd50] width 1024 pitch 4096 (/4 1024)
>[  5447.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cdd50]
>[  5447.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cdd50] width 1024 pitch 4096 (/4 1024)
>[  5447.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5447.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5447.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  5447.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  5447.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5447.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5447.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  5447.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  5447.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5447.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5447.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5447.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5447.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5447.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5447.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b20f0]
>[  5447.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b20f0] width 1024 pitch 4096 (/4 1024)
>[  5447.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2749c10]
>[  5447.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2749c10] width 1024 pitch 4096 (/4 1024)
>[  5455.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e46a0]
>[  5455.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e46a0] width 1024 pitch 4096 (/4 1024)
>[  5455.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  5455.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  5455.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5455.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5455.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5455.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5455.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5455.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5455.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5455.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5455.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5455.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5456.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5456.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5456.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  5456.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  5457.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  5457.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  5457.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f40f0]
>[  5457.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f40f0] width 1024 pitch 4096 (/4 1024)
>[  5457.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2503b60]
>[  5457.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2503b60] width 1024 pitch 4096 (/4 1024)
>[  5457.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2642940]
>[  5457.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2642940] width 1024 pitch 4096 (/4 1024)
>[  5457.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255b340]
>[  5457.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255b340] width 1024 pitch 4096 (/4 1024)
>[  5457.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d5c0]
>[  5457.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d5c0] width 1024 pitch 4096 (/4 1024)
>[  5457.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb510]
>[  5457.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb510] width 1024 pitch 4096 (/4 1024)
>[  5457.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d5c0]
>[  5457.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d5c0] width 1024 pitch 4096 (/4 1024)
>[  5457.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255b340]
>[  5457.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255b340] width 1024 pitch 4096 (/4 1024)
>[  5457.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2642940]
>[  5457.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2642940] width 1024 pitch 4096 (/4 1024)
>[  5457.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2503b60]
>[  5457.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2503b60] width 1024 pitch 4096 (/4 1024)
>[  5457.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f66f0]
>[  5457.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f66f0] width 1024 pitch 4096 (/4 1024)
>[  5457.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5457.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5457.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f40f0]
>[  5457.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f40f0] width 1024 pitch 4096 (/4 1024)
>[  5466.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae4c0]
>[  5466.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae4c0] width 1024 pitch 4096 (/4 1024)
>[  5466.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2642940]
>[  5466.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2642940] width 1024 pitch 4096 (/4 1024)
>[  5466.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2503b60]
>[  5466.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2503b60] width 1024 pitch 4096 (/4 1024)
>[  5466.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eb510]
>[  5466.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eb510] width 1024 pitch 4096 (/4 1024)
>[  5466.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f40f0]
>[  5466.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f40f0] width 1024 pitch 4096 (/4 1024)
>[  5466.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ae4c0]
>[  5466.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ae4c0] width 1024 pitch 4096 (/4 1024)
>[  5466.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac560]
>[  5466.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac560] width 1024 pitch 4096 (/4 1024)
>[  5466.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5466.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5469.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255b340]
>[  5469.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255b340] width 1024 pitch 4096 (/4 1024)
>[  5470.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2642940]
>[  5470.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2642940] width 1024 pitch 4096 (/4 1024)
>[  5470.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5470.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5470.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5470.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5470.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5470.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5470.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  5470.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  5470.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5470.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5470.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  5470.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  5470.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5470.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5480.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5480.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5480.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1300]
>[  5480.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1300] width 1024 pitch 4096 (/4 1024)
>[  5480.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2587e50]
>[  5480.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2587e50] width 1024 pitch 4096 (/4 1024)
>[  5480.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b20f0]
>[  5480.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b20f0] width 1024 pitch 4096 (/4 1024)
>[  5481.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbe00]
>[  5481.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbe00] width 1024 pitch 4096 (/4 1024)
>[  5481.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  5481.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  5481.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cbe00]
>[  5481.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cbe00] width 1024 pitch 4096 (/4 1024)
>[  5481.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  5481.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  5481.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5481.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5481.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5481.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5481.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2543920]
>[  5481.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2543920] width 1024 pitch 4096 (/4 1024)
>[  5482.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5482.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5482.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x255b340]
>[  5482.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x255b340] width 1024 pitch 4096 (/4 1024)
>[  5482.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2644ac0]
>[  5482.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2644ac0] width 1024 pitch 4096 (/4 1024)
>[  5482.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  5482.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  5482.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29ece50]
>[  5482.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29ece50] width 1024 pitch 4096 (/4 1024)
>[  5482.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  5482.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  5482.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d500]
>[  5482.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d500] width 1024 pitch 4096 (/4 1024)
>[  5482.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  5482.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  5482.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d500]
>[  5482.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d500] width 1024 pitch 4096 (/4 1024)
>[  5482.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  5482.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  5482.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d500]
>[  5482.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d500] width 1024 pitch 4096 (/4 1024)
>[  5482.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  5482.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  5482.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260d500]
>[  5482.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260d500] width 1024 pitch 4096 (/4 1024)
>[  5517.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5517.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5517.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5517.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5518.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5518.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5518.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5518.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5518.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5518.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5518.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5518.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5518.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5518.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5518.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5518.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5518.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5518.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5518.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5518.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5518.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5518.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5519.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5519.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5519.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5519.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5519.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5519.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5519.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5519.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5519.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5519.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5519.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5519.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5519.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5519.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5519.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5519.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5519.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5519.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  5519.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  5540.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e4390]
>[  5540.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e4390] width 1024 pitch 4096 (/4 1024)
>[  5540.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5540.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5540.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5540.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5540.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5540.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5540.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5541.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5541.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5541.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5541.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5541.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5541.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  5541.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  5544.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273a230]
>[  5544.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273a230] width 1024 pitch 4096 (/4 1024)
>[  5589.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e6f90]
>[  5589.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e6f90] width 1024 pitch 4096 (/4 1024)
>[  5589.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2604ca0]
>[  5589.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2604ca0] width 1024 pitch 4096 (/4 1024)
>[  5589.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5589.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b93d0]
>[  5589.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b93d0] width 1024 pitch 4096 (/4 1024)
>[  5589.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d5370]
>[  5589.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d5370] width 1024 pitch 4096 (/4 1024)
>[  5591.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f5550]
>[  5591.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f5550] width 1024 pitch 4096 (/4 1024)
>[  5596.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5596.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5596.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5596.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5596.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5596.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[  5596.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[  5601.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5601.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5621.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  5621.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  5621.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5621.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5621.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5621.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5622.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5622.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5622.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5622.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5622.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5622.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5622.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5622.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5622.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5623.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  5623.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  5623.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273a7d0]
>[  5623.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273a7d0] width 1024 pitch 4096 (/4 1024)
>[  5623.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26da1c0]
>[  5623.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26da1c0] width 1024 pitch 4096 (/4 1024)
>[  5623.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273a7a0]
>[  5623.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273a7a0] width 1024 pitch 4096 (/4 1024)
>[  5623.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26da1c0]
>[  5623.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26da1c0] width 1024 pitch 4096 (/4 1024)
>[  5623.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273a7a0]
>[  5623.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273a7a0] width 1024 pitch 4096 (/4 1024)
>[  5625.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2584c10]
>[  5625.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2584c10] width 1024 pitch 4096 (/4 1024)
>[  5626.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258f2f0]
>[  5626.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258f2f0] width 1024 pitch 4096 (/4 1024)
>[  5634.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4960]
>[  5634.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4960] width 1024 pitch 4096 (/4 1024)
>[  5634.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4960]
>[  5634.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4960] width 1024 pitch 4096 (/4 1024)
>[  5634.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  5635.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  5635.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5635.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5641.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5641.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5641.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  5641.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  5641.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  5641.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  5641.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25efff0]
>[  5641.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25efff0] width 1024 pitch 4096 (/4 1024)
>[  5715.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  5715.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  5715.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d6250]
>[  5715.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d6250] width 1024 pitch 4096 (/4 1024)
>[  5715.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  5715.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  5715.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  5715.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  5719.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c5360]
>[  5719.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c5360] width 1024 pitch 4096 (/4 1024)
>[  5719.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d62e0]
>[  5719.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d62e0] width 1024 pitch 4096 (/4 1024)
>[  5759.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d62e0]
>[  5759.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d62e0] width 1024 pitch 4096 (/4 1024)
>[  5759.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27201e0]
>[  5759.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27201e0] width 1024 pitch 4096 (/4 1024)
>[  5759.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  5759.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  5759.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5759.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5767.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b5460]
>[  5767.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b5460] width 1024 pitch 4096 (/4 1024)
>[  5767.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b55f0]
>[  5767.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b55f0] width 1024 pitch 4096 (/4 1024)
>[  5780.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502010]
>[  5780.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502010] width 1024 pitch 4096 (/4 1024)
>[  5780.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646c20]
>[  5780.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646c20] width 1024 pitch 4096 (/4 1024)
>[  5780.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  5780.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  5780.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  5780.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  5785.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5785.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5785.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5785.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5785.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2585e80]
>[  5785.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2585e80] width 1024 pitch 4096 (/4 1024)
>[  5785.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5785.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5792.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2585e80]
>[  5792.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2585e80] width 1024 pitch 4096 (/4 1024)
>[  5792.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  5792.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  5792.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502010]
>[  5792.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502010] width 1024 pitch 4096 (/4 1024)
>[  5792.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502010]
>[  5792.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502010] width 1024 pitch 4096 (/4 1024)
>[  5797.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  5797.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  5797.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  5797.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  5797.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2501e30]
>[  5797.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2501e30] width 1024 pitch 4096 (/4 1024)
>[  5797.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2585c80]
>[  5797.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2585c80] width 1024 pitch 4096 (/4 1024)
>[  5798.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5798.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5799.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5799.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5799.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  5799.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  5799.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  5799.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  5802.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5802.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5802.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646c20]
>[  5802.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646c20] width 1024 pitch 4096 (/4 1024)
>[  5802.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5802.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5802.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  5802.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  5804.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5804.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5804.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5804.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5804.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  5804.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  5804.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2541920]
>[  5804.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2541920] width 1024 pitch 4096 (/4 1024)
>[  5839.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5839.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5839.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5839.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5839.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  5839.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  5839.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  5839.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  5851.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5851.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5854.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5854.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5854.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5854.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5855.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5855.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5855.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5855.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5863.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5863.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5863.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5863.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5863.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5863.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5863.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5863.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5873.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  5873.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  5873.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5873.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5873.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5873.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5873.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ca3c0]
>[  5873.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ca3c0] width 1024 pitch 4096 (/4 1024)
>[  5881.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  5881.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  5881.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  5881.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  5881.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5881.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5881.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  5881.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  5910.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  5910.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  5910.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  5910.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  5910.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d52f0]
>[  5910.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d52f0] width 1024 pitch 4096 (/4 1024)
>[  5910.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d52f0]
>[  5910.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d52f0] width 1024 pitch 4096 (/4 1024)
>[  5934.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  5934.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  5934.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  5934.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  5934.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  5934.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  5934.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646c20]
>[  5934.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646c20] width 1024 pitch 4096 (/4 1024)
>[  5940.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5940.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5940.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  5940.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  5940.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cace0]
>[  5940.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cace0] width 1024 pitch 4096 (/4 1024)
>[  5940.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  5940.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  5946.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  5946.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  5946.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  5946.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  5946.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  5947.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  5947.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  5947.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  5954.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  5954.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  5954.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  5954.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  5954.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  5954.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  5954.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  5954.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  5957.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  5957.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  5957.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5957.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5973.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  5973.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  5973.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  5973.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  5973.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5973.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5973.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  5973.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  5973.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5973.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5973.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  5973.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  5973.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  5973.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  5973.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  5973.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  5973.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  5973.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  5973.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  5973.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  5973.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  5973.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  5973.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5974.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5974.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8ae0]
>[  5974.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8ae0] width 1024 pitch 4096 (/4 1024)
>[  5974.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5974.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5974.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  5974.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  5974.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26461f0]
>[  5974.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26461f0] width 1024 pitch 4096 (/4 1024)
>[  5974.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  5974.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  5974.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5974.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5974.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  5974.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  5974.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5974.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5974.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  5974.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  5974.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258e650]
>[  5974.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258e650] width 1024 pitch 4096 (/4 1024)
>[  5974.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3530]
>[  5974.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3530] width 1024 pitch 4096 (/4 1024)
>[  5974.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e56b0]
>[  5974.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e56b0] width 1024 pitch 4096 (/4 1024)
>[  5974.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3530]
>[  5974.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3530] width 1024 pitch 4096 (/4 1024)
>[  5974.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e56b0]
>[  5974.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e56b0] width 1024 pitch 4096 (/4 1024)
>[  5974.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e3530]
>[  5974.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e3530] width 1024 pitch 4096 (/4 1024)
>[  5974.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e56b0]
>[  5974.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e56b0] width 1024 pitch 4096 (/4 1024)
>[  5976.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2645c00]
>[  5976.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2645c00] width 1024 pitch 4096 (/4 1024)
>[  5976.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b8d50]
>[  5976.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b8d50] width 1024 pitch 4096 (/4 1024)
>[  5977.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  5977.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  5981.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  5981.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  5981.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  5981.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  5988.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  5988.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  5988.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646c20]
>[  5988.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646c20] width 1024 pitch 4096 (/4 1024)
>[  5988.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2472990]
>[  5988.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2472990] width 1024 pitch 4096 (/4 1024)
>[  5988.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646c20]
>[  5988.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646c20] width 1024 pitch 4096 (/4 1024)
>[  6006.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6006.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6007.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  6007.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  6019.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  6019.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  6019.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  6019.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  6019.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6019.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6019.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26476f0]
>[  6019.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26476f0] width 1024 pitch 4096 (/4 1024)
>[  6020.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  6020.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  6021.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6b30]
>[  6021.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6b30] width 1024 pitch 4096 (/4 1024)
>[  6021.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6021.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6021.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6021.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6059.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6059.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6059.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3b50]
>[  6059.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3b50] width 1024 pitch 4096 (/4 1024)
>[  6064.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  6064.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  6064.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  6064.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  6064.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6064.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  6064.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  6064.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6064.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6065.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6065.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6065.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6065.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6065.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6091.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269be60]
>[  6091.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269be60] width 1024 pitch 4096 (/4 1024)
>[  6091.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  6091.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  6091.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  6091.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  6091.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2591fb0]
>[  6091.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2591fb0] width 1024 pitch 4096 (/4 1024)
>[  6093.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  6093.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  6093.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f81b0]
>[  6093.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f81b0] width 1024 pitch 4096 (/4 1024)
>[  6093.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  6093.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  6093.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6093.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6134.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6134.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6135.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  6135.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  6135.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6c40]
>[  6135.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6c40] width 1024 pitch 4096 (/4 1024)
>[  6135.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6135.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6138.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558780]
>[  6138.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558780] width 1024 pitch 4096 (/4 1024)
>[  6138.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556d70]
>[  6138.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556d70] width 1024 pitch 4096 (/4 1024)
>[  6138.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556e30]
>[  6138.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556e30] width 1024 pitch 4096 (/4 1024)
>[  6138.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556e30]
>[  6138.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556e30] width 1024 pitch 4096 (/4 1024)
>[  6138.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6138.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6138.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6138.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6138.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6141.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25555d0]
>[  6141.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25555d0] width 1024 pitch 4096 (/4 1024)
>[  6141.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556910]
>[  6141.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556910] width 1024 pitch 4096 (/4 1024)
>[  6141.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6141.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6141.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25555d0]
>[  6141.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25555d0] width 1024 pitch 4096 (/4 1024)
>[  6141.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556910]
>[  6141.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556910] width 1024 pitch 4096 (/4 1024)
>[  6141.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6141.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6141.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25314d0]
>[  6141.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25314d0] width 1024 pitch 4096 (/4 1024)
>[  6141.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556910]
>[  6141.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556910] width 1024 pitch 4096 (/4 1024)
>[  6141.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2555490]
>[  6141.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2555490] width 1024 pitch 4096 (/4 1024)
>[  6141.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2555490]
>[  6141.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2555490] width 1024 pitch 4096 (/4 1024)
>[  6141.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2531310]
>[  6141.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2531310] width 1024 pitch 4096 (/4 1024)
>[  6141.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2556910]
>[  6141.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2556910] width 1024 pitch 4096 (/4 1024)
>[  6141.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6141.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6141.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2555490]
>[  6141.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2555490] width 1024 pitch 4096 (/4 1024)
>[  6141.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2531390]
>[  6141.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2531390] width 1024 pitch 4096 (/4 1024)
>[  6141.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25314d0]
>[  6141.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25314d0] width 1024 pitch 4096 (/4 1024)
>[  6141.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6141.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6141.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2531310]
>[  6141.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2531310] width 1024 pitch 4096 (/4 1024)
>[  6143.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259e770]
>[  6143.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259e770] width 1024 pitch 4096 (/4 1024)
>[  6143.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2598220]
>[  6143.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2598220] width 1024 pitch 4096 (/4 1024)
>[  6143.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25986f0]
>[  6143.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25986f0] width 1024 pitch 4096 (/4 1024)
>[  6143.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f3270]
>[  6143.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f3270] width 1024 pitch 4096 (/4 1024)
>[  6143.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6143.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6143.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2701680]
>[  6143.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2701680] width 1024 pitch 4096 (/4 1024)
>[  6143.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6143.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6143.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2701680]
>[  6143.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2701680] width 1024 pitch 4096 (/4 1024)
>[  6143.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6143.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6143.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2701680]
>[  6143.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2701680] width 1024 pitch 4096 (/4 1024)
>[  6143.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6143.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6144.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25986f0]
>[  6144.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25986f0] width 1024 pitch 4096 (/4 1024)
>[  6144.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6144.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6144.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25986f0]
>[  6144.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25986f0] width 1024 pitch 4096 (/4 1024)
>[  6144.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6144.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6144.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25986f0]
>[  6144.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25986f0] width 1024 pitch 4096 (/4 1024)
>[  6144.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6144.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6144.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25986f0]
>[  6144.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25986f0] width 1024 pitch 4096 (/4 1024)
>[  6144.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  6144.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  6145.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6145.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6145.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6145.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6145.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6145.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6145.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6145.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6145.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d350]
>[  6145.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d350] width 1024 pitch 4096 (/4 1024)
>[  6145.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2532aa0]
>[  6145.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2532aa0] width 1024 pitch 4096 (/4 1024)
>[  6146.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2543300]
>[  6146.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2543300] width 1024 pitch 4096 (/4 1024)
>[  6148.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6148.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6148.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259d400]
>[  6148.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259d400] width 1024 pitch 4096 (/4 1024)
>[  6148.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6148.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6158.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  6158.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  6158.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6158.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6158.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2598430]
>[  6158.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2598430] width 1024 pitch 4096 (/4 1024)
>[  6158.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6158.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6162.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6162.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6162.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6c40]
>[  6162.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6c40] width 1024 pitch 4096 (/4 1024)
>[  6162.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6162.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6162.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29b90a0]
>[  6162.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29b90a0] width 1024 pitch 4096 (/4 1024)
>[  6269.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260ffc0]
>[  6269.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260ffc0] width 1024 pitch 4096 (/4 1024)
>[  6274.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8c40]
>[  6274.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8c40] width 1024 pitch 4096 (/4 1024)
>[  6274.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f2a0]
>[  6275.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f2a0] width 1024 pitch 4096 (/4 1024)
>[  6275.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e740]
>[  6275.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e740] width 1024 pitch 4096 (/4 1024)
>[  6275.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d7600]
>[  6275.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d7600] width 1024 pitch 4096 (/4 1024)
>[  6275.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f490]
>[  6275.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f490] width 1024 pitch 4096 (/4 1024)
>[  6275.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f490]
>[  6275.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f490] width 1024 pitch 4096 (/4 1024)
>[  6275.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f2a0]
>[  6275.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f2a0] width 1024 pitch 4096 (/4 1024)
>[  6275.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f2a0]
>[  6275.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f2a0] width 1024 pitch 4096 (/4 1024)
>[  6275.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8a10]
>[  6275.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8a10] width 1024 pitch 4096 (/4 1024)
>[  6275.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25592b0]
>[  6275.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25592b0] width 1024 pitch 4096 (/4 1024)
>[  6275.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8a10]
>[  6275.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8a10] width 1024 pitch 4096 (/4 1024)
>[  6282.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a44e0]
>[  6282.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a44e0] width 1024 pitch 4096 (/4 1024)
>[  6282.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4290]
>[  6282.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4290] width 1024 pitch 4096 (/4 1024)
>[  6282.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  6282.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  6282.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d74f0]
>[  6282.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d74f0] width 1024 pitch 4096 (/4 1024)
>[  6282.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4290]
>[  6282.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4290] width 1024 pitch 4096 (/4 1024)
>[  6282.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2695810]
>[  6282.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2695810] width 1024 pitch 4096 (/4 1024)
>[  6282.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa380]
>[  6282.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa380] width 1024 pitch 4096 (/4 1024)
>[  6282.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa380]
>[  6282.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa380] width 1024 pitch 4096 (/4 1024)
>[  6282.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  6282.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  6282.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4550]
>[  6282.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4550] width 1024 pitch 4096 (/4 1024)
>[  6282.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa380]
>[  6282.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa380] width 1024 pitch 4096 (/4 1024)
>[  6282.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2695810]
>[  6282.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2695810] width 1024 pitch 4096 (/4 1024)
>[  6282.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fa380]
>[  6282.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fa380] width 1024 pitch 4096 (/4 1024)
>[  6282.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2695810]
>[  6282.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2695810] width 1024 pitch 4096 (/4 1024)
>[  6282.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4550]
>[  6282.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4550] width 1024 pitch 4096 (/4 1024)
>[  6282.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2695810]
>[  6282.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2695810] width 1024 pitch 4096 (/4 1024)
>[  6282.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  6282.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  6282.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  6282.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  6282.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  6282.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  6283.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  6283.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  6284.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6284.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6285.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  6285.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  6285.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  6285.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  6312.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9aa0]
>[  6312.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9aa0] width 1024 pitch 4096 (/4 1024)
>[  6314.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  6314.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  6314.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9aa0]
>[  6314.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9aa0] width 1024 pitch 4096 (/4 1024)
>[  6404.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1de6940]
>[  6404.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1de6940] width 1024 pitch 4096 (/4 1024)
>[  6404.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d92a0]
>[  6404.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d92a0] width 1024 pitch 4096 (/4 1024)
>[  6404.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  6404.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  6404.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  6404.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  6415.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6415.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6415.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6415.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6415.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  6415.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  6415.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6415.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6465.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6465.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6466.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  6466.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  6466.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  6466.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  6466.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  6466.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  6473.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  6473.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  6473.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  6473.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  6473.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6473.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6473.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6473.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6475.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6475.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6475.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  6475.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  6475.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  6475.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  6475.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6475.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6482.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  6482.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  6482.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6482.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6482.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6482.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6482.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6482.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6491.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6491.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6493.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6493.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6493.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6493.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6493.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2555490]
>[  6493.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2555490] width 1024 pitch 4096 (/4 1024)
>[  6496.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2a20]
>[  6496.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2a20] width 1024 pitch 4096 (/4 1024)
>[  6498.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6498.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6499.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6499.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6500.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6500.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6500.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db500]
>[  6500.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db500] width 1024 pitch 4096 (/4 1024)
>[  6500.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529440]
>[  6500.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529440] width 1024 pitch 4096 (/4 1024)
>[  6504.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2748440]
>[  6504.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2748440] width 1024 pitch 4096 (/4 1024)
>[  6515.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25cc610]
>[  6515.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25cc610] width 1024 pitch 4096 (/4 1024)
>[  6547.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6547.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6470]
>[  6548.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6470] width 1024 pitch 4096 (/4 1024)
>[  6548.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6548.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6548.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6548.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6548.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6548.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6548.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6548.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25597d0]
>[  6548.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25597d0] width 1024 pitch 4096 (/4 1024)
>[  6549.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6549.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6551.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6551.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6551.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6551.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6552.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6490]
>[  6552.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6490] width 1024 pitch 4096 (/4 1024)
>[  6552.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6552.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6490]
>[  6552.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6490] width 1024 pitch 4096 (/4 1024)
>[  6552.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6552.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6490]
>[  6552.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6490] width 1024 pitch 4096 (/4 1024)
>[  6552.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6552.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6490]
>[  6552.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6490] width 1024 pitch 4096 (/4 1024)
>[  6552.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6552.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6552.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6552.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6552.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6552.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6552.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6552.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6605.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6605.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6606.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6606.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6607.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6607.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6607.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a84e0]
>[  6607.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a84e0] width 1024 pitch 4096 (/4 1024)
>[  6607.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6607.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6656.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6656.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6656.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6656.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6657.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6657.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6657.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6657.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6657.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6690]
>[  6657.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6690] width 1024 pitch 4096 (/4 1024)
>[  6657.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6690]
>[  6657.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6690] width 1024 pitch 4096 (/4 1024)
>[  6657.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6690]
>[  6657.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6690] width 1024 pitch 4096 (/4 1024)
>[  6657.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6657.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e6690]
>[  6657.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e6690] width 1024 pitch 4096 (/4 1024)
>[  6657.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6657.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6658.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6658.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6659.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6659.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6659.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6659.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6659.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6659.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6659.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6660.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6660.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6660.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6660.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6660.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6660.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6660.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6660.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6660.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6660.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6660.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6660.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6660.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6660.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6660.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6660.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6660.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6660.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6660.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6663.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f3d0]
>[  6663.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f3d0] width 1024 pitch 4096 (/4 1024)
>[  6663.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1f00]
>[  6663.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1f00] width 1024 pitch 4096 (/4 1024)
>[  6663.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6663.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6664.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6664.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6664.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6664.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6664.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6664.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6664.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6664.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6664.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6664.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6664.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6664.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6664.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  6664.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  6664.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6664.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  6664.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  6664.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6664.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6664.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6664.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6665.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6665.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6665.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2502010]
>[  6665.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2502010] width 1024 pitch 4096 (/4 1024)
>[  6665.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6665.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6665.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6665.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6665.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6665.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6665.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  6665.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  6665.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6665.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6715.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6715.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6716.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6716.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6716.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6716.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6716.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6716.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6716.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6716.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6716.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6716.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6716.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6716.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6716.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6716.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6716.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6716.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6716.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6717.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6717.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6717.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6717.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6718.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6718.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6718.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d5530]
>[  6718.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d5530] width 1024 pitch 4096 (/4 1024)
>[  6718.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f6fe0]
>[  6718.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f6fe0] width 1024 pitch 4096 (/4 1024)
>[  6718.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d5530]
>[  6718.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d5530] width 1024 pitch 4096 (/4 1024)
>[  6718.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f6fe0]
>[  6718.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f6fe0] width 1024 pitch 4096 (/4 1024)
>[  6718.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d5530]
>[  6718.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d5530] width 1024 pitch 4096 (/4 1024)
>[  6718.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f6fe0]
>[  6718.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f6fe0] width 1024 pitch 4096 (/4 1024)
>[  6718.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d33a0]
>[  6718.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d33a0] width 1024 pitch 4096 (/4 1024)
>[  6730.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6730.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6730.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6730.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6731.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6731.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6731.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6731.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6731.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6731.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6731.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6731.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6731.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6731.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6731.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6731.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6732.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6732.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6732.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6732.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6732.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6732.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6732.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6732.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6732.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd130]
>[  6732.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd130] width 1024 pitch 4096 (/4 1024)
>[  6733.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6733.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6733.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d5530]
>[  6733.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d5530] width 1024 pitch 4096 (/4 1024)
>[  6733.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6733.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6733.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6733.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6733.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6733.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6733.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6733.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6733.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6733.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6733.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6733.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6733.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6733.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6733.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6733.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6733.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6733.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6733.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6733.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6733.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6733.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6745.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  6745.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  6745.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6745.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6745.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6745.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6745.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6745.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6745.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6745.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6745.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6745.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6745.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6745.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6745.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6745.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6745.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6745.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6745.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6745.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6745.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6745.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6745.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6745.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6747.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6747.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6747.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6747.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6747.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  6747.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  6747.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6747.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6747.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6747.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6747.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6747.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6747.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6747.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6747.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6747.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6747.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6747.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6748.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6748.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6748.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6748.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6748.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6748.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6748.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6748.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6748.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6748.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6748.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6748.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6748.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  6748.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  6748.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6748.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6756.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  6756.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  6756.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  6756.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  6757.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  6757.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  6757.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  6757.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  6757.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6757.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6757.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6757.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6757.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6757.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6757.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6757.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  6757.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  6758.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  6758.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  6759.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  6759.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  6760.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  6760.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  6761.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6761.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6761.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  6761.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  6761.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  6761.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  6761.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  6761.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  6761.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  6761.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  6761.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  6761.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  6761.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a5a00]
>[  6761.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a5a00] width 1024 pitch 4096 (/4 1024)
>[  6761.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  6761.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  6761.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  6761.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  6761.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  6761.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  6761.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  6761.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  6830.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fc9e0]
>[  6830.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fc9e0] width 1024 pitch 4096 (/4 1024)
>[  6831.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x254f8e0]
>[  6831.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x254f8e0] width 1024 pitch 4096 (/4 1024)
>[  6850.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdbe0]
>[  6850.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdbe0] width 1024 pitch 4096 (/4 1024)
>[  7003.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7770]
>[  7003.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7770] width 1024 pitch 4096 (/4 1024)
>[  7003.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  7003.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  7003.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7003.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7003.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  7003.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  7003.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7003.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7003.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  7003.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  7003.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7003.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7003.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7003.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7003.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25573b0]
>[  7003.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25573b0] width 1024 pitch 4096 (/4 1024)
>[  7003.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7003.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7003.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7003.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7003.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c7310]
>[  7003.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c7310] width 1024 pitch 4096 (/4 1024)
>[  7003.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7003.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7003.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7003.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7104.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7104.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7104.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7104.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7104.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  7104.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  7104.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  7104.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  7104.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  7104.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  7105.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7105.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7105.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7105.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7105.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7105.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7105.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7105.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7106.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  7106.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  7106.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  7106.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  7107.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c3d20]
>[  7107.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c3d20] width 1024 pitch 4096 (/4 1024)
>[  7107.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  7107.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  7107.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7107.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7107.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  7107.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  7107.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7107.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7107.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7107.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7107.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  7107.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  7214.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7214.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7215.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0fd0]
>[  7215.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0fd0] width 1024 pitch 4096 (/4 1024)
>[  7215.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7215.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7215.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7215.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7261.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7261.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7261.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f6fe0]
>[  7261.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f6fe0] width 1024 pitch 4096 (/4 1024)
>[  7262.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7262.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7262.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7262.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7262.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7263.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7263.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7263.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646610]
>[  7263.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646610] width 1024 pitch 4096 (/4 1024)
>[  7264.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7264.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7264.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7264.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7264.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7264.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7264.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7264.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7264.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7264.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7264.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7264.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7264.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7264.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7264.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7264.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7264.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7264.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7264.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7264.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7264.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7264.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7267.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7267.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7268.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7268.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7268.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7268.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7268.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7268.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7268.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7268.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7268.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7268.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7268.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7268.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7268.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7268.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7268.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7268.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7268.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7268.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7269.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4660]
>[  7269.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4660] width 1024 pitch 4096 (/4 1024)
>[  7269.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7269.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7269.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2bb0]
>[  7269.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2bb0] width 1024 pitch 4096 (/4 1024)
>[  7270.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7270.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7270.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7270.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7270.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  7270.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  7270.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7270.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7270.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7270.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7306.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7306.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7306.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745de0]
>[  7306.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745de0] width 1024 pitch 4096 (/4 1024)
>[  7306.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7306.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7306.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745de0]
>[  7306.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745de0] width 1024 pitch 4096 (/4 1024)
>[  7306.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7306.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7306.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745de0]
>[  7306.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745de0] width 1024 pitch 4096 (/4 1024)
>[  7306.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7306.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7306.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745de0]
>[  7306.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745de0] width 1024 pitch 4096 (/4 1024)
>[  7306.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7306.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7306.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745de0]
>[  7306.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745de0] width 1024 pitch 4096 (/4 1024)
>[  7306.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7306.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7306.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7306.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7307.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7307.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7308.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7308.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7308.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7308.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7308.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7308.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7308.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7308.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7308.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7308.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7308.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7308.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7308.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7308.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7308.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7311.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7311.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7311.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  7311.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  7312.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7312.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7312.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7312.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7314.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c81d0]
>[  7314.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c81d0] width 1024 pitch 4096 (/4 1024)
>[  7314.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7314.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7314.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7314.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7314.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7314.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7314.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7314.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7314.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7314.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7314.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7314.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7314.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7314.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7314.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7314.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7314.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7314.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7314.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7314.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7314.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7314.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7314.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7314.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7314.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7314.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7315.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7315.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7315.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7315.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7316.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7316.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7316.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7316.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7316.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7316.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7316.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7316.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7316.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2b50]
>[  7316.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2b50] width 1024 pitch 4096 (/4 1024)
>[  7316.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7316.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7316.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7316.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7316.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2b50]
>[  7316.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2b50] width 1024 pitch 4096 (/4 1024)
>[  7316.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7316.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7316.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7316.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7316.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2b50]
>[  7316.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2b50] width 1024 pitch 4096 (/4 1024)
>[  7332.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7332.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7333.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7333.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7333.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d2b50]
>[  7333.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d2b50] width 1024 pitch 4096 (/4 1024)
>[  7333.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7333.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7333.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7333.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7347.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7347.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7347.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7347.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7347.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7347.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7347.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7347.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7349.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe130]
>[  7349.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe130] width 1024 pitch 4096 (/4 1024)
>[  7349.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7349.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7349.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7349.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7349.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7349.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7510.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7510.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7510.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7510.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7511.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7511.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7511.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7511.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7511.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7511.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7512.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7512.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7513.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7513.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7513.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7513.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7513.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  7513.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  7513.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7513.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7513.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  7513.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  7513.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7513.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7513.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4530]
>[  7513.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4530] width 1024 pitch 4096 (/4 1024)
>[  7513.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7513.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7531.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7531.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7532.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7532.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7532.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7532.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7532.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7532.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7532.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7532.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7532.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7532.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7532.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7532.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7532.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7532.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7532.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7532.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7532.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7533.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7533.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7533.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7533.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7533.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7533.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7533.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7533.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7533.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7533.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7533.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7533.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7533.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7533.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7533.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7533.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7533.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7533.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7533.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7533.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7533.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7533.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7533.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430cc0]
>[  7533.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430cc0] width 1024 pitch 4096 (/4 1024)
>[  7584.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7584.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7584.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7584.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7584.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7584.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7585.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7585.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7585.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7585.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7585.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7585.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7585.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7585.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7585.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7585.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7585.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7585.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7587.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7587.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7587.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7587.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7588.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7588.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7589.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6f70]
>[  7589.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6f70] width 1024 pitch 4096 (/4 1024)
>[  7590.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7590.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7590.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7590.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7590.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7590.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7590.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a1bf0]
>[  7590.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a1bf0] width 1024 pitch 4096 (/4 1024)
>[  7590.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a97c0]
>[  7590.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a97c0] width 1024 pitch 4096 (/4 1024)
>[  7590.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558800]
>[  7590.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558800] width 1024 pitch 4096 (/4 1024)
>[  7668.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  7668.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  7671.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7671.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7671.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dd8d0]
>[  7671.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dd8d0] width 1024 pitch 4096 (/4 1024)
>[  7671.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7671.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7671.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7671.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7671.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  7672.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  7672.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  7673.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7673.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7673.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7673.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7674.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  7674.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  7674.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7674.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7674.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  7674.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  7674.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb540]
>[  7674.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb540] width 1024 pitch 4096 (/4 1024)
>[  7674.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  7674.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  7674.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dd8d0]
>[  7674.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dd8d0] width 1024 pitch 4096 (/4 1024)
>[  7674.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca80]
>[  7674.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca80] width 1024 pitch 4096 (/4 1024)
>[  7674.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dd8d0]
>[  7674.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dd8d0] width 1024 pitch 4096 (/4 1024)
>[  7674.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca80]
>[  7674.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca80] width 1024 pitch 4096 (/4 1024)
>[  7674.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26dd8d0]
>[  7674.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26dd8d0] width 1024 pitch 4096 (/4 1024)
>[  7674.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca80]
>[  7674.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca80] width 1024 pitch 4096 (/4 1024)
>[  7674.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7674.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7681.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  7681.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  7681.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7681.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7681.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7681.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7681.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  7681.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  7681.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7681.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7681.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7681.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7681.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7681.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7681.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7681.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7681.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7682.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7682.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7682.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7682.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7682.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7682.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7682.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7682.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7682.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7689.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  7689.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  7689.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7689.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7690.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca80]
>[  7690.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca80] width 1024 pitch 4096 (/4 1024)
>[  7690.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  7690.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  7690.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7690.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7690.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  7690.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  7690.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7690.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7690.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde4a0]
>[  7690.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde4a0] width 1024 pitch 4096 (/4 1024)
>[  7690.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7690.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7690.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  7690.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  7690.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7690.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7690.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7690.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7690.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7690.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7690.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7690.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7690.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7690.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7690.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7690.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7690.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7690.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7690.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270c300]
>[  7690.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270c300] width 1024 pitch 4096 (/4 1024)
>[  7690.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a40e0]
>[  7690.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a40e0] width 1024 pitch 4096 (/4 1024)
>[  7691.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  7691.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  7692.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7692.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7693.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  7693.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  7693.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7693.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7693.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7693.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7693.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7693.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7693.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7693.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7693.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7693.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7693.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7693.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7693.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7693.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7693.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7693.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7693.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  7693.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  7693.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  7693.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  7697.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  7697.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  7698.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  7698.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  7698.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7698.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7698.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7698.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7698.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7698.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7698.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7698.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7698.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7698.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7698.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7698.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7698.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7698.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7698.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  7698.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  7698.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  7698.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  7698.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb540]
>[  7698.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb540] width 1024 pitch 4096 (/4 1024)
>[  7698.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  7698.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  7698.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7698.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7699.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d1440]
>[  7699.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d1440] width 1024 pitch 4096 (/4 1024)
>[  7699.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  7699.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  7699.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  7699.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  7699.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7699.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7699.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  7699.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  7699.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7699.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7699.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  7699.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  7699.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7699.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7699.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  7699.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  7699.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  7699.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  7699.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  7699.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  7704.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  7704.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  7710.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e74a0]
>[  7710.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e74a0] width 1024 pitch 4096 (/4 1024)
>[  7718.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4490]
>[  7718.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4490] width 1024 pitch 4096 (/4 1024)
>[  7718.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f6300]
>[  7718.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f6300] width 1024 pitch 4096 (/4 1024)
>[  7725.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2696a50]
>[  7725.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2696a50] width 1024 pitch 4096 (/4 1024)
>[  7725.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3d00]
>[  7725.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3d00] width 1024 pitch 4096 (/4 1024)
>[  7725.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f660]
>[  7725.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f660] width 1024 pitch 4096 (/4 1024)
>[  7739.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253b7d0]
>[  7739.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253b7d0] width 1024 pitch 4096 (/4 1024)
>[  7754.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26967a0]
>[  7754.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26967a0] width 1024 pitch 4096 (/4 1024)
>[  7754.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7754.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498230]
>[  7755.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498230] width 1024 pitch 4096 (/4 1024)
>[  7755.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7755.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  7755.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  7755.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7755.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  7755.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  7755.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7755.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  7755.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  7755.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498130]
>[  7755.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498130] width 1024 pitch 4096 (/4 1024)
>[  7755.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7755.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2696800]
>[  7755.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2696800] width 1024 pitch 4096 (/4 1024)
>[  7755.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26abb80]
>[  7755.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26abb80] width 1024 pitch 4096 (/4 1024)
>[  7755.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2696800]
>[  7755.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2696800] width 1024 pitch 4096 (/4 1024)
>[  7756.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x270f610]
>[  7756.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x270f610] width 1024 pitch 4096 (/4 1024)
>[  7757.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2512300]
>[  7757.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2512300] width 1024 pitch 4096 (/4 1024)
>[  7757.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253ba40]
>[  7757.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253ba40] width 1024 pitch 4096 (/4 1024)
>[  7757.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253ba40]
>[  7757.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253ba40] width 1024 pitch 4096 (/4 1024)
>[  7757.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  7757.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  7757.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7757.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7757.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  7757.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  7757.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7757.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7757.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  7757.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  7761.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7761.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7761.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253ba60]
>[  7761.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253ba60] width 1024 pitch 4096 (/4 1024)
>[  7761.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259cab0]
>[  7761.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259cab0] width 1024 pitch 4096 (/4 1024)
>[  7762.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7762.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3e20]
>[  7762.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3e20] width 1024 pitch 4096 (/4 1024)
>[  7762.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7762.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7763.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3ca0]
>[  7763.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3ca0] width 1024 pitch 4096 (/4 1024)
>[  7764.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253b7e0]
>[  7764.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253b7e0] width 1024 pitch 4096 (/4 1024)
>[  7764.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253b7e0]
>[  7764.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253b7e0] width 1024 pitch 4096 (/4 1024)
>[  7764.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2498450]
>[  7764.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2498450] width 1024 pitch 4096 (/4 1024)
>[  7796.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2536e60]
>[  7796.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2536e60] width 1024 pitch 4096 (/4 1024)
>[  7798.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d7e30]
>[  7798.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d7e30] width 1024 pitch 4096 (/4 1024)
>[  7798.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2536a70]
>[  7798.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2536a70] width 1024 pitch 4096 (/4 1024)
>[  7841.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26110e0]
>[  7841.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26110e0] width 1024 pitch 4096 (/4 1024)
>[  7895.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278a2e0]
>[  7895.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278a2e0] width 1024 pitch 4096 (/4 1024)
>[  7895.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2610d60]
>[  7895.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2610d60] width 1024 pitch 4096 (/4 1024)
>[  7895.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2789f80]
>[  7895.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2789f80] width 1024 pitch 4096 (/4 1024)
>[  7895.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x268db30]
>[  7895.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x268db30] width 1024 pitch 4096 (/4 1024)
>[  7902.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25519c0]
>[  7902.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25519c0] width 1024 pitch 4096 (/4 1024)
>[  7904.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  7904.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  7904.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  7905.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  7905.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[  7905.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[  7905.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  7905.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  7905.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244f590]
>[  7905.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244f590] width 1024 pitch 4096 (/4 1024)
>[  7905.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7905.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7905.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7905.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7905.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7905.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7905.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7905.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7905.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cd9e0]
>[  7905.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cd9e0] width 1024 pitch 4096 (/4 1024)
>[  7905.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  7905.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  7907.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e4390]
>[  7907.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e4390] width 1024 pitch 4096 (/4 1024)
>[  7908.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  7908.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  7908.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7908.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7908.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7908.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7908.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7908.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7908.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7908.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7908.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7908.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7908.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7908.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7908.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7908.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  7908.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  7908.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[  7908.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[  7944.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7944.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7944.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7944.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7944.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7944.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7944.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  7944.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  7944.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  7944.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  7944.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7944.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7944.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7944.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7944.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7944.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7944.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7944.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7944.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7944.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7944.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7944.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7944.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7944.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7944.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7944.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7944.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  7944.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  7944.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529ba0]
>[  7944.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529ba0] width 1024 pitch 4096 (/4 1024)
>[  7945.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  7945.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  7946.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  7946.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  7946.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  7946.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  7946.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  7946.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  7946.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  7946.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  8261.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ac3e0]
>[  8261.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ac3e0] width 1024 pitch 4096 (/4 1024)
>[  8261.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  8261.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  8262.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb540]
>[  8262.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb540] width 1024 pitch 4096 (/4 1024)
>[  8262.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2527ea0]
>[  8262.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2527ea0] width 1024 pitch 4096 (/4 1024)
>[  8262.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8262.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8262.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8262.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8262.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8262.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8263.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a5610]
>[  8263.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a5610] width 1024 pitch 4096 (/4 1024)
>[  8263.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8263.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8263.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8263.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8263.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8263.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8263.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8263.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8263.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8263.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8263.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8263.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8263.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8263.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8263.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8264.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8264.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8264.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8264.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8264.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8264.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8264.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8264.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  8264.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  8321.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8321.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8321.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8321.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8321.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8325.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8325.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8325.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ce930]
>[  8325.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ce930] width 1024 pitch 4096 (/4 1024)
>[  8326.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8326.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8326.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8326.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8326.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8326.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  8326.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  8326.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1e40]
>[  8326.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1e40] width 1024 pitch 4096 (/4 1024)
>[  8476.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  8476.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  8477.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8477.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8477.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8477.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8477.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  8477.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  8477.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  8477.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  8519.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8519.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8520.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8520.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8520.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8520.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8521.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8521.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8521.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2745f30]
>[  8521.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2745f30] width 1024 pitch 4096 (/4 1024)
>[  8521.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8521.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8522.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244edf0]
>[  8522.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244edf0] width 1024 pitch 4096 (/4 1024)
>[  8522.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8522.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8522.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  8522.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  8522.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8522.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8522.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  8522.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  8522.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8522.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8522.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  8522.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  8522.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8522.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8522.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  8522.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  8522.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  8522.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  8955.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f0a60]
>[  8955.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f0a60] width 1024 pitch 4096 (/4 1024)
>[  8955.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  8955.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  8956.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8956.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8956.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8956.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8956.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8957.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8957.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8957.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  8957.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  8957.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8957.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8958.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[  8958.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[  8958.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8958.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8958.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8958.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8958.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8958.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8958.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8958.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8958.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8958.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8958.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8958.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8958.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8958.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8958.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8958.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  8958.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  8970.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  8970.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  8970.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  8970.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  8970.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  8970.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  8970.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  8970.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  8970.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  8970.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  8970.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  8970.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  8970.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  8970.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  8970.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8970.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8971.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24300f0]
>[  8971.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24300f0] width 1024 pitch 4096 (/4 1024)
>[  8971.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269a6d0]
>[  8971.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269a6d0] width 1024 pitch 4096 (/4 1024)
>[  8971.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24300f0]
>[  8971.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24300f0] width 1024 pitch 4096 (/4 1024)
>[  8971.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25108c0]
>[  8971.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25108c0] width 1024 pitch 4096 (/4 1024)
>[  8971.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8971.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8971.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ca110]
>[  8971.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ca110] width 1024 pitch 4096 (/4 1024)
>[  8971.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  8972.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  8972.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8972.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8972.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  8972.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  8972.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  8972.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  8972.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4400]
>[  8972.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4400] width 1024 pitch 4096 (/4 1024)
>[  9041.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9041.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9041.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9041.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9041.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9042.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9042.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9042.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9042.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9042.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9042.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9042.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9042.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9042.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9042.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9042.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9042.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9042.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9042.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9042.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9042.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9042.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9042.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9042.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9042.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9042.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9043.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9046.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9046.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9046.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9046.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9046.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9047.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9047.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9047.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9047.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9047.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[  9047.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[  9047.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9047.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9048.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9048.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9048.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2591d20]
>[  9048.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2591d20] width 1024 pitch 4096 (/4 1024)
>[  9048.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca60]
>[  9048.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca60] width 1024 pitch 4096 (/4 1024)
>[  9048.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2591d20]
>[  9048.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2591d20] width 1024 pitch 4096 (/4 1024)
>[  9048.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca60]
>[  9048.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca60] width 1024 pitch 4096 (/4 1024)
>[  9048.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2591d20]
>[  9048.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2591d20] width 1024 pitch 4096 (/4 1024)
>[  9048.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca60]
>[  9048.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca60] width 1024 pitch 4096 (/4 1024)
>[  9048.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2591d20]
>[  9048.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2591d20] width 1024 pitch 4096 (/4 1024)
>[  9048.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25eca60]
>[  9048.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25eca60] width 1024 pitch 4096 (/4 1024)
>[  9119.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9119.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9119.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  9119.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  9119.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  9119.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  9119.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  9119.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  9119.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639d10]
>[  9119.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639d10] width 1024 pitch 4096 (/4 1024)
>[  9119.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  9119.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  9119.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9119.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9119.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25b6b10]
>[  9119.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25b6b10] width 1024 pitch 4096 (/4 1024)
>[  9119.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9119.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9119.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26043f0]
>[  9119.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26043f0] width 1024 pitch 4096 (/4 1024)
>[  9119.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[  9119.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[  9119.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[  9119.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[  9119.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9119.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9119.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2696610]
>[  9119.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2696610] width 1024 pitch 4096 (/4 1024)
>[  9119.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[  9119.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[  9120.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9120.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9120.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[  9120.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[  9120.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9120.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9120.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[  9120.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[  9121.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e5030]
>[  9121.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e5030] width 1024 pitch 4096 (/4 1024)
>[  9121.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  9121.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  9121.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  9121.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  9121.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9121.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9121.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  9121.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  9121.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9121.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9121.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  9121.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  9121.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9121.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9121.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  9121.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  9121.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9121.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9121.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9121.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9153.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9153.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9154.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9154.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9154.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9154.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9157.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9157.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9157.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9157.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9157.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9157.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9157.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9157.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9157.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9157.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9157.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9157.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9157.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9157.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9157.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9157.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9157.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9157.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9177.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  9177.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  9177.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b1850]
>[  9177.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b1850] width 1024 pitch 4096 (/4 1024)
>[  9177.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9177.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9177.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9177.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9177.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9177.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9177.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9177.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9177.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9177.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9178.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9178.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9178.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9178.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9178.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e4250]
>[  9178.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e4250] width 1024 pitch 4096 (/4 1024)
>[  9178.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a42f0]
>[  9178.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a42f0] width 1024 pitch 4096 (/4 1024)
>[  9178.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4a20]
>[  9178.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4a20] width 1024 pitch 4096 (/4 1024)
>[  9178.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9178.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9178.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9178.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9178.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9178.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9178.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  9178.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  9178.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9178.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9178.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  9178.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  9178.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9178.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9178.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  9178.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  9178.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9178.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9178.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  9178.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  9178.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9178.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9178.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9178.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9190.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9190.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9190.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9190.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9190.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9191.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9191.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9191.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9191.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9191.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9191.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9191.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e3da0]
>[  9191.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e3da0] width 1024 pitch 4096 (/4 1024)
>[  9191.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4290]
>[  9191.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4290] width 1024 pitch 4096 (/4 1024)
>[  9191.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9191.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9191.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a4290]
>[  9191.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a4290] width 1024 pitch 4096 (/4 1024)
>[  9191.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9191.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9191.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2511b60]
>[  9191.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2511b60] width 1024 pitch 4096 (/4 1024)
>[  9191.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9191.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9271.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9271.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9271.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9271.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9271.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9271.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9271.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9271.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9271.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9272.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9272.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9272.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9272.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9272.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9272.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9272.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273aa00]
>[  9272.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273aa00] width 1024 pitch 4096 (/4 1024)
>[  9272.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ded60]
>[  9272.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ded60] width 1024 pitch 4096 (/4 1024)
>[  9272.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9272.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9272.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9272.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9272.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9272.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9272.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9273.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9273.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  9273.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  9273.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26db200]
>[  9273.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26db200] width 1024 pitch 4096 (/4 1024)
>[  9273.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed790]
>[  9273.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed790] width 1024 pitch 4096 (/4 1024)
>[  9280.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9280.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9280.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9280.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9280.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9280.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9280.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9280.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9280.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9280.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9280.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9280.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9280.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9281.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9281.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9281.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9281.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9281.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9281.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9281.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9281.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9281.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9281.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9281.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9281.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x253bae0]
>[  9281.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x253bae0] width 1024 pitch 4096 (/4 1024)
>[  9281.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9282.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9282.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9282.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9282.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9282.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9282.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9282.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9282.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d8870]
>[  9282.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d8870] width 1024 pitch 4096 (/4 1024)
>[  9282.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9282.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9282.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9282.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9282.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9282.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9282.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9282.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9282.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e19f0]
>[  9282.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e19f0] width 1024 pitch 4096 (/4 1024)
>[  9390.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9390.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9390.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9390.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9390.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9390.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9390.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9391.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9391.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9391.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9391.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9391.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ba3e0]
>[  9391.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ba3e0] width 1024 pitch 4096 (/4 1024)
>[  9391.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9391.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9391.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9391.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9391.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9391.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9391.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  9391.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  9391.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9391.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9391.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  9391.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  9391.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9392.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9392.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e42d0]
>[  9392.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e42d0] width 1024 pitch 4096 (/4 1024)
>[  9392.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9392.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9392.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2529800]
>[  9392.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2529800] width 1024 pitch 4096 (/4 1024)
>[  9392.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  9392.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  9473.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9473.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9474.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9474.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9474.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9474.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9476.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9476.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9476.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9476.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9476.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[  9476.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[  9478.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[  9478.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[  9479.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2611010]
>[  9479.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2611010] width 1024 pitch 4096 (/4 1024)
>[  9482.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ad630]
>[  9482.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ad630] width 1024 pitch 4096 (/4 1024)
>[  9482.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ad950]
>[  9482.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ad950] width 1024 pitch 4096 (/4 1024)
>[  9482.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd160]
>[  9482.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd160] width 1024 pitch 4096 (/4 1024)
>[  9498.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25baee0]
>[  9498.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25baee0] width 1024 pitch 4096 (/4 1024)
>[  9498.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26cb340]
>[  9498.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26cb340] width 1024 pitch 4096 (/4 1024)
>[  9499.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2606b10]
>[  9499.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2606b10] width 1024 pitch 4096 (/4 1024)
>[  9499.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25430e0]
>[  9499.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25430e0] width 1024 pitch 4096 (/4 1024)
>[  9499.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9499.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9499.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  9499.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  9502.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4cc0]
>[  9502.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4cc0] width 1024 pitch 4096 (/4 1024)
>[  9502.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9502.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9502.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9502.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9502.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9502.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9503.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x260e920]
>[  9503.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x260e920] width 1024 pitch 4096 (/4 1024)
>[  9509.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fb540]
>[  9510.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fb540] width 1024 pitch 4096 (/4 1024)
>[  9510.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251f210]
>[  9510.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251f210] width 1024 pitch 4096 (/4 1024)
>[  9510.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x259dc00]
>[  9510.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x259dc00] width 1024 pitch 4096 (/4 1024)
>[  9510.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c4cc0]
>[  9510.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c4cc0] width 1024 pitch 4096 (/4 1024)
>[  9695.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9695.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9695.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9695.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9695.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9695.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9695.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9695.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9695.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9695.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9695.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9695.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9695.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9695.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9695.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9695.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9695.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9695.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9696.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9696.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9696.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9696.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9696.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9696.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9696.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9696.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9696.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9696.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9697.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[  9697.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[  9697.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  9697.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  9697.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1cde760]
>[  9697.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1cde760] width 1024 pitch 4096 (/4 1024)
>[  9697.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  9697.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  9697.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[  9697.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[  9697.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  9697.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  9697.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[  9697.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[  9697.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[  9697.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[  9697.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[  9697.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[  9701.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9701.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9701.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  9701.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  9701.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9701.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9701.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  9701.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  9701.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9701.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9701.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  9701.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  9701.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9701.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9701.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  9701.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  9701.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9701.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9701.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a16d0]
>[  9702.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a16d0] width 1024 pitch 4096 (/4 1024)
>[  9702.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x278f020]
>[  9702.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x278f020] width 1024 pitch 4096 (/4 1024)
>[  9702.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[  9702.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[  9702.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eb1c0]
>[  9702.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eb1c0] width 1024 pitch 4096 (/4 1024)
>[  9702.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x273b1e0]
>[  9702.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x273b1e0] width 1024 pitch 4096 (/4 1024)
>[  9702.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9702.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9702.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f5c70]
>[  9703.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f5c70] width 1024 pitch 4096 (/4 1024)
>[  9703.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9703.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9703.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f5c70]
>[  9703.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f5c70] width 1024 pitch 4096 (/4 1024)
>[  9703.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9703.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9703.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9703.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9703.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9703.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9703.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2639ba0]
>[  9703.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2639ba0] width 1024 pitch 4096 (/4 1024)
>[  9703.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9703.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9703.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524460]
>[  9703.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524460] width 1024 pitch 4096 (/4 1024)
>[  9871.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a03a0]
>[  9871.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a03a0] width 1024 pitch 4096 (/4 1024)
>[  9871.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2559040]
>[  9871.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2559040] width 1024 pitch 4096 (/4 1024)
>[  9871.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa4c0]
>[  9871.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa4c0] width 1024 pitch 4096 (/4 1024)
>[  9871.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa7a0]
>[  9871.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa7a0] width 1024 pitch 4096 (/4 1024)
>[  9871.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa4c0]
>[  9871.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa4c0] width 1024 pitch 4096 (/4 1024)
>[  9871.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa7a0]
>[  9871.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa7a0] width 1024 pitch 4096 (/4 1024)
>[  9871.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa4c0]
>[  9871.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa4c0] width 1024 pitch 4096 (/4 1024)
>[  9871.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa7a0]
>[  9871.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa7a0] width 1024 pitch 4096 (/4 1024)
>[  9871.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa4c0]
>[  9871.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa4c0] width 1024 pitch 4096 (/4 1024)
>[  9871.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26aa7a0]
>[  9871.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26aa7a0] width 1024 pitch 4096 (/4 1024)
>[  9872.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2645f20]
>[  9872.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2645f20] width 1024 pitch 4096 (/4 1024)
>[  9872.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9872.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9872.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9872.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9872.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9872.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9872.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9872.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9872.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9872.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9872.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9872.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9872.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9872.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9872.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9872.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9872.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9872.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9872.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[  9873.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[  9873.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9873.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a43f0]
>[  9873.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a43f0] width 1024 pitch 4096 (/4 1024)
>[  9873.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b2020]
>[  9873.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b2020] width 1024 pitch 4096 (/4 1024)
>[  9874.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25ec750]
>[  9874.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25ec750] width 1024 pitch 4096 (/4 1024)
>[  9874.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29e75f0]
>[  9874.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29e75f0] width 1024 pitch 4096 (/4 1024)
>[  9874.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c82d0]
>[  9874.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c82d0] width 1024 pitch 4096 (/4 1024)
>[  9875.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[  9875.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[  9875.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2540a50]
>[  9875.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2540a50] width 1024 pitch 4096 (/4 1024)
>[  9875.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24f48f0]
>[  9875.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24f48f0] width 1024 pitch 4096 (/4 1024)
>[  9881.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251d840]
>[  9881.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251d840] width 1024 pitch 4096 (/4 1024)
>[  9881.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x251d840]
>[  9881.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x251d840] width 1024 pitch 4096 (/4 1024)
>[  9881.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24ed9e0]
>[  9881.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24ed9e0] width 1024 pitch 4096 (/4 1024)
>[  9881.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df790]
>[  9881.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df790] width 1024 pitch 4096 (/4 1024)
>[  9881.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26b22a0]
>[  9881.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26b22a0] width 1024 pitch 4096 (/4 1024)
>[  9882.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2696350]
>[  9882.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2696350] width 1024 pitch 4096 (/4 1024)
>[  9882.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9882.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b73b0]
>[  9882.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b73b0] width 1024 pitch 4096 (/4 1024)
>[  9882.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[  9882.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[  9888.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d6c80]
>[  9888.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d6c80] width 1024 pitch 4096 (/4 1024)
>[ 10142.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04e0]
>[ 10142.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04e0] width 1024 pitch 4096 (/4 1024)
>[ 10142.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10142.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10143.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24abc10]
>[ 10143.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24abc10] width 1024 pitch 4096 (/4 1024)
>[ 10143.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[ 10143.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[ 10143.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24abc10]
>[ 10143.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24abc10] width 1024 pitch 4096 (/4 1024)
>[ 10143.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[ 10143.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[ 10143.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24abc10]
>[ 10143.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24abc10] width 1024 pitch 4096 (/4 1024)
>[ 10143.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[ 10143.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[ 10143.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24abc10]
>[ 10143.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24abc10] width 1024 pitch 4096 (/4 1024)
>[ 10144.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10144.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10144.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04e0]
>[ 10144.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04e0] width 1024 pitch 4096 (/4 1024)
>[ 10144.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10144.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10144.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04e0]
>[ 10144.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04e0] width 1024 pitch 4096 (/4 1024)
>[ 10144.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25be250]
>[ 10144.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25be250] width 1024 pitch 4096 (/4 1024)
>[ 10145.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04e0]
>[ 10145.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04e0] width 1024 pitch 4096 (/4 1024)
>[ 10146.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24abc10]
>[ 10146.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24abc10] width 1024 pitch 4096 (/4 1024)
>[ 10147.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a6f60]
>[ 10148.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a6f60] width 1024 pitch 4096 (/4 1024)
>[ 10148.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0820]
>[ 10148.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0820] width 1024 pitch 4096 (/4 1024)
>[ 10148.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0570]
>[ 10148.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0570] width 1024 pitch 4096 (/4 1024)
>[ 10148.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10148.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10148.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e0570]
>[ 10148.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e0570] width 1024 pitch 4096 (/4 1024)
>[ 10148.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10148.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10148.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10148.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10148.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10148.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10148.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10148.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10148.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10148.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10148.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10148.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10148.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26df730]
>[ 10148.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26df730] width 1024 pitch 4096 (/4 1024)
>[ 10148.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10148.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10155.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04b0]
>[ 10155.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04b0] width 1024 pitch 4096 (/4 1024)
>[ 10155.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10155.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10155.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25e04b0]
>[ 10155.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25e04b0] width 1024 pitch 4096 (/4 1024)
>[ 10155.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10155.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10155.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10155.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10156.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b78b0]
>[ 10156.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b78b0] width 1024 pitch 4096 (/4 1024)
>[ 10156.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10156.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10156.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10156.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10156.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10156.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10156.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10156.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10156.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10156.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10156.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10156.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10156.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10157.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10157.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2549b30]
>[ 10157.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2549b30] width 1024 pitch 4096 (/4 1024)
>[ 10157.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe080]
>[ 10157.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe080] width 1024 pitch 4096 (/4 1024)
>[ 10157.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d62c0]
>[ 10157.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d62c0] width 1024 pitch 4096 (/4 1024)
>[ 10157.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10157.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10157.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d62c0]
>[ 10157.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d62c0] width 1024 pitch 4096 (/4 1024)
>[ 10158.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430520]
>[ 10158.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430520] width 1024 pitch 4096 (/4 1024)
>[ 10158.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d62c0]
>[ 10158.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d62c0] width 1024 pitch 4096 (/4 1024)
>[ 10158.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2597fd0]
>[ 10158.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2597fd0] width 1024 pitch 4096 (/4 1024)
>[ 10159.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2597fd0]
>[ 10159.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2597fd0] width 1024 pitch 4096 (/4 1024)
>[ 10159.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2463f90]
>[ 10159.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2463f90] width 1024 pitch 4096 (/4 1024)
>[ 10159.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10159.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10159.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[ 10159.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[ 10159.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[ 10159.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[ 10159.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[ 10159.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[ 10159.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[ 10159.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[ 10159.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[ 10159.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[ 10159.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[ 10159.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[ 10159.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29eac40]
>[ 10159.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29eac40] width 1024 pitch 4096 (/4 1024)
>[ 10159.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a7d10]
>[ 10159.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a7d10] width 1024 pitch 4096 (/4 1024)
>[ 10160.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e44d0]
>[ 10160.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e44d0] width 1024 pitch 4096 (/4 1024)
>[ 10160.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x244b8a0]
>[ 10160.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x244b8a0] width 1024 pitch 4096 (/4 1024)
>[ 10160.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10160.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10160.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10160.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10160.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10160.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10160.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10160.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10160.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10160.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10160.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10160.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10160.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10160.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10160.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10160.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10160.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10161.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2646600]
>[ 10161.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2646600] width 1024 pitch 4096 (/4 1024)
>[ 10161.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26130b0]
>[ 10161.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26130b0] width 1024 pitch 4096 (/4 1024)
>[ 10161.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2524510]
>[ 10161.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2524510] width 1024 pitch 4096 (/4 1024)
>[ 10162.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0a50]
>[ 10162.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0a50] width 1024 pitch 4096 (/4 1024)
>[ 10162.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25a8e10]
>[ 10162.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25a8e10] width 1024 pitch 4096 (/4 1024)
>[ 10162.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f0870]
>[ 10162.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f0870] width 1024 pitch 4096 (/4 1024)
>[ 10162.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26e62f0]
>[ 10162.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26e62f0] width 1024 pitch 4096 (/4 1024)
>[ 10168.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24b9fc0]
>[ 10168.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24b9fc0] width 1024 pitch 4096 (/4 1024)
>[ 10168.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258b6b0]
>[ 10168.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258b6b0] width 1024 pitch 4096 (/4 1024)
>[ 10168.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258b6b0]
>[ 10168.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258b6b0] width 1024 pitch 4096 (/4 1024)
>[ 10168.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258b6b0]
>[ 10168.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258b6b0] width 1024 pitch 4096 (/4 1024)
>[ 10168.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258b6b0]
>[ 10168.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258b6b0] width 1024 pitch 4096 (/4 1024)
>[ 10168.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x258b6b0]
>[ 10168.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x258b6b0] width 1024 pitch 4096 (/4 1024)
>[ 10168.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[ 10168.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[ 10168.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[ 10168.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[ 10168.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26c43c0]
>[ 10168.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26c43c0] width 1024 pitch 4096 (/4 1024)
>[ 10168.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x1d93ed0]
>[ 10168.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x1d93ed0] width 1024 pitch 4096 (/4 1024)
>[ 10168.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d91e0]
>[ 10168.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d91e0] width 1024 pitch 4096 (/4 1024)
>[ 10169.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10169.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558450]
>[ 10169.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558450] width 1024 pitch 4096 (/4 1024)
>[ 10169.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2558530]
>[ 10169.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2558530] width 1024 pitch 4096 (/4 1024)
>[ 10175.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24d9c40]
>[ 10175.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24d9c40] width 1024 pitch 4096 (/4 1024)
>[ 10392.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da4d0]
>[ 10392.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da4d0] width 1024 pitch 4096 (/4 1024)
>[ 10392.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fe150]
>[ 10392.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fe150] width 1024 pitch 4096 (/4 1024)
>[ 10392.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[ 10392.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[ 10392.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3180]
>[ 10392.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3180] width 1024 pitch 4096 (/4 1024)
>[ 10392.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[ 10392.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[ 10393.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2430bf0]
>[ 10393.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2430bf0] width 1024 pitch 4096 (/4 1024)
>[ 10393.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3180]
>[ 10393.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3180] width 1024 pitch 4096 (/4 1024)
>[ 10393.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c8160]
>[ 10393.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c8160] width 1024 pitch 4096 (/4 1024)
>[ 10394.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10394.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10394.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10394.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10394.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10394.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10394.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10394.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10394.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10394.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10394.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10394.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10394.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10394.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10394.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10394.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10394.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10394.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10397.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10397.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10397.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10397.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10397.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10397.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10397.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10397.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10397.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10397.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10397.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10397.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10397.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2613ba0]
>[ 10397.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2613ba0] width 1024 pitch 4096 (/4 1024)
>[ 10397.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10397.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10398.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25946f0]
>[ 10398.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25946f0] width 1024 pitch 4096 (/4 1024)
>[ 10398.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26d8e60]
>[ 10398.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26d8e60] width 1024 pitch 4096 (/4 1024)
>[ 10398.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25946f0]
>[ 10399.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25946f0] width 1024 pitch 4096 (/4 1024)
>[ 10399.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25946f0]
>[ 10399.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25946f0] width 1024 pitch 4096 (/4 1024)
>[ 10493.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da360]
>[ 10493.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da360] width 1024 pitch 4096 (/4 1024)
>[ 10493.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4b50]
>[ 10493.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4b50] width 1024 pitch 4096 (/4 1024)
>[ 10493.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da360]
>[ 10493.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da360] width 1024 pitch 4096 (/4 1024)
>[ 10493.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4b50]
>[ 10493.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4b50] width 1024 pitch 4096 (/4 1024)
>[ 10493.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da360]
>[ 10493.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da360] width 1024 pitch 4096 (/4 1024)
>[ 10493.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4b50]
>[ 10493.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4b50] width 1024 pitch 4096 (/4 1024)
>[ 10493.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3180]
>[ 10493.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3180] width 1024 pitch 4096 (/4 1024)
>[ 10493.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26a4b50]
>[ 10493.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26a4b50] width 1024 pitch 4096 (/4 1024)
>[ 10493.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f3180]
>[ 10493.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f3180] width 1024 pitch 4096 (/4 1024)
>[ 10493.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25da360]
>[ 10493.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25da360] width 1024 pitch 4096 (/4 1024)
>[ 10493.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2539100]
>[ 10493.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2539100] width 1024 pitch 4096 (/4 1024)
>[ 10493.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2539160]
>[ 10493.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2539160] width 1024 pitch 4096 (/4 1024)
>[ 10498.078] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[ 10498.078] 
>[ 10498.078] Backtrace:
>[ 10498.394] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[ 10498.394] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x5514db]
>[ 10498.394] 2: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[ 10498.394] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f760ec8b000+0x60e4) [0x7f760ec910e4]
>[ 10498.394] 4: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[ 10498.394] 5: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[ 10498.394] 6: /lib64/libpthread.so.0 (0x30a4400000+0xefe0) [0x30a440efe0]
>[ 10498.394] 7: /lib64/libc.so.6 (ioctl+0x7) [0x30a40ea2f7]
>[ 10498.394] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x30bd0035f8]
>[ 10498.394] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x30bd00586c]
>[ 10498.450] 10: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x1e89) [0x7f76119ffe89]
>[ 10498.450] 11: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x20b4) [0x7f7611a000b4]
>[ 10498.450] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f7611c08000+0xacb4a) [0x7f7611cb4b4a]
>[ 10498.450] 13: /usr/lib64/xorg/modules/libexa.so (0x7f76111d5000+0xb007) [0x7f76111e0007]
>[ 10498.450] 14: /usr/bin/Xorg (0x400000+0x1604b3) [0x5604b3]
>[ 10498.450] 15: /usr/bin/Xorg (0x400000+0xc9d80) [0x4c9d80]
>[ 10498.450] 16: /usr/bin/Xorg (0x400000+0x3164a) [0x43164a]
>[ 10498.450] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[ 10498.450] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[ 10498.450] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x30a4021735]
>[ 10498.450] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[ 10498.450] 
>[ 10498.450] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[ 10498.450] [mi] mieq is *NOT* the cause.  It is a victim.
>[ 10503.831] [mi] EQ overflow continuing.  100 events have been dropped.
>[ 10503.831] 
>[ 10503.831] Backtrace:
>[ 10503.831] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[ 10503.831] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[ 10503.831] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f760ec8b000+0x60e4) [0x7f760ec910e4]
>[ 10503.831] 3: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[ 10503.831] 4: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[ 10503.831] 5: /lib64/libpthread.so.0 (0x30a4400000+0xefe0) [0x30a440efe0]
>[ 10503.831] 6: /lib64/libc.so.6 (ioctl+0x7) [0x30a40ea2f7]
>[ 10503.831] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x30bd0035f8]
>[ 10503.831] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x30bd00586c]
>[ 10503.831] 9: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x1e89) [0x7f76119ffe89]
>[ 10503.831] 10: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x20b4) [0x7f7611a000b4]
>[ 10503.831] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f7611c08000+0xacb4a) [0x7f7611cb4b4a]
>[ 10503.832] 12: /usr/lib64/xorg/modules/libexa.so (0x7f76111d5000+0xb007) [0x7f76111e0007]
>[ 10503.832] 13: /usr/bin/Xorg (0x400000+0x1604b3) [0x5604b3]
>[ 10503.832] 14: /usr/bin/Xorg (0x400000+0xc9d80) [0x4c9d80]
>[ 10503.832] 15: /usr/bin/Xorg (0x400000+0x3164a) [0x43164a]
>[ 10503.832] 16: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[ 10503.832] 17: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[ 10503.832] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x30a4021735]
>[ 10503.832] 19: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[ 10503.832] 
>[ 10504.239] [mi] EQ overflow continuing.  200 events have been dropped.
>[ 10504.239] 
>[ 10504.239] Backtrace:
>[ 10504.239] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[ 10504.239] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[ 10504.239] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f760ec8b000+0x60e4) [0x7f760ec910e4]
>[ 10504.239] 3: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[ 10504.239] 4: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[ 10504.239] 5: /lib64/libpthread.so.0 (0x30a4400000+0xefe0) [0x30a440efe0]
>[ 10504.239] 6: /lib64/libc.so.6 (ioctl+0x7) [0x30a40ea2f7]
>[ 10504.239] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x30bd0035f8]
>[ 10504.239] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x30bd00586c]
>[ 10504.239] 9: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x1e89) [0x7f76119ffe89]
>[ 10504.239] 10: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x20b4) [0x7f7611a000b4]
>[ 10504.239] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f7611c08000+0xacb4a) [0x7f7611cb4b4a]
>[ 10504.239] 12: /usr/lib64/xorg/modules/libexa.so (0x7f76111d5000+0xb007) [0x7f76111e0007]
>[ 10504.239] 13: /usr/bin/Xorg (0x400000+0x1604b3) [0x5604b3]
>[ 10504.239] 14: /usr/bin/Xorg (0x400000+0xc9d80) [0x4c9d80]
>[ 10504.239] 15: /usr/bin/Xorg (0x400000+0x3164a) [0x43164a]
>[ 10504.239] 16: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[ 10504.239] 17: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[ 10504.239] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x30a4021735]
>[ 10504.239] 19: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[ 10504.239] 
>[ 10504.671] [mi] EQ overflow continuing.  300 events have been dropped.
>[ 10504.671] 
>[ 10504.671] Backtrace:
>[ 10504.671] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6]
>[ 10504.671] 1: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32]
>[ 10504.671] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7f760ec8b000+0x60e4) [0x7f760ec910e4]
>[ 10504.671] 3: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7]
>[ 10504.671] 4: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0]
>[ 10504.671] 5: /lib64/libpthread.so.0 (0x30a4400000+0xefe0) [0x30a440efe0]
>[ 10504.671] 6: /lib64/libc.so.6 (ioctl+0x7) [0x30a40ea2f7]
>[ 10504.671] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x30bd0035f8]
>[ 10504.671] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x30bd00586c]
>[ 10504.671] 9: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x1e89) [0x7f76119ffe89]
>[ 10504.671] 10: /lib64/libdrm_radeon.so.1 (0x7f76119fe000+0x20b4) [0x7f7611a000b4]
>[ 10504.671] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f7611c08000+0xacb4a) [0x7f7611cb4b4a]
>[ 10504.671] 12: /usr/lib64/xorg/modules/libexa.so (0x7f76111d5000+0xb007) [0x7f76111e0007]
>[ 10504.671] 13: /usr/bin/Xorg (0x400000+0x1604b3) [0x5604b3]
>[ 10504.671] 14: /usr/bin/Xorg (0x400000+0xc9d80) [0x4c9d80]
>[ 10504.671] 15: /usr/bin/Xorg (0x400000+0x3164a) [0x43164a]
>[ 10504.671] 16: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a]
>[ 10504.671] 17: /usr/bin/Xorg (0x400000+0x23485) [0x423485]
>[ 10504.671] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x30a4021735]
>[ 10504.671] 19: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d]
>[ 10504.671]

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Attachments on bug 869872: 633130 | 633131 | 633132 | 633133