Attachment 638094 Details for Bug 872973 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 227.82 KB, created by danielecoccato on 2012-11-04 17:40:33 UTC

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Creator: danielecoccato

Created: 2012-11-04 17:40:33 UTC

Size: 227.82 KB

patch

obsolete

>[    34.028] 
>X.Org X Server 1.12.3
>Release Date: 2012-07-09
>[    34.028] X Protocol Version 11, Revision 0
>[    34.028] Build Operating System:  2.6.32-279.2.1.el6.x86_64 
>[    34.029] Current Operating System: Linux NB550D 3.6.3-1.fc17.i686 #1 SMP Mon Oct 22 16:10:29 UTC 2012 i686
>[    34.029] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.3-1.fc17.i686 root=/dev/mapper/vg_nb550d-lv_root ro rd.md=0 rd.dm=0 SYSFONT=True rd.lvm.lv=vg_nb550d/lv_root rd.luks=0 rd.lvm.lv=vg_nb550d/lv_swap KEYTABLE=it LANG=en_US.UTF-8 rhgb quiet
>[    34.029] Build Date: 20 September 2012  07:52:02AM
>[    34.029] Build ID: xorg-x11-server 1.12.3-2.fc17 
>[    34.029] Current version of pixman: 0.24.4
>[    34.029] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    34.030] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    34.030] (==) Log file: "/var/log/Xorg.0.log", Time: Sun Nov  4 01:16:34 2012
>[    34.047] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    34.047] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    34.048] (==) No Layout section.  Using the first Screen section.
>[    34.049] (==) No screen section available. Using defaults.
>[    34.049] (**) |-->Screen "Default Screen Section" (0)
>[    34.049] (**) |   |-->Monitor "<default monitor>"
>[    34.049] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    34.049] (==) Automatically adding devices
>[    34.049] (==) Automatically enabling devices
>[    34.049] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    34.049] (==) ModulePath set to "/usr/lib/xorg/modules"
>[    34.049] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    34.049] (II) Loader magic: 0x8224580
>[    34.049] (II) Module ABI versions:
>[    34.049] 	X.Org ANSI C Emulation: 0.4
>[    34.049] 	X.Org Video Driver: 12.0
>[    34.050] 	X.Org XInput driver : 16.0
>[    34.050] 	X.Org Server Extension : 6.0
>[    34.054] (--) PCI:*(0:0:1:0) 1002:9804:1179:fdc0 rev 0, Mem @ 0xd0000000/268435456, 0xfeb00000/262144, I/O @ 0x0000f000/256, BIOS @ 0x????????/131072
>[    34.054] (II) LoadModule: "extmod"
>[    34.056] (II) Loading /usr/lib/xorg/modules/extensions/libextmod.so
>[    34.058] (II) Module extmod: vendor="X.Org Foundation"
>[    34.058] 	compiled for 1.12.3, module version = 1.0.0
>[    34.058] 	Module class: X.Org Server Extension
>[    34.058] 	ABI class: X.Org Server Extension, version 6.0
>[    34.059] (II) Loading extension SELinux
>[    34.059] (II) Loading extension MIT-SCREEN-SAVER
>[    34.059] (II) Loading extension XFree86-VidModeExtension
>[    34.059] (II) Loading extension XFree86-DGA
>[    34.059] (II) Loading extension DPMS
>[    34.059] (II) Loading extension XVideo
>[    34.059] (II) Loading extension XVideo-MotionCompensation
>[    34.059] (II) Loading extension X-Resource
>[    34.059] (II) LoadModule: "dbe"
>[    34.060] (II) Loading /usr/lib/xorg/modules/extensions/libdbe.so
>[    34.060] (II) Module dbe: vendor="X.Org Foundation"
>[    34.060] 	compiled for 1.12.3, module version = 1.0.0
>[    34.060] 	Module class: X.Org Server Extension
>[    34.060] 	ABI class: X.Org Server Extension, version 6.0
>[    34.060] (II) Loading extension DOUBLE-BUFFER
>[    34.060] (II) LoadModule: "glx"
>[    34.061] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
>[    34.062] (II) Module glx: vendor="X.Org Foundation"
>[    34.062] 	compiled for 1.12.3, module version = 1.0.0
>[    34.062] 	ABI class: X.Org Server Extension, version 6.0
>[    34.062] (==) AIGLX enabled
>[    34.062] (II) Loading extension GLX
>[    34.062] (II) LoadModule: "record"
>[    34.063] (II) Loading /usr/lib/xorg/modules/extensions/librecord.so
>[    34.063] (II) Module record: vendor="X.Org Foundation"
>[    34.063] 	compiled for 1.12.3, module version = 1.13.0
>[    34.063] 	Module class: X.Org Server Extension
>[    34.063] 	ABI class: X.Org Server Extension, version 6.0
>[    34.063] (II) Loading extension RECORD
>[    34.063] (II) LoadModule: "dri"
>[    34.064] (II) Loading /usr/lib/xorg/modules/extensions/libdri.so
>[    34.065] (II) Module dri: vendor="X.Org Foundation"
>[    34.065] 	compiled for 1.12.3, module version = 1.0.0
>[    34.065] 	ABI class: X.Org Server Extension, version 6.0
>[    34.065] (II) Loading extension XFree86-DRI
>[    34.065] (II) LoadModule: "dri2"
>[    34.066] (II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
>[    34.066] (II) Module dri2: vendor="X.Org Foundation"
>[    34.066] 	compiled for 1.12.3, module version = 1.2.0
>[    34.066] 	ABI class: X.Org Server Extension, version 6.0
>[    34.066] (II) Loading extension DRI2
>[    34.066] (==) Matched ati as autoconfigured driver 0
>[    34.067] (==) Matched vesa as autoconfigured driver 1
>[    34.067] (==) Matched modesetting as autoconfigured driver 2
>[    34.067] (==) Matched fbdev as autoconfigured driver 3
>[    34.067] (==) Assigned the driver to the xf86ConfigLayout
>[    34.067] (II) LoadModule: "ati"
>[    34.067] (II) Loading /usr/lib/xorg/modules/drivers/ati_drv.so
>[    34.067] (II) Module ati: vendor="X.Org Foundation"
>[    34.067] 	compiled for 1.12.0, module version = 6.14.99
>[    34.067] 	Module class: X.Org Video Driver
>[    34.067] 	ABI class: X.Org Video Driver, version 12.0
>[    34.067] (II) LoadModule: "radeon"
>[    34.068] (II) Loading /usr/lib/xorg/modules/drivers/radeon_drv.so
>[    34.069] (II) Module radeon: vendor="X.Org Foundation"
>[    34.069] 	compiled for 1.12.0, module version = 6.14.99
>[    34.069] 	Module class: X.Org Video Driver
>[    34.069] 	ABI class: X.Org Video Driver, version 12.0
>[    34.069] (II) LoadModule: "vesa"
>[    34.070] (II) Loading /usr/lib/xorg/modules/drivers/vesa_drv.so
>[    34.070] (II) Module vesa: vendor="X.Org Foundation"
>[    34.070] 	compiled for 1.12.0, module version = 2.3.1
>[    34.070] 	Module class: X.Org Video Driver
>[    34.070] 	ABI class: X.Org Video Driver, version 12.0
>[    34.070] (II) LoadModule: "modesetting"
>[    34.072] (WW) Warning, couldn't open module modesetting
>[    34.072] (II) UnloadModule: "modesetting"
>[    34.072] (II) Unloading modesetting
>[    34.072] (EE) Failed to load module "modesetting" (module does not exist, 0)
>[    34.072] (II) LoadModule: "fbdev"
>[    34.072] (II) Loading /usr/lib/xorg/modules/drivers/fbdev_drv.so
>[    34.073] (II) Module fbdev: vendor="X.Org Foundation"
>[    34.073] 	compiled for 1.11.99.901, module version = 0.4.2
>[    34.073] 	ABI class: X.Org Video Driver, version 12.0
>[    34.073] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    34.087] (II) VESA: driver for VESA chipsets: vesa
>[    34.087] (II) FBDEV: driver for framebuffer: fbdev
>[    34.087] (++) using VT number 1
>
>[    34.090] (II) [KMS] Kernel modesetting enabled.
>[    34.090] (WW) Falling back to old probe method for vesa
>[    34.090] (WW) Falling back to old probe method for fbdev
>[    34.090] (II) Loading sub module "fbdevhw"
>[    34.090] (II) LoadModule: "fbdevhw"
>[    34.090] (II) Loading /usr/lib/xorg/modules/libfbdevhw.so
>[    34.090] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    34.091] 	compiled for 1.12.3, module version = 0.0.2
>[    34.091] 	ABI class: X.Org Video Driver, version 12.0
>[    34.091] (II) RADEON(0): RADEONPreInit_KMS
>[    34.091] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    34.091] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    34.091] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    34.091] (==) RADEON(0): Default visual is TrueColor
>[    34.091] (==) RADEON(0): RGB weight 888
>[    34.091] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    34.091] (--) RADEON(0): Chipset: "AMD Radeon HD 6250 Graphics" (ChipID = 0x9804)
>[    34.092] (II) RADEON(0): PCIE card detected
>[    34.092] drmOpenDevice: node name is /dev/dri/card0
>[    34.092] drmOpenDevice: open result is 8, (OK)
>[    34.092] drmOpenByBusid: Searching for BusID pci:0000:00:01.0
>[    34.092] drmOpenDevice: node name is /dev/dri/card0
>[    34.092] drmOpenDevice: open result is 8, (OK)
>[    34.092] drmOpenByBusid: drmOpenMinor returns 8
>[    34.092] drmOpenByBusid: drmGetBusid reports pci:0000:00:01.0
>[    34.092] (II) Loading sub module "exa"
>[    34.092] (II) LoadModule: "exa"
>[    34.093] (II) Loading /usr/lib/xorg/modules/libexa.so
>[    34.094] (II) Module exa: vendor="X.Org Foundation"
>[    34.094] 	compiled for 1.12.3, module version = 2.5.0
>[    34.094] 	ABI class: X.Org Video Driver, version 12.0
>[    34.094] (II) RADEON(0): KMS Color Tiling: enabled
>[    34.094] (II) RADEON(0): KMS Pageflipping: enabled
>[    34.094] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    34.094] (II) RADEON(0): Output LVDS has no monitor section
>[    34.097] (II) RADEON(0): Output HDMI-0 has no monitor section
>[    34.173] (II) RADEON(0): Output VGA-0 has no monitor section
>[    34.173] (II) RADEON(0): EDID for output LVDS
>[    34.174] (II) RADEON(0): Manufacturer: AUO  Model: 30d2  Serial#: 0
>[    34.174] (II) RADEON(0): Year: 2008  Week: 1
>[    34.174] (II) RADEON(0): EDID Version: 1.3
>[    34.174] (II) RADEON(0): Digital Display Input
>[    34.174] (II) RADEON(0): Max Image Size [cm]: horiz.: 22  vert.: 13
>[    34.174] (II) RADEON(0): Gamma: 2.20
>[    34.174] (II) RADEON(0): No DPMS capabilities specified
>[    34.174] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>[    34.174] (II) RADEON(0): First detailed timing is preferred mode
>[    34.174] (II) RADEON(0): redX: 0.588 redY: 0.351   greenX: 0.342 greenY: 0.567
>[    34.174] (II) RADEON(0): blueX: 0.158 blueY: 0.123   whiteX: 0.313 whiteY: 0.329
>[    34.174] (II) RADEON(0): Manufacturer's mask: 0
>[    34.174] (II) RADEON(0): Supported detailed timing:
>[    34.174] (II) RADEON(0): clock: 50.4 MHz   Image Size:  223 x 125 mm
>[    34.174] (II) RADEON(0): h_active: 1024  h_sync: 1048  h_sync_end 1184 h_blank_end 1344 h_border: 0
>[    34.174] (II) RADEON(0): v_active: 600  v_sync: 603  v_sync_end 604 v_blanking: 625 v_border: 0
>[    34.174] (II) RADEON(0): Unknown vendor-specific block f
>[    34.174] (II) RADEON(0):  AUO
>[    34.174] (II) RADEON(0):  B101AW03 V0
>[    34.174] (II) RADEON(0): EDID (in hex):
>[    34.174] (II) RADEON(0): 	00ffffffffffff0006afd23000000000
>[    34.174] (II) RADEON(0): 	0112010380160d780ab9a59659579128
>[    34.174] (II) RADEON(0): 	1f505400000001010101010101010101
>[    34.175] (II) RADEON(0): 	010101010101b0130040415819201888
>[    34.175] (II) RADEON(0): 	3100df7d000000180000000f00000000
>[    34.175] (II) RADEON(0): 	00000000000000000020000000fe0041
>[    34.175] (II) RADEON(0): 	554f0a202020202020202020000000fe
>[    34.175] (II) RADEON(0): 	004231303141573033205630200a00f0
>[    34.175] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    34.175] (II) RADEON(0): Printing DDC gathered Modelines:
>[    34.175] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    34.175] (II) RADEON(0): Printing probed modes for output LVDS
>[    34.175] (II) RADEON(0): Modeline "1024x600"x60.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    34.175] (II) RADEON(0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
>[    34.175] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
>[    34.176] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    34.176] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
>[    34.176] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    34.176] (II) RADEON(0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
>[    34.176] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    34.176] (II) RADEON(0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
>[    34.176] (II) RADEON(0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
>[    34.176] (II) RADEON(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
>[    34.176] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    34.176] (II) RADEON(0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
>[    34.176] (II) RADEON(0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
>[    34.176] (II) RADEON(0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
>[    34.176] (II) RADEON(0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
>[    34.179] (II) RADEON(0): EDID for output HDMI-0
>[    34.255] (II) RADEON(0): EDID for output VGA-0
>[    34.255] (II) RADEON(0): Output LVDS connected
>[    34.255] (II) RADEON(0): Output HDMI-0 disconnected
>[    34.255] (II) RADEON(0): Output VGA-0 disconnected
>[    34.255] (II) RADEON(0): Using exact sizes for initial modes
>[    34.255] (II) RADEON(0): Output LVDS using initial mode 1024x600 +0+0
>[    34.255] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    34.256] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fd68000
>[    34.256] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    34.256] (**) RADEON(0): Display dimensions: (220, 130) mm
>[    34.256] (**) RADEON(0): DPI set to (118, 117)
>[    34.256] (II) Loading sub module "fb"
>[    34.256] (II) LoadModule: "fb"
>[    34.257] (II) Loading /usr/lib/xorg/modules/libfb.so
>[    34.259] (II) Module fb: vendor="X.Org Foundation"
>[    34.259] 	compiled for 1.12.3, module version = 1.0.0
>[    34.260] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    34.260] (II) Loading sub module "ramdac"
>[    34.260] (II) LoadModule: "ramdac"
>[    34.260] (II) Module "ramdac" already built-in
>[    34.260] (II) UnloadModule: "vesa"
>[    34.260] (II) Unloading vesa
>[    34.260] (II) UnloadModule: "fbdev"
>[    34.260] (II) Unloading fbdev
>[    34.260] (II) UnloadSubModule: "fbdevhw"
>[    34.260] (II) Unloading fbdevhw
>[    34.260] (--) Depth 24 pixmap format is 32 bpp
>[    34.260] (II) RADEON(0): [DRI2] Setup complete
>[    34.261] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    34.261] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    34.261] (II) RADEON(0): Front buffer size: 2400K
>[    34.261] (II) RADEON(0): VRAM usage limit set to 231379K
>[    34.262] (II) RADEON(0): Initializing backing store
>[    34.262] (==) RADEON(0): Backing store disabled
>[    34.262] (II) RADEON(0): Direct rendering enabled
>[    34.262] (II) RADEON(0): Initializing Acceleration
>[    34.262] (II) RADEON(0): Setting EXA maxPitchBytes
>[    34.262] (II) EXA(0): Driver allocated offscreen pixmaps
>[    34.262] (II) EXA(0): Driver registered support for the following operations:
>[    34.262] (II)         Solid
>[    34.262] (II)         Copy
>[    34.262] (II)         Composite (RENDER acceleration)
>[    34.262] (II)         UploadToScreen
>[    34.262] (II)         DownloadFromScreen
>[    34.262] (II) RADEON(0): Acceleration enabled
>[    34.262] (II) RADEON(0): Initializing DPMS
>[    34.262] (==) RADEON(0): DPMS enabled
>[    34.262] (II) RADEON(0): Initializing Cursor
>[    34.262] (==) RADEON(0): Silken mouse enabled
>[    34.263] (II) RADEON(0): Initializing Xv
>[    34.263] (II) RADEON(0): Set up textured video
>[    34.263] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    34.263] (II) RADEON(0): [XvMC] Extension initialized.
>[    34.263] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    34.263] (II) RADEON(0): Initializing kms color map
>[    34.264] (II) RADEON(0): RADEONScreenInit finished
>[    34.264] (--) RandR disabled
>[    34.264] (II) Initializing built-in extension Generic Event Extension
>[    34.264] (II) Initializing built-in extension SHAPE
>[    34.264] (II) Initializing built-in extension MIT-SHM
>[    34.264] (II) Initializing built-in extension XInputExtension
>[    34.264] (II) Initializing built-in extension XTEST
>[    34.264] (II) Initializing built-in extension BIG-REQUESTS
>[    34.264] (II) Initializing built-in extension SYNC
>[    34.264] (II) Initializing built-in extension XKEYBOARD
>[    34.264] (II) Initializing built-in extension XC-MISC
>[    34.264] (II) Initializing built-in extension XINERAMA
>[    34.264] (II) Initializing built-in extension XFIXES
>[    34.264] (II) Initializing built-in extension RENDER
>[    34.264] (II) Initializing built-in extension RANDR
>[    34.264] (II) Initializing built-in extension COMPOSITE
>[    34.264] (II) Initializing built-in extension DAMAGE
>[    34.268] (II) SELinux: Disabled by boolean
>[    34.858] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    34.858] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    34.858] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    34.858] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    34.859] (II) AIGLX: Loaded and initialized r600
>[    34.859] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    34.864] (II) RADEON(0): Setting screen physical size to 270 x 158
>[    35.023] (II) XKB: Reusing cached keymap
>[    35.033] (II) config/udev: Adding input device Power Button (/dev/input/event2)
>[    35.033] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    35.033] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    35.033] (II) LoadModule: "evdev"
>[    35.033] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    35.034] (II) Module evdev: vendor="X.Org Foundation"
>[    35.034] 	compiled for 1.12.0, module version = 2.7.0
>[    35.034] 	Module class: X.Org XInput Driver
>[    35.034] 	ABI class: X.Org XInput driver, version 16.0
>[    35.034] (II) Using input driver 'evdev' for 'Power Button'
>[    35.034] 	Option "XkbRules" "evdev"
>[    35.034] 	Option "XkbModel" "pc105"
>[    35.034] 	Option "XkbLayout" "it"
>[    35.034] 	Option "_source" "server/udev"
>[    35.035] 	Option "name" "Power Button"
>[    35.035] 	Option "path" "/dev/input/event2"
>[    35.035] 	Option "device" "/dev/input/event2"
>[    35.035] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    35.035] 	Option "driver" "evdev"
>[    35.035] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.035] (**) Power Button: always reports core events
>[    35.035] (**) evdev: Power Button: Device: "/dev/input/event2"
>[    35.035] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    35.035] (--) evdev: Power Button: Found keys
>[    35.035] (II) evdev: Power Button: Configuring as keyboard
>[    35.035] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    35.035] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    35.035] (**) Option "xkb_rules" "evdev"
>[    35.035] (**) Option "xkb_model" "pc105"
>[    35.036] (**) Option "xkb_layout" "it"
>[    35.036] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.121] (II) config/udev: Adding input device Video Bus (/dev/input/event5)
>[    35.121] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    35.121] (**) Video Bus: Applying InputClass "system-setup-keyboard"
>[    35.121] (II) Using input driver 'evdev' for 'Video Bus'
>[    35.121] 	Option "XkbRules" "evdev"
>[    35.121] 	Option "XkbModel" "pc105"
>[    35.121] 	Option "XkbLayout" "it"
>[    35.121] 	Option "_source" "server/udev"
>[    35.121] 	Option "name" "Video Bus"
>[    35.121] 	Option "path" "/dev/input/event5"
>[    35.121] 	Option "device" "/dev/input/event5"
>[    35.121] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input5/event5"
>[    35.121] 	Option "driver" "evdev"
>[    35.121] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.122] (**) Video Bus: always reports core events
>[    35.122] (**) evdev: Video Bus: Device: "/dev/input/event5"
>[    35.122] (--) evdev: Video Bus: Vendor 0 Product 0x6
>[    35.122] (--) evdev: Video Bus: Found keys
>[    35.122] (II) evdev: Video Bus: Configuring as keyboard
>[    35.122] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input5/event5"
>[    35.122] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7)
>[    35.122] (**) Option "xkb_rules" "evdev"
>[    35.122] (**) Option "xkb_model" "pc105"
>[    35.122] (**) Option "xkb_layout" "it"
>[    35.122] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.122] (II) XKB: Reusing cached keymap
>[    35.125] (II) config/udev: Adding input device Power Button (/dev/input/event0)
>[    35.125] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    35.125] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    35.125] (II) Using input driver 'evdev' for 'Power Button'
>[    35.125] 	Option "XkbRules" "evdev"
>[    35.125] 	Option "XkbModel" "pc105"
>[    35.125] 	Option "XkbLayout" "it"
>[    35.125] 	Option "_source" "server/udev"
>[    35.125] 	Option "name" "Power Button"
>[    35.125] 	Option "path" "/dev/input/event0"
>[    35.125] 	Option "device" "/dev/input/event0"
>[    35.125] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    35.125] 	Option "driver" "evdev"
>[    35.125] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.125] (**) Power Button: always reports core events
>[    35.125] (**) evdev: Power Button: Device: "/dev/input/event0"
>[    35.125] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    35.126] (--) evdev: Power Button: Found keys
>[    35.126] (II) evdev: Power Button: Configuring as keyboard
>[    35.126] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
>[    35.126] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 8)
>[    35.126] (**) Option "xkb_rules" "evdev"
>[    35.126] (**) Option "xkb_model" "pc105"
>[    35.126] (**) Option "xkb_layout" "it"
>[    35.126] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.126] (II) XKB: Reusing cached keymap
>[    35.128] (II) config/udev: Adding input device Lid Switch (/dev/input/event1)
>[    35.128] (II) No input driver specified, ignoring this device.
>[    35.128] (II) This device may have been added with another device file.
>[    35.129] (II) config/udev: Adding input device HD-Audio Generic HDMI/DP,pcm=3 (/dev/input/event7)
>[    35.129] (II) No input driver specified, ignoring this device.
>[    35.129] (II) This device may have been added with another device file.
>[    35.130] (II) config/udev: Adding input device CNF9055 (/dev/input/event10)
>[    35.130] (**) CNF9055: Applying InputClass "evdev keyboard catchall"
>[    35.130] (**) CNF9055: Applying InputClass "system-setup-keyboard"
>[    35.130] (II) Using input driver 'evdev' for 'CNF9055'
>[    35.130] 	Option "XkbRules" "evdev"
>[    35.130] 	Option "XkbModel" "pc105"
>[    35.130] 	Option "XkbLayout" "it"
>[    35.130] 	Option "_source" "server/udev"
>[    35.130] 	Option "name" "CNF9055"
>[    35.130] 	Option "path" "/dev/input/event10"
>[    35.130] 	Option "device" "/dev/input/event10"
>[    35.130] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.2/usb2/2-1/2-1:1.0/input/input10/event10"
>[    35.131] 	Option "driver" "evdev"
>[    35.131] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.131] (**) CNF9055: always reports core events
>[    35.131] (**) evdev: CNF9055: Device: "/dev/input/event10"
>[    35.131] (--) evdev: CNF9055: Vendor 0x4f2 Product 0xb1d6
>[    35.131] (--) evdev: CNF9055: Found keys
>[    35.131] (II) evdev: CNF9055: Configuring as keyboard
>[    35.131] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:13.2/usb2/2-1/2-1:1.0/input/input10/event10"
>[    35.131] (II) XINPUT: Adding extended input device "CNF9055" (type: KEYBOARD, id 9)
>[    35.131] (**) Option "xkb_rules" "evdev"
>[    35.131] (**) Option "xkb_model" "pc105"
>[    35.131] (**) Option "xkb_layout" "it"
>[    35.131] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.131] (II) XKB: Reusing cached keymap
>[    35.134] (II) config/udev: Adding input device HDA ATI SB Mic (/dev/input/event8)
>[    35.134] (II) No input driver specified, ignoring this device.
>[    35.134] (II) This device may have been added with another device file.
>[    35.134] (II) config/udev: Adding input device HDA ATI SB Headphone (/dev/input/event9)
>[    35.135] (II) No input driver specified, ignoring this device.
>[    35.135] (II) This device may have been added with another device file.
>[    35.135] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event3)
>[    35.136] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    35.136] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard"
>[    35.136] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    35.136] 	Option "XkbRules" "evdev"
>[    35.136] 	Option "XkbModel" "pc105"
>[    35.136] 	Option "XkbLayout" "it"
>[    35.136] 	Option "_source" "server/udev"
>[    35.136] 	Option "name" "AT Translated Set 2 keyboard"
>[    35.136] 	Option "path" "/dev/input/event3"
>[    35.136] 	Option "device" "/dev/input/event3"
>[    35.136] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    35.136] 	Option "driver" "evdev"
>[    35.136] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.136] (**) AT Translated Set 2 keyboard: always reports core events
>[    35.136] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event3"
>[    35.136] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    35.136] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    35.136] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    35.136] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    35.136] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 10)
>[    35.136] (**) Option "xkb_rules" "evdev"
>[    35.136] (**) Option "xkb_model" "pc105"
>[    35.137] (**) Option "xkb_layout" "it"
>[    35.137] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.137] (II) XKB: Reusing cached keymap
>[    35.138] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event4)
>[    35.139] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    35.139] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    35.139] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons"
>[    35.139] (II) LoadModule: "synaptics"
>[    35.139] (II) Loading /usr/lib/xorg/modules/input/synaptics_drv.so
>[    35.140] (II) Module synaptics: vendor="X.Org Foundation"
>[    35.140] 	compiled for 1.12.3, module version = 1.6.2
>[    35.140] 	Module class: X.Org XInput Driver
>[    35.140] 	ABI class: X.Org XInput driver, version 16.0
>[    35.140] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    35.140] 	Option "_source" "server/udev"
>[    35.140] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    35.140] 	Option "path" "/dev/input/event4"
>[    35.140] 	Option "device" "/dev/input/event4"
>[    35.140] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input4/event4"
>[    35.140] 	Option "driver" "synaptics"
>[    35.140] 	Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0"
>[    35.140] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    35.140] (**) Option "Device" "/dev/input/event4"
>[    35.160] (**) Option "Device" "/dev/input/event4"
>[    35.160] port opened successfully
>[    35.160] (II) synaptics: SynPS/2 Synaptics TouchPad: ignoring touch events for semi-multitouch device
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5612
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4618
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right double triple
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7
>[    35.160] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    35.160] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    35.174] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input4/event4"
>[    35.174] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 11)
>[    35.174] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    35.174] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    35.174] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.038
>[    35.174] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    35.174] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    35.174] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    35.174] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    35.174] (**) Option "Device" "/dev/input/event4"
>[    35.175] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    35.176] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0)
>[    35.176] (II) No input driver specified, ignoring this device.
>[    35.176] (II) This device may have been added with another device file.
>[    35.178] (II) config/udev: Adding input device Toshiba input device (/dev/input/event6)
>[    35.178] (**) Toshiba input device: Applying InputClass "evdev keyboard catchall"
>[    35.178] (**) Toshiba input device: Applying InputClass "system-setup-keyboard"
>[    35.178] (II) Using input driver 'evdev' for 'Toshiba input device'
>[    35.178] 	Option "XkbRules" "evdev"
>[    35.178] 	Option "XkbModel" "pc105"
>[    35.178] 	Option "XkbLayout" "it"
>[    35.179] 	Option "_source" "server/udev"
>[    35.179] 	Option "name" "Toshiba input device"
>[    35.179] 	Option "path" "/dev/input/event6"
>[    35.179] 	Option "device" "/dev/input/event6"
>[    35.179] 	Option "config_info" "udev:/sys/devices/virtual/input/input6/event6"
>[    35.179] 	Option "driver" "evdev"
>[    35.179] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    35.179] (**) Toshiba input device: always reports core events
>[    35.179] (**) evdev: Toshiba input device: Device: "/dev/input/event6"
>[    35.179] (--) evdev: Toshiba input device: Vendor 0 Product 0
>[    35.179] (--) evdev: Toshiba input device: Found keys
>[    35.179] (II) evdev: Toshiba input device: Configuring as keyboard
>[    35.179] (**) Option "config_info" "udev:/sys/devices/virtual/input/input6/event6"
>[    35.179] (II) XINPUT: Adding extended input device "Toshiba input device" (type: KEYBOARD, id 12)
>[    35.179] (**) Option "xkb_rules" "evdev"
>[    35.179] (**) Option "xkb_model" "pc105"
>[    35.179] (**) Option "xkb_layout" "it"
>[    35.180] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    35.180] (II) XKB: Reusing cached keymap
>[    35.199] (II) RADEON(0): RADEONSaveScreen(2)
>[    35.214] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    35.214] (II) RADEON(0): Printing DDC gathered Modelines:
>[    35.214] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    37.887] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    37.888] (II) RADEON(0): Printing DDC gathered Modelines:
>[    37.888] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    43.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8e0]
>[    43.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8e0] width 1024 pitch 4096 (/4 1024)
>[    43.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    43.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    43.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8e0]
>[    43.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8e0] width 1024 pitch 4096 (/4 1024)
>[    43.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    43.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    43.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8e0]
>[    43.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8e0] width 1024 pitch 4096 (/4 1024)
>[    43.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    43.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    43.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8e0]
>[    43.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8e0] width 1024 pitch 4096 (/4 1024)
>[    43.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    43.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    44.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1d8b0]
>[    44.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1d8b0] width 1024 pitch 4096 (/4 1024)
>[    44.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e868]
>[    44.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e868] width 1024 pitch 4096 (/4 1024)
>[    46.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    46.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    46.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    46.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    48.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    48.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    48.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    48.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    49.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    49.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    49.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    49.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    49.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    49.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    49.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    49.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    49.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c1e850]
>[    49.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c1e850] width 1024 pitch 4096 (/4 1024)
>[    49.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c16488]
>[    49.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c16488] width 1024 pitch 4096 (/4 1024)
>[    50.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c225b8]
>[    50.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c225b8] width 1024 pitch 4096 (/4 1024)
>[    50.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c22718]
>[    50.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c22718] width 1024 pitch 4096 (/4 1024)
>[    50.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c225b8]
>[    50.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c225b8] width 1024 pitch 4096 (/4 1024)
>[    51.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c22718]
>[    51.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c22718] width 1024 pitch 4096 (/4 1024)
>[    51.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c225b8]
>[    51.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c225b8] width 1024 pitch 4096 (/4 1024)
>[    51.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c22718]
>[    51.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c22718] width 1024 pitch 4096 (/4 1024)
>[    52.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c225b8]
>[    52.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c225b8] width 1024 pitch 4096 (/4 1024)
>[    52.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c22718]
>[    52.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c22718] width 1024 pitch 4096 (/4 1024)
>[    53.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c225b8]
>[    53.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c225b8] width 1024 pitch 4096 (/4 1024)
>[    56.427] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    56.427] (II) RADEON(0): Printing DDC gathered Modelines:
>[    56.427] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    60.254] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    60.254] (II) RADEON(0): Printing DDC gathered Modelines:
>[    60.254] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    60.588] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[    60.588] (II) RADEON(0): Printing DDC gathered Modelines:
>[    60.588] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[    66.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c606c8]
>[    66.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c606c8] width 1024 pitch 4096 (/4 1024)
>[    66.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c60698]
>[    66.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c60698] width 1024 pitch 4096 (/4 1024)
>[    66.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63308]
>[    66.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63308] width 1024 pitch 4096 (/4 1024)
>[    67.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c632d8]
>[    67.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c632d8] width 1024 pitch 4096 (/4 1024)
>[    72.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63360]
>[    72.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63360] width 1024 pitch 4096 (/4 1024)
>[    72.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    72.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    73.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c60718]
>[    73.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c60718] width 1024 pitch 4096 (/4 1024)
>[    73.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    73.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    73.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    73.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    86.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    86.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    89.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    89.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    89.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    89.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    89.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c634d0]
>[    89.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c634d0] width 1024 pitch 4096 (/4 1024)
>[    89.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63298]
>[    89.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63298] width 1024 pitch 4096 (/4 1024)
>[    94.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c9b758]
>[    94.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c9b758] width 1024 pitch 4096 (/4 1024)
>[    94.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cac138]
>[    94.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cac138] width 1024 pitch 4096 (/4 1024)
>[    94.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca58a8]
>[    94.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca58a8] width 1024 pitch 4096 (/4 1024)
>[    94.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cac280]
>[    94.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cac280] width 1024 pitch 4096 (/4 1024)
>[    94.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca58a8]
>[    94.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca58a8] width 1024 pitch 4096 (/4 1024)
>[   123.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   123.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   123.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   123.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   123.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   124.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   124.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   124.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   124.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   124.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c64e38]
>[   124.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c64e38] width 1024 pitch 4096 (/4 1024)
>[   124.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   124.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   124.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c64e38]
>[   124.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c64e38] width 1024 pitch 4096 (/4 1024)
>[   124.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   124.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   124.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c64e38]
>[   124.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c64e38] width 1024 pitch 4096 (/4 1024)
>[   124.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c82230]
>[   124.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c82230] width 1024 pitch 4096 (/4 1024)
>[   124.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   124.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   125.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c95e30]
>[   125.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c95e30] width 1024 pitch 4096 (/4 1024)
>[   125.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   125.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   125.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c95e30]
>[   125.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c95e30] width 1024 pitch 4096 (/4 1024)
>[   129.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   129.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   130.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c95e30]
>[   130.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c95e30] width 1024 pitch 4096 (/4 1024)
>[   130.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   130.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   130.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c95e30]
>[   130.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c95e30] width 1024 pitch 4096 (/4 1024)
>[   131.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   131.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   134.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c95e30]
>[   134.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c95e30] width 1024 pitch 4096 (/4 1024)
>[   134.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   134.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   134.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   134.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   134.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   134.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   134.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   134.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   134.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   134.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   134.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   134.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   134.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c96078]
>[   134.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c96078] width 1024 pitch 4096 (/4 1024)
>[   134.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca12c0]
>[   134.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca12c0] width 1024 pitch 4096 (/4 1024)
>[   139.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   139.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   139.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   139.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   139.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   139.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f58]
>[   139.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f58] width 1024 pitch 4096 (/4 1024)
>[   139.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6f28]
>[   139.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6f28] width 1024 pitch 4096 (/4 1024)
>[   159.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c6db50]
>[   159.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c6db50] width 1024 pitch 4096 (/4 1024)
>[   238.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d18808]
>[   238.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d18808] width 1024 pitch 4096 (/4 1024)
>[   286.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d22038]
>[   286.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d22038] width 1024 pitch 4096 (/4 1024)
>[   290.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c6f4c8]
>[   290.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c6f4c8] width 1024 pitch 4096 (/4 1024)
>[   290.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ce4e68]
>[   290.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ce4e68] width 1024 pitch 4096 (/4 1024)
>[   290.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d17100]
>[   290.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d17100] width 1024 pitch 4096 (/4 1024)
>[   290.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cde3f0]
>[   290.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cde3f0] width 1024 pitch 4096 (/4 1024)
>[   311.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76c60]
>[   311.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76c60] width 1024 pitch 4096 (/4 1024)
>[   312.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ce8cc8]
>[   312.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ce8cc8] width 1024 pitch 4096 (/4 1024)
>[   312.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   312.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   312.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ce8cc8]
>[   312.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ce8cc8] width 1024 pitch 4096 (/4 1024)
>[   313.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   313.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   313.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ce8cc8]
>[   313.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ce8cc8] width 1024 pitch 4096 (/4 1024)
>[   313.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   313.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   313.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76c60]
>[   313.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76c60] width 1024 pitch 4096 (/4 1024)
>[   313.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   313.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   313.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76c60]
>[   313.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76c60] width 1024 pitch 4096 (/4 1024)
>[   313.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   313.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   313.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76c60]
>[   313.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76c60] width 1024 pitch 4096 (/4 1024)
>[   313.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4c378]
>[   313.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4c378] width 1024 pitch 4096 (/4 1024)
>[   314.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d24150]
>[   314.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d24150] width 1024 pitch 4096 (/4 1024)
>[   314.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf4130]
>[   314.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf4130] width 1024 pitch 4096 (/4 1024)
>[   314.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bd7068]
>[   314.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bd7068] width 1024 pitch 4096 (/4 1024)
>[   326.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2d090]
>[   326.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2d090] width 1024 pitch 4096 (/4 1024)
>[   327.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d33cf8]
>[   327.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d33cf8] width 1024 pitch 4096 (/4 1024)
>[   336.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d34d30]
>[   336.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d34d30] width 1024 pitch 4096 (/4 1024)
>[   336.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59390]
>[   336.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59390] width 1024 pitch 4096 (/4 1024)
>[   337.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d20470]
>[   337.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d20470] width 1024 pitch 4096 (/4 1024)
>[   347.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2c768]
>[   347.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2c768] width 1024 pitch 4096 (/4 1024)
>[   347.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59a20]
>[   347.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59a20] width 1024 pitch 4096 (/4 1024)
>[   347.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ce55a0]
>[   347.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ce55a0] width 1024 pitch 4096 (/4 1024)
>[   347.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c730f8]
>[   347.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c730f8] width 1024 pitch 4096 (/4 1024)
>[   358.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d23190]
>[   358.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d23190] width 1024 pitch 4096 (/4 1024)
>[   362.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c79da8]
>[   362.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c79da8] width 1024 pitch 4096 (/4 1024)
>[   362.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2e0b0]
>[   362.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2e0b0] width 1024 pitch 4096 (/4 1024)
>[   362.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c79da8]
>[   362.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c79da8] width 1024 pitch 4096 (/4 1024)
>[   362.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2acd8]
>[   362.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2acd8] width 1024 pitch 4096 (/4 1024)
>[   525.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8db0858]
>[   525.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8db0858] width 1024 pitch 4096 (/4 1024)
>[   526.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cd55b0]
>[   526.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cd55b0] width 1024 pitch 4096 (/4 1024)
>[   530.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c995a8]
>[   530.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c995a8] width 1024 pitch 4096 (/4 1024)
>[   530.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2ffe0]
>[   530.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2ffe0] width 1024 pitch 4096 (/4 1024)
>[   530.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c995a8]
>[   530.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c995a8] width 1024 pitch 4096 (/4 1024)
>[   530.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d37208]
>[   530.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d37208] width 1024 pitch 4096 (/4 1024)
>[   530.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c995a8]
>[   530.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c995a8] width 1024 pitch 4096 (/4 1024)
>[   586.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d32978]
>[   586.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d32978] width 1024 pitch 4096 (/4 1024)
>[   604.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1ef18]
>[   604.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1ef18] width 1024 pitch 4096 (/4 1024)
>[   604.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d323c8]
>[   604.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d323c8] width 1024 pitch 4096 (/4 1024)
>[   604.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1ef18]
>[   604.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1ef18] width 1024 pitch 4096 (/4 1024)
>[   604.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1ef18]
>[   604.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1ef18] width 1024 pitch 4096 (/4 1024)
>[   745.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3c460]
>[   745.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3c460] width 1024 pitch 4096 (/4 1024)
>[   749.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3b060]
>[   749.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3b060] width 1024 pitch 4096 (/4 1024)
>[   749.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d38490]
>[   749.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d38490] width 1024 pitch 4096 (/4 1024)
>[   749.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d56c48]
>[   749.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d56c48] width 1024 pitch 4096 (/4 1024)
>[   750.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bd7068]
>[   750.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bd7068] width 1024 pitch 4096 (/4 1024)
>[   834.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62c50]
>[   834.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62c50] width 1024 pitch 4096 (/4 1024)
>[   836.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d24dc0]
>[   836.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d24dc0] width 1024 pitch 4096 (/4 1024)
>[   836.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5abd8]
>[   836.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5abd8] width 1024 pitch 4096 (/4 1024)
>[   836.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   836.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   836.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5abd8]
>[   836.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5abd8] width 1024 pitch 4096 (/4 1024)
>[   836.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   836.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5abd8]
>[   837.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5abd8] width 1024 pitch 4096 (/4 1024)
>[   837.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   837.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   837.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d24dc0]
>[   837.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d24dc0] width 1024 pitch 4096 (/4 1024)
>[   837.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   837.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   837.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   837.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   837.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3b608]
>[   837.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3b608] width 1024 pitch 4096 (/4 1024)
>[   838.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d24dc0]
>[   838.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d24dc0] width 1024 pitch 4096 (/4 1024)
>[   838.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   838.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   838.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3b608]
>[   838.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3b608] width 1024 pitch 4096 (/4 1024)
>[   841.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3b608]
>[   841.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3b608] width 1024 pitch 4096 (/4 1024)
>[   841.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d32268]
>[   841.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d32268] width 1024 pitch 4096 (/4 1024)
>[   841.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf2898]
>[   841.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf2898] width 1024 pitch 4096 (/4 1024)
>[   841.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62c60]
>[   841.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62c60] width 1024 pitch 4096 (/4 1024)
>[   886.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d34770]
>[   886.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d34770] width 1024 pitch 4096 (/4 1024)
>[   886.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   886.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   886.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   886.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   886.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   886.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   886.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   886.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   886.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   886.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   886.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   886.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   887.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   887.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   888.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   888.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   888.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   888.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   896.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   896.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   896.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   896.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   898.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   898.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   898.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   898.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   899.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   899.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   899.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   899.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   899.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62018]
>[   899.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62018] width 1024 pitch 4096 (/4 1024)
>[   900.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55c90]
>[   900.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55c90] width 1024 pitch 4096 (/4 1024)
>[   902.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d380c8]
>[   902.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d380c8] width 1024 pitch 4096 (/4 1024)
>[   903.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d577c8]
>[   903.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d577c8] width 1024 pitch 4096 (/4 1024)
>[   907.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6a390]
>[   907.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6a390] width 1024 pitch 4096 (/4 1024)
>[   926.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8db0658]
>[   926.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8db0658] width 1024 pitch 4096 (/4 1024)
>[   989.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5a920]
>[   989.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5a920] width 1024 pitch 4096 (/4 1024)
>[   991.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d40058]
>[   991.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d40058] width 1024 pitch 4096 (/4 1024)
>[   991.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5a920]
>[   991.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5a920] width 1024 pitch 4096 (/4 1024)
>[   991.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb3f8]
>[   991.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb3f8] width 1024 pitch 4096 (/4 1024)
>[   994.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d43820]
>[   994.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d43820] width 1024 pitch 4096 (/4 1024)
>[   994.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb3f8]
>[   994.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb3f8] width 1024 pitch 4096 (/4 1024)
>[   994.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d43820]
>[   994.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d43820] width 1024 pitch 4096 (/4 1024)
>[   995.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb3f8]
>[   995.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb3f8] width 1024 pitch 4096 (/4 1024)
>[   995.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d43820]
>[   995.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d43820] width 1024 pitch 4096 (/4 1024)
>[   995.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb3f8]
>[   995.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb3f8] width 1024 pitch 4096 (/4 1024)
>[   996.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d43820]
>[   996.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d43820] width 1024 pitch 4096 (/4 1024)
>[   996.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb3f8]
>[   996.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb3f8] width 1024 pitch 4096 (/4 1024)
>[   997.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5a920]
>[   997.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5a920] width 1024 pitch 4096 (/4 1024)
>[   997.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d40058]
>[   997.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d40058] width 1024 pitch 4096 (/4 1024)
>[   998.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5a920]
>[   998.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5a920] width 1024 pitch 4096 (/4 1024)
>[  1215.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1215.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1274.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1274.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1335.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c6b540]
>[  1335.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c6b540] width 1024 pitch 4096 (/4 1024)
>[  1336.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a6b0]
>[  1336.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a6b0] width 1024 pitch 4096 (/4 1024)
>[  1359.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2dd78]
>[  1359.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2dd78] width 1024 pitch 4096 (/4 1024)
>[  1359.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a700]
>[  1359.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a700] width 1024 pitch 4096 (/4 1024)
>[  1359.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2dd78]
>[  1359.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2dd78] width 1024 pitch 4096 (/4 1024)
>[  1359.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a700]
>[  1359.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a700] width 1024 pitch 4096 (/4 1024)
>[  1364.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cdf780]
>[  1364.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cdf780] width 1024 pitch 4096 (/4 1024)
>[  1380.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6de60]
>[  1380.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6de60] width 1024 pitch 4096 (/4 1024)
>[  1381.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d55050]
>[  1381.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d55050] width 1024 pitch 4096 (/4 1024)
>[  1384.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83098]
>[  1384.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83098] width 1024 pitch 4096 (/4 1024)
>[  1401.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc4618]
>[  1401.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc4618] width 1024 pitch 4096 (/4 1024)
>[  1432.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d9db58]
>[  1432.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d9db58] width 1024 pitch 4096 (/4 1024)
>[  1476.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d54f88]
>[  1477.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d54f88] width 1024 pitch 4096 (/4 1024)
>[  1477.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83048]
>[  1477.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83048] width 1024 pitch 4096 (/4 1024)
>[  1477.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83048]
>[  1477.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83048] width 1024 pitch 4096 (/4 1024)
>[  1477.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1477.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1477.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83048]
>[  1477.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83048] width 1024 pitch 4096 (/4 1024)
>[  1477.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1477.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1477.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83048]
>[  1477.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83048] width 1024 pitch 4096 (/4 1024)
>[  1477.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1477.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1477.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c83048]
>[  1477.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c83048] width 1024 pitch 4096 (/4 1024)
>[  1477.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d59830]
>[  1477.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d59830] width 1024 pitch 4096 (/4 1024)
>[  1678.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc8008]
>[  1678.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc8008] width 1024 pitch 4096 (/4 1024)
>[  1678.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1fa90]
>[  1678.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1fa90] width 1024 pitch 4096 (/4 1024)
>[  1685.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d4fd80]
>[  1685.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d4fd80] width 1024 pitch 4096 (/4 1024)
>[  1685.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc8008]
>[  1685.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc8008] width 1024 pitch 4096 (/4 1024)
>[  1685.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d4fd80]
>[  1685.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d4fd80] width 1024 pitch 4096 (/4 1024)
>[  1685.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc8008]
>[  1685.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc8008] width 1024 pitch 4096 (/4 1024)
>[  1685.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d4fd80]
>[  1685.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d4fd80] width 1024 pitch 4096 (/4 1024)
>[  1685.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc8008]
>[  1685.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc8008] width 1024 pitch 4096 (/4 1024)
>[  1691.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca9ac0]
>[  1691.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca9ac0] width 1024 pitch 4096 (/4 1024)
>[  1907.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc9778]
>[  1907.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc9778] width 1024 pitch 4096 (/4 1024)
>[  1926.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc3770]
>[  1926.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc3770] width 1024 pitch 4096 (/4 1024)
>[  1929.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d53810]
>[  1929.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d53810] width 1024 pitch 4096 (/4 1024)
>[  1933.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0e88]
>[  1933.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0e88] width 1024 pitch 4096 (/4 1024)
>[  1946.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ced0d0]
>[  1946.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ced0d0] width 1024 pitch 4096 (/4 1024)
>[  2107.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddc098]
>[  2107.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddc098] width 1024 pitch 4096 (/4 1024)
>[  2108.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd8ec8]
>[  2108.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd8ec8] width 1024 pitch 4096 (/4 1024)
>[  2108.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d91360]
>[  2108.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d91360] width 1024 pitch 4096 (/4 1024)
>[  2108.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddb238]
>[  2108.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddb238] width 1024 pitch 4096 (/4 1024)
>[  2108.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc09c8]
>[  2108.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc09c8] width 1024 pitch 4096 (/4 1024)
>[  2109.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddc098]
>[  2109.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddc098] width 1024 pitch 4096 (/4 1024)
>[  2110.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62168]
>[  2110.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62168] width 1024 pitch 4096 (/4 1024)
>[  2135.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3c710]
>[  2135.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3c710] width 1024 pitch 4096 (/4 1024)
>[  2136.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2136.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2136.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de0048]
>[  2136.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de0048] width 1024 pitch 4096 (/4 1024)
>[  2136.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2136.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2136.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d3c710]
>[  2136.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d3c710] width 1024 pitch 4096 (/4 1024)
>[  2136.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2136.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2136.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2136.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2136.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2136.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2137.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2137.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2137.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2137.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2137.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2137.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2137.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2137.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2138.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2138.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2138.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2138.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2138.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2138.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2138.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de0048]
>[  2138.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de0048] width 1024 pitch 4096 (/4 1024)
>[  2138.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2138.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2138.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de0048]
>[  2138.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de0048] width 1024 pitch 4096 (/4 1024)
>[  2138.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2138.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2155.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df8aa8]
>[  2155.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df8aa8] width 1024 pitch 4096 (/4 1024)
>[  2162.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de9b18]
>[  2162.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de9b18] width 1024 pitch 4096 (/4 1024)
>[  2169.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2169.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2169.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2169.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2169.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2169.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2169.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2169.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2169.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2169.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2169.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2169.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2169.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2169.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2169.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2169.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2169.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2169.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2169.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2170.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2170.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2170.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7638]
>[  2170.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7638] width 1024 pitch 4096 (/4 1024)
>[  2170.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2170.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2174.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02b20]
>[  2174.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02b20] width 1024 pitch 4096 (/4 1024)
>[  2174.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2174.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2174.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2174.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2174.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2174.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2174.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2174.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2175.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2175.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2175.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2175.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2175.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2175.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2176.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09770]
>[  2176.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09770] width 1024 pitch 4096 (/4 1024)
>[  2177.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8cb8]
>[  2177.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8cb8] width 1024 pitch 4096 (/4 1024)
>[  2178.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd49c8]
>[  2178.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd49c8] width 1024 pitch 4096 (/4 1024)
>[  2184.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de8950]
>[  2184.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de8950] width 1024 pitch 4096 (/4 1024)
>[  2185.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e16660]
>[  2185.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e16660] width 1024 pitch 4096 (/4 1024)
>[  2199.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de3018]
>[  2199.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de3018] width 1024 pitch 4096 (/4 1024)
>[  2201.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e16020]
>[  2201.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e16020] width 1024 pitch 4096 (/4 1024)
>[  2202.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e16020]
>[  2202.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e16020] width 1024 pitch 4096 (/4 1024)
>[  2202.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de30c0]
>[  2202.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de30c0] width 1024 pitch 4096 (/4 1024)
>[  2205.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ebc918]
>[  2205.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ebc918] width 1024 pitch 4096 (/4 1024)
>[  2217.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1d3b8]
>[  2217.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1d3b8] width 1024 pitch 4096 (/4 1024)
>[  2219.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0a670]
>[  2219.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0a670] width 1024 pitch 4096 (/4 1024)
>[  2483.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e4cb08]
>[  2483.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e4cb08] width 1024 pitch 4096 (/4 1024)
>[  2499.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3ce88]
>[  2499.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3ce88] width 1024 pitch 4096 (/4 1024)
>[  2523.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3c8d8]
>[  2523.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3c8d8] width 1024 pitch 4096 (/4 1024)
>[  2523.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2523.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd5c28]
>[  2523.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd5c28] width 1024 pitch 4096 (/4 1024)
>[  2523.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e138e0]
>[  2523.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e138e0] width 1024 pitch 4096 (/4 1024)
>[  2537.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e34180]
>[  2537.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e34180] width 1024 pitch 4096 (/4 1024)
>[  2540.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e207d8]
>[  2540.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e207d8] width 1024 pitch 4096 (/4 1024)
>[  2558.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dddbf8]
>[  2558.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dddbf8] width 1024 pitch 4096 (/4 1024)
>[  2572.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d0c900]
>[  2572.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d0c900] width 1024 pitch 4096 (/4 1024)
>[  2576.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc38c0]
>[  2576.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc38c0] width 1024 pitch 4096 (/4 1024)
>[  2576.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd8e50]
>[  2576.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd8e50] width 1024 pitch 4096 (/4 1024)
>[  2576.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd8e50]
>[  2576.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd8e50] width 1024 pitch 4096 (/4 1024)
>[  2578.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6fcc0]
>[  2578.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6fcc0] width 1024 pitch 4096 (/4 1024)
>[  2594.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de7920]
>[  2594.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de7920] width 1024 pitch 4096 (/4 1024)
>[  2594.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d4ec38]
>[  2594.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d4ec38] width 1024 pitch 4096 (/4 1024)
>[  2594.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45ca8]
>[  2594.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45ca8] width 1024 pitch 4096 (/4 1024)
>[  2594.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc4338]
>[  2594.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc4338] width 1024 pitch 4096 (/4 1024)
>[  2594.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2594.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2594.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d72160]
>[  2594.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d72160] width 1024 pitch 4096 (/4 1024)
>[  2594.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45ca8]
>[  2594.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45ca8] width 1024 pitch 4096 (/4 1024)
>[  2594.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d72160]
>[  2594.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d72160] width 1024 pitch 4096 (/4 1024)
>[  2594.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45ca8]
>[  2594.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45ca8] width 1024 pitch 4096 (/4 1024)
>[  2594.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d72160]
>[  2594.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d72160] width 1024 pitch 4096 (/4 1024)
>[  2599.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d598a8]
>[  2599.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d598a8] width 1024 pitch 4096 (/4 1024)
>[  2600.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e17218]
>[  2600.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e17218] width 1024 pitch 4096 (/4 1024)
>[  2611.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e213f0]
>[  2611.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e213f0] width 1024 pitch 4096 (/4 1024)
>[  2611.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd9d48]
>[  2611.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd9d48] width 1024 pitch 4096 (/4 1024)
>[  2611.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e213f0]
>[  2611.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e213f0] width 1024 pitch 4096 (/4 1024)
>[  2614.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d651c8]
>[  2614.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d651c8] width 1024 pitch 4096 (/4 1024)
>[  2646.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfc120]
>[  2646.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfc120] width 1024 pitch 4096 (/4 1024)
>[  2651.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d04228]
>[  2651.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d04228] width 1024 pitch 4096 (/4 1024)
>[  2651.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d031e0]
>[  2651.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d031e0] width 1024 pitch 4096 (/4 1024)
>[  2651.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbf30]
>[  2651.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbf30] width 1024 pitch 4096 (/4 1024)
>[  2651.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d04228]
>[  2651.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d04228] width 1024 pitch 4096 (/4 1024)
>[  2651.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbf30]
>[  2651.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbf30] width 1024 pitch 4096 (/4 1024)
>[  2651.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d04228]
>[  2651.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d04228] width 1024 pitch 4096 (/4 1024)
>[  2651.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbf30]
>[  2651.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbf30] width 1024 pitch 4096 (/4 1024)
>[  2651.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d04228]
>[  2651.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d04228] width 1024 pitch 4096 (/4 1024)
>[  2651.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbf30]
>[  2651.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbf30] width 1024 pitch 4096 (/4 1024)
>[  2651.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d04228]
>[  2651.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d04228] width 1024 pitch 4096 (/4 1024)
>[  2651.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbf30]
>[  2651.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbf30] width 1024 pitch 4096 (/4 1024)
>[  2653.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e067e0]
>[  2653.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e067e0] width 1024 pitch 4096 (/4 1024)
>[  2653.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e067e0]
>[  2653.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e067e0] width 1024 pitch 4096 (/4 1024)
>[  2653.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e067e0]
>[  2653.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e067e0] width 1024 pitch 4096 (/4 1024)
>[  2653.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc31b0]
>[  2653.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc31b0] width 1024 pitch 4096 (/4 1024)
>[  2653.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dda7d8]
>[  2653.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dda7d8] width 1024 pitch 4096 (/4 1024)
>[  2653.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e066d0]
>[  2653.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e066d0] width 1024 pitch 4096 (/4 1024)
>[  2653.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e067e0]
>[  2653.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e067e0] width 1024 pitch 4096 (/4 1024)
>[  2658.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03730]
>[  2658.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03730] width 1024 pitch 4096 (/4 1024)
>[  2658.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1b640]
>[  2658.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1b640] width 1024 pitch 4096 (/4 1024)
>[  2658.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dda7d8]
>[  2658.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dda7d8] width 1024 pitch 4096 (/4 1024)
>[  2662.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d99188]
>[  2662.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d99188] width 1024 pitch 4096 (/4 1024)
>[  2664.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfbc30]
>[  2664.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfbc30] width 1024 pitch 4096 (/4 1024)
>[  2664.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e46868]
>[  2664.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e46868] width 1024 pitch 4096 (/4 1024)
>[  2664.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e46868]
>[  2664.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e46868] width 1024 pitch 4096 (/4 1024)
>[  2669.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0e98]
>[  2669.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0e98] width 1024 pitch 4096 (/4 1024)
>[  2669.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de98d0]
>[  2669.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de98d0] width 1024 pitch 4096 (/4 1024)
>[  2669.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d72160]
>[  2669.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d72160] width 1024 pitch 4096 (/4 1024)
>[  2672.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2672.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2672.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2672.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8b94008]
>[  2672.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8b94008] width 1024 pitch 4096 (/4 1024)
>[  2672.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2672.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2674.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb598]
>[  2674.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb598] width 1024 pitch 4096 (/4 1024)
>[  2674.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2674.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2674.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2674.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2674.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2674.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2674.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2674.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2674.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2674.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2675.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2675.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2675.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc0ed8]
>[  2675.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc0ed8] width 1024 pitch 4096 (/4 1024)
>[  2675.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2676.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2676.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3b638]
>[  2676.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3b638] width 1024 pitch 4096 (/4 1024)
>[  2676.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb598]
>[  2676.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb598] width 1024 pitch 4096 (/4 1024)
>[  2677.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc4338]
>[  2677.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc4338] width 1024 pitch 4096 (/4 1024)
>[  2677.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d973b8]
>[  2677.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d973b8] width 1024 pitch 4096 (/4 1024)
>[  2677.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dec7f0]
>[  2677.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dec7f0] width 1024 pitch 4096 (/4 1024)
>[  2680.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d515b0]
>[  2680.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d515b0] width 1024 pitch 4096 (/4 1024)
>[  2681.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddc3b0]
>[  2681.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddc3b0] width 1024 pitch 4096 (/4 1024)
>[  2681.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da6558]
>[  2681.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da6558] width 1024 pitch 4096 (/4 1024)
>[  2694.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d5b718]
>[  2694.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d5b718] width 1024 pitch 4096 (/4 1024)
>[  2700.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dc3d40]
>[  2700.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dc3d40] width 1024 pitch 4096 (/4 1024)
>[  2705.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d62f80]
>[  2705.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d62f80] width 1024 pitch 4096 (/4 1024)
>[  2787.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df4bb8]
>[  2787.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df4bb8] width 1024 pitch 4096 (/4 1024)
>[  2799.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb4a78]
>[  2799.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb4a78] width 1024 pitch 4096 (/4 1024)
>[  2799.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df4b20]
>[  2799.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df4b20] width 1024 pitch 4096 (/4 1024)
>[  2799.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb4a78]
>[  2799.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb4a78] width 1024 pitch 4096 (/4 1024)
>[  2799.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdb8c8]
>[  2799.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdb8c8] width 1024 pitch 4096 (/4 1024)
>[  2810.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da6cb0]
>[  2810.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da6cb0] width 1024 pitch 4096 (/4 1024)
>[  2926.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da75a0]
>[  2926.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da75a0] width 1024 pitch 4096 (/4 1024)
>[  2930.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d53850]
>[  2930.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d53850] width 1024 pitch 4096 (/4 1024)
>[  2930.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2f5c0]
>[  2930.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2f5c0] width 1024 pitch 4096 (/4 1024)
>[  2930.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d543b0]
>[  2930.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d543b0] width 1024 pitch 4096 (/4 1024)
>[  2930.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc6ba8]
>[  2930.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc6ba8] width 1024 pitch 4096 (/4 1024)
>[  2973.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2e5e0]
>[  2973.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2e5e0] width 1024 pitch 4096 (/4 1024)
>[  2977.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c4bf48]
>[  2977.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c4bf48] width 1024 pitch 4096 (/4 1024)
>[  2977.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dbff38]
>[  2977.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dbff38] width 1024 pitch 4096 (/4 1024)
>[  2977.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d07fa0]
>[  2977.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d07fa0] width 1024 pitch 4096 (/4 1024)
>[  2977.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2f5c0]
>[  2977.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2f5c0] width 1024 pitch 4096 (/4 1024)
>[  3038.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca95c8]
>[  3038.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca95c8] width 1024 pitch 4096 (/4 1024)
>[  3042.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d774b8]
>[  3042.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d774b8] width 1024 pitch 4096 (/4 1024)
>[  3042.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d543b0]
>[  3042.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d543b0] width 1024 pitch 4096 (/4 1024)
>[  3042.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2f5c0]
>[  3042.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2f5c0] width 1024 pitch 4096 (/4 1024)
>[  3060.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e15db0]
>[  3060.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e15db0] width 1024 pitch 4096 (/4 1024)
>[  3506.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c63960]
>[  3506.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c63960] width 1024 pitch 4096 (/4 1024)
>[  3506.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d9ca98]
>[  3506.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d9ca98] width 1024 pitch 4096 (/4 1024)
>[  3938.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3938.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  3938.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76b80]
>[  3938.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76b80] width 1024 pitch 4096 (/4 1024)
>[  3941.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3941.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  3941.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76b80]
>[  3941.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76b80] width 1024 pitch 4096 (/4 1024)
>[  3941.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3941.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  3941.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76b80]
>[  3941.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76b80] width 1024 pitch 4096 (/4 1024)
>[  3941.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3941.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  3941.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76b80]
>[  3942.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76b80] width 1024 pitch 4096 (/4 1024)
>[  3942.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3942.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  3942.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c76b80]
>[  3942.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c76b80] width 1024 pitch 4096 (/4 1024)
>[  3942.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cc56b8]
>[  3942.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cc56b8] width 1024 pitch 4096 (/4 1024)
>[  4559.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4559.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4559.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45838]
>[  4559.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45838] width 1024 pitch 4096 (/4 1024)
>[  4559.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddd7a8]
>[  4559.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddd7a8] width 1024 pitch 4096 (/4 1024)
>[  4559.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45838]
>[  4559.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45838] width 1024 pitch 4096 (/4 1024)
>[  4559.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddd7a8]
>[  4559.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddd7a8] width 1024 pitch 4096 (/4 1024)
>[  4559.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45838]
>[  4559.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45838] width 1024 pitch 4096 (/4 1024)
>[  4560.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddd7a8]
>[  4560.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddd7a8] width 1024 pitch 4096 (/4 1024)
>[  4560.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45838]
>[  4560.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45838] width 1024 pitch 4096 (/4 1024)
>[  4560.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45838]
>[  4560.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45838] width 1024 pitch 4096 (/4 1024)
>[  4561.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4561.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4561.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4561.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4561.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e16d50]
>[  4561.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e16d50] width 1024 pitch 4096 (/4 1024)
>[  4565.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddd7a8]
>[  4565.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddd7a8] width 1024 pitch 4096 (/4 1024)
>[  4565.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e16d50]
>[  4565.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e16d50] width 1024 pitch 4096 (/4 1024)
>[  4565.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddd7a8]
>[  4566.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddd7a8] width 1024 pitch 4096 (/4 1024)
>[  4568.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03e38]
>[  4568.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03e38] width 1024 pitch 4096 (/4 1024)
>[  4569.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d01a38]
>[  4569.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d01a38] width 1024 pitch 4096 (/4 1024)
>[  4574.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf4f80]
>[  4574.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf4f80] width 1024 pitch 4096 (/4 1024)
>[  4575.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd83c0]
>[  4575.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd83c0] width 1024 pitch 4096 (/4 1024)
>[  4575.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da1e70]
>[  4575.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da1e70] width 1024 pitch 4096 (/4 1024)
>[  4586.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da1fb8]
>[  4586.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da1fb8] width 1024 pitch 4096 (/4 1024)
>[  4589.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd2868]
>[  4589.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd2868] width 1024 pitch 4096 (/4 1024)
>[  4589.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4589.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4589.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41d88]
>[  4589.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41d88] width 1024 pitch 4096 (/4 1024)
>[  4589.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4589.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4589.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41d88]
>[  4589.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41d88] width 1024 pitch 4096 (/4 1024)
>[  4590.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4590.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4590.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41d88]
>[  4590.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41d88] width 1024 pitch 4096 (/4 1024)
>[  4590.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4590.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4590.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41d88]
>[  4590.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41d88] width 1024 pitch 4096 (/4 1024)
>[  4590.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4590.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4591.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41d88]
>[  4591.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41d88] width 1024 pitch 4096 (/4 1024)
>[  4591.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2deb8]
>[  4591.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2deb8] width 1024 pitch 4096 (/4 1024)
>[  4591.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deba40]
>[  4591.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deba40] width 1024 pitch 4096 (/4 1024)
>[  4592.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd2868]
>[  4592.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd2868] width 1024 pitch 4096 (/4 1024)
>[  4592.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deba40]
>[  4592.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deba40] width 1024 pitch 4096 (/4 1024)
>[  4592.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd2868]
>[  4592.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd2868] width 1024 pitch 4096 (/4 1024)
>[  4592.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deba40]
>[  4592.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deba40] width 1024 pitch 4096 (/4 1024)
>[  4618.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddfe50]
>[  4618.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddfe50] width 1024 pitch 4096 (/4 1024)
>[  4618.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4618.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4618.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0acf0]
>[  4618.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0acf0] width 1024 pitch 4096 (/4 1024)
>[  4618.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4618.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4618.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0acf0]
>[  4618.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0acf0] width 1024 pitch 4096 (/4 1024)
>[  4618.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4618.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4618.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0acf0]
>[  4618.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0acf0] width 1024 pitch 4096 (/4 1024)
>[  4618.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4618.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4619.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0acf0]
>[  4619.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0acf0] width 1024 pitch 4096 (/4 1024)
>[  4619.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4619.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4619.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0acf0]
>[  4619.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0acf0] width 1024 pitch 4096 (/4 1024)
>[  4620.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4620.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4620.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4620.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4620.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddfe50]
>[  4620.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddfe50] width 1024 pitch 4096 (/4 1024)
>[  4620.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cff808]
>[  4620.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cff808] width 1024 pitch 4096 (/4 1024)
>[  4620.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddfe50]
>[  4620.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddfe50] width 1024 pitch 4096 (/4 1024)
>[  4654.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e41700]
>[  4654.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e41700] width 1024 pitch 4096 (/4 1024)
>[  4665.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddfe50]
>[  4665.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddfe50] width 1024 pitch 4096 (/4 1024)
>[  4665.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4665.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4665.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03ff8]
>[  4665.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03ff8] width 1024 pitch 4096 (/4 1024)
>[  4665.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfa2f8]
>[  4665.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfa2f8] width 1024 pitch 4096 (/4 1024)
>[  4665.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4665.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4665.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4665.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4665.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4665.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4665.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4665.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4666.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4666.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4666.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4666.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4666.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4666.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4667.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfa2f8]
>[  4667.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfa2f8] width 1024 pitch 4096 (/4 1024)
>[  4667.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4667.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4669.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  4669.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  4670.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  4670.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  4670.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcb240]
>[  4671.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcb240] width 1024 pitch 4096 (/4 1024)
>[  4671.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da8ba0]
>[  4671.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da8ba0] width 1024 pitch 4096 (/4 1024)
>[  4671.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcc280]
>[  4671.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcc280] width 1024 pitch 4096 (/4 1024)
>[  4672.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ded0e0]
>[  4672.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ded0e0] width 1024 pitch 4096 (/4 1024)
>[  4672.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da78a8]
>[  4672.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da78a8] width 1024 pitch 4096 (/4 1024)
>[  4679.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d98fe0]
>[  4679.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d98fe0] width 1024 pitch 4096 (/4 1024)
>[  4679.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca9240]
>[  4679.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca9240] width 1024 pitch 4096 (/4 1024)
>[  4679.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e05d80]
>[  4679.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e05d80] width 1024 pitch 4096 (/4 1024)
>[  4693.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e12688]
>[  4693.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e12688] width 1024 pitch 4096 (/4 1024)
>[  4702.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4702.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4702.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4702.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4703.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4703.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4703.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4703.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4703.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4703.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4703.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4703.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4703.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4703.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4703.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4703.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4703.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4703.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4703.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4703.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4704.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4704.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4704.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4704.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4704.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4704.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4704.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddad40]
>[  4704.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddad40] width 1024 pitch 4096 (/4 1024)
>[  4705.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4705.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4705.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddad40]
>[  4705.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddad40] width 1024 pitch 4096 (/4 1024)
>[  4705.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddad40]
>[  4705.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddad40] width 1024 pitch 4096 (/4 1024)
>[  4718.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb6350]
>[  4718.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb6350] width 1024 pitch 4096 (/4 1024)
>[  4718.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4718.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4718.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4718.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4718.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4718.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4718.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4718.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4718.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4718.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4718.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4718.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4719.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4719.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4719.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4719.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4719.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  4719.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  4719.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4719.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4720.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4720.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4720.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4720.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4720.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2b098]
>[  4720.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2b098] width 1024 pitch 4096 (/4 1024)
>[  4720.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4720.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4720.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb6350]
>[  4720.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb6350] width 1024 pitch 4096 (/4 1024)
>[  4720.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4720.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4720.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45588]
>[  4720.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45588] width 1024 pitch 4096 (/4 1024)
>[  4731.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4731.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4731.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4731.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4731.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da9e80]
>[  4731.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da9e80] width 1024 pitch 4096 (/4 1024)
>[  4731.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e456b0]
>[  4731.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e456b0] width 1024 pitch 4096 (/4 1024)
>[  4731.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e48fe0]
>[  4731.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e48fe0] width 1024 pitch 4096 (/4 1024)
>[  4731.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7b608]
>[  4731.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7b608] width 1024 pitch 4096 (/4 1024)
>[  4731.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aaf8]
>[  4731.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aaf8] width 1024 pitch 4096 (/4 1024)
>[  4732.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4732.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4732.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aaf8]
>[  4732.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aaf8] width 1024 pitch 4096 (/4 1024)
>[  4732.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4732.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4732.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aaf8]
>[  4732.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aaf8] width 1024 pitch 4096 (/4 1024)
>[  4733.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4733.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4733.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4733.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4733.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4733.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4733.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4733.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4807.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ddf390]
>[  4807.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ddf390] width 1024 pitch 4096 (/4 1024)
>[  4807.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df8608]
>[  4807.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df8608] width 1024 pitch 4096 (/4 1024)
>[  4808.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4808.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4808.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4808.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4808.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da9e80]
>[  4808.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da9e80] width 1024 pitch 4096 (/4 1024)
>[  4808.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e48fe0]
>[  4808.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e48fe0] width 1024 pitch 4096 (/4 1024)
>[  4808.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7b608]
>[  4808.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7b608] width 1024 pitch 4096 (/4 1024)
>[  4808.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45508]
>[  4808.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45508] width 1024 pitch 4096 (/4 1024)
>[  4808.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4808.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4808.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45508]
>[  4808.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45508] width 1024 pitch 4096 (/4 1024)
>[  4809.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4809.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4809.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45508]
>[  4809.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45508] width 1024 pitch 4096 (/4 1024)
>[  4809.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4809.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4809.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e45508]
>[  4809.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e45508] width 1024 pitch 4096 (/4 1024)
>[  4812.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d934c8]
>[  4812.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d934c8] width 1024 pitch 4096 (/4 1024)
>[  4812.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  4812.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  4812.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e7bac8]
>[  4812.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e7bac8] width 1024 pitch 4096 (/4 1024)
>[  4812.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  4812.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  4823.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  4823.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  4823.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e011d8]
>[  4823.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e011d8] width 1024 pitch 4096 (/4 1024)
>[  4823.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4823.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4823.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e011d8]
>[  4823.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e011d8] width 1024 pitch 4096 (/4 1024)
>[  4823.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4823.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4823.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e011d8]
>[  4823.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e011d8] width 1024 pitch 4096 (/4 1024)
>[  4824.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4824.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4824.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e011d8]
>[  4824.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e011d8] width 1024 pitch 4096 (/4 1024)
>[  4824.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4824.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4825.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e011d8]
>[  4825.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e011d8] width 1024 pitch 4096 (/4 1024)
>[  4825.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4825.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4826.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d71db0]
>[  4826.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d71db0] width 1024 pitch 4096 (/4 1024)
>[  4826.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd8458]
>[  4826.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd8458] width 1024 pitch 4096 (/4 1024)
>[  4826.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  4826.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  4826.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd8458]
>[  4826.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd8458] width 1024 pitch 4096 (/4 1024)
>[  4826.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  4826.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5189.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5189.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5189.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5189.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5189.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5189.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5189.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5189.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5189.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5189.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5189.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5189.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5189.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5189.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5190.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5190.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5190.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5190.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5190.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5190.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5190.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5190.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5190.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5190.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5191.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5191.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5191.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5191.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5191.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5191.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5191.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5191.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5191.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5191.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5201.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5201.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5201.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5201.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5201.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5201.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5201.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5201.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5201.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5201.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5201.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5201.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5201.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5201.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5201.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5201.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5202.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5202.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5202.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5202.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5202.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5202.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5203.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d968]
>[  5203.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d968] width 1024 pitch 4096 (/4 1024)
>[  5203.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5203.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5203.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5203.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5203.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5203.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5203.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d2a2d0]
>[  5203.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d2a2d0] width 1024 pitch 4096 (/4 1024)
>[  5203.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5203.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5413.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5413.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5413.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5413.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5413.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5413.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5413.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5413.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5413.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5413.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5414.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5414.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5414.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5414.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5414.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5414.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5414.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5414.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5415.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5415.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5415.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5415.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5415.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78038]
>[  5415.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78038] width 1024 pitch 4096 (/4 1024)
>[  5415.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5415.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5415.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5415.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5415.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5415.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5415.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5415.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5415.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5415.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5466.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5466.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5466.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5466.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5466.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5466.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5466.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5466.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5467.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5467.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5467.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5467.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5467.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5467.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5467.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5467.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5468.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5468.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5468.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5468.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5468.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2aef8]
>[  5468.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2aef8] width 1024 pitch 4096 (/4 1024)
>[  5469.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  5469.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  5469.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5469.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5469.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5469.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5469.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5469.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  5469.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  5469.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  5469.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c7d218]
>[  5469.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c7d218] width 1024 pitch 4096 (/4 1024)
>[  6242.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6242.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6242.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6242.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6242.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6242.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6242.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6242.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6242.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6242.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6242.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6242.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6243.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6243.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6243.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6243.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6243.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6243.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6243.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6243.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6243.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6243.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6243.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6243.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6243.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6243.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6243.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6243.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6243.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03fe8]
>[  6243.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03fe8] width 1024 pitch 4096 (/4 1024)
>[  6290.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6290.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6290.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6290.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6290.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6290.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6290.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfa730]
>[  6290.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfa730] width 1024 pitch 4096 (/4 1024)
>[  6290.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6290.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6290.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e12160]
>[  6290.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e12160] width 1024 pitch 4096 (/4 1024)
>[  6290.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d428a8]
>[  6290.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d428a8] width 1024 pitch 4096 (/4 1024)
>[  6290.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6290.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6290.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6290.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6294.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfa730]
>[  6294.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfa730] width 1024 pitch 4096 (/4 1024)
>[  6294.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6294.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6294.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfa730]
>[  6294.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfa730] width 1024 pitch 4096 (/4 1024)
>[  6294.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6294.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6294.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6294.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6294.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6294.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6294.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6294.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6294.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfc328]
>[  6294.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfc328] width 1024 pitch 4096 (/4 1024)
>[  6294.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6294.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6294.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6294.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6559.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfa730]
>[  6559.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfa730] width 1024 pitch 4096 (/4 1024)
>[  6559.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d95190]
>[  6559.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d95190] width 1024 pitch 4096 (/4 1024)
>[  6559.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6559.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6559.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d95190]
>[  6559.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d95190] width 1024 pitch 4096 (/4 1024)
>[  6559.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6559.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6560.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d95190]
>[  6560.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d95190] width 1024 pitch 4096 (/4 1024)
>[  6560.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6560.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6560.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d95190]
>[  6560.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d95190] width 1024 pitch 4096 (/4 1024)
>[  6561.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6561.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6561.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfa730]
>[  6561.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfa730] width 1024 pitch 4096 (/4 1024)
>[  6561.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6561.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6561.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d95190]
>[  6561.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d95190] width 1024 pitch 4096 (/4 1024)
>[  6562.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2ab68]
>[  6562.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2ab68] width 1024 pitch 4096 (/4 1024)
>[  6562.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d428a8]
>[  6562.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d428a8] width 1024 pitch 4096 (/4 1024)
>[  6562.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcc280]
>[  6562.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcc280] width 1024 pitch 4096 (/4 1024)
>[  6562.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d553f0]
>[  6562.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d553f0] width 1024 pitch 4096 (/4 1024)
>[  6564.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dbb140]
>[  6564.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dbb140] width 1024 pitch 4096 (/4 1024)
>[  6566.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dfc900]
>[  6566.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dfc900] width 1024 pitch 4096 (/4 1024)
>[  6566.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e10a60]
>[  6566.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e10a60] width 1024 pitch 4096 (/4 1024)
>[  6566.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e4b520]
>[  6566.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e4b520] width 1024 pitch 4096 (/4 1024)
>[  6576.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9ecf8]
>[  6576.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9ecf8] width 1024 pitch 4096 (/4 1024)
>[  6576.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcdfa8]
>[  6576.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcdfa8] width 1024 pitch 4096 (/4 1024)
>[  6576.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da8ba0]
>[  6576.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da8ba0] width 1024 pitch 4096 (/4 1024)
>[  6576.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df68a8]
>[  6576.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df68a8] width 1024 pitch 4096 (/4 1024)
>[  6579.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da1e80]
>[  6579.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da1e80] width 1024 pitch 4096 (/4 1024)
>[  6580.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da1e80]
>[  6580.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da1e80] width 1024 pitch 4096 (/4 1024)
>[  6606.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8db95b8]
>[  6606.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8db95b8] width 1024 pitch 4096 (/4 1024)
>[  6609.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bd6ea0]
>[  6609.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bd6ea0] width 1024 pitch 4096 (/4 1024)
>[  6609.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da78a8]
>[  6609.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da78a8] width 1024 pitch 4096 (/4 1024)
>[  6612.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d93770]
>[  6612.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d93770] width 1024 pitch 4096 (/4 1024)
>[  6612.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e11fd8]
>[  6612.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e11fd8] width 1024 pitch 4096 (/4 1024)
>[  6612.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfacd8]
>[  6612.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfacd8] width 1024 pitch 4096 (/4 1024)
>[  6619.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df3928]
>[  6619.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df3928] width 1024 pitch 4096 (/4 1024)
>[  6622.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9b568]
>[  6622.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9b568] width 1024 pitch 4096 (/4 1024)
>[  6622.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d78998]
>[  6622.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d78998] width 1024 pitch 4096 (/4 1024)
>[  6622.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6622.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6622.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6622.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6622.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6623.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6623.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6623.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6623.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6623.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6623.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6623.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6623.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6623.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6623.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6623.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6623.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6623.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6623.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6623.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6623.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6623.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6623.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e38df8]
>[  6623.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e38df8] width 1024 pitch 4096 (/4 1024)
>[  6625.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6625.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6625.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df92b8]
>[  6625.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df92b8] width 1024 pitch 4096 (/4 1024)
>[  6625.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e13028]
>[  6625.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e13028] width 1024 pitch 4096 (/4 1024)
>[  6625.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d80788]
>[  6625.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d80788] width 1024 pitch 4096 (/4 1024)
>[  6625.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e350c8]
>[  6625.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e350c8] width 1024 pitch 4096 (/4 1024)
>[  6625.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9d110]
>[  6625.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9d110] width 1024 pitch 4096 (/4 1024)
>[  6625.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d80788]
>[  6625.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d80788] width 1024 pitch 4096 (/4 1024)
>[  6625.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dca8b0]
>[  6625.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dca8b0] width 1024 pitch 4096 (/4 1024)
>[  6630.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02c08]
>[  6630.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02c08] width 1024 pitch 4096 (/4 1024)
>[  6639.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8df8a10]
>[  6639.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8df8a10] width 1024 pitch 4096 (/4 1024)
>[  6639.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6639.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6639.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02c08]
>[  6639.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02c08] width 1024 pitch 4096 (/4 1024)
>[  6639.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6639.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6639.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e02c08]
>[  6639.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e02c08] width 1024 pitch 4096 (/4 1024)
>[  6688.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e49a00]
>[  6688.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e49a00] width 1024 pitch 4096 (/4 1024)
>[  6695.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfcb98]
>[  6695.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfcb98] width 1024 pitch 4096 (/4 1024)
>[  6695.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e49410]
>[  6695.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e49410] width 1024 pitch 4096 (/4 1024)
>[  6695.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8deb640]
>[  6695.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8deb640] width 1024 pitch 4096 (/4 1024)
>[  6696.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ded3c0]
>[  6696.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ded3c0] width 1024 pitch 4096 (/4 1024)
>[  6808.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d973b8]
>[  6808.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d973b8] width 1024 pitch 4096 (/4 1024)
>[  6810.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6810.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6810.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e49338]
>[  6811.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e49338] width 1024 pitch 4096 (/4 1024)
>[  6811.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e259b0]
>[  6811.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e259b0] width 1024 pitch 4096 (/4 1024)
>[  6816.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb6438]
>[  6816.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb6438] width 1024 pitch 4096 (/4 1024)
>[  6816.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6816.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6816.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6816.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6816.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6816.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6816.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6816.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6816.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6816.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6816.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6816.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6816.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6816.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6817.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6817.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6817.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6817.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6817.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28de0]
>[  6817.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28de0] width 1024 pitch 4096 (/4 1024)
>[  6817.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6817.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6817.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6818.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6818.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb6438]
>[  6818.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb6438] width 1024 pitch 4096 (/4 1024)
>[  6818.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e49338]
>[  6818.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e49338] width 1024 pitch 4096 (/4 1024)
>[  6818.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e200a8]
>[  6818.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e200a8] width 1024 pitch 4096 (/4 1024)
>[  6818.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c8f4e8]
>[  6818.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c8f4e8] width 1024 pitch 4096 (/4 1024)
>[  6818.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d6d6b0]
>[  6818.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d6d6b0] width 1024 pitch 4096 (/4 1024)
>[  6818.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c8f4e8]
>[  6818.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c8f4e8] width 1024 pitch 4096 (/4 1024)
>[  6820.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e0ac68]
>[  6820.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e0ac68] width 1024 pitch 4096 (/4 1024)
>[  6820.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e28798]
>[  6820.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e28798] width 1024 pitch 4096 (/4 1024)
>[  6830.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da1db0]
>[  6830.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da1db0] width 1024 pitch 4096 (/4 1024)
>[  6833.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cf5b48]
>[  6833.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cf5b48] width 1024 pitch 4096 (/4 1024)
>[  6833.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfe338]
>[  6833.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfe338] width 1024 pitch 4096 (/4 1024)
>[  6833.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bd5fa0]
>[  6833.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bd5fa0] width 1024 pitch 4096 (/4 1024)
>[  6840.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de6468]
>[  6840.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de6468] width 1024 pitch 4096 (/4 1024)
>[  6844.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09740]
>[  6844.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09740] width 1024 pitch 4096 (/4 1024)
>[  6844.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e398e0]
>[  6844.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e398e0] width 1024 pitch 4096 (/4 1024)
>[  6844.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e398e0]
>[  6844.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e398e0] width 1024 pitch 4096 (/4 1024)
>[  6844.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcba00]
>[  6844.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcba00] width 1024 pitch 4096 (/4 1024)
>[  6860.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3a798]
>[  6860.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3a798] width 1024 pitch 4096 (/4 1024)
>[  6861.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d63f70]
>[  6861.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d63f70] width 1024 pitch 4096 (/4 1024)
>[  6862.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1f9e0]
>[  6862.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1f9e0] width 1024 pitch 4096 (/4 1024)
>[  6862.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1cac8]
>[  6862.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1cac8] width 1024 pitch 4096 (/4 1024)
>[  6868.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d66908]
>[  6868.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d66908] width 1024 pitch 4096 (/4 1024)
>[  6868.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1fbf0]
>[  6868.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1fbf0] width 1024 pitch 4096 (/4 1024)
>[  6868.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e27c48]
>[  6868.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e27c48] width 1024 pitch 4096 (/4 1024)
>[  6868.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9bca0]
>[  6868.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9bca0] width 1024 pitch 4096 (/4 1024)
>[  6872.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03260]
>[  6872.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03260] width 1024 pitch 4096 (/4 1024)
>[  6873.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d46ef8]
>[  6873.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d46ef8] width 1024 pitch 4096 (/4 1024)
>[  6874.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d1c950]
>[  6874.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d1c950] width 1024 pitch 4096 (/4 1024)
>[  6874.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfb490]
>[  6874.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfb490] width 1024 pitch 4096 (/4 1024)
>[  6876.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da8a00]
>[  6876.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da8a00] width 1024 pitch 4096 (/4 1024)
>[  6876.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e3a538]
>[  6876.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e3a538] width 1024 pitch 4096 (/4 1024)
>[  6876.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1fbf0]
>[  6876.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1fbf0] width 1024 pitch 4096 (/4 1024)
>[  6876.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9c8e0]
>[  6876.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9c8e0] width 1024 pitch 4096 (/4 1024)
>[  6876.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e310b0]
>[  6876.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e310b0] width 1024 pitch 4096 (/4 1024)
>[  6876.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9c8e0]
>[  6876.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9c8e0] width 1024 pitch 4096 (/4 1024)
>[  6876.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e310b0]
>[  6876.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e310b0] width 1024 pitch 4096 (/4 1024)
>[  6876.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9c8e0]
>[  6876.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9c8e0] width 1024 pitch 4096 (/4 1024)
>[  6876.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e310b0]
>[  6876.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e310b0] width 1024 pitch 4096 (/4 1024)
>[  6877.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d03340]
>[  6877.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d03340] width 1024 pitch 4096 (/4 1024)
>[  6879.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e35d98]
>[  6879.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e35d98] width 1024 pitch 4096 (/4 1024)
>[  6879.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d47620]
>[  6879.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d47620] width 1024 pitch 4096 (/4 1024)
>[  6879.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1f468]
>[  6879.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1f468] width 1024 pitch 4096 (/4 1024)
>[  6885.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da3238]
>[  6885.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da3238] width 1024 pitch 4096 (/4 1024)
>[  6885.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1f8b8]
>[  6885.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1f8b8] width 1024 pitch 4096 (/4 1024)
>[  6885.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca79e0]
>[  6885.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca79e0] width 1024 pitch 4096 (/4 1024)
>[  6885.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca79e0]
>[  6885.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca79e0] width 1024 pitch 4096 (/4 1024)
>[  6886.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9c8e0]
>[  6886.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9c8e0] width 1024 pitch 4096 (/4 1024)
>[  6886.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e27c48]
>[  6886.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e27c48] width 1024 pitch 4096 (/4 1024)
>[  6886.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca79e0]
>[  6886.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca79e0] width 1024 pitch 4096 (/4 1024)
>[  6886.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e1fbf0]
>[  6886.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e1fbf0] width 1024 pitch 4096 (/4 1024)
>[  6886.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8c36dc8]
>[  6886.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8c36dc8] width 1024 pitch 4096 (/4 1024)
>[  6887.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e361a8]
>[  6887.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e361a8] width 1024 pitch 4096 (/4 1024)
>[  6888.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e9c5f8]
>[  6889.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e9c5f8] width 1024 pitch 4096 (/4 1024)
>[  6889.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d09710]
>[  6889.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d09710] width 1024 pitch 4096 (/4 1024)
>[  6889.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da2af8]
>[  6889.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da2af8] width 1024 pitch 4096 (/4 1024)
>[  6892.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d5a8]
>[  6892.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d5a8] width 1024 pitch 4096 (/4 1024)
>[  6892.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e36190]
>[  6892.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e36190] width 1024 pitch 4096 (/4 1024)
>[  6892.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da0328]
>[  6892.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da0328] width 1024 pitch 4096 (/4 1024)
>[  6892.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8ca79e0]
>[  6892.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8ca79e0] width 1024 pitch 4096 (/4 1024)
>[  6892.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e27c48]
>[  6892.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e27c48] width 1024 pitch 4096 (/4 1024)
>[  6892.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfbca0]
>[  6892.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfbca0] width 1024 pitch 4096 (/4 1024)
>[  6892.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de4d60]
>[  6892.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de4d60] width 1024 pitch 4096 (/4 1024)
>[  6892.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfbca0]
>[  6892.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfbca0] width 1024 pitch 4096 (/4 1024)
>[  6892.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de4d60]
>[  6892.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de4d60] width 1024 pitch 4096 (/4 1024)
>[  6892.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cfbca0]
>[  6892.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cfbca0] width 1024 pitch 4096 (/4 1024)
>[  6893.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8cb6438]
>[  6893.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8cb6438] width 1024 pitch 4096 (/4 1024)
>[  6909.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e4c4d0]
>[  6909.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e4c4d0] width 1024 pitch 4096 (/4 1024)
>[  7001.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dbec10]
>[  7001.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dbec10] width 1024 pitch 4096 (/4 1024)
>[  7001.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e20d00]
>[  7001.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e20d00] width 1024 pitch 4096 (/4 1024)
>[  7001.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7001.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7001.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e20d00]
>[  7001.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e20d00] width 1024 pitch 4096 (/4 1024)
>[  7001.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7001.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7001.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e20d00]
>[  7001.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e20d00] width 1024 pitch 4096 (/4 1024)
>[  7001.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7001.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7002.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e20d00]
>[  7002.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e20d00] width 1024 pitch 4096 (/4 1024)
>[  7002.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7002.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7002.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e20d00]
>[  7002.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e20d00] width 1024 pitch 4096 (/4 1024)
>[  7002.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7002.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7003.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7003.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7003.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dbec10]
>[  7003.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dbec10] width 1024 pitch 4096 (/4 1024)
>[  7003.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bc0000]
>[  7003.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bc0000] width 1024 pitch 4096 (/4 1024)
>[  7003.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e39278]
>[  7003.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e39278] width 1024 pitch 4096 (/4 1024)
>[  7003.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdaba0]
>[  7003.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdaba0] width 1024 pitch 4096 (/4 1024)
>[  7003.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e39278]
>[  7003.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e39278] width 1024 pitch 4096 (/4 1024)
>[  7003.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8bdaba0]
>[  7003.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8bdaba0] width 1024 pitch 4096 (/4 1024)
>[  7003.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e39278]
>[  7003.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e39278] width 1024 pitch 4096 (/4 1024)
>[  7004.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcdc30]
>[  7004.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcdc30] width 1024 pitch 4096 (/4 1024)
>[  7005.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e016a8]
>[  7005.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e016a8] width 1024 pitch 4096 (/4 1024)
>[  7005.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e299d8]
>[  7005.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e299d8] width 1024 pitch 4096 (/4 1024)
>[  7007.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcda88]
>[  7007.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcda88] width 1024 pitch 4096 (/4 1024)
>[  7007.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd50b0]
>[  7007.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd50b0] width 1024 pitch 4096 (/4 1024)
>[  7008.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e440a8]
>[  7008.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e440a8] width 1024 pitch 4096 (/4 1024)
>[  7008.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8de21f8]
>[  7008.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8de21f8] width 1024 pitch 4096 (/4 1024)
>[  7009.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd18a8]
>[  7009.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd18a8] width 1024 pitch 4096 (/4 1024)
>[  7023.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e2d6f8]
>[  7023.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e2d6f8] width 1024 pitch 4096 (/4 1024)
>[  7023.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dd18a8]
>[  7023.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dd18a8] width 1024 pitch 4096 (/4 1024)
>[  7023.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8daea18]
>[  7023.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8daea18] width 1024 pitch 4096 (/4 1024)
>[  7023.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e19bf0]
>[  7023.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e19bf0] width 1024 pitch 4096 (/4 1024)
>[  7023.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e19bf0]
>[  7023.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e19bf0] width 1024 pitch 4096 (/4 1024)
>[  7023.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcd8d8]
>[  7023.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcd8d8] width 1024 pitch 4096 (/4 1024)
>[  7023.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8dcd8d8]
>[  7023.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8dcd8d8] width 1024 pitch 4096 (/4 1024)
>[  7025.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8beefb8]
>[  7025.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8beefb8] width 1024 pitch 4096 (/4 1024)
>[  7039.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8da30c8]
>[  7039.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8da30c8] width 1024 pitch 4096 (/4 1024)
>[  7039.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8e299d8]
>[  7039.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8e299d8] width 1024 pitch 4096 (/4 1024)
>[  7039.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d9a908]
>[  7039.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d9a908] width 1024 pitch 4096 (/4 1024)
>[  7039.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x8d9b298]
>[  7039.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x8d9b298] width 1024 pitch 4096 (/4 1024)
>[  7062.165] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7062.165] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7062.165] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7065.467] (II) AIGLX: Suspending AIGLX clients for VT switch
>[  7065.475] (II) RADEON(0): RADEONLeaveVT_KMS
>[  7065.475] (II) RADEON(0): Ok, leaving now...
>[  7074.675] (II) AIGLX: Resuming AIGLX clients after VT switch
>[  7075.108] (II) RADEON(0): RADEONEnterVT_KMS
>[  7077.399] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7077.399] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7077.399] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7078.719] (II) RADEON(0): RADEONSaveScreen(2)
>[  7079.719] (**) Option "Device" "/dev/input/event4"
>[  7079.752] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[  7092.177] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7092.177] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7092.178] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7092.489] (II) RADEON(0): RADEONSaveScreen(2)
>[  7092.489] (II) RADEON(0): RADEONSaveScreen(0)
>[  7099.790] (II) AIGLX: Suspending AIGLX clients for VT switch
>[  7099.790] (II) RADEON(0): RADEONLeaveVT_KMS
>[  7099.790] (II) RADEON(0): Ok, leaving now...
>[  7102.603] (II) AIGLX: Resuming AIGLX clients after VT switch
>[  7102.603] (II) RADEON(0): RADEONEnterVT_KMS
>[  7102.607] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7102.607] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7102.607] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7102.703] (II) RADEON(0): RADEONSaveScreen(2)
>[  7102.703] (II) RADEON(0): RADEONSaveScreen(1)
>[  7102.704] (**) Option "Device" "/dev/input/event4"
>[  7102.704] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[  7116.915] (II) AIGLX: Suspending AIGLX clients for VT switch
>[  7116.915] (II) RADEON(0): RADEONLeaveVT_KMS
>[  7116.915] (II) RADEON(0): Ok, leaving now...
>[  7144.749] (II) AIGLX: Resuming AIGLX clients after VT switch
>[  7147.248] (II) RADEON(0): RADEONEnterVT_KMS
>[  7149.035] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7149.036] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7149.036] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7149.606] (II) RADEON(0): RADEONSaveScreen(2)
>[  7153.048] (**) Option "Device" "/dev/input/event4"
>[  7153.137] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[  7166.378] (II) AIGLX: Suspending AIGLX clients for VT switch
>[  7166.378] (II) RADEON(0): RADEONLeaveVT_KMS
>[  7166.378] (II) RADEON(0): Ok, leaving now...
>[  7209.099] (II) AIGLX: Resuming AIGLX clients after VT switch
>[  7209.654] (II) RADEON(0): RADEONEnterVT_KMS
>[  7210.660] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7210.660] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7210.660] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7211.111] (II) RADEON(0): RADEONSaveScreen(2)
>[  7211.798] (**) Option "Device" "/dev/input/event4"
>[  7211.799] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[  7218.575] (II) RADEON(0): EDID vendor "AUO", prod id 12498
>[  7218.575] (II) RADEON(0): Printing DDC gathered Modelines:
>[  7218.575] (II) RADEON(0): Modeline "1024x600"x0.0   50.40  1024 1048 1184 1344  600 603 604 625 -hsync -vsync (37.5 kHz eP)
>[  7227.297] [mi] Increasing EQ size to 512 to prevent dropped events.
>[  7227.388] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[  7227.388] 
>[  7227.388] Backtrace:
>[  7228.403] 0: /usr/bin/Xorg (xorg_backtrace+0x4a) [0x80ac45a]
>[  7228.403] 1: /usr/bin/Xorg (mieqEnqueue+0x22b) [0x81aacfb]
>[  7228.403] 2: /usr/bin/Xorg (0x8047000+0x4589c) [0x808c89c]
>[  7228.403] 3: /usr/bin/Xorg (xf86PostMotionEventM+0x253) [0x80d9ec3]
>[  7228.403] 4: /usr/bin/Xorg (xf86PostMotionEvent+0xaa) [0x80da10a]
>[  7228.404] 5: /usr/lib/xorg/modules/input/synaptics_drv.so (0xb5993000+0x477e) [0xb599777e]
>[  7228.404] 6: /usr/lib/xorg/modules/input/synaptics_drv.so (0xb5993000+0x6c61) [0xb5999c61]
>[  7228.404] 7: /usr/bin/Xorg (0x8047000+0x82302) [0x80c9302]
>[  7228.404] 8: /usr/bin/Xorg (0x8047000+0xa8693) [0x80ef693]
>[  7228.404] 9: (vdso) (__kernel_sigreturn+0x0) [0xb77d1400]
>[  7228.404] 10: /lib/libc.so.6 (0x47180000+0x7e6a7) [0x471fe6a7]
>[  7228.404] 11: /lib/libc.so.6 (__libc_calloc+0x1a2) [0x471f9dc2]
>[  7228.405] 12: /usr/bin/Xorg (0x8047000+0x163850) [0x81aa850]
>[  7228.405] 13: /usr/bin/Xorg (mieqProcessInputEvents+0x201) [0x81ab341]
>[  7228.405] 14: /usr/bin/Xorg (ProcessInputEvents+0x15) [0x80c93c5]
>[  7228.405] 15: /usr/bin/Xorg (0x8047000+0x300f0) [0x80770f0]
>[  7228.405] 16: /usr/bin/Xorg (0x8047000+0x1dce5) [0x8064ce5]
>[  7228.405] 17: /lib/libc.so.6 (__libc_start_main+0xf5) [0x47199635]
>[  7228.405] 18: /usr/bin/Xorg (0x8047000+0x1e029) [0x8065029]
>[  7228.405] 
>[  7228.406] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[  7228.406] [mi] mieq is *NOT* the cause.  It is a victim.
>[  7229.265] [mi] EQ processing has resumed after 9 dropped events.
>[  7229.265] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.

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Attachments on bug 872973: 638091 | 638092 | 638093 | 638094 | 638095